WO2012079358A1 - Procédé, appareil, et système de traitement des données - Google Patents

Procédé, appareil, et système de traitement des données Download PDF

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Publication number
WO2012079358A1
WO2012079358A1 PCT/CN2011/076327 CN2011076327W WO2012079358A1 WO 2012079358 A1 WO2012079358 A1 WO 2012079358A1 CN 2011076327 W CN2011076327 W CN 2011076327W WO 2012079358 A1 WO2012079358 A1 WO 2012079358A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit
data sequence
scrambling code
seed
scrambling
Prior art date
Application number
PCT/CN2011/076327
Other languages
English (en)
Chinese (zh)
Inventor
段灿
许进
徐俊
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2012079358A1 publication Critical patent/WO2012079358A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/34—Encoding or coding, e.g. Huffman coding or error correction

Definitions

  • WLANs Wireless Local Area Networks
  • IEEE802.il is one of the mainstream technologies of wireless LAN. This protocol mainly specifies the physical layer (PHY) and media access control (MAC) layer specifications.
  • the channel coding process is as follows: The data information is scrambled by a sequence of random codes and then modulated into OFDM symbols by coding, spatial shunting, modulation, mapping, OFDM modulation, etc., and then transmitted.
  • the scrambling code seed is the initial state of the scrambling code generator.
  • the scrambling code seed at the transmitting end obtains the scrambling code sequence through the scrambling code generator, and then adds 4 to the data information.
  • the scrambling code sequence is obtained by the same 4 semaphore seed and 4 sigma generator as the transmitting end, and the decoding information is used to implement descrambling.
  • the receiving end scrambling code seed is notified by the transmitting end, and if the scrambling code seed has an error during the transmission, the data error after descrambling is caused.
  • the main object of the present invention is to provide a data processing method, device and system. To solve the above problem.
  • a data processing method comprises: scrambling a data sequence using a scrambling code seed, wherein the data sequence carries a parity bit, the parity bit is used to verify the scrambling code seed; and the scrambled data sequence is transmitted.
  • the check bits are used to verify a portion of the bits in the scrambling code seed.
  • the partial bits are bits out of the bits in the 4 sigma seed except for the bits corresponding to the tap position of the 4 sigma generator.
  • Scrambling the data sequence using the scrambling code seed includes: generating a random scrambling code sequence using the scrambling code seed; scrambling the data sequence using the random scrambling code sequence. ⁇ Verify the scrambling seed by parity.
  • the data processing method according to the present invention comprises: receiving a scrambled data sequence, wherein the scrambled data sequence uses a scrambling code seed to scramble the data sequence, the data sequence carries a check digit, and the check digit is used. Checking the scrambling code seed; determining that the check digit is correct; using the scrambling code seed to solve the scrambled data sequence.
  • the check digit When the check digit is used to check a part of the bits in the scrambling code seed, it is determined that the check digit is correctly included: using all the bits in the bits in the 4 sigma seed to determine that the school-risk is correct , wherein some of the bits are bits other than the bits corresponding to the 4th code generator tap position in the 4th code seed.
  • determining the check bit correctly comprises: using a part of the bits in the scrambling code seed to determine that the check bit is correct, wherein The partial bits are bits out of the bits in the 4 sigma seed except for the bits corresponding to the tap position of the 4 sigma generator.
  • a data processing apparatus includes: a scrambling module configured to scramble a data sequence using a scrambling code seed, wherein the data sequence carries a parity bit, the parity bit is used to verify the scrambling code seed; the transmitting module, setting To send a scrambled data sequence.
  • a data processing apparatus is also provided.
  • the data processing apparatus comprises: a receiving module configured to receive the scrambled data sequence 'J, wherein the scrambled data sequence scrambles the data sequence using the scrambling code seed, and the data sequence carries the school
  • the check bit is used to check the scrambling code seed; the determining module is set to determine that the check bit is correct; the descrambling module is set to descramble the scrambled data sequence using the scrambling code seed.
  • a data processing system includes a transmitting end and a receiving end, wherein the transmitting end includes: a scrambling module configured to scramble the data sequence using the scrambling code seed, wherein the data sequence carries a check digit, and the check bit is used for The scrambling code seed is sent; the sending module is configured to send the scrambled data sequence; the receiving end comprises: a receiving module, configured to receive the scrambled data sequence; a determining module, configured to determine that the check digit is correct; the descrambling module , set to descramble the scrambled data sequence using the scrambling code seed.
  • the invention solves the error in the transmission process of the scrambling code seed in the related art by carrying the check digit in the data sequence by the transmitting end and verifying the scrambling code seed by using the check bit by the receiving end, thereby causing the descrambling error
  • the problem of data error can ensure the correctness of the scrambling code seed and avoid the data error.
  • FIG. 1 is a flow chart 1 of a data processing method according to an embodiment of the present invention.
  • FIG. 2 is a second flowchart of a data processing method according to an embodiment of the present invention
  • Figure 4 is a flow chart of a data processing method according to a preferred embodiment of the present invention
  • Figure 5 is a flow chart of a data processing method according to a preferred embodiment 2 of the present invention
  • Figure 6 is a flowchart of a preferred embodiment of the present invention.
  • 7 is a flowchart of a data processing method according to a preferred embodiment 4 of the present invention
  • FIG. 8 is a block diagram showing the structure of a data processing apparatus according to an embodiment of the present invention
  • FIG. 9 is a block diagram showing the structure of a data processing apparatus according to an embodiment of the present invention.
  • FIG. 10 is a block diagram showing the structure of a data processing system according to an embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments.
  • the embodiment of the invention provides a data processing method.
  • 1 is a flow chart 1 of a data processing method according to an embodiment of the present invention. As shown in FIG. 1, the following steps include a step S1 to a step S4.
  • Step S102 Scrambling the data sequence by using the scrambling code seed, wherein the data sequence carries a check digit, wherein the school-risk is used for the school-risk 4 special code seed.
  • Step S104 Send the scrambled data sequence.
  • the scrambling code seed may have an error during transmission, thereby causing data error after descrambling.
  • the check bit can be used to check whether the scrambling code seed is correctly transmitted. Therefore, the transmitting end carries the school-risk position in the data sequence and uses the school-risk position to pass the risk through the receiving end. You code seed, can guarantee the correctness of the 4 special code seeds, thus avoiding the solution of the 4 special data.
  • the check bits are used to verify a portion of the bits in the scrambling code seed.
  • the effect of adding 4 especially to the school-risk position is such that when the school-risk is used for a part of the bits in the school-risk 4 special code seed, the scrambled check bit is used. Is the verification of all bits.
  • the partial bits are the bits of the bits in the scrambling code seed that are removed from the bits corresponding to the tap position of the scrambling code generator.
  • scrambling the data sequence using the scrambling code seed comprises: generating a random scrambling code sequence using the scrambling code seed; scrambling the data sequence using the random scrambling code sequence.
  • the odd-school-risk method is used to remedy the 4 yards seed.
  • the scrambling code seed is verified by means of parity, and the implementation manner is simple and reliable.
  • the embodiment of the invention provides a data processing method. 2 is a second flowchart of a data processing method according to an embodiment of the present invention. As shown in FIG. 2, the following steps include step S202 to step 4: S206. Step S202, receiving the scrambled data sequence, wherein the scrambled data sequence uses a scrambling code seed to scramble the data sequence, where the data sequence carries the scrambling code seed and the check digit, and the check digit is used for Verify the scrambling code seed.
  • step S204 it is determined that the school-risk position is correct.
  • step S206 using the scrambling code seed to descramble the scrambled data sequence.
  • determining the parity bit correctly comprises: determining the parity bit using all of the bits in the scrambling code seed Correctly, some of the bits are bits in the bits in the scrambling code seed except for the bits corresponding to the tap position of the scrambling code generator.
  • determining the check digit correctly comprises: using a part of the bits in the scrambling code seed to determine the school The bit is correctly verified, and some of the bits are bits other than the bit corresponding to the bit position of the scrambling code generator in the bit in the scrambling code seed.
  • 4 is a flowchart of a data processing method according to a preferred embodiment of the present invention. As shown in FIG. 4, the transmitting end needs to transmit data with a length of 108 bits, wherein the first 7 bits plus 4 especially the front 0 are used to save 4
  • the code generator seed is 1001001 and the information bit is 100 bits.
  • FIG. 5 is a flowchart of a data processing method according to a preferred embodiment 2 of the present invention. As shown in FIG.
  • the transmitting end needs to transmit data with a length of 3080 bits, wherein the first 7 bits plus 4 are especially used for 0.
  • FIG. 6 is a flowchart of a data processing method according to a preferred embodiment 3 of the present invention. As shown in FIG. 6, the transmitting end needs to transmit data with a length of 10016 bits, wherein the first 7 bits plus 4 are especially used for 0.
  • FIG. 7 is a flowchart of a data processing method according to a preferred embodiment 4 of the present invention.
  • the transmitting end needs to transmit data with a length of 25201 bits, wherein the first seven bits are 4 ⁇ seeds, and the information bits 25193 bit, then set the seven-bit scrambling code seed to 1100001 when scrambling.
  • FIG. 8 is a block diagram showing the structure of a data processing apparatus according to an embodiment of the present invention. As shown in FIG. 8, a scrambling module 82 and a transmitting module 84 are included. This will be described in detail below.
  • the scrambling module 82 is configured to scramble the data sequence by using the scrambling code seed, wherein the scrambled data sequence carries a check digit, where the check digit is used to check the scrambling code seed; the sending module 84 is connected to the adding The scrambling module 82 is configured to send the scrambled data sequence by the scrambling module 82.
  • the embodiment of the invention provides a data processing device, which can be used to implement the above data processing method.
  • 9 is a structural block diagram 2 of a data processing apparatus according to an embodiment of the present invention, such as As shown in FIG. 9, the receiving module 92, the determining module 94 and the descrambling module 96 are included. This will be described in detail below.
  • the receiving module 92 is configured to receive the scrambled data sequence, wherein the scrambled data sequence uses a scrambling code seed to scramble the data sequence, where the data sequence carries a check digit, and the check digit is used for verifying a scrambling seed; a determining module 94, coupled to the receiving module 92, configured to determine that the school-risk bit received by the receiving module 92 is correct; a solution 4 module 96, coupled to the determining module 94, configured to be used after the determining module 94 determines The scrambling seed descrambles the scrambled data sequence.
  • the embodiment of the invention provides a data processing system, which can be used to implement the above data processing method. FIG.
  • the sending end 1002 includes: a 4 special module 10022, configured to scramble the data sequence by using 4 special code seeds, wherein the scrambled data sequence carries the scrambling code seed and the check digit, wherein the check digit is used for verifying
  • the receiving module 10024 is configured to send the scrambled data sequence that carries the scrambling code seed and the check bit of the carrying module 10022.
  • the receiving end 1004 includes: a receiving module 10042, configured to receive the scrambling The subsequent data sequence; the determining module 10044 is connected to the receiving module 10042, and is configured to determine that the school-risk bit received by the receiving module 10042 is correct; the solution 4 module 10046 is connected to the determining module 10044, and is set to be determined by the determining module 10044, The scrambled data sequence is descrambled using the scrambling code seed.
  • the transmitting end carries the check digit in the data sequence and uses the check bit to check the scrambling code seed by the receiving end, which solves the error in the transmission process of the scrambling code seed in the related art, thereby causing data error after descrambling.
  • the problem is that the correctness of the scrambling code seed can be guaranteed, thereby avoiding descrambling data errors.
  • modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be Each of the integrated circuit modules is fabricated separately, or a plurality of modules or steps thereof are fabricated into a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software.
  • the above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Abstract

La présente invention concerne un procédé, un appareil, et un système de traitement des données. Ce procédé consiste d'abord à utiliser une base d'embrouillage pour embrouiller une séquence de données comportant un bit de contrôle permettant de vérifier la base d'embrouillage (S102), puis à transmettre la séquence de données embrouillée (S104). La présente invention permet de garantir la validité de la base d'embrouillage, et donc d'éviter les erreurs de désembrouillage des données.
PCT/CN2011/076327 2010-12-17 2011-06-24 Procédé, appareil, et système de traitement des données WO2012079358A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010594723.0 2010-12-17
CN201010594723.0A CN102546079B (zh) 2010-12-17 2010-12-17 数据处理方法、装置及系统

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Publication Number Publication Date
WO2012079358A1 true WO2012079358A1 (fr) 2012-06-21

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WO (1) WO2012079358A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5648440B2 (ja) * 2010-11-22 2015-01-07 ソニー株式会社 データ処理装置、及び、データ処理方法
CN108255464B (zh) * 2016-12-28 2021-09-28 北京忆恒创源科技股份有限公司 数据加扰方法、解扰方法及其装置
CN107885459B (zh) * 2017-09-30 2020-12-18 记忆科技(深圳)有限公司 一种软件实现固态硬盘写入数据加扰的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1675883A (zh) * 2002-07-04 2005-09-28 因芬尼昂技术股份公司 Wlan差错控制
US7158058B1 (en) * 2002-12-09 2007-01-02 Marvell International Ltd. Method and apparatus for generating a seed set in a data dependent seed selector
US7234097B1 (en) * 2003-01-27 2007-06-19 Marvell International Ltd. Methods of supporting host CRC in data storage systems without RLL coding
US7269778B1 (en) * 2002-10-15 2007-09-11 Marvell International Ltd. Data coding for enforcing constraints on ones and zeros in a communications channel

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1675883A (zh) * 2002-07-04 2005-09-28 因芬尼昂技术股份公司 Wlan差错控制
US7269778B1 (en) * 2002-10-15 2007-09-11 Marvell International Ltd. Data coding for enforcing constraints on ones and zeros in a communications channel
US7158058B1 (en) * 2002-12-09 2007-01-02 Marvell International Ltd. Method and apparatus for generating a seed set in a data dependent seed selector
US7234097B1 (en) * 2003-01-27 2007-06-19 Marvell International Ltd. Methods of supporting host CRC in data storage systems without RLL coding

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CN102546079B (zh) 2016-04-13

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