WO2012076838A3 - Hardware quadratic programming solver and method of use - Google Patents

Hardware quadratic programming solver and method of use Download PDF

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Publication number
WO2012076838A3
WO2012076838A3 PCT/GB2011/001679 GB2011001679W WO2012076838A3 WO 2012076838 A3 WO2012076838 A3 WO 2012076838A3 GB 2011001679 W GB2011001679 W GB 2011001679W WO 2012076838 A3 WO2012076838 A3 WO 2012076838A3
Authority
WO
WIPO (PCT)
Prior art keywords
hardware block
arithmetic processing
processing means
hardware
quadratic programming
Prior art date
Application number
PCT/GB2011/001679
Other languages
French (fr)
Other versions
WO2012076838A2 (en
Inventor
George Anthony Constantinides
Eric Colin Kerrigan
Juan Luis Jerez Fullana
Original Assignee
Imperial Innovations Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imperial Innovations Limited filed Critical Imperial Innovations Limited
Publication of WO2012076838A2 publication Critical patent/WO2012076838A2/en
Publication of WO2012076838A3 publication Critical patent/WO2012076838A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)

Abstract

A quadratic programming solver architecture comprising: a first hardware block arranged to perform parallel dot-product operations and thereby carry out matrix-vector multiplication, the first hardware block comprising a plurality of parallel multipliers and an adder tree arranged to combine the outputs from the parallel multipliers; a second hardware block comprising arithmetic processing means arranged to receive input data comprising constants and variables and to perform scalar operations thereon, the output from the arithmetic processing means being arranged to supply the parallel multipliers of the first hardware block, the variables being output from the first hardware block and fed back to the second hardware block; and control means configured to selectively schedule the sequence of scalar operations performed by the arithmetic processing means.
PCT/GB2011/001679 2010-12-07 2011-12-02 Hardware quadratic programming solver and method of use WO2012076838A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1020748.8 2010-12-07
GBGB1020748.8A GB201020748D0 (en) 2010-12-07 2010-12-07 Hardware quadratic programming solver and method of use

Publications (2)

Publication Number Publication Date
WO2012076838A2 WO2012076838A2 (en) 2012-06-14
WO2012076838A3 true WO2012076838A3 (en) 2012-09-27

Family

ID=43531616

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2011/001679 WO2012076838A2 (en) 2010-12-07 2011-12-02 Hardware quadratic programming solver and method of use

Country Status (2)

Country Link
GB (1) GB201020748D0 (en)
WO (1) WO2012076838A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9677493B2 (en) 2011-09-19 2017-06-13 Honeywell Spol, S.R.O. Coordinated engine and emissions control system
US20130111905A1 (en) 2011-11-04 2013-05-09 Honeywell Spol. S.R.O. Integrated optimization and control of an engine and aftertreatment system
US9650934B2 (en) 2011-11-04 2017-05-16 Honeywell spol.s.r.o. Engine and aftertreatment optimization system
EP3051367B1 (en) 2015-01-28 2020-11-25 Honeywell spol s.r.o. An approach and system for handling constraints for measured disturbances with uncertain preview
EP3056706A1 (en) 2015-02-16 2016-08-17 Honeywell International Inc. An approach for aftertreatment system modeling and model identification
EP3091212A1 (en) 2015-05-06 2016-11-09 Honeywell International Inc. An identification approach for internal combustion engine mean value models
CN108156832B (en) 2015-07-09 2020-05-08 Abb瑞士股份有限公司 Control of electrical converters based on optimized pulse patterns
EP3125052B1 (en) 2015-07-31 2020-09-02 Garrett Transportation I Inc. Quadratic program solver for mpc using variable ordering
US10272779B2 (en) 2015-08-05 2019-04-30 Garrett Transportation I Inc. System and approach for dynamic vehicle speed optimization
US10415492B2 (en) 2016-01-29 2019-09-17 Garrett Transportation I Inc. Engine system with inferential sensor
US10036338B2 (en) 2016-04-26 2018-07-31 Honeywell International Inc. Condition-based powertrain control system
US10124750B2 (en) 2016-04-26 2018-11-13 Honeywell International Inc. Vehicle security module system
EP3548729B1 (en) 2016-11-29 2023-02-22 Garrett Transportation I Inc. An inferential flow sensor
US11057213B2 (en) 2017-10-13 2021-07-06 Garrett Transportation I, Inc. Authentication system for electronic control unit on a bus

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
DAVID BOLAND ET AL: "An FPGA-based implementation of the MINRES algorithm", FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2008. FPL 2008. INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 8 September 2008 (2008-09-08), pages 379 - 384, XP031324382, ISBN: 978-1-4244-1960-9 *
DAVID BOLAND ET AL: "Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods", 17 March 2010, RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, SPRINGER BERLIN HEIDELBERG, BERLIN, HEIDELBERG, PAGE(S) 169 - 181, ISBN: 978-3-642-12132-6, XP019139327 *
FLORIAN A. POTRA ET AL: "Interior-Point Methods", 10 February 2000 (2000-02-10), XP055030453, Retrieved from the Internet <URL:http://pages.cs.wisc.edu/~swright/papers/potra-wright.pdf> [retrieved on 20120620] *
MINGHUA HE ET AL: "Model Predictive Control On A Chip", CONTROL AND AUTOMATION, 2005. ICCA '05. INTERNATIONAL CONFERENCE ON BUDAPEST, HUNGARY 26-29 JUNE 2005, PISCATAWAY, NJ, USA,IEEE, vol. 1, 26 June 2005 (2005-06-26), pages 528 - 532, XP010849799, ISBN: 978-0-7803-9137-6, DOI: 10.1109/ICCA.2005.1528175 *
S. J. WRIGHT: "Applying new optimization algorithms to model predictive control", PROC. INT. CONF. CHEMICAL PROCESS CONTROL, 1 January 1997 (1997-01-01), pages 147 - 155, XP055030444, Retrieved from the Internet <URL:ftp://info.mcs.anl.gov/pub/tech_reports/reports/P561.pdf> [retrieved on 20120620] *

Also Published As

Publication number Publication date
WO2012076838A2 (en) 2012-06-14
GB201020748D0 (en) 2011-01-19

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