WO2012073448A1

WO2012073448A1 - Solid state image capturing device

Info

Publication number: WO2012073448A1
Application number: PCT/JP2011/006457
Authority: WO
Inventors: 楠田　将之; 隆史森本
Original assignee: コニカミノルタオプト株式会社
Priority date: 2010-11-29
Filing date: 2011-11-21
Publication date: 2012-06-07
Also published as: JPWO2012073448A1

Abstract

At the time (t0) in the anterior half period of an exposure period (T_E), φTX=VL is set, and the gate of a transfer transistor (TX) is closed. Therefore, a PD accumulates signal charges to have a linear characteristic. At the time (t1) in the posterior half period (period tint_log) of the exposure period (T_E), φTX=VM is set, and the gate of the transfer transistor (TX) is half-open. Thereby, the PD accumulates the signal charges to have a linear log characteristic. By elongating the period (tint_log), the sensitivity of a logarithmic characteristic portion can be increased.

Description

Solid-state imaging device

The present invention relates to a solid-state imaging device including a pixel circuit having a linear characteristic when a low luminance light is incident and a logarithmic photoelectric characteristic when a high luminance light is incident.

In recent years, a solid-state imaging device including a pixel circuit including an embedded photoelectric conversion element (hereinafter referred to as “PD”) is known. In such a solid-state imaging device, it is possible to drive the transfer transistor in an intermediate state between a conductive state and a non-conductive state during the exposure period, logarithmically compress the signal charge accumulated in the PD, and widen the dynamic range. (For example, patent document 1).

That is, when high-intensity light is incident, the PD enters a subthreshold state, and the signal charge is accumulated while flowing part of the signal charge through a floating diffusion layer (hereinafter referred to as “FD”). Thereby, PD has logarithmic characteristics. On the other hand, when the low-luminance light is incident, the PD does not enter the subthreshold state and accumulates all signal charges. Thereby, PD has a linear characteristic. Therefore, the photoelectric conversion characteristics of the pixel circuit have two characteristics (linear log characteristics), with the linear characteristic portion showing the linear characteristic on the low luminance side and the logarithmic characteristic portion showing the logarithmic characteristic on the high luminance side, at the inflection point. become.

However, in Patent Document 1, there is no description about controlling the sensitivity of the logarithmic characteristic portion of the photoelectric conversion characteristic.

JP 2006-50544 A

An object of the present invention is to provide a solid-state imaging device capable of controlling the sensitivity of the logarithmic characteristic portion of the linear log characteristic.

A solid-state imaging device according to one aspect of the present invention is a solid-state imaging device including a pixel circuit having a linear log characteristic including a linear characteristic unit that exhibits linear characteristics on a low luminance side and a logarithmic characteristic unit that exhibits logarithmic characteristics on a high luminance side. The pixel circuit includes a photodiode that accumulates signal charges according to an incident light amount, a floating diffusion layer, and a transfer transistor that transfers the signal charges accumulated in the photodiode to the floating diffusion layer. A control unit is provided that changes the sensitivity of the logarithmic characteristic unit by applying a plurality of voltages to the gate of the transfer transistor during an exposure period of exposure.

1 is an overall configuration diagram of a solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the pixel circuit shown in FIG. 1. 6 is a timing chart of a pixel circuit when a transfer transistor is driven with an intermediate voltage during the entire exposure period. 4 is a graph showing photoelectric conversion characteristics of a pixel circuit driven according to the timing chart of FIG. 3. FIG. 4 is an energy band diagram of a pixel circuit corresponding to time t0 in FIG. FIG. 4 is an energy band diagram of a pixel circuit corresponding to time t1 in FIG. FIG. 4 is an energy band diagram of a pixel circuit corresponding to time t2 in FIG. FIG. 4 is an energy band diagram of a pixel circuit corresponding to time t3 in FIG. FIG. 4 is an energy band diagram of a pixel circuit corresponding to time t4 in FIG. FIG. 2 is a circuit diagram of the column ADC shown in FIG. 1. It is a timing chart of column ADC shown in FIG. 3 is a graph showing photoelectric conversion characteristics when sensitivity is changed in the pixel circuit shown in FIG. 2. 3 is a timing chart of a transfer transistor in the first embodiment of the present invention. The photoelectric conversion characteristics C (a), C (b), and C (c) of the pixel circuit GC when the transfer transistor is driven with φTX in FIGS. 13 (a), (b), and (c). 6 is a timing chart of the pixel circuit when the transfer transistor is driven with the first half period of the exposure period set to φTX = VL and the second half period set to φTX = VM. FIG. 16 is an energy band diagram of a pixel circuit corresponding to time t0 in FIG. FIG. 16 is an energy band diagram of the pixel circuit corresponding to time t1 in FIG. FIG. 16 is an energy band diagram of the pixel circuit corresponding to time t2 in FIG. 15. FIG. 16 is an energy band diagram of a pixel circuit corresponding to time t3 in FIG. FIG. 16 is an energy band diagram of the pixel circuit corresponding to time t4 in FIG. 15. FIG. 16 is an energy band diagram of the pixel circuit corresponding to time t5 in FIG. 15. It is a timing chart of the transfer transistor in Embodiment 2 of this invention. The photoelectric conversion characteristics C (a), C (b), and C (c) of the pixel circuit when the transfer transistor is driven with φTX in (a), (b), and (c) of FIG. 10 is a timing chart of the pixel circuit when the transfer transistor is driven with the first half period of the exposure period set to φTX = VM1 and the second half period set to φTX = VM2. FIG. 25 is an energy band diagram of the pixel circuit corresponding to time t0 in FIG. 24. FIG. 25 is an energy band diagram of the pixel circuit corresponding to time t1 in FIG. 24.

(Embodiment 1)
FIG. 1 is an overall configuration diagram of a solid-state imaging device according to an embodiment of the present invention. As shown in FIG. 1, the solid-state imaging device is a columnar parallel AD conversion type (column AD conversion type) CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging device, which includes a pixel array unit 1, a row decoder 2, a column. ADC array unit 3, column decoder 4, PLL 5, timing generator (hereinafter referred to as “TG”) 6, DAC 7, sense amplifier 8, ramp generation circuit 9, serializer 10, clock terminal 11, control terminal 12, output terminal 13 and a control unit 14.

In the present embodiment, the pixel array unit 1 to the output terminal 13 are integrated on one chip, and constitute a solid-state imaging device. However, this is an example, and the solid-state imaging device may be configured by integrating the pixel array unit 1 to the control unit 14 on one chip.

The pixel array unit 1 includes a plurality of pixel circuits GC (not shown) arranged in a matrix in M (M is a positive integer of 2 or more) rows × N (N is a positive integer of 2 or more) columns. ing. In the example of FIG. 1, the pixel circuits GC are arranged in a matrix of 14 rows × 17 columns.

The row decoder 2 includes, for example, a vertical scanning circuit and a driver circuit. The vertical scanning circuit is configured by, for example, a shift register, and performs vertical scanning of the pixel array unit 1 by cyclically selecting each row of the pixel array unit 1 in synchronization with a vertical synchronization signal output from the TG 6.

The driver circuit generates a pixel control signal and outputs the pixel control signal to each pixel circuit GC belonging to the row selected by the vertical scanning circuit, thereby driving each pixel circuit GC.

The column ADC array unit 3 includes N column ADCs 31 corresponding to the respective columns of the pixel array unit 1. The column ADC 31 is connected to the pixel circuit GC of each column via the vertical signal line L_1 corresponding to each column of the pixel array unit 1, and receives a noise signal and a signal signal from the pixel circuit GC of the row selected by the vertical scanning circuit. read out. Then, the column ADC 31 performs a correlated double sampling process on the read noise signal and signal signal to acquire a video signal. The column ADC 31 performs analog-digital conversion processing on the acquired video signal and holds the digital video signal.

The column decoder 4 is composed of, for example, a shift register, and cyclically selects the column ADC 31 of each column in one horizontal scanning period by outputting a column selection signal synchronized with the horizontal synchronization signal output from the TG 6. The column ADC array unit 3 is horizontally scanned, and the digital video signals held by the column ADCs 31 of each column are sequentially output to the sense amplifier 8.

The PLL 5 multiplies a clock signal (SYSCLK) supplied from an external device (for example, the control unit 14) via the clock terminal 11, and outputs the multiplied signal to the TG 6. In the present embodiment, for example, a 54 MHz clock signal is supplied to the clock terminal 11, and the PLL 5 multiplies the 54 MHz clock signal by 2 and supplies the 108 MHz clock signal to the TG 6.

The TG 6 generates timing signals necessary for controlling the solid-state imaging device, such as a vertical synchronization signal and a horizontal synchronization signal, according to the clock signal supplied from the PLL 5, and controls the entire solid-state imaging device.

Also, the TG 6 includes a register for storing a setting value of the timing signal. Note that setting values are written in the register by, for example, serial communication with an external device (for example, the control unit 14) connected via the control terminal 12. Here, as the set value, for example, a later-described transfer transistor TX (see FIG. 2) is driven in an intermediate state between a conductive state and a non-conductive state, and an intermediate voltage value for half-opening the gate of the transfer transistor TX is determined. For example.

In the present embodiment, the pixel array unit 1 includes, for example, a plurality of types of pixel circuits GC for acquiring video signals of a plurality of color components such as R (red), G (green), and B (blue). They are regularly arranged according to a predetermined arrangement method such as an arrangement. Therefore, the TG 6 stores a predetermined setting value that defines an intermediate voltage for each type of the pixel circuit GC in the register. The TG 6 controls the DAC 7 and the row decoder 2 so that each pixel circuit GC is driven by an intermediate voltage defined by a set value corresponding to the type of the pixel circuit GC.

Specifically, the TG 6 stores in advance which type of pixel circuit GC is arranged in each row and column of the pixel array unit 1. When one row with the row decoder 2 is selected, the TG 6 specifies which type of pixel circuit GC is arranged in each column of the row, and outputs a setting value corresponding to the specified type to the DAC 7.

TG6 converts the set value to DAC7 from digital to analog. The set value that has been converted from digital to analog is input to the row decoder 2. Under the control of TG6, the row decoder 2 outputs an intermediate voltage defined by the input set value to the transfer transistor TX (see FIG. 2) of the pixel circuit GC of each selected column.

Thus, by driving the pixel circuit GC with the intermediate voltage corresponding to the type, each pixel circuit GC can obtain an appropriate dynamic range according to its type.

The DAC (digital analog converter) 7 converts a digital signal output from the TG 6 into an analog signal and supplies the analog signal to the row decoder 2. For example, the DAC 7 converts the set value for defining the intermediate voltage output from the TG 6 into an analog signal to generate an intermediate voltage, and supplies the intermediate voltage to the row decoder 2.

The ramp generation circuit 9 generates a ramp signal and outputs it to each column ADC 31. The sense amplifier 8 amplifies the digital video signal output from the column ADC array unit 3 via the horizontal signal line L_2 and outputs the amplified signal to the serializer 10. In the present embodiment, the column ADC 31 generates a 14-bit digital video signal, shifts the phase of the signal of each bit by 180 degrees, and signals that are shifted in phase by 180 degrees and signals that are not shifted in phase. A total of 28 signals consisting of are output to the sense amplifier 8. Therefore, the total number of horizontal signal lines L_2 connecting the column ADC array unit 3 and the sense amplifier 8 is 28. The sense amplifier 8 amplifies the signals flowing through the 28 horizontal signal lines L_2, shapes the waveform of each signal, and outputs the waveform to the serializer 10.

The serializer 10 is composed of, for example, a serializer conforming to the LVDS (Low Voltage Differential Signalings) standard, and differentially amplifies a signal output in parallel via the 28 horizontal signal lines L_2 from the sense amplifier 8 to 14 bits. The signal is converted to serial and output to the output terminal 13. The output terminal 13 outputs a signal from the serializer 10 to the control unit 14.

The control unit 14 is configured by, for example, a dedicated hardware circuit, and changes the sensitivity of the logarithmic characteristics by applying a plurality of voltages to the gate of the transfer transistor TX during the exposure period (see FIG. 2). Here, the control unit 14 writes, for example, a plurality of types of setting values into the register of the TG 6 via the control terminal 12. The TG 6 applies an intermediate voltage according to the written set value to the gate of the transfer transistor TX via the DAC 7 and the row decoder 2. Details of the control unit 14 will be described later.

FIG. 2 is a circuit diagram of the pixel circuit GC shown in FIG. As shown in FIG. 2, the pixel circuit GC includes a photoelectric conversion element (hereinafter referred to as “PD”), a transfer transistor (hereinafter referred to as “TX”), and a reset transistor (hereinafter referred to as “RST”). ), An amplification transistor (hereinafter referred to as “SF”), and a row selection transistor (hereinafter referred to as “SEL”).

PD receives light from the subject, generates signal charge according to the received light quantity, and accumulates it with parasitic capacitance. Here, the PD has an anode connected to the source of TX, and PVSS as a driving voltage is input to the anode.

TX is composed of, for example, nMOS (Negative Channel Metal Oxide Semiconductor), and transfers signal charges accumulated by PD to a floating diffusion layer (hereinafter referred to as “FD” floating 」diffusion). A signal (hereinafter referred to as “φTX”) for driving TX in a conductive state, a non-conductive state, and an intermediate state is input to the gate of TX. The drain of TX is connected to FD. When φTX becomes zero voltage or negative voltage (hereinafter referred to as “VL”), the TX gate closes and TX becomes non-conductive. When φTX becomes an intermediate voltage (hereinafter referred to as “VM”), the gate of TX is half-opened, and TX is in an intermediate state between a conductive state and a non-conductive state. When φTX becomes a high level voltage (hereinafter referred to as “VH”), the gate of TX is opened and TX is turned on.

FD accumulates signal charges transferred from PD. As a result, a voltage corresponding to the signal charge appears in the FD.

RST is composed of, for example, an nMOS, φRST that is a signal for making RST conductive or non-conductive is input to a gate, PVDD that is a driving voltage is input to a drain, and a source of SF is connected through FD. Connected to the gate. When φRST = VH, RST becomes conductive, and when φRST = VL, RST becomes nonconductive.

RST then discharges the FD signal charge and resets the FD when it becomes conductive. PVDD and PVSS are output from a voltage source (not shown), and φRST is output from the row decoder 2.

SF is composed of, for example, an nMOS, the gate is connected to TX and RST via FD, the drive voltage PVDD is input to the drain, and the source is connected to SEL. The SF amplifies the voltage appearing on the FD and outputs it to the SEL.

SEL is composed of, for example, an nMOS, and a gate selection signal φVSEN is input to the gate, the drain is connected to SF, and the source is connected to the column ADC 31 of the corresponding column via the vertical signal line L_1. The SEL outputs the voltage amplified by the SF as an output signal to the column ADC 31 in the corresponding column via the vertical signal line L_1. Here, φVSEN is output from the row decoder 2.

FIG. 3 is a timing chart of the pixel circuit GC when the transfer transistor TX is driven with an intermediate voltage during the entire exposure period T_E. The exposure period is a period during which the subject is exposed, and the PD accumulates signal charges from the subject. As shown in FIG. 3, the pixel circuit GC cyclically repeats the exposure period T_E and the readout period T_R, and outputs a signal signal corresponding to the signal charge accumulated in the exposure period T_E.

In the exposure period T_E, as shown at time t0, φTX = VM. Therefore, the PD is in a subthreshold state when high-luminance light is incident, and accumulates signal charges while allowing signal charges to flow through the FD. Thereby, linear log characteristics are realized.

In the exposure period T_E, since the FD is always reset by RST, the signal charge flowing out from the PD is continuously discharged and the signal charge is not accumulated. Therefore, the voltage of the FD is constantly maintained at PVDD. Further, since φVSEN = VL in the exposure period T_E, no signal signal is output from the pixel circuit GC to the column ADC 31.

When the exposure period T_E is ended and the reading period T_R is started, φRST = VL is set, RST finishes resetting the FD, φTX = VL, and TX is in a non-conduction state.

At time t1, φVSEN = VH and SEL is in a conductive state. Thereby, from the vertical signal line L_1, the noise level voltage V_n appearing in the FD is amplified by SF and output to the column ADC 31 as a noise signal. Here, the reason why the voltage of the FD decreases from PVDD to the voltage V_n is mainly due to the influence of the parasitic capacitance between the FD and RST caused by changing φRST from VH to VL. The effect of ktc noise is also included. Since the ktc noise varies for each pixel circuit GC, the noise signal varies for each pixel circuit GC. Note that the voltage of the FD decreases as the amount of accumulated signal charge increases.

At time t2, φVSEN = VL, SEL is in a non-conductive state, and the output of the noise signal is stopped. Further, at time t2, φTX = VH is set, TX becomes conductive, and the signal charge of the PD is transferred to the FD.

Thereby, the voltage of the FD decreases according to the signal charge transferred to the FD, and becomes a signal level voltage V_s.

At time t3, φVSEN = VH, the voltage V_s of the FD is current amplified by SF, and is output as a signal signal to the column ADC 31 via the vertical signal line L_1. The output signal signal is differentiated from the noise signal by the column ADC 31, and a video signal is generated. Here, the video signal has a value corresponding to the difference between the FD noise level voltage V_n and the signal level voltage V_s. Therefore, by taking the difference between the noise signal and the signal signal, a video signal from which the noise component included in the signal signal has been removed can be obtained.

When the reading period T_R ends, φRST = VH, φVSEN = VL, and φTX = VM are set again, and an exposure period T_E for obtaining a video signal of the next frame is started.

FIG. 4 is a graph showing the photoelectric conversion characteristics of the pixel circuit GC driven according to the timing chart of FIG. In FIG. 4, the vertical axis is a linear axis and indicates a video signal output from the pixel circuit GC, and the horizontal axis is a logarithmic axis and indicates the intensity of incident light incident on the photoelectric conversion element PD.

As can be seen from this graph, the photoelectric conversion characteristics include a linear characteristic portion D1 in which the low luminance region exhibits a linear characteristic from the inflection point P1 and a logarithmic characteristic portion in which the high luminance region exhibits a logarithmic (log) characteristic. It has a linear log characteristic consisting of D2. In the graph of FIG. 4, the linear characteristic portion D1 rises while drawing a curve and the logarithmic characteristic portion D2 rises substantially linearly because the horizontal axis is a logarithmic axis.

5 to 9 are energy band diagrams of the pixel circuit GC corresponding to the time t0 to the time t4 in FIG. The energy band diagrams shown in FIGS. 5 to 9 show that the voltage is higher toward the lower side.

At time t0 shown in FIG. 5, since φRST = VH, FD is reset by RST and maintains the voltage of PVDD. Further, since φTX = VM is set, an energy barrier ES is generated between PD and FD. When the amount of signal charge accumulated in the PD is less than a certain value, the signal charge accumulated in the PD cannot move over the energy barrier ES and cannot move from the PD to the FD. Therefore, the signal charge of the first layer L1 has a linear characteristic with respect to the amount of incident light.

On the other hand, when the amount of signal charge accumulated in the PD becomes a certain value or more, the signal charge can move from the PD to the FD over the energy barrier ES. As a result, the PD enters a subthreshold state and accumulates signal charges while leaking signal charges to the FD. As a result, the signal charge of the second layer L2 has a logarithmic characteristic with respect to the amount of incident light. Thereby, the linear log characteristic is realized in the exposure period T_E shown at time t0.

At time t1 shown in FIG. 6, since the exposure period T_E has ended, φTX = VL, and TX becomes non-conductive. For this reason, the energy barrier ES becomes high, and the signal charge cannot move from the PD to the FD.

At time t1, since the resetting of the FD is completed, the voltage of the FD decreases from the PVDD to the voltage V_n mainly due to the influence of the parasitic capacitance between the FD and the RST caused by changing φRST from VH to VL. is doing. At time t1, φVSEN = VH, voltage V_n is current amplified by SF, and current amplified voltage V_n is output as a noise signal from vertical signal line L_1 via SEL.

At time t2 shown in FIG. 7, φTX = VH and TX is turned on. Thereby, the energy barrier ES is eliminated, and the signal charge is transferred from the PD to the FD. The FD accumulates signal charges including the first layer L1 and the second layer L2, and the voltage drops from the voltage V_n to the voltage V_s.

At time t3 shown in FIG. 8, φTX = VL and TX is turned off. Then, φVSEN = VH is set, the voltage V_s is current-amplified by SF, and the current-amplified voltage V_s is output as a signal signal from the vertical signal line L_1 via SEL.

At time t4 shown in FIG. 9, since the reading period T_R is ended and the exposure period T_E is started, φTX = VM, TX is in an intermediate state, and exposure is performed again. At time t4, since φRST = VH, the voltage of the FD rises again to PVDD.

FIG. 10 is a circuit diagram of the column ADC 31 shown in FIG. The column ADC includes a CDS circuit 41, a clamp unit 42, a comparison unit 43, and a latch circuit 44 in order from the upstream side. The CDS circuit 41 includes an inverting amplifier (hereinafter referred to as “AMP”), capacitors CIN and CF, and a switch SW1.

The input node I_1 of the AMP is connected to the vertical signal line L_1 via the capacitor CIN. A capacitor CF is connected between the input and output nodes of the AMP. A switch SW1 is connected in parallel to the capacitor CF. The terminal on the vertical signal line L_1 side of the capacitor CIN is a node VPIX.

The clamp unit 42 includes a capacitor C0 and a switch SW2. When φCL becomes high level, the switch SW2 is turned on, and the voltage at the node BB is clamped by the clamp voltage VCL.

The comparison unit 43 includes switches SW3, SW4, SW5, SW6, a comparator COMP1 (hereinafter referred to as “COMP1”), a comparator COMP2 (hereinafter referred to as “COMP2”), and capacitors C1 and C2. .

The switch SW3 is connected between the node BB and the node CC. The switch SW4 has one end connected to the node CC and the other end connected to a voltage source of a ramp signal (hereinafter referred to as “VRAMP”).

COMP1 has an input node (hereinafter referred to as “node DD”) connected to a node CC via a capacitor C1. A switch SW5 is connected between the input / output nodes of COMP1. The output node of COMP1 is connected to COMP2 via a capacitor C2. A switch SW6 is connected between the input / output nodes of COMP2. A latch circuit 44 is connected to the output node of COMP2 via an inverter I1. The latch circuit 44 is an n + 1-bit latch circuit that holds an n + 1-bit digital video signal having the most significant bit D0 and the least significant bit D (n). In the present embodiment, for example, n = 13 is employed, and the latch circuit 44 holds a 14-bit video signal.

FIG. 11 is a timing chart of the column ADC 31 shown in FIG. Note that times t1 and t3 shown in FIG. 11 correspond to the same times in FIG.

When the readout period T_R is started, a noise signal is output from the pixel circuit GC. Thereby, the voltage of the node VPIX rises to the noise level LV_n (time t1). Note that the voltage of the noise level LV_n is held by the CDS circuit 41.

Next, φPRST, φCL, φS1, and φS2 are each set to a high level for a predetermined time, and the CDS circuit 41, the clamp unit 42, and COMP1 and COMP2 are reset. As a result, the voltage at the node AA becomes VTH (AMP), the voltages at the nodes BB and CC become VCL, and the voltage at the node DD becomes VTH (COMP1).

Next, when a signal signal is output from the pixel circuit GC, the voltage of the node VPIX decreases by ΔV to reach the signal level LV_s (time t3).

As the voltage of the node VPIX decreases by ΔV, the voltages of the nodes AA, BB, CC, DD increase. Specifically, the nodes AA and BB increase by ΔV × CIN / CF. The nodes CC and DD rise by ΔV × (CIN / CF) × C0 / (C0 + C1). That is, the CDS circuit 41 calculates a difference between the noise signal and the signal signal, and a voltage corresponding to ΔV indicating the difference appears at the nodes AA to DD.

Next, φSH becomes low level and φSHX becomes high level, switch SW3 is turned on, switch SW4 is turned off, and VRAMP input is started (time TT1).

Also, at time TT1, the counting operation of the counter 45 is started. At time TT2, when the voltage at node DD exceeds VTH (COMP1), the output of COMP1 is inverted, and in response to the inversion, COMPOUT, which is an output signal from inverter I1, is inverted.

When COMPOUT is inverted, the latch circuit 44 latches the count value at that time. At time TT1, the voltage of the node CC decreases from ΔV × (CIN / CF) × C0 / (C0 + C1) by the voltage Va at the start of input of VRAMP. Therefore, the level of the node CC at this time corresponds to ΔV Has a value. Therefore, the period from time TT1 to time TT2 has a value corresponding to ΔV. Therefore, by counting the time from when VRAMP is input to when COMPOUT is inverted, a digital value corresponding to ΔV, that is, a digital value of the video signal can be obtained.

FIG. 12 is a graph showing photoelectric conversion characteristics when the sensitivity is changed in the pixel circuit GC shown in FIG. In FIG. 12, the vertical axis is a linear axis and indicates a video signal output from the pixel circuit GC, and the horizontal axis is a logarithmic axis and indicates the intensity of incident light incident on the photoelectric conversion element PD.

The photoelectric conversion characteristic C (a) is a photoelectric conversion characteristic of the pixel circuit GC in which the sensitivity shown in FIG. 4 is set as a standard. In the photoelectric conversion characteristic C (a), when it is desired to increase the sensitivity of the linear characteristic portion D1 (a), for example, i) increase the gain of the column ADC 31, ii) decrease the input range of the column ADC 31, iii) after AD conversion It is conceivable to add digital gain to the video signal.

Here, in order to realize i), CIN / CF shown in FIG. 10 may be increased. In order to realize ii), the amplitude of VRAMP shown in FIG. 11 may be reduced. In order to reduce the amplitude of VRAMP, the difference Vb−Va may be reduced. In order to realize iii), the control unit 14 that has captured the AD-converted video signal may multiply the digital video signal by a predetermined number (for example, two times or three times).

For example, consider a case where a double gain is given to the photoelectric conversion characteristic C (a). In this case, the photoelectric conversion characteristic C (b) is obtained. As shown in the photoelectric conversion characteristic C (b), if a double gain is simply given to the photoelectric conversion characteristic C (a), the sensitivity of not only the linear characteristic part D1 (a) but also the logarithmic characteristic part D2 (a). Will also go up. Therefore, the dynamic range DM (b) of the photoelectric conversion characteristic C (b) is lower than the dynamic range DM (a) of the photoelectric conversion characteristic C (a).

Therefore, in the present embodiment, only the sensitivity of the logarithmic characteristic portion D2 is made variable to obtain the photoelectric conversion characteristic C (c). In the photoelectric conversion characteristic C (c), the slope of the linear characteristic part D1 (c) is twice the slope of the linear characteristic part D1 (a), and the sensitivity of the linear characteristic part D1 (c) is the linear characteristic part D1 ( It is twice that of a). On the other hand, the slope of the logarithmic characteristic portion D2 (c) is ½ of the slope of the logarithmic characteristic portion D2 (a), and the sensitivity of the logarithmic characteristic portion D2 (c) is 1 / th of the sensitivity of the logarithmic characteristic portion D2 (a). 2

Therefore, the dynamic range DM (c) of the photoelectric conversion characteristic C (c) is increased and is the same as the dynamic range DM (a) of the photoelectric conversion characteristic C (a). In order to realize this, in the present embodiment, the control unit 14 changes the application time of φTX = VM as described above.

FIG. 13 is a TX timing chart according to Embodiment 1 of the present invention. VD indicates the start timing of the exposure period T_E of one frame. (A) shows the case where the sensitivity is not changed, (b) shows the case where the sensitivity is made lower than (a), and (c) shows the case where the sensitivity is made lower than (b). Note that since the readout period T_R is significantly shorter than the exposure period T_E, the readout period T_R is not shown in FIG. 13, and the exposure periods T_E of the respective frames are connected.

In FIG. 13A, φTX = VM is always set in the exposure period T_E of one frame, and the intermediate voltage VM is always applied to the gate of TX.

On the other hand, in FIGS. 13B and 13C, φTX = VL is set in the first half period of the exposure period T_E of one frame, the gate of the transfer transistor TX is closed, and φTX = VM is set in the second half period. The TX gate is half open.

FIG. 14 shows photoelectric conversion characteristics C (a), C (b), and C (c) of the pixel circuit GC when TX is driven with φTX in FIGS. 13 (a), (b), and (c). .

As shown in FIG. 14, it can be seen that the slope of the logarithmic characteristic portions D2 (a) to (c) decreases in the order of photoelectric conversion characteristics C (a) to photoelectric conversion characteristics C (c), and the sensitivity decreases. . That is, in the exposure period T_E, as the period of φTX = VM becomes longer, the slope of the logarithmic characteristic portion D2 increases and the sensitivity increases.

FIG. 15 is a timing chart of the pixel circuit GC when the first half period of the exposure period T_E is φTX = VL and the second half period is φTX = VM to drive the TX.

At time t0 in the first half of the exposure period T_E, φTX = VL is set, and the TX gate is closed. Therefore, the PD accumulates signal charges with linear characteristics.

At time t1 in the second half of the exposure period T_E, φTX = VM is set, and the gate of the transfer transistor TX is half opened. As a result, the PD accumulates signal charges with linear log characteristics. The period tint_log in FIG. 15 is the second half period, and the gate of the transfer transistor TX is half open. The operation in the reading period T_R is the same as that in FIG.

At time t5 in the first half period of the next exposure period T_E, φTX = VL, and the TX gate is closed. As a result, during the first half of the exposure period T_E, TX is driven with the gate closed.

16 to 21 are energy band diagrams of the pixel circuit GC corresponding to the time t0 to the time t5 in FIG. The energy band diagrams shown in FIGS. 16 to 21 show that the voltage is higher toward the lower side.

Hereinafter, the relationship between the period tint_log and the sensitivity of the logarithmic characteristic part D2 will be described with reference to FIGS.

At time t0 shown in FIG. 16, since φTX = VL and the TX gate is closed, a large energy barrier ES is generated between PD and FD. Therefore, the signal charge accumulated in the PD cannot get over the energy barrier ES and cannot move from the PD to the FD. Therefore, the signal charge consisting only of the first layer L1 having a linear characteristic with respect to the incident light quantity is accumulated in the PD. In this state, when the luminance of the subject is high, the PD is saturated.

At time t1 shown in FIG. 17, φTX = VM and the gate of the transfer transistor TX is half open. As a result, the energy barrier ES is reduced, and the signal charge accumulated on the upper part of the PD leaks toward the FD.

信号 Leakage of signal charge from PD to FD does not occur instantaneously, requires a certain time, and has time response. Therefore, the amount of signal charge finally remaining in the PD at the end of the exposure period T_E varies depending on the time of the period tint_log. Here, as the period tint_log increases, the amount of logarithmic characteristic signal charge finally remaining in the PD approaches the amount of logarithmic characteristic signal charge that should be originally stored in the PD. Therefore, as the period tint_log becomes longer, the slope of the logarithmic characteristic portion D2 increases and the sensitivity of the logarithmic characteristic portion D2 becomes higher. On the other hand, as the period tint_log becomes shorter, the amount of logarithmic characteristic signal charge finally remaining in the PD deviates from the amount of logarithmic characteristic signal charge that should originally be accumulated in the PD. Therefore, as the period tint_log becomes shorter, the slope of the logarithmic characteristic portion D2 decreases, and the sensitivity of the logarithmic characteristic portion D2 becomes lower.

Therefore, in the first embodiment, the control unit 14 obtains the luminance of the subject, shortens the period tint_log as the luminance of the subject increases, and reduces the sensitivity of the logarithmic characteristic unit D2 to ensure the dynamic range. On the other hand, the control unit 14 increases the sensitivity of the logarithmic characteristic unit D2 by extending the period tint_log as the luminance of the subject decreases.

Note that the control unit 14 may obtain the period tint_log using a function or LUT in which the relationship between the luminance of the subject and the period tint_log is determined in advance. Then, a control signal for driving TX in the obtained period tint_log may be output to TG6. The TG 6 that has received this control signal may control the row decoder 2 so that TX is driven with φTX having the period tint_log obtained by the control unit 14.

Here, the control unit 14 may calculate an average value of video signals output from all or some of the pixel circuits GC constituting the pixel array unit 1 as the luminance of the subject. The control unit 14 may obtain a histogram of video signals output from all or some of the pixel circuits GC constituting the pixel array unit 1 and calculate the maximum peak of the histogram as the luminance of the subject.

At time t2 shown in FIG. 18, as in the case of time t1 in FIG. 6, since the exposure period T_E has ended, φTX = VL is set and TX is turned off. For this reason, the energy barrier ES becomes high, and the signal charge cannot move from the PD to the FD.

At time t3 shown in FIG. 19, similarly to time t2 shown in FIG. 7, φTX = VH, and TX is turned on. Thereby, the energy barrier ES is eliminated, and the signal charge is transferred from the PD to the FD.

At time t4 shown in FIG. 20, similarly to time t4 shown in FIG. 9, φTX = VL and TX is turned off. Then, φVSEN = VH is set, the voltage V_s is current-amplified by SF, and the current-amplified voltage V_s is output as a signal signal from the vertical signal line L_1 via SEL.

21. At time t5 shown in FIG. 21, since the reading period T_R is ended and the exposure period T_E is started, φTX = VH is established, and TX is turned off and exposure is performed again. Here, since φTX = VH, it can be seen that the energy barrier ES is higher than that at the time t4 in FIG. 9 where φTX = VM.

Thus, in the present embodiment, the first half period of the exposure period T_E is φTX = VL, and the second half period of the exposure period T_E is φTX = VM. When the luminance of the subject is high, the period tint_log is shortened to secure a dynamic range. On the other hand, when the luminance of the subject is low, the period tint_log is lengthened and the sensitivity is increased. Therefore, it is possible to achieve both an increase in sensitivity and a secure dynamic range.

(Embodiment 2)
Next, the solid-state imaging device of Embodiment 2 will be described. The solid-state imaging device of Embodiment 2 is characterized in that an intermediate voltage (hereinafter referred to as “VM1”) and an intermediate voltage (hereinafter referred to as “VM2”) are applied during the exposure period T_E. In the present embodiment, the same elements as those in the first embodiment will not be described.

FIG. 22 is a TX timing chart according to Embodiment 2 of the present invention. (A) shows the case where the sensitivity is not changed, (b) shows the case where the sensitivity is made higher than (a), and (c) shows the case where the sensitivity is made higher than (b). Note that since the readout period T_R is significantly shorter than the exposure period T_E, the readout period T_R is not shown in FIG. 22 and the exposure periods T_E of the respective frames are connected.

(A) In the exposure period T_E of one frame, φTX = VM2 is always established, and VM2 is always applied to the gate of the transfer transistor TX.

On the other hand, in FIGS. 22B and 22C, φTX = VM1 is set in the first half period of the exposure period T_E of one frame, and φTX = VM2 is set in the second half period.

Here, VM1 <VM2. Therefore, the TX gate is half open in both the first half period and the second half period, but the gate is opened more greatly in the second half period than in the first half period. Note that VM2 is an intermediate voltage for setting the inflection point P1 of the photoelectric conversion characteristics of the pixel circuit GC to a target value.

FIG. 23 shows photoelectric conversion characteristics C (a), C (b), and C (c) of the pixel circuit GC when TX is driven with φTX in FIGS. 22 (a), (b), and (c). .

As shown in FIG. 23, it can be seen that the slopes of the logarithmic characteristic portions D2 (a) to D2 (c) increase in the order of photoelectric conversion characteristics C (a) to photoelectric conversion characteristics C (c), and the sensitivity is increased. . That is, in the exposure period T_E, as the period of φTX = VM2 becomes shorter, the slope of the logarithmic characteristic portion D2 increases and the sensitivity increases.

FIG. 24 is a timing chart of the pixel circuit GC when the TX is driven with the first half period of the exposure period T_E being φTX = VM1 and the second half period being φTX = VM2.

At time t0 of the first half period of the exposure period T_E, φTX = VM1 is set, and the TX gate is half open. Therefore, the PD accumulates signal charges with linear log characteristics.

At time t1 in the second half of the exposure period, φTX = VM2 is set, and the TX gate is opened halfway in a state where it is further opened than in the first half period. As a result, the PD accumulates signal charges with linear log characteristics. The period tlog_sec in FIG. 24 is the second half period. The operation in the reading period T_R is the same as that in FIG.

At time t5 in the first half period of the next exposure period T_E, φTX = VM1 is set, and the TX gate is half opened. As a result, during the first half of the exposure period T_E, TX is driven with the gate half open.

25 and 26 are energy band diagrams of the pixel circuit GC corresponding to time t0 and time t1 in FIG. The energy band diagrams shown in FIGS. 25 and 26 indicate that the voltage is higher toward the lower side. Note that the energy band diagram at times t2, t3, and t4 shown in FIG.

Hereinafter, the relationship between the period tlog_sec and the sensitivity of the logarithmic characteristic portion D2 will be described with reference to FIGS.

At time t0 shown in FIG. 25, φTX = VM1, the gate of TX is half-opened, and an energy barrier ES is generated between PD and FD. In this state, when the luminance of the subject is high, the PD is in a subthreshold state determined by VM1 and accumulates signal charges with linear log characteristics. In this state, the PD accumulates signal charges belonging to the first layer L1 below VM1 with linear characteristics, and accumulates signal charges belonging to the second layer L2 above VM1 with logarithmic characteristics.

At time t1 shown in FIG. 26, φTX = VM2, and the TX gate is further opened more than at time t0. As a result, the energy barrier ES becomes lower than that at time t0.

In this state, the signal charge belonging to the layer above VM2 leaks toward the FD, but this leakage of signal charge does not occur instantaneously and has a certain time response. Yes.

Therefore, when the period tlog_sec is short, the signal charge belonging to the second layer L2 is placed on the signal charge accumulated in the layer L1 ′ between VM1 and VM2. The signal charge belonging to this layer L1 ′ is the signal charge belonging to the first layer L1 at time t0.

As the period tlog_sec becomes longer, the signal charge of the layer L1 ′ leaks to the FD side, and the layer L1 ′ becomes logarithmic and is absorbed by the second layer L2, and eventually disappears, but if the period tlog_sec is shorter, It behaves like a logarithmic characteristic and becomes an offset of the second layer L2. Therefore, if the period tlog_sec is short, at the end of the exposure period T_E, the signal charge component accumulated in the logarithmic characteristic among the signal charges remaining in the PD increases, and the sensitivity of the logarithmic characteristic portion D2 increases.

Also, when the difference between VM1 and VM2 is large, the sensitivity of the logarithmic characteristic portion D2 can be increased similarly. That is, the greater the difference between VM1 and VM2, the more the height of the layer L1 ′ increases, so the offset of the second layer L2 increases. Therefore, at the end of the exposure period T_E, the signal charge component accumulated in the logarithmic characteristic among the signal charges remaining in the PD increases, and the sensitivity of the logarithmic characteristic portion D2 increases.

From the above, the sensitivity of the logarithmic characteristic portion D2 depends on the length of the period tlog_sec and the voltage difference between VM2 and VM1.

Therefore, the control unit 14 obtains the brightness of the subject in the same manner as in the first embodiment, and performs control to increase the period tlog_sec as the brightness of the subject increases, and increases VM1 to reduce the voltage difference between VM1 and VM2. By executing at least one of the controls, the sensitivity of the logarithmic characteristic portion D2 is lowered and the dynamic range is secured.

On the other hand, the control unit 14 performs logarithmic characteristics by executing at least one of control for shortening the period tlog_sec and control for increasing the voltage difference between VM1 and VM2 by decreasing VM1 as the luminance of the subject decreases. The sensitivity of the part D2 is increased.

Here, the control unit 14 may obtain the period tlog_sec using a function or LUT in which the relationship between the luminance of the subject and the period tlog_sec is determined in advance. Alternatively, VM1 may be obtained by using a function or LUT that predetermines the relationship between the luminance of the subject and the period VM1. Then, a control signal for driving TX in the obtained period tlog_sec or VM1 may be output to TG6. The TG 6 that has received this control signal may control the row decoder 2 so that TX is driven with φTX having the period tlog_sec, VM1 obtained by the control unit 14.

In the second embodiment, the exposure period T_E is divided into three periods, and the first period is φTX = VL, the second period is φTX = VM1, and the third period is φTX = VM2. Good. By providing a period of φTX = VL, it is possible to prevent signal charges caused by the dark current of TX from being accumulated in the FD.

As described above, in the second embodiment, in the exposure period T_E, after φTX = VM1, φTX = VM2, and control for changing the period in which VM2 is applied according to the luminance of the subject, and the voltage difference between VM1 and VM2 are set. At least one of the changing controls is performed. Therefore, it is possible to achieve both the increase in sensitivity and the securing of the dynamic range.

(Embodiment 3)
In the third embodiment, the presence / absence of a bright subject is determined, and the method of the first embodiment is used to perform control to lower the sensitivity when a bright subject exists, and the sensitivity is increased when there is no bright subject. It is characterized by performing control.

In the present embodiment, the same elements as those in the first and second embodiments are not described. In the present embodiment, the control unit 14 shortens the period tint_log when it is determined that there is a bright subject, compared to when it is determined that there is no bright subject. Thereby, the sensitivity of the logarithmic characteristic portion D2 is lowered, and a dynamic range is secured.

On the other hand, when the control unit 14 determines that there is no bright subject, the control unit 14 lengthens the period tint_log compared to the case where it is determined that there is a bright subject. This increases the sensitivity of the logarithmic characteristic portion D2.

Specifically, when it is determined that a bright subject exists, the control unit 14 sets the period tint_log to a predetermined period T_down when a bright subject exists. On the other hand, when it is determined that there is no bright subject, the control unit 14 may set the period tint_log to a predetermined period T_up when there is no bright subject. Here, the period T_up> the period T_down. Therefore, when a bright subject exists, the period tint_log is shortened and the dynamic range is secured by lowering the sensitivity. When there is no bright subject, the period tint_log is lengthened and the sensitivity can be increased.

Note that when the control unit 14 determines that there is no bright subject, the entire period of the exposure period T_E may be set as the period tint_log. In this way, it is possible to maximize the sensitivity when there is no bright subject.

Here, the control unit 14 may determine the presence or absence of a bright subject based on the average value of the video signal output from each pixel circuit GC.

Specifically, the control unit 14 obtains an average value of the video signals output from all or some of the pixel circuits GC configuring the pixel array unit 1, compares the average value with a specified value V_th1, and calculates the average value. Can be determined that there is a bright subject, and if the average value is less than the specified value V_th1, it can be determined that there is no bright subject.

As the specified value V_th1, a predetermined level on the high luminance side of the logarithmic characteristic portion D2 shown in FIG. 4 may be adopted.

Further, the control unit 14 obtains a histogram of video signals output from all or some of the pixel circuits GC constituting the pixel array unit 1 and determines whether or not the subject is bright based on this histogram. Good. In this case, the control unit 14 obtains a graph of the histogram of the video signal that defines the gradation value of the video signal on the horizontal axis and the frequency on the vertical axis, identifies the peak on the highest gradation side from this graph, If the tone value is equal to or greater than the specified value V_th2, it is determined that the subject is bright, and if the peak tone value is less than the specified value V_th2, the subject is determined to be dark.

As the prescribed value V_th2, the prescribed value V_th1 shown in FIG. 4 may be adopted, a value slightly lower than the prescribed value V_th1 may be adopted, or a value slightly higher than the prescribed value V_th1 may be adopted. Good.

Further, the control unit 14 obtains a total value of the frequencies of the gradation values higher than the specified value V_th1 in the histogram, and determines that a bright subject exists if the total value is equal to or greater than the specified value V_th3. If it is less than the prescribed value Vth_3, it may be determined that there is no bright subject. Here, as the specified value V_th3, for example, the number of pixel circuits GC that output a video signal having a gradation value equal to or higher than the specified value V_th1 with respect to the number of all the pixel circuits GC configuring the pixel array unit 1 is predetermined. What is necessary is just to employ | adopt the value which becomes a ratio (for example, 90%, 80%).

Thus, in the present embodiment, the dynamic range can be ensured when a bright subject exists, and the sensitivity can be increased when there is no bright subject.

(Embodiment 4)
In the fourth embodiment, the presence / absence of a bright subject is determined, and the method of the second embodiment is used to perform control to lower the sensitivity when a bright subject exists, and the sensitivity is increased when there is no bright subject. It is characterized by performing control. In the present embodiment, the description of the same elements as in the first to third embodiments is omitted.

In the present embodiment, the control unit 14 determines the presence or absence of a bright subject using the same method as in the third embodiment. Then, the control unit 14 determines whether or not there is a bright subject, and when it is determined that there is a bright subject, the control unit 14 lengthens the period tlog_sec compared to when it is determined that there is no bright subject.

Specifically, when it is determined that there is a bright subject, the control unit 14 sets the period tlog_sec to a predetermined period T_up. On the other hand, when determining that there is no bright subject, the control unit 14 sets the period tlog_sec to a predetermined period T_down. Here, the period T_up> the period T_down.

Therefore, when there is a bright subject, the period tlog_sec is set to the period T_up, the period of φTX = VM2 is increased, and the sensitivity of the logarithmic characteristic portion D2 is decreased. On the other hand, when there is no bright subject, the period tlog_sec is set to the period T_down, the period of φTX = VM2 is decreased, and the sensitivity of the logarithmic characteristic portion D2 is increased.

Note that the control unit 14 may reduce the voltage difference between the VM1 and the VM2 when it is determined that a bright subject exists, compared to a case where it is determined that there is no bright subject. On the other hand, when determining that there is no bright subject, the control unit 14 may increase the voltage difference between VM1 and VM2 as compared with the case where it is determined that there is a bright subject. Specifically, since VM2 is fixed in order to set the inflection point P1 to a desired value, when there is a bright subject, the value of VM1 is a larger value VM1_big than when there is no bright subject. And the voltage difference between VM1 and VM2 may be reduced. On the other hand, if there is no bright subject, the value of VM1 is set to the value VM1_small and the voltage difference between VM1 and VM2 is increased. In addition, what is necessary is just to employ | adopt as a value VM1_big a predetermined value beforehand, when ensuring a dynamic range. In addition, as the value VM1_small, a suitable value determined in advance for increasing the sensitivity of the logarithmic characteristic portion D2 may be adopted.

In the present embodiment, the control for changing the period tlog_sec and the control for changing the voltage difference between VM1 and VM2 may be combined.

Thus, according to the present embodiment, the same effect as in the third embodiment can be obtained.

The technical features of the solid-state imaging device described above can be summarized as follows.

(1) A solid-state image pickup device according to the present invention is a solid-state image pickup device including a pixel circuit having a linear log characteristic including a linear characteristic portion having a linear characteristic on a low luminance side and a logarithmic characteristic portion having a logarithmic characteristic on a high luminance side. The pixel circuit includes a photodiode that accumulates signal charges according to an incident light amount, a floating diffusion layer, and a transfer transistor that transfers the signal charges accumulated in the photodiode to the floating diffusion layer. A control unit is provided that changes the sensitivity of the logarithmic characteristic unit by applying a plurality of voltages to the gate of the transfer transistor during an exposure period of exposure.

According to this configuration, plural kinds of voltages are applied to the gate of the transfer transistor during the exposure period. Therefore, it is possible to control only the sensitivity of the logarithmic characteristic part while maintaining the sensitivity of the linear characteristic part. Therefore, when the luminance of the subject is high, the sensitivity of the logarithmic characteristic portion can be secured by lowering the sensitivity of the logarithmic characteristic portion, and when the subject sensitivity is low, the sensitivity of the logarithmic characteristic portion can be increased.

(2) The control unit applies the intermediate voltage to the gate of the transfer transistor at least at the last period of the exposure period to half-open the gate, and changes the period of applying the intermediate voltage to change the logarithmic characteristic. It is preferable to change the sensitivity of the part.

According to this configuration, at least the last period of the exposure period, the intermediate voltage is applied to the gate of the transfer transistor and the gate is half-opened. The sensitivity of the logarithmic characteristic portion is changed by changing the period during which the intermediate voltage is applied. Here, if the period during which the intermediate voltage is applied becomes longer in the exposure period, the signal charge finally remaining in the photoelectric conversion element at the end of the exposure period approaches the amount of signal charge having the logarithmic characteristic that should be inherent. It will be. Therefore, the sensitivity of the logarithmic characteristic portion can be increased by lengthening the period during which the intermediate voltage is applied.

Note that at least the last period refers to the last period when the exposure period is divided into a plurality of periods. For example, when the exposure period is divided into two periods, a first half period and a second half period, the second half period corresponds to at least the last period.

(3) Preferably, the control unit divides the exposure period into two periods, applies a voltage for closing the gate to the gate in the first half period, and applies the intermediate voltage to the gate in the second half period.

According to this configuration, since the gate of the transfer transistor is closed in the first half of the exposure period, it is possible to suppress dark current generated at the interface between the substrate layer and the insulating layer below the gate electrode of the transfer transistor. .

(4) In the exposure period, the control unit applies a first intermediate voltage to the gate to partially open the gate, and then applies a second intermediate voltage higher than the first intermediate voltage to the gate. The sensitivity of the logarithmic characteristic portion is changed by performing at least one of control for changing the period for applying the second intermediate voltage and changing the voltage difference between the first intermediate voltage and the second intermediate voltage by further opening the gate. It is preferable to make it.

According to this configuration, since the first intermediate voltage is switched to the second intermediate voltage during the exposure period, the gate is further opened. Therefore, at the end of the exposure period, the signal charge component having the logarithmic characteristic among the signal charges remaining in the photoelectric conversion element can be increased, and the sensitivity of the logarithmic characteristic portion can be increased.

Here, if the period during which the second intermediate voltage is applied is shortened or the voltage difference between the first intermediate voltage and the second intermediate voltage is increased, the signal charge component of the logarithmic characteristic is increased and the sensitivity of the logarithmic characteristic part is increased. be able to. On the other hand, when the period during which the second intermediate voltage is applied is lengthened or the voltage difference is decreased, the signal charge component of the logarithmic characteristic can be reduced and the sensitivity of the logarithmic characteristic part can be lowered. Therefore, the sensitivity of the logarithmic characteristic portion can be changed by performing at least one of control for changing the time for applying the second intermediate voltage and control for changing the voltage difference.

(5) The control unit determines whether or not there is a bright subject. When the bright subject is determined to be present, the controller applies a period during which the intermediate voltage is applied compared to when the bright subject is determined not to exist. It is preferable to shorten it.

According to this configuration, when there is a bright subject, the period during which the intermediate voltage is applied is shortened, so that the sensitivity of the logarithmic characteristic portion is lowered and the dynamic range can be secured. On the other hand, when there is no bright subject, the period of applying the intermediate voltage is lengthened, so that the sensitivity of the logarithmic characteristic portion can be increased.

(6) The control unit determines whether or not a bright subject exists, and determines that the bright subject exists, and applies a second intermediate voltage compared to a case where the bright subject does not exist. It is preferable to perform at least one of control for increasing the voltage difference and control for reducing the voltage difference as compared with a case where it is determined that the bright subject does not exist.

According to this configuration, when there is a bright subject, at least one of control in which the period during which the second intermediate voltage is applied is shortened and control in which the voltage difference is made smaller than when there is no bright subject. Therefore, the sensitivity of the logarithmic characteristic portion is lowered, and a dynamic range can be secured. On the other hand, when there is no bright subject, at least one of control for increasing the period during which the second intermediate voltage is applied and control for increasing the voltage difference is performed as compared with the case where there is a bright subject. Therefore, the sensitivity of the logarithmic characteristic part can be increased.

(7) It is preferable that there are a plurality of the pixel circuits, and the control unit determines whether or not the bright subject exists based on an average value of pixel signals output from each pixel circuit.

According to this configuration, it is possible to accurately determine the presence or absence of a bright subject.

(8) It is preferable that there are a plurality of the pixel circuits, and the control unit determines the presence / absence of the bright subject based on a histogram of pixel signals output from each pixel circuit.

Claims

A solid-state imaging device including a pixel circuit having a linear log characteristic including a linear characteristic unit having a linear characteristic on a low luminance side and a logarithmic characteristic unit having a logarithmic characteristic on a high luminance side,
The pixel circuit includes a photodiode that accumulates signal charges according to the amount of incident light, a floating diffusion layer, and a transfer transistor that transfers signal charges accumulated in the photodiode to the floating diffusion layer,
A solid-state imaging device including a control unit that changes the sensitivity of the logarithmic characteristic unit by applying a plurality of voltages to the gate of the transfer transistor during an exposure period in which an object is exposed.
The control unit applies the intermediate voltage to the gate of the transfer transistor at least at the last period of the exposure period to half-open the gate, and changes the period of applying the intermediate voltage to change the sensitivity of the logarithmic characteristic unit. The solid-state imaging device according to claim 1, wherein
3. The solid-state imaging device according to claim 2, wherein the control unit divides the exposure period into two periods, applies a voltage for closing the gate in the first half period to the gate, and applies the intermediate voltage to the gate in the second half period. .
The control unit applies a first intermediate voltage to the gate and half-opens the gate during the exposure period, and then applies a second intermediate voltage higher than the first intermediate voltage to the gate. The sensitivity of the logarithmic characteristic section is changed by further opening and performing at least one of control for changing a period during which the second intermediate voltage is applied and control for changing a voltage difference between the first intermediate voltage and the second intermediate voltage. The solid-state imaging device according to 1.
The control unit determines whether or not there is a bright subject, and when the bright subject is present, the control unit reduces the period during which the intermediate voltage is applied, compared to when the bright subject is not present. Item 6. The solid-state imaging device according to Item 2 or 3.
The control unit determines whether or not a bright subject is present, and if it is determined that the bright subject is present, a period during which the second intermediate voltage is applied is longer than that in the case where it is determined that the bright subject is not present. The solid-state imaging device according to claim 4, wherein at least one of control and control for reducing the voltage difference compared to a case where it is determined that the bright subject does not exist are performed.
There are a plurality of the pixel circuits,
The solid-state imaging device according to claim 5, wherein the control unit determines whether or not the bright subject exists based on an average value of pixel signals output from each pixel circuit.
There are a plurality of the pixel circuits,
The solid-state imaging device according to claim 5, wherein the control unit determines whether or not the bright subject exists based on a histogram of pixel signals output from each pixel circuit.