WO2012072646A1 - A field effect transistor - Google Patents

A field effect transistor Download PDF

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WO2012072646A1
WO2012072646A1 PCT/EP2011/071316 EP2011071316W WO2012072646A1 WO 2012072646 A1 WO2012072646 A1 WO 2012072646A1 EP 2011071316 W EP2011071316 W EP 2011071316W WO 2012072646 A1 WO2012072646 A1 WO 2012072646A1
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layer
doped layer
doped
delta region
transistor according
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PCT/EP2011/071316
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French (fr)
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Richard John Lang
Christopher Maxwell Snowden
Richard Stuart Balmer
Paul Gideon Huggett
James Pilkington
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Diamond Microwave Devices Limited
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H01L21/042—Changing their shape, e.g. forming recesses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1602—Diamond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66045—Field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/7725—Field effect transistors with delta-doped channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

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  • Junction Field-Effect Transistors (AREA)

Abstract

A diamond semiconductor field effect transistor having source, drain and gate contacts, comprising: a substantially intrinsic layer, and a doped layer adjacent the intrinsic buffer layer, the transistor having a delta region and a non-delta region, the delta region being provided between the gate contact and the substrate, and the non-delta region being provided between at least one of the source and drain contacts and the substrate, and methods of manufacturing such a transistor.

Description

A FIELD EFFECT TRANSISTOR
The present invention relates to field effect transistors, and more particularly to diamond semiconductor field effect transistors.
BACKGROUND
Due to physical limitations, silicon, indium phosphide and gallium arsenide devices cannot achieve power levels higher than a few hundred watts, depending on the frequency to be amplified. A wider bandgap material, such as diamond, offers the potential of higher power output per unit gate length at microwave frequencies. This is because a larger bias voltage, and hence the voltage amplitude of the microwave signal, can be supported across the transistor channel region over which the current is modulated. In effect this exploits the higher breakdown electric field of a wide bandgap semiconductor. As well as its high bandgap (5.47 eV), further attractions of the diamond system include high bulk thermal conductivity and high intrinsic carrier mobility.
Dopants in wide bandgap semiconductors tend to have higher ionisation energies than those of narrow bandgap semiconductors, resulting in low activation at room temperature. Common dopants in chemical vapour deposition (CVD) diamond and their ionization energies are: boron (0.37 eV) for p-type doping; and nitrogen (1 .7 eV) and phosphorus (0.6 eV) for n-type doping. As boron is readily incorporated into CVD diamond as a dopant impurity, much activity has focussed upon the production of unipolar devices using boron. However, at conventional doping levels, boron acceptors are only weakly activated at room temperature, due to their ionization energy. To mitigate this, the boron solid concentration must be increased to very high levels, where the conduction mechanism changes first from band type conduction to hopping, then at higher doping levels (>1019 cm"3) eventually becoming metallic-like as the acceptor band begins to overlap the valence band maximum and the ionization energy approaches zero. This metallic-like conduction condition results in much lower bulk resistivity. However, the high mobility of intrinsic diamond (up to 3800 cm2V"V1 for holes) is very severely reduced when the material is doped, due to ionized impurity scattering. The metallic-like conduction condition requires dopant levels (NA) greater than 1020 cm"3, at which the hole mobility would be in the region of 1 -3 cm2V"V1, severely limiting the maximum potential ohmic current transport between the source and drain contacts of a FET with a channel formed of a bulk highly boron doped layer.
Because of these design limitations in boron doped diamond, conventional device designs cannot be expected to yield high performance RF devices. Instead a more creative approach to device design is required in order to utilise the superior properties of intrinsic diamond. In particular it is desirable to achieve some degree of spatial separation between ionized acceptors and holes.
A known epitaxial arrangement that seeks to achieve such separation comprises a 'delta' doping layer having an adjacent intrinsic bulk layer. The delta layer is a very thin highly (boron) doped region that acts as a source of carriers (holes). The delta layer forms a quantum well (which is approximately a V-shape, having one vertical side, adjacent the intrinsic layer). The spatial extent of the ground state wavefunction of the quantum well in the delta layer significantly overlaps the intrinsic layer (typically the ground state wavefunction is wider than the thickness of the delta layer). Accordingly, carriers migrate from the low mobility delta doped layer into the high mobility intrinsic layer. Consequently, conduction occurs in both the delta layer and in the intrinsic layer. Conduction in the intrinsic layer will typically be the dominant conduction mechanism, with quantum mechanical calculations predicting that for a delta layer thickness of 2 nm, 95% of the hole transport may take place within the delta layer, in the intrinsic layer. In such an epitaxial arrangement, greater migration of carriers into the intrinsic layer will occur with a thinner delta layer, having the same sheet charge density. Accordingly, the channel current will be greater for a narrower delta layer thickness (with the same sheet charge density), in contrast to a bulk doped layer where the channel current increases with layer width.
The delta doping layer has a sheet charge density in the region of 1013 cm"2 to enable full channel pinch-off by the gate. Accordingly, the highly doped delta doping layer has a thickness of less than 10nm, and advantageously is a monolayer. Figure 1 illustrates a FET 100 having a delta doping layer 106 and adjacent intrinsic layer 1 18 formed on a substrate 102. The delta doping layer 106 is common beneath the source, gate and drain contacts of the FET 1 12, 120 and 1 14. Such a device is disclosed in WO20061 17621 .
However, disadvantageously, such a device has high parasitic 'access resistance', caused by the following series resistances: (i) the sheet contact resistance of the junctions between the ohmic source and drain contacts and the delta doping layer of the semiconductor, and (ii) the semiconductor sheet resistance experienced by the current flowing through the access regions between the ohmic contacts and the channel beneath the gate contact. Such parasitic resistances degrade high power, high frequency performance of a microwave FET. The specific contact resistance of the source and drain contacts is a function of the doping level of the delta doping layer, which governs the metal-semiconductor barrier height and therefore the hole tunnelling through the barrier. However, the doping level of the delta doping layer is limited by epitaxial growth limitations. Potential for reducing the separation between the gate contact and the ohmic source and drain contacts, in order to reduce the parasitic resistance due to the sheet resistance is also limited by the physical limits of lithography and the aspect ratio of the contacts. A further limitation is the breakdown voltage between the source and drain contacts, which would limit the maximum drain bias.
So, design limitations impose conflicting pulls upon the design parameters for thickness and dopant level of the delta doping layer, in turn limiting the possible performance of a device such that is illustrated in Figure 1 . In the case of typical non-delta layer FETs (i.e. a relatively thick doped layer, having conduction entirely within the channel), it is known to determine the maximum channel current with a recess that is etched into the doped layer beneath the gate contact. This recess limits the maximum channel current, since in the case that the Λ
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conduction channel is formed in a bulk doped layer, the maximum channel current reduces with reducing channel width.
BRIEF SUMMARY OF THE DISCLOSURE
A first aspect of the present invention provides a diamond semiconductor field effect transistor having source, drain and gate contacts, comprising: a substantially intrinsic layer, a doped layer adjacent the intrinsic layer, and a gate dielectric layer comprising dielectric material, the transistor having a delta region and a non-delta region, the delta region being provided between the gate contact and the substrate, and the non-delta region being provided between at least one of the source and drain contacts and the substrate, such that in the delta region, the doped layer is disposed between the gate dielectric layer and the substantially intrinsic layer. A second aspect of the present invention provides a method of manufacturing a diamond semiconductor field effect transistor having source, drain and gate contacts, comprising: a substantially intrinsic layer, a doped layer adjacent the intrinsic layer, and a gate dielectric layer comprising dielectric material, the transistor having a delta region and a non-delta region, the delta region being provided between the gate contact and the substrate, and the non-delta region being provided between at least one of the source and drain contacts and the substrate, such that in the delta region, the doped layer is disposed between the gate dielectric layer and the substantially intrinsic layer, the method comprising epitaxially growing the doped layer, masking the doped layer with a lithographic mask, and selectively etching the doped layer to provide the delta region.
A third aspect of the present invention provides a method of manufacturing a diamond semiconductor field effect transistor having source, drain and gate contacts, comprising: a substantially intrinsic layer, a composite doped layer having a first doped layer adjacent the intrinsic layer and a second doped layer adjacent the first doped layer, and a gate dielectric layer comprising dielectric material, the transistor having a delta region and a non-delta region, the delta region being provided between the gate contact and the substrate, and the non-delta region being provided between at least one of the source and drain contacts and the substrate, such that in the delta region, the doped layer is disposed between the gate dielectric layer and the substantially intrinsic layer, the method comprising epitaxially growing the first doped layer, masking the first doped layer with a lithographic mask, selectively epitaxially growing the second doped layer to provide the non-delta region, and removing the lithographic mask.
Advantageously, the sheet resistance of the non-delta regions (in particular the source and drain access regions between the source and drain contacts and the gated delta region) is lower than would be the case were they formed as a delta layer identical to that of the gated delta region. Accordingly, this provides a reduced parasitic access resistance between the source and drain contacts and the gated channel beneath the gate contact.
Advantageously, the parasitic sheet contact resistance of the junctions between the source and drain contacts and the doped layer of the non-delta regions is lower than the parasitic sheet contact resistance would be if the source and drain contacts were made onto a delta layer identical to that of the gated delta region.
The delta region may comprise a region of the doped layer that is of such a thickness that it forms a quantum well. The quantum well may be approximately V- shaped. The quantum well may have a steep (almost vertical) side adjacent the intrinsic layer. The spatial extent of the ground state wavefunction of the quantum well in the delta layer may significantly overlap the intrinsic layer. The ground state wavefunction may be wider than the thickness of the delta layer. Accordingly, and advantageously, carriers may migrate from the low mobility delta doped layer into the high mobility intrinsic layer.
The non-delta region may be provided within at least part of one of a source access region and a drain access region. The non-delta region may be provided between both the source and drain contacts and the substrate. The intrinsic layer may be provided between the substrate and the doped layer.
The doped layer may have a dopant concentration of at least 1 x 1020 cm"3, preferably at least 3 x 1020 cm"3, preferably at least 1 x 1021 cm"3, and preferably at ^
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least 2 x 1021 cm"3. The doped layer may have a thickness in the delta region of 5 nm or less, preferably 3 nm or less, preferably 2 nm or less, preferably 1 nm or less, preferably at least 0.1 nm, and preferably at least 0.2 nm. The doped layer may have a thickness of at least 5 nm in the non-delta region, preferably at least than 10 nm, preferably 30 nm or less, and preferably 20 nm or less. The dopant concentration of the doped layer may be such that in all or part of the doped layer, the dopant concentration may result in substantially full activation of acceptors (or donors) at room temperature. The upper limit of the sheet charge of the doped layer within the delta region may such that the electrical channel formed beneath the gate contact (between the source and drain contacts) may be pinched off by electrical control of the gate contact.
The doped layer may have a substantially homogeneous dopant concentration. It will be appreciated by those skilled in the art that practical considerations of the manufacturing process (e.g. dopant species diffusion during and following epitaxial growth) typically limit the homogeneity that can be achieved.
The doped layer may have an inhomogeneous dopant concentration. The doped layer may have a minimum dopant concentration adjacent the intrinsic layer. The dopant concentration adjacent the intrinsic layer may be in the range of 1 x 1020 cm"3 to 5 x 1020 cm"3. The doped layer may have a maximum dopant concentration of at least 1 x 1021 cm"3. The maximum dopant concentration may be at the surface of the doped layer opposite to the surface that is adjacent to the intrinsic layer. The doped layer may have a dopant concentration that increases monotonically away from the intrinsic layer.
The doped layer may be a composite doped layer comprising a first and a second doped layer, the first doped layer being adjacent the intrinsic layer. The second doped layer may have a higher dopant concentration than the first doped layer. Alternatively, the first and second doped layers may be substantially equally doped.
The first doped layer may have a dopant concentration of at least 1 x 1020 cm"3, preferably at least 3 x 1020 cm"3, and preferably 5 x 1020 cm"3 or less. The second doped layer may have a dopant concentration of at least 1 x 1021 cm"3, and preferably 3 x 1021 cm"3. The first doped layer may have a thickness of 5 nm or less. The second doped layer may have a thickness of at least 5 nm, and preferably at least 8 nm. Advantageously the first and second doped layer may be substantially equally doped in the case that two separate epitaxial growth stages are used to produce a doped layer of a homogeneous dopant concentration.
Advantageously, the provision of a composite doped layer enables more accurate fabrication of the delta layer, which is formed as a recess within the thicker non-delta region of the doped layer. Advantageously, in the case of a composite doped layer that is grown in a single epitaxial growth stage, and in which the delta region is formed by etching, the composite structure facilitates accurate control of the etch depth, in etching the delta region. Advantageously, in the case that the layers of the composite doped layer are formed in separate epitaxial growth steps, with an intervening lithographic masking step, the composite doped layer avoids the incidence of surface or epitaxial damage, which is typically associated with etching processes.
The doped layer may be a composite doped layer comprising a first, a second and a third doped layer, the first doped layer being adjacent the intrinsic layer, and the second doped layer being intermediate the first and third doped layers. The first and third doped layers may have higher dopant concentrations than the second doped layer. The second doped layer may be an etch stop layer. The third doped layer may have a higher dopant concentration than the first doped layer. Advantageously, the provision of a composite layer having an intermediary etch stop layer enables more accurate fabrication of the delta layer.
The doped layer may be doped with boron. Alternatively, the doped layer may be doped with nitrogen. In a further alternative, the doped layer may be doped with phosphorus.
The non-delta region may comprise a metal boride layer adjacent the doped layer. The metal boride may comprise a transition metal and boron. The metal boride may comprise a refractory metal and boron. The refractory metal may be selected from ο
the group consisting of titanium, zirconium, tantalum, molybdenum, tungsten, hafnium and niobium. The metal boride may be selected from the group consisting of titanium boride and zirconium boride. The metal boride layer may have a thickness of at least 1 nm, and preferably at least 2 nm and preferably at least 5 nm, 150 nm or less, preferably 50 nm or less, and preferably 10 nm or less. The metal boride layer may have a sheet resistance of less than 300 Ω/sqr, preferably of less than 200 Ω/sqr, and may be between 100 and 200 Ω/sqr. Patterning of the metal boride layer and the delta region may be self-aligned. Alternatively, patterning of the metal boride layer and the delta region may be by fabrication steps that are not self- aligned. A passivating layer may be provided between the metal boride layer and the doped layer.
A doped shielding layer may be provided between the substrate and the intrinsic layer.
A further intrinsic layer may be provided on at least the doped layer where it forms a delta layer within the delta region. The further intrinsic layer may be less than 10 nm thick, and preferably has a thickness of 1 -5 nm. The transistor may comprise a substrate, and wherein the substantially intrinsic layer is a substantially intrinsic buffer layer provided between the substrate and the doped layer.
The substantially intrinsic layer may be a substantially intrinsic substrate.
The gate dielectric layer may be any suitable dielectric material. An example of a suitable dielectric material is aluminium oxide. Where the gate dielectric layer is aluminium oxide, the aluminium oxide may be aluminium oxide deposited by atomic layer deposition (ALD).
The method may further comprise monitoring a parameter of the etching process associated with the depth of the etch. The selective etching may comprise a first etching step and a second etching step, the first etching step etching at a higher rate (faster) than the second etching step. Λ
The method may further comprise epitaxially growing a further intrinsic layer onto at least the doped layer within the delta region. BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention are further described hereinafter with reference to the accompanying drawings, in which:
• Figure 1 schematically illustrates a known FET;
• Figure 2A schematically illustrates a FET according to the present invention, having a homogeneously doped layer;
• Figure 2B schematically illustrates a further FET according to the present invention, having an inhomogeneously doped layer;
• Figure 3 schematically illustrates a further FET according to the present invention, having first and second doped layers;
• Figure 4 schematically illustrates a further FET according to the present invention, having a doped layer and a metal boride layer;
• Figure 5 schematically illustrates a further FET according to the present invention, having first and second doped layers and a metal boride layer;
• Figure 6 schematically illustrates a further FET according to the present invention, having first, second and third doped layers; and
• Figure 7 schematically illustrates a further FET according to the present invention, having first, second and third doped layers and a metal boride layer.
DETAILED DESCRIPTION
Referring now to Figure 2A of the drawings. Figure 2A shows a diamond semiconductor field effect transistor (FET) 200 according to an embodiment of the present invention.
The FET 200 comprises a substrate 202, an intrinsic diamond buffer layer 204, a substantially homogeneously doped layer 206 having non-delta regions 208 and a delta region 210, ohmic source contact 212, source access region 213, ohmic drain Λ n
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contact 214, drain access region 215, silicon nitride (silicon oxide or silicon oxy- nitride) etch mask layer 216, gate dielectric layer 218, and gate contact 220.
The substrate 202 is a diamond substrate, which may be formed by known means, such as high pressure high temperature manufacturing or growth by chemical vapour deposition (CVD). The intrinsic buffer layer 204 is grown onto the substrate by CVD, and advantageously has low levels of impurities, to provide high charge carrier mobility. The intrinsic layer 204 has a thickness of 0.1 -0.2 nm. The doped CVD diamond layer 206 is grown with a high dopant concentration, e.g. at least 3 x 1020 cm"3, to a thickness of 20 nm. Ohmic contacts 212 and 214 are formed on the doped layer 206 in the known way, for example from tungsten silicide or titanium-platinum-gold.
The delta layer 222 of the doped layer 206 is formed by an etching process, in which the doped layer is partially etched through the silicon nitride etch mask layer 216 to form a recessed delta thickness layer 222 and leaving the non-delta regions 208 unetched. The doped layer 206 is selectively etched through the mask to produce the delta region 210. The doped layer 206 is etched by known methods, such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP). The delta layer 222 in the delta region 210 has a thickness of between 0.5 and 2 nm, providing a sheet charge density of 1 -3x1013 cm"3 in the delta layer within the delta region. A high degree of control is required to achieve this thickness, and the etching of the doped layer 206 is advantageously conducted using an etch-to-current technique, in which the etch depth is determined in correspondence with a current between the source and drain contacts 212 and 214. Care should also be taken to avoid or minimize any damage by the etching of the crystal lattice of the underlying material, and to minimize the surface roughness of the underlying material. The aluminium oxide gate dielectric 218 of 10-20 nm is deposited by atomic layer deposition (ALD), covering the delta layer 222 of the delta region 210 and covering the adjacent etch mask layer 216. A gate contact 220 is formed over the delta region 210, for example from titanium-gold. Λ Λ
1 1
The doped delta layer 222 of the delta region 210 provides a source of charge carriers, which partially migrate from the delta layer into the adjacent intrinsic buffer layer 204. In the case of a 1 nm thick delta layer 222, having a boron dopant level of 3 x 1020 cm"3, it is estimated that 15 to 20% of holes in the delta region will migrate out of the confining potential well of the delta layer and into the intrinsic buffer layer 204. Accordingly, when a bias is provided between the source and drain contacts 212 and 214, a conduction channel is formed beneath the gate contact 220 by a current of the carriers through both the delta layer 222 and the intrinsic layer 204. Due to the higher mobility of the charge carriers in the intrinsic buffer layer 204 than in the delta layer 222, a significant proportion of the carrier conduction will occur in the intrinsic buffer layer.
A quantum well forms within the delta layer 222, and carriers in the ground state partially spatially overlap the intrinsic layer 204. Consequently, at the boundary between the intrinsic buffer layer 204 and the delta layer 222, beneath the gate contact, where the FET's modulatable channel is formed within the delta region 210, the narrow delta doped layer leads to greater migration of charge carriers (holes) into the intrinsic buffer layer than at the boundary of the intrinsic buffer layer and the thicker non-delta layer 208. Accordingly, the carrier mobility in the channel (formed beneath the gate contact 220) is higher than outside the channel.
Away from the gate contact 220, the unetched regions of the doped layer 206 provide thicker non-delta regions 208, including within the source and drain access regions 213 and 215. The carrier (hole or electron) mobility within the non-delta regions 208 is lower than that of the channel beneath the gate contact 220. However, advantageously the non-delta regions 208 are thicker than the delta layer 222 of the doped layer 206 within the delta region 210, such that the sheet resistance of the non-delta regions (in particular the source and drain access regions 213 and 215) is lower than that of the delta region. This reduces the corresponding parasitic resistance between the ohmic source and drain contacts 212 and 214 and the channel beneath the gate contact 220, relative to an FET 100 with only a common delta doping layer, such as is shown in Figure 1 . Λ n
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Further, the junctions between the ohmic source and drain contacts 212 and 214 and the non-delta regions 208 of the doped layer 206 have a lower parasitic sheet contact resistance than the corresponding junctions would if formed with the delta doping layer 106 in the FET 100 of Figure 1 . Advantageously, this further reduces the parasitic access resistance of the FET 200 relative to the FET 100 of Figure 1 .
Having a dopant concentration of 3 x 1020 cm"3 and a thickness of 20 nm, may provide a sheet resistance of 5000 Ω/sqr, in the non-delta regions 208, which would equate to an access resistance of 5 Q.mm for a 1 pm length of access region. Further, a non-delta region 208 of 8 nm thickness and 2.4 x 1021 cm"3 doping would have a sheet resistance of approximately 1500 Ω/sqr and a sheet contact resistance of approximately 1 x 10"6 Q.cm2, resulting in a combined sheet access resistance of 1 .5 Q.mm between the source or drain contact, through a 1 pm length of access region to the channel.
Accordingly, a device according to an embodiment of the present invention may provide a microwave FET with higher power and higher frequency performance than known devices. Referring now to Figure 2B of the drawings. Figure 2B shows a diamond semiconductor field effect transistor (FET) 200' according to a further embodiment of the present invention. For reasons of clarity, features of the FET 200' of Figure 2B that are like features of the FET 200 of Figure 2A have been given like numbers, distinguished by an additional apostrophe. For example, the delta layer 222' of Figure 2B corresponds with the delta layer 222 of Figure 2A.
The FET 200' of Figure 2B differs from the FET 200 of Figure 2A by the doped CVD diamond layer 206' of FET 200' being inhomogeneously doped. Rather the dopant concentration of the doped layer 206' increases monotonically away from the intrinsic layer 204'. In particular, the dopant concentration of the doped layer 206' is lowest adjacent the intrinsic layer 204'. Accordingly, the dopant concentration of the delta layer 222' of the doped layer 206' within the delta region 210' is lower than the dopant concentration of portions of the doped layer further from the intrinsic layer Λ„
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204'. The dopant concentration of the doped layer 206' is 3x1020 cm"3 adjacent the intrinsic layer 204' and 3x1021 cm"3 furthest from the intrinsic layer.
Referring now to Figure 3 of the drawings. Figure 3 shows a diamond semiconductor field effect transistor (FET) 300 according to a yet further embodiment of the present invention. For reasons of clarity, features of the FET 300 of Figure 3 that are like features of the FET 200 of Figure 2A have been given like numbers, incremented by 100. For example, the substrate 302 of Figure 3 corresponds with the substrate 202 of Figure 2A.
The FET 300 of Figure 3 differs from the FET 200 of Figure 2A by the doped CVD diamond layer of FET 300 being composite, comprising a first doped layer 306A and a second doped layer 306B. Accordingly, the non-delta region 308 is also composite, comprising portions of the first and second doped layers 306A and 306B. In contrast, the delta layer 222 within the delta region 310 comprises only a portion of the first doped layer 306A.
The lower, first doped layer 306A is a thinner and less highly doped layer than the upper, second doped layer 306B, which is a thicker and more highly doped layer. For example, the first doped layer 306A has dopant concentration of 3 x 1020 cm"3 and a thickness of 3 to 4 nm, and the second doped layer 306B has dopant concentration of 3 x 1021 cm"3 and a thickness of 10 to 20 nm.
The method of manufacture of the FET 300 of Figure 3 may be similar to that of FET 200 of Figure 2A. A silicon nitride etch mask layer 316 is formed on the second doped layer 306B, covering the unetched non-delta regions 308. The second doped layer 306B is selectively etched through the mask. In the example of Figure 3, the second doped layer 306B is completely etched through, and the first doped layer 306A is partially etched away, to produce a recess in the composite doped layer with a delta layer 322 having a thickness of approximately 0.5 nm.
A second doped layer of dopant concentration 3 x 1021 cm"3 and a thickness of 20 nm, provides a sheet resistance of 500 Ω/sqr, in the non-delta regions, which Λ Λ
14
would contribute 0.5 Q.mm to the access resistance of the FET for a 1 pm length of access region.
During etching, the etch rate is monitored (e.g. by an etch and measure process) to detect when the second doped layer has been etched through. Advantageously, by detecting when the second doped layer has been etched through, the thickness of the delta layer at the bottom of the etch pit can be determined more accurately than with a single doped layer of uniform dopant concentration. Further, the second doped layer may be etched with a more rapid etch rate process, and once it has been determined that the second doped layer has been etched through, the etch conditions may be changed to etch the first doped layer with a slower etch rate process. Advantageously, by detecting when the second doped layer has been etched through, and switching to a slower etch rate process, the thickness of the delta layer at the bottom of the etch pit can be determined more accurately than with a rate of single etch. Accordingly, such a design may be etched with increased accuracy, leading to an increased manufacturing yield.
In contrast to the FET 300 illustrated in Figure 3, the second doped layer 306B may alternatively be only partially etched through, or in a further alternative the etch may be stopped at the boundary between the first and second doped layers 306A and 306B.
In an alternative method of manufacturing the FET 300, the epitaxial growth of the doped layers 306A and 306B may comprise two epitaxial growth stages separated by other processing steps. In a first epitaxial growth stage the first doped layer is grown. Then the surface is patterned with a lithographic shadow mask, before the second doped layer is selectively epitaxially grown onto the exposed areas of the first doped layer in a second growth stage. The shadow mask covers the delta region 310, such that the second doped layer is only grown in the non-delta region 308. The shadow mask may, for example, be silicon nitride, or aluminium oxide and silicon nitride. In the latter case, following the second epitaxial growth stage, the silicon nitride may be removed, leaving the aluminium oxide for use as the gate dielectric, ready to receive deposition of the gate contact. Λ r
15
The two stage epitaxial growth method may be applied both to the growth of doped layers in which the first and second doped layers have different dopant concentrations (e.g. the first doped layer has a higher dopant concentration than the second doped layer), and to the growth of first and second doped layers having substantially the same dopant concentrations. Accordingly, this method may be also employed in producing the FET 200 of Figure 2A.
Referring now to Figure 4 of the drawings. Figure 4 shows a diamond semiconductor field effect transistor (FET) 400 according to a yet further embodiment of the present invention. For reasons of clarity, features of the FET 400 of Figure 4 that are like features of the FET 200 of Figure 2A have been given like numbers, incremented by 200. For example, the substrate 402 of Figure 4 corresponds with the substrate 202 of Figure 2A.
The FET 400 of Figure 4 differs from the FET 200 of Figure 2A by the provision of a metal boride layer (titanium boride) 424 on the non-delta regions 408 of the doped layer 406. Such a metal boride layer 424 provides a low access resistance between each of the source and drain contacts 412 and 414 and the channel beneath the gate contact 420 in the delta region 410. The thickness of the metal boride layer 424 is 5-10 nm, and the sheet resistance is 100-200 Ω/sqr.
The recess in the doped layer 406 to define the delta region 410 is aligned with an aperture (e.g. second recess) in the metal boride layer 424. Advantageously the recess and aperture are self-aligned, i.e. being formed by one or more fabrication steps that are aligned by a common feature, e.g. etching through a common etch mask 416. Alternatively, the recess and aperture may not be self-aligned, for example, being formed by etching through different etch masks. Referring now to Figure 5 of the drawings. Figure 5 shows a diamond semiconductor field effect transistor (FET) 500 according to a yet further embodiment of the present invention. For reasons of clarity, features of the FET 500 of Figure 5 that are like features of the FET 200 of Figure 2A have been given like numbers, incremented by 300. For example, the substrate 502 of Figure 5 corresponds with the substrate 202 of Figure 2A.
In common with the FET 300 of Figure 3, the FET 500 of Figure 5 comprises a composite doped layer 506A and 506B. The lower, first doped layer 506A has a thickness of 5nm or less and a dopant concentration 5 x 1020 cm"3, and the upper, second doped layer 506B has a thickness of 5nm and a dopant concentration of 2 x 1021 cm"3 In common with the FET 400 of Figure 4, the FET 500 of Figure 5 comprises a metal boride layer 524. The thickness of the metal boride layer 524 is 5-10 nm, and the sheet resistance is 100-200 Ω/sqr.
Referring now to Figure 6 of the drawings. Figure 6 shows a diamond semiconductor field effect transistor (FET) 600 according to a yet further embodiment of the present invention. For reasons of clarity, features of the FET 500 of Figure 5 that are like features of the FET 200 of Figure 2A have been given like numbers, incremented by 400. For example, the substrate 602 of Figure 6 corresponds with the substrate 202 of Figure 2A.
Like the FET 300 of Figure 3, the FET 600 of Figure 6 comprises a composite doped layer. However, in contrast to the composite doped layer of the FET 300 of Figure 3, which has two doped layers 306A and 306B, the composite doped layer of the FET 600 of Figure 6 comprises three doped layer 606A, 606B and 606C. The lower, first doped layer 606A has a thickness of 1 nm or less and a dopant concentration 5 x 1020 cm"3, the intermediary, second doped layer 606B has a thickness of 1 -2 nm and a dopant concentration 5 x 1019 cm"3, and the upper, third doped layer 606C has a thickness of 3 nm and a dopant concentration of 2 x 1021 cm"3. The intermediary doped layer 606B has a low dopant concentration and provides an etch stop layer, which simplifies the fabrication of the recess that defines the delta region 610. In fabricating the recess that defines the delta region 610, a first rapid etch is stopped within the intermediary doped layer 606B, before a second slower Λ
17
etch is used to etch down to define the delta layer 622 with greater precision than would be possible using the rapid etch.
Referring now to Figure 7 of the drawings. Figure 7 shows a diamond semiconductor field effect transistor (FET) 700 according to a yet further embodiment of the present invention. For reasons of clarity, features of the FET 700 of Figure 7 that are like features of the FET 200 of Figure 2A have been given like numbers, incremented by 500. For example, the substrate 702 of Figure 7 corresponds with the substrate 202 of Figure 2A.
In common with the FET 600 of Figure 6, the FET 700 of Figure 7 comprises a composite doped layer 706A, 706B and 706C. The lower, first doped layer 706A has a thickness of 1 nm or less and a dopant concentration 5 x 1020 cm"3, the intermediary, second doped layer 706B has a thickness of 1 -2 nm and a dopant concentration 5 x 1019 cm"3, and the upper, third doped layer 706C has a thickness of 3nm and a dopant concentration of 2 x 1021 cm"3.
The intermediary doped layer 706B has a low dopant concentration and provides an etch stop layer, which simplifies the fabrication of the recess that defines the delta region 710. In fabricating the recess that defines the delta region 710, the presence of the intermediary doped etch stop layer 706B enables an etch to be stopped with precision within that layer. In operation, the narrow region of the intermediary layer 706B that remains within the delta region 710 is easily depleted by electrically biasing the gate contact.
In common with the FET 400 of Figure 4, the FET 700 of Figure 7 comprises a metal boride layer 724. The thickness of the metal boride layer 724 is 5-10 nm, and the sheet resistance is 100-200 Ω/sqr. Although in the FETs of Figures 3 to 7 the doped CVD diamond layers and the sublayers of the composite CVD diamond layers have been illustrated in the case that they have substantially homogeneous dopant concentrations, it will be appreciated by the skilled person that one or more of these layers or sub-layers may be inhomogeneously doped. Optionally, a thin (1 -5 nm) top layer of intrinsic CVD diamond may be provided above the delta region to offset the upper surface of the diamond semiconductor from the doped layer, and thus avoid any unwanted depletion arising due to oxygen terminated surface dangling bonds.
Optionally, a doped shielding layer may be provided between substrate and intrinsic buffer layer. Performance of the FETs according to the present invention may be further enhanced by offsetting the gate towards the source, to allow for extension of the gate-drain depletion region, and thus operation at higher drain bias. Further, performance may be improved by use of a T gate to reduce the lateral resistance of ultra-short gate profiles, and field plate technology to reduce the peak electric field at the gate edge to increase the maximum drain bias.
The figures provided herein are schematic and not to scale.
Throughout the description and claims of this specification, the words "comprise" and "contain" and variations of them mean "including but not limited to", and they are not intended to (and do not) exclude other moieties, additives, components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.
Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The invention is not restricted to the Λ n
19
details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Claims

1 . A diamond semiconductor field effect transistor having source, drain and gate contacts, comprising:
a substantially intrinsic layer,
a doped layer adjacent the intrinsic layer, and
a gate dielectric layer comprising dielectric material,
the transistor having a delta region and a non-delta region, the delta region being provided between the gate contact and the substrate, and
the non-delta region being provided between at least one of the source and drain contacts and the substrate, such that in the delta region, the doped layer is disposed between the gate dielectric layer and the substantially intrinsic layer.
2. A transistor according to claim 1 , wherein the non-delta region is provided within at least part of one of a source access region and a drain access region.
3. A transistor according to claim 1 or 2, wherein the non-delta region is provided between both the source and drain contacts and the substrate.
4. A transistor according to claim 1 , 2 or 3, wherein the intrinsic layer is provided between the substrate and the doped layer.
5. A transistor according to any preceding claim, wherein the doped layer has a dopant concentration of at least 1 x 1021 cm"3.
6. A transistor according to any preceding claim, wherein the doped layer has a thickness in the delta region 5nm or less.
7. A transistor according to claim 6, wherein the doped layer has a thickness of at least 5 nm in the non-delta region.
8. A transistor according to any preceding claim, wherein the doped layer has a substantially homogeneous dopant concentration.
9. A transistor according to any of claims 1 to 7, wherein the doped layer has an inhomogeneous dopant concentration.
10. A transistor according to claim 9, wherein the doped layer has a minimum dopant concentration adjacent the intrinsic layer.
1 1 . A transistor according to claim 10 or 1 1 , wherein the dopant concentration adjacent the intrinsic layer is in the range of 1 x 1020 cm"3 to 5 x 1020 cm"3.
12. A transistor according to claim 10, 1 1 or 12, wherein the doped layer has a maximum dopant concentration of at least 1 x 1021 cm"3.
13. A transistor according to any preceding claim, wherein the doped layer is a composite doped layer comprising a first and a second doped layer, the first doped layer being adjacent the intrinsic layer.
14. A transistor according to claim 13, wherein the second doped layer has a higher dopant concentration than the first doped layer.
15. A transistor according to claim 14, wherein the first doped layer has a dopant concentration in the range of 1 x 1020 cm"3 to 5 x 1020 cm"3, and the second doped layer has a dopant concentration of at least 1 x 1021 cm"3.
16. A transistor according to one of claim 13, 14 or 15, wherein the first doped layer has a thickness of 5 nm or less, and the second doped layer has a thickness of at least 5 nm.
17. A transistor according to any of claims 1 to 12, wherein the doped layer is a composite doped layer comprising a first, a second and a third doped layer, the first doped layer being adjacent the intrinsic layer, and the second doped layer being intermediate the first and third doped layers.
18. A transistor according to claim 17, wherein the first and third doped layers have higher dopant concentrations than the second doped layer.
19. A transistor according to claim 17 or 18, wherein the second doped layer is an etch stop layer.
20. A transistor according to claims 17, 18 or 19, wherein the third doped layer has a higher dopant concentration than the first doped layer.
21 . A transistor according to any preceding claim, wherein the doped layer is doped with boron.
22. A transistor according to any preceding claim, wherein the non-delta region comprises a metal boride layer adjacent the doped layer.
23. A transistor according to any preceding claim, wherein a doped shielding layer is provided between the substrate and the intrinsic layer.
24. A transistor according to any preceding claim, wherein a further intrinsic layer is provided on at least the doped layer within the delta region.
25. A transistor according to any preceding claim, wherein the transistor comprises a substrate, and wherein the substantially intrinsic layer is a substantially intrinsic buffer layer provided between the substrate and the doped layer.
26. A transistor according to any of claims 1 to 24, wherein the substantially intrinsic layer is a substantially intrinsic substrate.
27. A transistor according to any preceding claim, wherein the gate dielectric layer comprises aluminium oxide.
28. A method of manufacturing a diamond semiconductor field effect transistor having source, drain and gate contacts, comprising:
a substantially intrinsic layer, a doped layer adjacent the intrinsic layer, and
a gate dielectric layer comprising dielectric material,
the transistor having a delta region and a non-delta region,
the delta region being provided between the gate contact and the substrate, and the non-delta region being provided between at least one of the source and drain contacts and the substrate, such that in the delta region, the doped layer is disposed between the gate dielectric layer and the substantially intrinsic layer,
the method comprising
epitaxially growing the doped layer,
masking the doped layer with a lithographic mask, and
selectively etching the doped layer to provide the delta region.
29. A method according to claim 28, wherein the method further comprises monitoring a parameter of the etching process associated with the depth of the etch.
30. A method according to claim 28 or 29, wherein the selective etching comprises a first etching step and a second etching step, the first etching step etching at a higher rate than the second etching step.
31 . A method according to claim 28, 29 or 30, wherein the doped layer is a composite doped layer comprising a first doped layer and second doped layer, and the second doped layer has a dopant concentration higher than the first doped layer.
32. A method according to one of claims 28 to 31 , wherein a further intrinsic layer is epitaxially grown onto at least the doped layer within the delta region.
33. A method of manufacturing a diamond semiconductor field effect transistor having source, drain and gate contacts, comprising:
a substantially intrinsic layer,
a composite doped layer having a first doped layer adjacent the intrinsic layer and a second doped layer adjacent the first doped layer, and
a gate dielectric layer comprising dielectric material,
the transistor having a delta region and a non-delta region,
the delta region being provided between the gate contact and the substrate, and the non-delta region being provided between at least one of the source and drain contacts and the substrate, such that in the delta region, the doped layer is disposed between the gate dielectric layer and the substantially intrinsic layer,
the method comprising
epitaxially growing the first doped layer,
masking the first doped layer with a lithographic mask,
selectively epitaxially growing the second doped layer to provide the non-delta region,
removing the lithographic mask.
34. A method according to claim 33, wherein the second doped layer is more highly doped than the first doped layer.
35. A method according to claim 33, wherein the first and second doped layers are substantially equally doped.
36. A method according to claim 33, 34 or 35, wherein a further intrinsic layer is epitaxially grown onto at least the first doped layer within the delta region.
37. A diamond semiconductor field effect transistor substantially as hereinbefore described with reference to the accompanying description and any one of Figures 2A to 7.
38. A method of manufacturing a diamond semiconductor field effect transistor substantially as hereinbefore described with reference to the accompanying description and any one of Figures 2A to 7.
PCT/EP2011/071316 2010-12-01 2011-11-29 A field effect transistor WO2012072646A1 (en)

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