WO2012065432A1 - Procédé de mise en oeuvre d'une horloge dans un système multicoeur et système multicoeur - Google Patents

Procédé de mise en oeuvre d'une horloge dans un système multicoeur et système multicoeur Download PDF

Info

Publication number
WO2012065432A1
WO2012065432A1 PCT/CN2011/075490 CN2011075490W WO2012065432A1 WO 2012065432 A1 WO2012065432 A1 WO 2012065432A1 CN 2011075490 W CN2011075490 W CN 2011075490W WO 2012065432 A1 WO2012065432 A1 WO 2012065432A1
Authority
WO
WIPO (PCT)
Prior art keywords
timer
processing
kernel
needs
sequence
Prior art date
Application number
PCT/CN2011/075490
Other languages
English (en)
Chinese (zh)
Inventor
赵阳
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2012065432A1 publication Critical patent/WO2012065432A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Definitions

  • the present invention relates to the field of computer operating systems, and in particular, to a method for implementing a timer in a multi-core system and a multi-core system.
  • BACKGROUND In a multi-core system, there are usually symmetric multi-processing and asymmetric multi-processing application modes, and the timer mechanism provided by the processor hardware is no different from the conventional single-core processor.
  • various service applications often have low operational efficiency and low system reliability due to the lack of a unified timer implementation mechanism in multi-core systems.
  • a primary object of the present invention is to provide an implementation of a timer in a multi-core system to at least solve the problem of low system performance due to centralized processing of all timers on one CPU in the above multi-core system.
  • a method of implementing a timer in a multi-core system includes the following steps:
  • the kernel that needs to create a timer determines the timer in accordance with the duration of the timer and the timing interval corresponding to each core in the multi-core system.
  • the processing sequence of the kernel that needs to be processed within the duration; the kernel that needs to be processed is processed sequentially according to the processing order and the timing interval.
  • the method before determining a processing sequence of a kernel that needs to be processed within a duration of the timer, the method further includes: each core in the multi-core system is separately established according to a corresponding timing interval thereof The respective timers process the linked list.
  • the kernel that needs to be processed is processed in sequence according to the processing sequence and the timing interval.
  • the kernel that needs to create a timer generates a timer entry, and sequentially adds the timer entry to the processing that needs to be processed according to the processing order.
  • the processing of the timer processing list in the kernel, wherein the timer entry includes at least one of the following: a remaining time of the timer, a kernel that needs to create a timer, and a processing order.
  • processing the timer entry in sequence to the timer processing list of the kernel that needs to be processed according to the processing sequence includes: processing the kernel that needs to be processed to process the timer stored in the timer processing list of the kernel Entry.
  • the processing of adding the timer entry to the timer processing list of the kernel that needs to be processed in sequence according to the processing sequence includes: the kernel that needs to create the timer adds the timer entry to the processing sequence first. After the processed kernel's timer processes the linked list, the remaining time of the timer begins to decrement; the first processing core updates the remaining time of the timer according to the timing interval, and the timer table is updated according to the remaining time of the updated timer.
  • the processing sequence of the kernel that needs to be processed within the duration of the timer includes: the kernel that needs to create the timer as the last processing core in the processing sequence.
  • the kernels that need to perform processing are sequentially processed according to the processing sequence and the timing interval.
  • the kernel that needs to perform processing performs processing, it is determined whether it is necessary to stop or delete the timer; if yes, the timer is discarded.
  • the kernels that need to be processed are processed sequentially according to the processing sequence and the timing interval: when the remaining time of the timer is zero, the timer expires.
  • a multi-core system includes a plurality of cores, wherein each of the plurality of cores includes: a calculation module configured to set a duration of the timer according to requirements and a timing interval corresponding to each core in the multi-core system, The processing sequence of the kernel that needs to be processed within the duration of the timer is determined; the execution module is configured to perform processing corresponding to the timer in accordance with the processing order and the timing interval.
  • each of the plurality of cores further comprises: a determining module, configured to determine whether it is necessary to stop or delete the timer; and ending the module, configured to discard the timing when the determining module determines that the timer needs to be stopped or deleted at present Device.
  • a determining module configured to determine whether it is necessary to stop or delete the timer
  • ending the module configured to discard the timing when the determining module determines that the timer needs to be stopped or deleted at present Device.
  • FIG. 1 is a flow chart showing a method for implementing a timer in a multi-core system according to an embodiment of the present invention
  • FIG. 2 is a block diagram showing a structure of a multi-core system according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a timer for creating a preferred embodiment of the present invention
  • FIG. 5 is a schematic diagram after 3 ms according to a preferred embodiment 2 of the present invention
  • FIG. 7 is a flow chart showing a method for implementing a timer in a multi-core system according to a preferred embodiment 3 of the present invention.
  • BEST MODE FOR CARRYING OUT THE INVENTION will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. According to an embodiment of the present invention, a method for implementing a timer in a multi-core system is provided.
  • FIG. 1 a method for implementing a timer in a multi-core system is provided.
  • Step S102 the kernel that needs to create a timer according to the duration of the timer and each of the multi-core systems
  • the timing interval corresponding to the kernel determines the processing sequence of the kernel that needs to be processed within the duration of the timer.
  • step S104 the kernels that need to perform processing are sequentially processed according to the processing order and the timing interval.
  • the method of using multiple kernel distributed cooperative processing timers solves the problem that the system performance is better due to the processing of all the timers on one CPU in the multi-core system, which is beneficial to the equalization processing of the multi-core system. , improve the reliability and stability of the system.
  • the timing interval may be used to indicate the time granularity of the timer that the kernel can implement.
  • the correspondence between the timing interval and each core in the multi-core system may also be configured.
  • each core in the multi-core system can establish a respective timer processing linked list according to the timing interval corresponding thereto. This can increase the flexibility and processing power of the system.
  • a multi-core system includes five cores.
  • the timing interval corresponding to kernel 1 is set to 10 ms
  • the timing interval corresponding to kernel 2 is set to 1 ms
  • the timing interval corresponding to kernel 3 is set to 5ms
  • the timing interval corresponding to kernel 4 is set to 20ms
  • the timing interval corresponding to kernel 5 is set to 2000ms.
  • Each core creates a timer processing list corresponding to its own timing interval.
  • the kernel of the timer is required to generate a timer entry, and the timer entry is sequentially added to the timer processing list of the kernel that needs to be processed according to the processing sequence, where The timer entry includes at least one of the following: the remaining time of the timer, the kernel that needs to create the timer, and the processing order.
  • the method is simple to implement and has high operability.
  • processing the timer entry in sequence to the timer processing list of the kernel that needs to be processed according to the processing sequence includes: processing the kernel that needs to be processed to process the timer stored in the timer processing list of the kernel Entry.
  • the method can utilize multiple cores to jointly implement a timer that needs to be created, so that the system can be balanced and improved, and the performance of the system is improved.
  • the timer processing list of each core in the core of the multi-core system can store the entries of all the timers that the kernel needs to create. For example, there are two timer entries in the timer processing list of kernel 1, one is the entry of timer T1 in kernel 2, and the other is the setting of kernel 1.
  • the processing of adding the timer entry to the timer processing list of the kernel that needs to be processed in sequence according to the processing sequence includes: the kernel that needs to create the timer adds the timer entry to the processing sequence first.
  • the remaining time of the timer begins to decrement; the first processing core updates the remaining time of the timer according to its timing interval, and the timer is based on the remaining time of the updated timer.
  • the entry is added to the timer processing list of the next processing core of the kernel that is the first to process in the processing sequence.
  • the method can make the implementation process of the timer orderly, and improve the accuracy and effectiveness of the system.
  • the processing sequence of the kernel that needs to be processed within the duration of the timer includes: the kernel that needs to create the timer as the last processing core in the processing sequence.
  • step S104 when the kernel that needs to perform processing performs processing, it is determined whether it is necessary to stop or delete the timer; if so, the timer is discarded.
  • the timer may be discarded after the timer to be created is completed, or may be discarded during the implementation of the timer.
  • there is a shared memory for storing the identification information of stopping or deleting a certain timer.
  • Each core in the multi-core system passes through the shared memory while processing the entry of the timer in the timer processing linked list thereof. Determine whether it is necessary to stop or delete the entry of the timer being executed.
  • step S104 when the remaining time of the timer is zero, the timer expires.
  • the kernels that need to be processed may be kernel 1 and kernel 2.
  • the timer processing list of the kernel 1 after the kernel 1 detects the entry of the timer, the remaining time of the timer in the entry is decremented, and when the remaining time of the timer is reduced to 2 ms, the kernel 1 The timer entry is added to the timer processing list of the kernel 2.
  • FIG. 2 is a structural block diagram of a multi-core system according to an embodiment of the present invention. As shown in FIG.
  • the multi-core system 20 includes a plurality of cores, among which Each core 22 of the kernel includes: a calculation module 222 configured to determine the duration of the timer according to the need and the timing interval corresponding to each core in the multi-core system to determine the processing of the kernel that needs to be processed within the duration of the timer.
  • the execution module 224 is coupled to the calculation module 222 and configured to perform processing corresponding to the timer in accordance with the processing order and the timing interval.
  • Each core 22 of the plurality of cores further includes: a determining module 226 configured to determine whether a timer needs to be stopped or deleted at present; the ending module 228 is coupled to the determining Module 226 is configured to discard the timer if decision module 226 determines that a timer needs to be stopped or deleted.
  • the multi-core system 20 may correspond to the foregoing method embodiments in the implementation process, and the descriptions already made in the method embodiments are not described herein again. The implementation process of the foregoing embodiment is described in detail below with reference to the preferred embodiment and the accompanying drawings.
  • the present invention provides a unified and reliable timer implementation mechanism for the application of the multi-core system.
  • a method for implementing a timer in a multi-core system comprising the following steps: Step 1 , system initialization, each core in the multi-core processing system respectively establishes a corresponding timer processing linked list in the shared memory, and each timer processes The linked list corresponds to the corresponding time interval.
  • Step 2 Create a timer.
  • the kernel that needs to create a timer first applies for a timer control block, and calculates according to the timer interval corresponding to each core, and divides the timer into a combination of intervals corresponding to each timer list.
  • Step 3 Add a timer, according to the principle of adding the kernel last, and then add it to the corresponding timer list according to the calculated combination order. In this way, it is beneficial to avoid the sending of timer messages.
  • Step 4. Delete and stop the timer. For example, when the timer needs to be deleted or stopped, the corresponding mask state is set in the kernel, and the timer that needs to be deleted or stopped is added to the corresponding kernel. When the linked list is to be processed, the corresponding timer is discarded.
  • the embodiments of the present invention can overcome the shortcomings of the related art in the lack of a unified and reliable timer implementation mechanism in the multi-core system, and utilize multiple cores to jointly process the timers, which is beneficial to the system load balancing and improve the system. reliability.
  • a method for implementing a timer in a multi-core system according to an embodiment of the present invention is described in detail by taking four CPUs in a multi-core system as an example.
  • the timer list of 4 CPUs corresponding to 1ms, 10ms, 100ms, 1000ms (ie, timing interval), CPU1 and CPU3 respectively create a timer with a timer duration of 303ms and 1323ms respectively.
  • a schematic diagram of a timer for creating a preferred embodiment 2 as shown in FIG.
  • FIG. 5 is a schematic diagram after 3 ms after the preferred embodiment 2 of the present invention. As shown in FIG.
  • the 303 ms timer created by the CPU 1 is added to the queue 2, and the remaining time of the timer is updated to 300ms, after 300ms, it is added to the timer processing queue of CPU1 (ie, queue 1); the 1323ms timer created by CPU3 is added to queue 1, the remaining time of the timer is updated to 1320ms, and then added after 20ms. Force to the team ⁇ 'J 2.
  • 6 is a schematic diagram of a timer according to a preferred embodiment 2 of the present invention. As shown in FIG. 6, the 303 ms timer created by the CPU 1 when the CPU 1 determines that the remaining time is 0, and the target CPU is itself, indicates that the setting is performed.
  • the timer expires; the 1323ms timer created by CPU3 is added to queue 3 after 300ms. After 1000ms, after CPU3 has processed the queue, when CPU3 judges that the remaining time is 0, and the target CPU When it is for itself, it indicates that the set timer expires. In the implementation process, if you want to delete or stop the timer, you can discard the corresponding timer in the corresponding CPU timer processing list, and set the mask to prohibit the target CPU from effectively processing the timeout timer.
  • FIG. 7 is a flowchart of a method for implementing a timer in a multi-core system according to a preferred embodiment 3 of the present invention. As shown in FIG. 7, the method may include the following processing steps: Step S702, System Initialization Create a timer processing list corresponding to each CPU. In step S704, the timer duration calculation sequence to be created is added to the corresponding timer processing list.
  • Step S706 each CPU periodically processes the timer of the corresponding linked list, and adds it to the corresponding timer linked list according to the remaining time of the timer.
  • Step S708 each CPU determines whether the timing queue has a timeout, that is, each CPU determines whether there is a timeout timer to be processed. If yes, go to step S710, otherwise go to step S706 to continue processing.
  • Step S710 determining whether the timer is blocked. If the timer is masked, further processing of the timer is discarded, and the timer resource is released; otherwise, the process proceeds to step S712.
  • Step 4 gathers S712 to process the timer.
  • all the timers connected to the CPU can be processed in sequence, and the remaining time of the timer is decremented by the timer interval corresponding to the CPU.
  • the value of the interval between the timer and the CPU is decremented to 0, if the remaining time of the timer is not 0, then it is hooked up to the processing list of the next CPU according to the hook order of the timer; if the remaining time of the timer is 0, it indicates that the timer expires.
  • the method of using multiple kernel distributed cooperative processing timers in the embodiment of the present invention solves the problem that the system performance is low due to the processing of all the timers on one CPU in the multi-core system, which is beneficial to the problem.
  • the equalization processing of the multi-core system improves the reliability and stability of the system.
  • modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices.
  • they may be implemented by program code executable by the computing device, such that they may be stored in the storage device for execution by the computing device, and
  • the steps shown or described may be performed in a different order than that herein, or they may be separately fabricated into individual integrated circuit modules, or a plurality of modules or steps thereof may be fabricated into a single integrated circuit. Module to achieve.
  • the invention is not limited to any specific combination of hardware and software.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Hardware Redundancy (AREA)

Abstract

L'invention concerne un procédé de mise en oeuvre d'une horloge dans un système multicoeur, ainsi que le système multicoeur. Le procédé comprend les étapes suivantes: détermination de l'ordre de traitement des coeurs devant exécuter un traitement dans la durée d'une horloge, par un coeur devant créer l'horloge en fonction de la durée de l'horloge et de l'intervalle de temps d'une plage fixe correspondant à chaque coeur dans le système multicoeur (S102); et réalisation ordonnée du traitement par les coeurs devant exécuter le traitement en fonction de l'ordre de traitement et de l'intervalle de temps d'une plage fixe (S104). Le procédé de l'invention favorise le traitement équilibré dans le système multicoeur et permet d'augmenter la fiabilité et la stabilité du système.
PCT/CN2011/075490 2010-11-15 2011-06-08 Procédé de mise en oeuvre d'une horloge dans un système multicoeur et système multicoeur WO2012065432A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201010555937.7 2010-11-15
CN201010555937.7A CN102012718B (zh) 2010-11-15 2010-11-15 多核系统中定时器的实现方法及多核系统

Publications (1)

Publication Number Publication Date
WO2012065432A1 true WO2012065432A1 (fr) 2012-05-24

Family

ID=43842910

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2011/075490 WO2012065432A1 (fr) 2010-11-15 2011-06-08 Procédé de mise en oeuvre d'une horloge dans un système multicoeur et système multicoeur

Country Status (2)

Country Link
CN (1) CN102012718B (fr)
WO (1) WO2012065432A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102012718B (zh) * 2010-11-15 2014-12-10 中兴通讯股份有限公司 多核系统中定时器的实现方法及多核系统
CN103019856A (zh) * 2012-11-23 2013-04-03 上海寰创通信科技股份有限公司 一种多核处理器的非对称调度方法
CN106020333B (zh) * 2016-05-20 2019-03-05 京信通信系统（中国）有限公司 多核定时器实现方法和多核系统
CN111949391A (zh) * 2020-08-25 2020-11-17 北京天融信网络安全技术有限公司 基于多核架构的定时器实现方法、装置、设备及存储介质
CN112948071B (zh) * 2021-01-26 2024-09-20 北京达佳互联信息技术有限公司 时间信息的处理方法、装置、设备、存储介质及程序产品

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477386A (zh) * 2009-01-12 2009-07-08 杭州华三通信技术有限公司 一种定时器实现方法和装置
CN101719080A (zh) * 2009-12-25 2010-06-02 联想网御科技(北京)有限公司 多核定时器实现方法及系统
CN101859260A (zh) * 2010-05-14 2010-10-13 中国科学院计算技术研究所 用于操作系统中的定时器管理装置和管理方法
CN102012718A (zh) * 2010-11-15 2011-04-13 中兴通讯股份有限公司 多核系统中定时器的实现方法及多核系统

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7650518B2 (en) * 2006-06-28 2010-01-19 Intel Corporation Method, apparatus, and system for increasing single core performance in a multi-core microprocessor
CN101770403B (zh) * 2008-12-30 2012-07-25 北京天融信网络安全技术有限公司 一种多核平台上控制系统配置并发与同步的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477386A (zh) * 2009-01-12 2009-07-08 杭州华三通信技术有限公司 一种定时器实现方法和装置
CN101719080A (zh) * 2009-12-25 2010-06-02 联想网御科技(北京)有限公司 多核定时器实现方法及系统
CN101859260A (zh) * 2010-05-14 2010-10-13 中国科学院计算技术研究所 用于操作系统中的定时器管理装置和管理方法
CN102012718A (zh) * 2010-11-15 2011-04-13 中兴通讯股份有限公司 多核系统中定时器的实现方法及多核系统

Also Published As

Publication number Publication date
CN102012718B (zh) 2014-12-10
CN102012718A (zh) 2011-04-13

Similar Documents

Publication Publication Date Title
US10592298B2 (en) Method for distributing load in a multi-core system
CN109697122B (zh) 任务处理方法、设备及计算机存储介质
TWI479850B (zh) 單數據機板之改良式多胞元支援方法及系統
US20160378570A1 (en) Techniques for Offloading Computational Tasks between Nodes
US8296490B2 (en) Method and apparatus for improving the efficiency of interrupt delivery at runtime in a network system
WO2010020159A1 (fr) Procédé et dispositif d'équilibrage de charge d'interruption de processeur multi-cœur
US10127091B1 (en) Intercepting socket metadata
US20140181818A1 (en) Optimization of packet processing by delaying a processor from entering an idle state
US8239873B2 (en) Speedy event processing
WO2016115831A1 (fr) Procédé, appareil et système à tolérance de pannes pour machine virtuelle
US9424103B2 (en) Adaptive lock for a computing system having multiple runtime environments and multiple processing units
WO2012065432A1 (fr) Procédé de mise en oeuvre d'une horloge dans un système multicoeur et système multicoeur
CN110990154B (zh) 一种大数据应用优化方法、装置及存储介质
JP2017504261A (ja) 動的チェックポインティングシステムおよび方法
EP2618257A2 (fr) Connecteur logiciel de réseau échelonnable
US9455907B1 (en) Multithreaded parallel packet processing in network devices
JP2006099331A5 (fr)
WO2014047902A1 (fr) Procédé, dispositif, système et support lisible par ordinateur d'équilibrage de charge
JP6088528B2 (ja) トランザクションミドルウェアマシン環境においてシングルポイントボトルネックを防止するためのシステムおよび方法
WO2016177081A1 (fr) Procédé et dispositif de traitement de message de notification
CN117290096A (zh) 完成侧客户端节流
EP3961415B1 (fr) Méthodes et appareils de confirmation de transaction dans un réseau de blockchain
US20150078394A1 (en) Hash perturbation with queue management in data communication
EP3084603B1 (fr) Système et procédé de prise en charge de l'attente adaptative en cas d'occupation dans un environnement informatique
Chakraborty et al. A low-latency multipath routing without elephant flow detection for data centers

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11841365

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11841365

Country of ref document: EP

Kind code of ref document: A1