WO2012064863A1 - Multi-mode unit cell with selectively operated anti-bloom and reset switches - Google Patents

Abstract

Various techniques are provided for operating a unit cell in different modes to detect thermal energy of different wavelengths. Switches such as transistors may be selectively operated as anti-bloom transistors or reset transistors depending on the type of integration performed by a detector. For example, a first transistor may be used as an anti-bloom transistor during a first integration performed using an N on P photodetector, and used as a reset transistor during a second integration performed using a P on N photodetector. A second transistor may be used as a reset transistor during the first integration, and used as an anti-bloom transistor during the second integration.

Description

MULTI -MODE UNIT CELL WITH SELECTIVELY OPERATED ANTI-BLOOM AND RESET

SWITCHES

CROSS-REFERENCE TO RELATED APPLICATIONS

This patent application claims the benefit of United States Provisional Patent Application No. 61/411,692 filed November 9, 2010, which is incorporated herein by reference in its entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with government support under Prime Contract No. W15P7T-06-D-E402 , Subcontract No. S10-108114 awarded by CACI, (INC. - FEDERAL) . The government has certain rights in the invention.

TECHNICAL FIELD

The invention relates generally to imaging systems and, more particularly, for example, to circuitry for detecting and capturing image data . BACKGROUND

There are a wide variety of image detectors, such as visible image detectors, infrared image detectors, or other types of image detectors that may be provided in an image detector array to capture an image to store or to display. As an example, a

plurality of photodiodes may be provided in an image detector array, such . as a focal plane array (FPA) , to detect energy at desired wavelengths. Such detectors may be connected to unit cells which capture image data in response to the detected energy.

Conventional FPAs may be susceptible to blooming which occurs when detected wavelengths are received with high intensity. In this regard, the unit cells may be driven to extreme voltages which cannot be easily reset with conventional reset circuitry. As a result, image data quality may suffer.

Although certain anti-blooming techniques have been developed, such approaches typically require dedicated circuitry which can substantially increase the cost of FPA implementations. As a result, there is a need for an improved approach to blooming reduction in FPAs .

SUMMARY

Various techniques are provided for operating a unit cell in different modes to detect thermal energy of different wavelengths . Transistors may be selectively operated as anti-bloom transistors or reset transistors depending on the type of integration performed by a detector. For example, a first transistor may be used as an anti-bloom transistor during a first integration performed using an N on P photodetector, and used as a reset transistor during a second integration performed using a P on N photodetector. A second transistor may be used as a reset transistor during the first integration, and used as an anti-bloom transistor during the second integration. In one embodiment, a focal plane array (FPA) includes a detector coupled to an integration node and adapted to provide a first current during a first integration operation in response to thermal energy of a first wavelength, and a second current during a second integration operation in response to thermal energy of a second wavelength; a capacitor adapted to store a first voltage at the integration node in response to the first current and a second voltage at the integration node in response to the second current; a first switch coupled to the integration node and adapted to prevent the first voltage from exceeding a first threshold during the first integration operation and adapted to reset the

integration node for the second integration operation; and a second switch coupled to the integration node and adapted to prevent the second voltage from exceeding a second threshold during the second integration operation and adapted to reset the integration node for the first integration operation.

In another embodiment, a method of operating a focal plane array (FPA) includes providing a first current from a detector during the first integration operation in response to thermal energy of a first wavelength; integrating the first current at the integration node to provide a first voltage; preventing the first voltage from exceeding a first threshold during the first

integration' operation using a first switch; resetting the

integration node using a second switch in preparation for a second integration operation; providing a second current from the detector during the second integration operation in response to thermal energy of a second wavelength; integrating the second current at the integration node to provide a second voltage; and preventing the second voltage from exceeding a second threshold during the second integration operation using the second switch; and resetting the integration node using the first switch in preparation for a further integration operation.

The scope of the invention is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be

described briefly.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram of a focal plane array in accordance with an embodiment of the invention. Fig. 2 is a block diagram of a detector, a unit cell, and read out circuitry of the focal plane array of Fig. 1 in accordance with an embodiment of the invention.

Fig. 3 is a block diagram of the unit cell of Fig. 2 in accordance with an embodiment of the invention. Fig. 4 is a circuit diagram of the unit cell of Fig. 2 in accordance with an embodiment of the invention.

Fig. 5 is a timing diagram of the unit cell of Fig. 2 in accordance with an embodiment of the invention.

Fig. 6 is a timing diagram illustrating voltages at various nodes while the unit cell of Fig. 2 is operated in an N on P mode in accordance with an embodiment of the invention.

Fig. 7 is a timing diagram illustrating voltages at various nodes while the unit cell of Fig. 2 is operated in a P on N mode in accordance with an embodiment of the invention. Embodiments of the present invention and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

DETAILED DESCRIPTION Fig. 1 is a block diagram of a focal plane array (FPA) 100 in accordance with an embodiment of the invention. FPA 100 may be implemented with an array 105 of unit cells 110 (e.g., an array of 320 x 256 unit cells or any other desired resolution, with each unit cell sized to be 30μπι x 30μιη or any other desired size) . Each unit cell 110 may be associated with a detector (e.g., a

photodetector or photosite) and associated sampling and readout circuits. In this regard, FPA 100 may be used to capture image data from the detectors in one or more image frames. For example, such image data may be infrared image data of a target scene . FPA 100 also includes a row multiplexer 120 and a column multiplexer 130 (e.g., also including associated amplifiers) for selecting various rows and columns of array 105 for reading data therefrom.

In one embodiment, each unit cell 110 may be associated with a detector capable of detecting different wavelengths. For example, each detector may have a first photodiode capable of detecting a first wavelength (e.g., a first color}, and a second photodiode capable of detecting a second wavelength (e.g., a second color).

The detectors may provide detector signals {e.g., charge, current, voltage, or other signal forms) to unit cells 110 in response to light (e.g., infrared light or other light) received by the detector during an integration period. In one embodiment, each unit cell 110 may be selectively operated to perform an integration at a node (e.g., to integrate currents provided by electrons or holes) in response to current provided in response to thermal energy incident on the first photodiode or the second photodiode during an integration period. The voltage at the integration node may be captured by sample and hold (S/H) circuitry of the unit cell 110 and read out from the unit cell 110 by row multiplexer 120 and column multiplexer 130.

One or more control circuits 140 may be provided as part of and/or separate from FPA 100 to provide various signals further described herein. Such control circuits 140 may be implemented in accordance with any appropriate control circuits such as one or more processors, logic, clocks, and/or other circuits as may be desired for particular implementations.

Fig. 2 is a block diagram of a unit cell 110, a detector 210, and read out circuitry 299 of FPA 100 of Fig. 1 in accordance with an embodiment of the invention. Fig. 3 is a block diagram

providing further details of unit cell 110 in accordance with an embodiment of the invention. Fig. 4 is a circuit diagram of unit cell 110 in accordance with an embodiment of the invention. Figs. 2-4 are collectively described below with regard to the various aspects shown therein. It will be appreciated that different configurations are provided in Figs. 2, 3, and 4. For example, Fig. 2 illustrates unit cell 110 in a particular operational configuration, Fig. 3 illustrates unit cell 110 in a generalized operational configuration, and Fig. 4 illustrates one example of a circuit implementation of unit cell 110. Detector 210 may be implemented with a photodiode 210A (e.g., an M on P photodiode) to provide a current IDETNP to a node 214 {e.g., also referred to as a reference voltage node) in response to thermal energy (e.g., infrared radiation) of a first wavelength incident on photodiode 210A. Detector 210 may also be implemented with a photodiode 210B (e.g., a P on N photodiode) to provide a current IDETPN from node 214 in response to thermal energy (e.g., infrared radiation) of a second wavelength incident on photodiode 210B. In this regard, detector 210 may be selectively operated in an N on P mode to detect a first wavelength using photodiode 210A, or in a P on N mode to detect a second wavelength using photodiode 210B. While detector 210 is operated in an N on P mode, node 214 may be set to a negative reference voltage VNEG (e.g., also

referred to as Vneg or Vneguc) . While detector 210 is operated in a P on N mode, node 214 may be set to a positive reference voltage VPOS (e.g., also referred to as Vpos) .

In one embodiment, detector 210 may be implemented as a strained layer superlattice detector. Other implementations of detector 210 are also contemplated. In various embodiments, detector 210 may be implemented with one or more avalanche

photodiodes or PIN diodes (e.g., each diode having an intrinsic region between a p-type region and an n-type region) . For example, in one embodiment, such PIN diodes may be implemented as reverse- biased indium gallium arsenide (inGaAs) PIN photodiodes.

Detector 210 may be connected to unit cell 110 by one or more indium bumps 212 (e.g., also referred to as a connection node) . In this regard, detector 210 may be separately fabricated from unit cell 110 and subsequently joined to unit cell 110 by indium bumps 212.

Unit cell 110 may also be selectively operated in either an N on P mode to perform an N on P integration operation, or a P on N mode to perform a P on N integration operation. Unit cell 110 includes transistors 220 and 222 which may be used to bias detector 210 and provide a direct injection input circuit. Transistors 220 and 222 may be selectively turned on and off to pass current IDETNP or current IDETPN between node 214 and a node 224 (e.g., also referred to as an integration node) .

For example, when detector 210 is operated in an N on P mode, transistor 220 may be off and transistor 222 may be switched on (e.g., in biased operation) . As a result, current IDETNP may be passed from node 224 to node 214 through transistor 222 and

photodiode 210A. In another example, when detector 210 is operated in a P on N mode, transistor 220 may be switched on (e.g., in biased operation) and transistor 222 may be off. As a result, current IDETPN may be passed from node 214 to node 224 through photodiode 210B and transistor 220. Accordingly, current IDETNP or current IDETPN may be provided (e.g., by direct injection) and integrated at node 224 to provide a voltage which may be captured and read out from unit cell 110 in a manner that facilitates high density and high charge storage.

Unit cell 110 also includes a transistor 230 and a transistor 232 (illustrated as a switch in Fig. 2) . Transistors 230 and 232 may be selectively operated as either reset transistors or anti- bloom transistors for different detection operations. In addition, transistors 230 and 232 may be disabled (e.g., in response to selective operation of signals BLMP_IRSTN and IRSTP_BLMN) if desired to operate unit cell 110 with anti-bloom features disabled (e.g., for testing and/or for expanded reverse bias operation).

In one example, when unit cell 110 is operated in an N on P mode, transistor 230 may be used as a reset transistor to

selectively reset the voltage of node 224 to VPOS . Also during N on P mode, transistor 232 may be used as an anti-bloom transistor to prevent the voltage of node 224 from falling below (e.g., exceeding below) a desired anti-bloom low threshold voltage. In one embodiment, the anti -bloom low threshold voltage may track the biasing of detector 210 (e.g., node 214 may be set to V EG while the drain of transistor 232 is set to VPOS) which may provide increased charge capacity when operating detector 210 with a low reverse bias . In another example, when unit cell 110 is operated in a P on N mode, transistor 230 may be used as an anti-bloom transistor to prevent the voltage of node 224 from rising above (e.g., exceeding above) a desired anti-bloom high threshold voltage. Also during P on N mode, transistor 232 may be used as a reset transistor to selectively reset the voltage of node 224 to VNEG. In one

embodiment, the anti-bloom high threshold voltage may track the biasing of detector 210 (e.g., node 214 may be set to VPOS while the drain of transistor 230 is set to VNEG) which may provide increased charge capacity when operating detector 210 with a low reverse bias .

Unit cell 110 also includes capacitors 240A and 240B

(illustrated collectively as a single capacitor 240 in Figs. 2 and 3) which may be used to store a voltage at node 224 during an integration period. In one embodiment, capacitors 24OA and 240B may collectively provide capacitor 240 as shown in Fig. 2.

Unit cell 110 also includes transistors 250A and 250B

(illustrated collectively as a switch 250 in Fig. 2) which may be used to sample the voltage of node 224. In one embodiment, transistors 250A and 250B may be implemented as a transfer gate (e.g., as shown in Figs. 3 and 4) with complementary MOSFETs to permit rail to rail operation (e.g., using voltages VNEG and VPOS) with capacitors 260A and 260B.

Transistors 250A and 250B may selectively pass the voltage from node 224 to a node 226 (e.g., also referred to as a sampling node or a sample and hold node) where the voltage is held by capacitors 260A and 260B (illustrated collectively as a single capacitor 260 in Figs. 2 and 3) . The voltage may be held by capacitors 260A and 260B while another voltage is output by other portions of read out circuitry (e.g., to provide full frame snap shot integration) , and while another integration is performed at node 224. In one embodiment, capacitors 260A and 260B may

collectively provide a capacitor 260 as shown in Fig. 2.

Unit cell 110 also includes a transistor 270 (illustrated as a switch in Fig. 2) which may be used to selectively reset the voltage at node 226. In this regard, transistor 270 may be used to selectively reset node 226 to VNEG.

Unit cell 110 also includes a buffer 280 (e.g., which may be implemented, for example, as a transistor providing a source follower as shown in Figs. 3 and 4) and a row select switch 282 (e.g., which may be implemented, for example, as a transistor as shown in Figs. 3 and 4) . Unit cell 110 may pass a sampled voltage held at node 226 through buffer 280 and switch 282 in response to, for example, a row select signal (e.g., also referred to as

RO SELn, Rowsel_B, or ROWSEL_B) .

As discussed, unit cell 110 may be part of array 105 of unit cells 110 in FPA 100 arranged in various rows and columns. Read out circuitry 299 may be implemented, for example, as a read out integrated circuit (ROIC) of FPA 100 to provide output signals from array 105. In this regard, additional row select switches 282 are provided for unit cells 110 of other rows of array 105 as part of read out circuitry 299. Read out circuitry 299 includes a current source 283 which may be used to bias a node 285 (e.g., also referred to as a row output node) . Read out circuitry 299 also includes a buffer 284 (e.g., also referred to as a column buffer), a switch 286 (e.g., for passing a voltage held by node 285 to be sampled at a node 289} , a capacitor 288 (e.g. for holding sampled voltages at node 289), a .buffer 290, column select switches .292, a node 293 (e.g., also referred to as a column output node), a bus select switch 294, an output driver 296, and a node 298 (e.g., also referred to as an FPA output node) . In one embodiment, the output signal provided at node 298 may be a voltage signal to conveniently interface with other circuits as may be desired.

In one embodiment, read out circuitry 299 may be implemented as an ROIC to read out sequentially captured images on a frame by frame basis. For example, a pixel for one image frame may be captured using photodiode 210A and read out separately from another pixel that is captured using photodiode 210B and read out for another image frame .

The operation of unit cell 110 may be further understood with reference to Fig. 5 which illustrates a timing diagram of unit cell 110 in accordance with an embodiment of the invention. In

particular, Fig. 5 illustrates the operation of various signals during N on P and P on N integration operations (e.g., also referred to as phases) performed by unit cell 110.

During a time period 510, unit cell 110 performs an N on P integration operation where photodiode 210A is used to detect thermal energy. At the beginning of time period 510, signal

VDETCOM (e.g., also referred to as Vdetcom) sets node 214 to V EG, signal IGP keeps transistor 220 off, and signal IGN keeps

transistor 222 on. As a result, current IDETNP passes from node 224 to node 214 which causes the voltage at node 224 to adjust in response thereto. During time period 510, transistor 232 operates as an anti- bloom transistor and transistor 230 operates as a reset transistor. In this regard, signal IRSTP_BL keeps transistor 232 on and signal BLMDRN keeps the drain of transistor 232 set to VPOS . Also, signal BLMP_IRSTN keeps transistor 230 off and signal BLMDRP keeps the drain of transistor 230 set to VPOS. In one embodiment, transistor 230 may be turned on and off prior to time period 510 to reset the voltage of node 224 in preparation for the integration performed during time period 510. Also during time period 510, signal UCSH and its complement signal UCSH_B (e.g., referenced in Figs. 3 and 4) keep transistors 250A and 250B turned off. Signal SHRST (e.g., also referred to as SHRSTG) keeps transistor 270 turned off at the beginning of time period 510, and synchronization signals FSYNC and LSYNC are set to logic low values. At a time (1), signal SHRST switches transistor 270 on to reset the voltage of node 226 in preparation for a sampling operation, and switches transistor 270 off shortly before a time (2} .

During a time period 520, the voltage at node 224 is sampled at node 226. At the beginning of time period 520, signal FSYNC transitions to a logic high value. At time (2), signal IGN turns off transistor 222 to stop the integration at node 224 prior to sampling (e.g., to avoid increased voltage ranges) . At a time (3), signal IRSTP_BLMN turns off transistor 232 which stops operating as an anti-bloom transistor. At a time (4), signals UCSH and UCSH_B turn transistors 250A and 250B on to pass {e.g., sample) the voltage at node 224 to node 226 where it is held by capacitors 260A and 260B. Signals UCSH and UCSH_B turn transistors 250A and 250B off at the end of time period 520. During a time period 530, unit cell 110 is reset in preparation for a P on N integration operation. At a time (5) , signals BLMDRP and BLMDRN set the drains (e.g., or other terminals) of transistors 230 and 232 to VKEG while transistors 230 and 232 remain off. At a time (6), signal IRSTP_BLMN turns on transistor 232 to reset the voltage of node 224 to VNEG. In this regard, transistor 232 is used as a reset transistor for a P on N

integration operation of unit cell 110.

At a time (7) , signal BLMP_IRSTN turns on transistor 230 to operate as an anti-bloom transistor for a P on N integration operation of unit cell 110. Also at time (7), signal IGP turns on transistor 220 in preparation for a P on N integration operation of unit cell 110. At a time (8), node 214 is set to VPOS also in preparation for a P on N integration operation of unit cell 110.

During a time period 540, unit cell 110 performs a P on N integration operation where photodiode 210B is used to detect thermal energy. At the beginning of time period 540, signal FSYNC transitions to a logic low value. At a time (9), signal IRSTP_BLMN turns off transistor 232. As a result, node 224 is no longer pulled to VNEG. Thus, the voltage at node 224 may adjust in response to current IDETPN passing to node 224 in response to thermal energy received by photodiode 210B.

At a time (10) , signal SHRST switches transistor 270 on to reset the voltage of node 226 in preparation for another sampling operation, and switches transistor 270 off shortly before times (11A) and (11B) .

During a time period 550, the voltage at node 224 is sampled at node 226. At the beginning of time period 550, signal FSYNC transitions to a logic high value. At time (11A) , signal IGP turns off transistor 220 to stop the integration at node 224 prior to sampling (e.g., to avoid increased voltage ranges).

At time (11B) , signal BLMP_IRSTN turns off transistor 230 which stops operating as an anti-bloom transistor. At a time (12) , signals UCSH and UCSH_B turn transistors 250A and 250B on to pass (e.g., sample) the voltage at node 224 to node 226 where it is held by capacitors 260A and 260B. Signals UCSH and UCSH_B turn transistors 250A and 250B off at the end of time period 550.

During a time period 560, unit cell 110 is reset in

preparation for an N on P integration operation. At a time (13) , signals BLMDRP and BLMDRN set the drains of transistors 230 and 232 to VPOS while transistors 230 and 232 remain off. At a time (14), signal BLMP_IRSTN turns on transistor 230 to reset the voltage of node 224 to VPOS. In this regard, transistor 230 is used as a reset transistor for an N on P integration operation of unit cell 110.

At a time (15) , signal IRSTP_BLMN turns on transistor 232 to operate as an anti-blooming transistor for an N on P integration operation of unit cell 110. Also at time (15), signal IGN turns on transistor 222 in preparation for an N on P integration operation of unit cell 110. At a time (16), node 214 is set to VNEG also in preparation for an N on P integration operation of unit cell 110.

During a time period 570, unit cell 110 performs an N on P integration operation where photodiode 210A is used to detect thermal energy. At the beginning of time period 570, signal FSYNC transitions to a logic low value. At a time (17), signal

BLMP_IRSTN turns off transistor 230. As a result, node 224 is no longer pulled to VPOS. Thus, the voltage at node 224 may adjust in response to current IDETNP passing to node 214 in response to thermal energy received by photodiode 210A.

Following time period 570, unit cell 110 may operate in the manner described with regard to time period 510 to complete the N on P integration operation. Thus, in one embodiment, unit cell 110 may be operated to alternate between N on P and P on N integration operations to detect different wavelengths during successive integration operations. In another embodiment, unit cell 110 may be operated to repeatedly detect the same wavelength in successive (e.g., further} N on P integration operations or P on N

integration operations. N various embodiments, any desired sequence of N on P integration operations and/or P on N integration operations may be performed (e.g., by using photodiode 210A and/or photodiode 21OB) . In some embodiments, the signal timings set forth in Fig. 5 may be used to operate the various switches, signals, and nodes of unit cell 110 to prevent various adverse or unintended results that might otherwise occur in conventional signaling schemes.

As one example, at time (6) , transistor 232 is turned on to reset node 224 low before transistor 230 is turned on to operate as an anti-bloom transistor at time (7} . This timing may help avoid a current spike in certain embodiments. In this regard, if

transistor 230 is turned on before transistor 232 is turned on (e.g., if time (7) occurs before time (6)), then a current spike (e.g., an undesired current flow) may be passed through transistor 230 if node 224 is at a threshold above the gate potential of transistor 230.

As another example, at time (5) , the drains of transistors 230 and 232 are both set to VKEG before transistor 230 is turned on to operate as an anti-bloom transistor at time (7} . This timing may help prevent a current spike in certain embodiments . In this regard, if transistor 230 is turned on before the drains of transistors 230 and 232 are both set to VNEG (e.g., if time (7) occurs before time (5) ) , then a current spike may be passed through transistor 230 when the potential at the gate of transistor 230 falls below a threshold to turn on transistor 230.

As another example, at time (5) , the drains of transistors 230 and 232 are both set to VNEG before transistor 232 is turned on to operate as a reset transistor at time (6) . This timing may help prevent a current spike in certain embodiments. In this regard, if transistor 232 is turned on before the drains of transistors 230 and 232 are both set to VNEG (e.g., if time (6) occurs before time (5) ) , then a current spike may be passed through transistor 232 when the potential at the gate of transistor 232 rises above a threshold to turn on transistor 232.

As another example, at time (7) , transistor 220 is turned on to conduct current between node 224 and detector 210 before node 214 is set to VPOS at time (8) . This timing may help prevent a current spike in certain embodiments. In this regard, if node 214 is set to VPOS before transistor 220 is turned on (e.g., if time (8) occurs before time (7)), the capacitance of detector 210 may permit residual charge on node 212 to cause the potential at node 212 to rise above the voltage supply level VPOS, resulting in undesirable conduction through a forward biased junction provided by transistor 220 to the VPOS potential at node 214.

As another example, at time (14) , transistor 230 is turned on to reset node 224 high before transistor 232 is turned on to operate as an anti-bloom transistor at time (15) . This timing may help avoid a current spike in certain embodiments. In this regard, if transistor 232 is turned on before transistor 230 is turned on (e.g., if time (15) occurs before time (14)}, then a current spike may be passed through transistor 232 if node 224 is at a threshold below the gate potential of transistor 232. As another example, at time (13) , the drains of transistors

230 and 232 are both set to VPOS before transistor 232 is turned on to operate as an anti-bloom transistor at time (15) . This timing may help prevent a current spike in certain embodiments. In this regard, if transistor 232 is turned on before the drains of transistors 230 and 232 are both set to VPOS (e.g., if time (15) occurs before time (13)), then a current spike may be passed through transistor 232 when the potential at the gate of transistor 232 rises above a threshold to turn on transistor 232.

As another example, at time (13) , the drains of transistors 230 and 232 are both set to VPOS before transistor 230 is turned on to operate as a reset transistor at time (14) . This timing may help prevent a current spike in certain embodiments. In this regard, if transistor 230 is turned on before the drains of transistors 230 and 232 are both set to VPOS (e.g., if time (14) occurs before time (13)), then a current spike may be passed through transistor 230 when the potential at the gate of transistor 232 falls below a threshold to turn on transistor 230.

As another example, at time (15) , transistor 222 is turned on to conduct current between node 224 and detector 210 before node 214 is set to V EG at time (16) . This timing may help prevent inadvertent lowering of the potential at node 212. In this regard, if node 214 is set to VNEG before transistor 222 is turned on

(e.g., if time (16) occurs before time (15)), the capacitance of detector 210 may permit residual charge on node 212 to cause the potential at node 212 to fall below VNEG, resulting in undesirable conduction through a forward biased junction provided by transistor 222 to the substrate.

As another example, at time ( 7 ) , transistors 230 and 220 turn on substantially simultaneously (e.g., coincidently or nearly coincidently) to permit transistor 230 to operate as an anti-bloom transistor and to permit transistor 220 to conduct current between node 224 and detector 210. Shortly thereafter, node 214 is set to VPOS at time (8) . This timing may help avoid a current spike in certain embodiments. In this regard, if transistor 230 is turned on after transistor 220 and also after node 214 is set to VPOS

(e.g., if transistor 230 is turned on after time (7) and after time {8}), then detector 210 (e.g., if implemented as a low impedance detector) may overcome the reset capability of signal IRSTP_BL N (which was used to turn on transistor 232 at earlier time (6) to operate as a reset transistor) . This may cause the voltage at node 224 to rise to the point of collapsing the^' headroom across

transistor 220. As a result, the subsequent enabling of signal BLMP_IRSTN (used to turn on transistor 230) would create a large current event when the potential at the gate of transistor 230 falls below the potential at node 224 by a threshold amount.

As another example, at time (15) , transistors 232 and 222 turn on substantially simultaneously (e.g., coincidently or nearly coincidently) to permit transistor 232 to operate as an anti-bloom transistor and to permit transistor 222 to conduct current between node 224 and detector 210. Shortly thereafter, node 214 is set to V EG at time (16) . This timing may help avoid a current spike in certain embodiments. In this regard, if transistor 232 is turned on after transistor 222 and also after node 214 is set to VNEG (e.g., if transistor 232 is turned on after time (15) and after time (16)), then detector 210 (e.g., if implemented as a low impedance detector) may overcome the reset capability of signal BLMP_IRSTN (which was used to turn on transistor 230 at earlier time (14) to operate as a reset transistor) . This may cause the voltage at node 224 to decline to the point of collapsing the headroom across transistor 222. As a result, the subsequent enabling of signal IRSTP_BLMN (used to turn on transistor 232) would create a large current event when the potential at the gate of transistor 232 rises above the potential at node 224 by a threshold amount .

As another example, as shown in Fig. 5, times (2) and (3) occur substantially simultaneously. In this regard, at time (2) , signal IGN turns off transistor 222 to stop the integration at node 224 prior to sampling (e.g., to avoid increased voltage ranges) . At time (3) , signal IRSTP_BL N turns off transistor 232 which stops operating as an anti-bloom transistor. This timing may help avoid a undesirable blooming of detector 210 which may affect other neighboring detectors 210. In this regard, if transistor 222 turns off substantially after transistor 232 (e.g., if time (2) occurs substantially after time (3}), then the voltage at node 224 may be integrated down to the point of collapsing headroom across

transistor 222, which may result in undesirable blooming of detector 210.

As another example, as shown in Fig. 5, times (11A) and (11B) occur substantially simultaneously. In this regard, at time (11A) , signal IGN turns off transistor 220 to stop the integration at node 224 prior to sampling (e.g., to avoid increased voltage ranges) . At time (11B) , signal BLMP_IRSTN turns off transistor 230 which stops operating as an anti-bloom transistor. This timing may help avoid a undesirable blooming of detector 210 which may affect other neighboring detectors 210. In this regard, if transistor 220 turns off substantially after transistor 230 (e.g., if time (11A) occurs substantially after time (11B) ) , then the voltage at node 224 may be integrated up to the point of collapsing headroom across transistor 220, which may result in undesirable blooming of detector 210.

The anti-bloom operations of transistors 230 and 232 may be further understood with reference to Figs. 6 and 7. In particular, Fig. 6 is a timing diagram illustrating voltages at nodes 224 and 226 in relation to various signals when unit cell 110 is operated to perform successive N on P integration operations in accordance with an embodiment of the invention.

At a time 610, the voltage at node 224 is reset to VPOS in response to signal BLMP_I STN turning on transistor 230 (e.g., while the drain of transistor 230 is set to VPOS) . Meanwhile, node 226 holds a previously sampled voltage.

At a time 620, signal BLMP_IRSTN turns off transistor 230 which permits an integration operation to begin. Accordingly, the voltage at node 224 drops between time 620 and a time 640 in response to current IDETNP passing from node 224 as a result of thermal energy detected by photodiode 210A.

At a time 630, signal SHRST turns on transistor 270 to reset the voltage at node 226. Accordingly, node 226 holds the reset voltage (e.g., VNEG} while the N on P integration operation continues . At time 640, the voltage at node 224 drops to an anti-bloom low threshold voltage. During the N on P integration, transistor 232 operates as an anti-bloom transistor to prevent the voltage at node 224 from dropping below the anti-bloom low threshold voltage. Accordingly, transistor 232 holds the voltage at node 224 at the anti-bloom low threshold voltage for the duration of the N on P integration {e.g., until a time 650) . In this regard, although photodiode 21OA may receive further thermal energy and provide further current IDETNP after time 640, the voltage at node 224 will drop no further. As a result, unit cell 110 can be prevented from exhibiting blooming errors (e.g., saturation errors) which may otherwise occur if the voltage at node 224 drops too low and cannot be efficiently reset. At time 650, signal IGN turns off transistor 222 which stops the N on P integration operation. Also at this time, signal

IRSTP_BLMN turns off transistor 232 (e.g., see time (3) of Fig. 5 previously described) to disable the anti-bloom operation of transistor 232. At a time 660, signal UCSH causes transistors 250A and 250B to pass the voltage at node 224 (e.g., corresponding to the anti-bloom low threshold voltage) to node 226. As a result, the voltage at node 226 transitions from VNEG to a sampled value (e.g., corresponding to VNEG plus the sampled voltage from node 224) . Additional N on P integration operations may be subsequently performed as shown in Fig. 6.

Fig. 7 is a timing diagram illustrating voltages at nodes 224 and 226 in relation to various signals when unit cell 110 is operated to perform successive P on N integration operations in accordance with an embodiment of the invention. At a time 710, the voltage at node 224 is reset to VNEG in response to signal IRSTP_BLMN turning on transistor 232 (e.g., while the drain of transistor 232 is set to VNEG) . Meanwhile, node 226 holds a previously sampled voltage. At a time 720, signal IRSTP_BLMN turns off transistor 232 which permits an integration operation to begin. Accordingly, the voltage at node 224 rises between time 720 and a time 740 in response to current IDETPN passing to node 224 as a result of thermal energy detected by photodiode 210B.

At a time 730, signal SHRST turns on transistor 270 to reset the voltage at node 226. Accordingly, node 226 holds the reset voltage (e.g., VNEG) while the P on N integration operation continues . At time 740, the voltage at node 224 rises to an anti-bloom high threshold voltage. During the P on N integration, transistor 230 operates as an anti-bloom transistor to prevent the voltage at node 224 from rising above the anti-bloom high threshold voltage. Accordingly, transistor 230 holds the voltage at node 224 at the anti-bloom high threshold voltage for the duration of the P on N integration (e.g., until a time 750) . In this regard, although photodiode 210B may receive further thermal energy and provide further current IDETPN after time 740, the voltage at node 224 will rise no f rther. As a result, unit cell 110 can be prevented from exhibiting blooming errors {e.g., saturation errors) which may otherwise occur if the voltage at node 224 rises too high and cannot be efficiently reset.

At time 750, signal IGP turns off transistor 220 which stops the P on N integration operation. Also at this time, signal

BLMP_IRSTN turns off transistor 230 (e.g., see time (11B) of Fig. 5 previously described} to disable the anti-bloom operation of transistor 230. At a time 760, signal UCSH causes transistors 250A and 250B to pass the voltage at node 224 (e.g., corresponding to the anti-bloom high threshold voltage) to node 226. As a result, the voltage at node 226 transitions from VNEG to a sampled value (e.g., corresponding to VNEG plus the sampled voltage from node 224) . Additional P on N integration operations may be subsequently performed as shown in Fig. 7.

Embodiments described above illustrate but do not limit the invention. It should also be understood that numerous

modifications and variations are possible in accordance with the principles of the present invention. Accordingly, the scope of the invention is defined only by the following claims.

Claims

CLAIMS We claim:

1. A focal plane array (FPA) comprising: a detector coupled to an integration node and adapted to provide a first current during a first integration operation in response to thermal energy of a first wavelength, and a second current during a second integration operation in response to thermal energy of a second wavelength; a capacitor adapted to store a first voltage at the

integration node in response to the first current and a second voltage at the integration node in response to the second current; a first switch coupled to the integration node and adapted to prevent the first voltage from exceeding a first threshold during the first integration operation and adapted to reset the

integration node for the second integration operation; and a second switch coupled to the integration node and adapted to prevent the second voltage from exceeding a second threshold during the second integration operation and adapted to reset the

integration node for the first integration operation.

2. The FPA of claim 1, wherein the detector comprises: an N on P photodiode adapted to provide the first current; and a P on N photodiode adapted to provide the second current .

3. The FPA of claim 1, wherein the first voltage corresponds to a pixel of a first image frame and the second voltage

corresponds to a pixel of a second image frame.

4. The FPA of claim 3, further comprising a read out integrated circuit (ROIC) adapted to sequentially read out the first and second image frames.

5. The FPA of claim 1, further comprising a control circuit adapted to : turn on the second switch to reset a voltage of the

integration node before the first switch is turned on in

preparation for the first integration operation to prevent an undesired current from flowing through the first switch; and turn on the first switch to reset a voltage of the integration node before the second switch is turned on in preparation for the second integration operation to prevent an additional undesired current from flowing through the second switch.

6. The FPA of claim 1, wherein the first and second switches are first and second transistors, the FPA further comprising a control circuit adapted to: set a first terminal voltage at terminals of the first and second transistors before the first and second transistors are turned on in preparation for the first integration operation to prevent undesired currents from flowing through the first and second transistors; and set a second terminal voltage at terminals of the first and second transistors before the first and second transistors are turned on in preparation for the second integration operation to prevent additional undesired currents from flowing through the first and second transistors .

7. The FPA of claim 1, further comprising: a third switch and a fourth switch, wherein the detector is coupled to the integration node through the third and fourth switches; wherein the third switch is coupled to the capacitor at the integration node and coupled to the detector at a connection node, wherein the third switch is adapted to selectively pass the first current between the detector and the integration node for the first integration operation; and wherein the fourth switch is coupled to the capacitor at the integration node and coupled to the detector at the connection node, wherein the fourth switch is adapted to selectively pass the second current between the detector and the integration node for the second integration operation.

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8. The FPA of claim 7, further comprising a control circuit adapted to : turn on the fourth switch to pass a first residual charge from the connection node to the integration node after the first integration operation and before the second integration operation to prevent a voltage at the connection node from exceeding a first reference voltage of the detector; and turn on the third switch to pass a second residual charge from the connection node to the integration node after the second integration operation and before a further integration operation to prevent the voltage at the connection node from exceeding a second reference voltage of the detector.

9. The FPA of claim 7, further comprising a control circuit adapted to: turn on the first and third switches substantially

simultaneously in preparation for the first integration operation to prevent an undesired current from flowing through the first switch; and turn on the second and fourth switches substantially

simultaneously in preparation for the second integration operation to prevent an additional undesired current from flowing through the second switch.

10. The FPA of claim 7, further comprising a control circuit adapted to: turn off the first and third switches substantially

simultaneously after the first integration operation to prevent an undesired current from flowing through the first switch; and turn off the second and fourth switches substantially

simultaneously after the second integration operation to prevent an additional undesired current from flowing through the second switch.

11. A method of operating a focal plane array {FPA), the method comprising: providing a first current from a detector during the first integration operation in response to thermal energy of a first wavelength; integrating the first current at the integration node to provide a first voltage; preventing the first voltage from exceeding a first threshold during the first integration operation using a first switch; resetting the integration node using a second switch in preparation for a second integration operation; providing a second current from the detector during the second integration operation in response to thermal energy of a second wavelength; integrating the second current at the integration node to provide a second voltage; preventing the second voltage from exceeding a second

threshold during the second integration operation using the second switch; and resetting the integration node using the first switch in preparation for a further integration operation.

12. The method of claim 11, wherein: the first current is provided by an N on P photodiode; and the second current is provided by a P on N photodiode.

13. The method of claim 11, wherein the first voltage corresponds to a pixel of a first image frame and the second voltage corresponds to a pixel of a second image frame.

14. The method of claim 13, further comprising sequentially reading out the first and second image frames.

15. The method of claim 11, further comprising: turning on the second switch to reset a voltage of the integration node before turning on the first switch in preparation for the first integration operation to prevent an undesired current from flowing through the first switch; and turning on the first switch to reset a voltage of the integration node before turning on the second switch in preparation for the second integration operation to prevent an additional undesired current from flowing through the second switch.

16. The method of claim 11, wherein the first and second switches are first and second transistors, the method further comprising: setting a first terminal voltage at terminals of the first and second transistors before turning on the first and second

transistors in preparation for the first integration operation to prevent undesired currents from flowing through the first and second transistors; and setting a second terminal voltage at terminals of the first and second transistors before turning on the first and second transistors in preparation for the second integration operation to prevent additional undesired currents from flowing through the first and second transistors.

17. The method of claim 11, further comprising: operating a third switch coupled to the capacitor at the integration node and coupled to the detector at a connection node to selectively pass the first current between the detector and the integration node for the first integration operation; and operating a fourth switch coupled to the capacitor at the integration node and coupled to the detector at the connection node to selectively pass the second current between the detector and the integration node for the second integration operation.

The method of claim 17, further comprising turning on the fourth switch to pass a first residual charge from the connection node to the integration node after the first integration operation and before the second integration operation to prevent a voltage at the connection node from exceeding a first reference voltage of the detector; and turning on the third switch to pass a second residual charge from the connection node to the integration node after the second integration operation and before the further integration operation to prevent the voltage at the connection node from exceeding a second reference voltage of the detector.

19. The method of claim 17, further comprising: turning on the first and third switches substantially

simultaneously in preparation for the first integration operation to prevent an undesired current from flowing through the first switch; and turning on the second and fourth switches substantially simultaneously in preparation for the second integration operation to prevent an additional undesired current from flowing through the second switch. The method of claim 17, further comprising turning off the first and third switches substantially simultaneously after the first integration operation to prevent an undesired current from flowing through the first switch; and turning off the second and fourth switches substantially simultaneously after the second integration operation to prevent an additional undesired current from flowing through the second switch.