WO2012064174A1

WO2012064174A1 - Quantum random number generator (qrng) with multi random source (mrs) processor

Info

Publication number: WO2012064174A1
Application number: PCT/MY2011/000106
Authority: WO
Inventors: Siswanto Meilana; Witjaksono Gunawan; Firdaus Hj Yaakob Wira
Original assignee: Mimos Berhad
Priority date: 2010-11-09
Filing date: 2011-06-17
Publication date: 2012-05-18
Also published as: MY169774A

Abstract

Apparatus (300) and method for producing parallel random high speed bits via Quantum Random Number Generator (QRNG). The apparatus includes an optical system (1 10) comprising optical component, analog processor and digital data processor for generating and converting analog signals to sequence of digital signals and a multi random source processor (MRSP) (120) for generating plurality of multiple output of sequence random number using asynchronous transmitters. The method, utilizing MRSP, includes processing generated analog signals, generating multi random digital data sequence, collecting 2-bit data of digital data sequence and saving into 4-bit register, collecting 4-bit data, transmitting to 8-bit register using serial to parallel module, XOR-ing 8-bit data with LFSR, asserting TxD start signal, sending 8-bit data (TxD_data) to multi asynchronous transmitters, serializing m-bit data using m-to-n converters, determining transmission status, sending busy signal when transmission occurs, sending TxD_Data 1 signal when transmission is undetected and generating TxD output to multiple outputs.

Description

QUANTUM RANDOM NUMBER GENERATOR (QRNG) WITH MULTI RANDOM

SOURCE (MRS) PROCESSOR

FIELD OF INVENTION

The present invention relates to a method and apparatus to produce parallel random bits of high speed via Quantum Random Number Generator (QRNG) utilizing multi random source (MRS) processor.

BACKGROUND ART

Random numbers are used in cryptography for securing data, Monte Carlo numerical simulations and calculations, tokens in identity management, statistical research, randomized algorithms, and gaming applications. A random number generator is a computational or physical device designed to generate a sequence of numbers or symbols that lack any pattern, i.e., appear random. A Quantum Random Number Generator (QRNG) relies on photons or light particles that are sent one by one onto a semi-transparent mirror and detected. The exclusive events of reflection and transmission are associated to "0" - "1" bit values. Because photonic emission is random, the number generated by the QRNG is random.

Presently, one-time pad (OTP) encryption requires a high-speed random bit. The true random numbers are used in applications where it requires non repetitive events which are becoming increasingly important. However, hardware-based random number generators are not reliable, are big in size, and do not have the capacity to run larger size applications due to a low output rate or speed.

The present invention establishes multi random source (MRS) processor in quantum random number generator (QRNG) to process digital output from optical signal and sequence in parallel processing, where digital signal can be captured in parallel processing to increased speed and maintaining true randomness of output bit of each channel. Thus, the present invention provides the ability of increasing higher output and randomness output bits. The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practice.

SUMMARY OF INVENTION

The present invention provides an apparatus (100) for producing parallel random high speed bits via Quantum Random Number Generator (QRNG).The apparatus comprising at least one optical system (110) and at least one multi random source (MRS) processor (120). The at least one optical system further comprising optical component, analog processor and digital data processor for generating analog signals and converting analog signals to sequence of digital signals and the at least one multi random source (MRS) processor (120) generates plurality of multiple output of sequence random number using asynchronous transmitters.

Preferably, the apparatus (100) having multi random source (MRS) processor (120) further comprises at least one multi random processor (MRP) (220) for collecting m-bit data from multi digital data sequence and processing m-bit data and asynchronous transmitter (230) for producing multiple random output. Multi random processor (MRP) (220) further comprises a plurality of serial to parallel modules (310) having 2" shift register to convert serial data sequence to parallel data sequence and a plurality of digital logical gates to process output of plurality of serial to parallel modules (310) to n- parallel random data sequence by XOR-ing with Linear Feedback Shift Registers (LFSR) (320).

Further, asynchronous transmitter (230) in multi random source processor (MRS) (120) receives plurality of inputs from multi random processor (MRP) (220) wherein the plurality of inputs includes TxD_data, TxD_start and Clock. Outputs of asynchronous transmitter (230) are busy signal and multi true random outputs TxD, wherein TxD is TxD_1 to TxD_n. Asynchronous transmitters (230) are multi Universal Asynchronous Receiver Transmitter UARTs.

Another aspect of the present invention provides a method (600) for producing parallel random high speed bits via Quantum Random Number Generator (QRNG) utilizing multi random source (MRS) processor. The method comprising steps of generating analog signals from at least one optical system quantum random number generator (QRNG) (602), processing generated analog signals (604), generating multi random digital data sequence (606), collecting 2-bit data of digital data sequence and saving the said data into 4-bit register A , collecting 4-bit data of the said register A, transmitting the said 4-bit data to 8-bit register B using serial to parallel module (608), XOR-ing 8-bit data with serial to parallel module (610), asserting TxD_start signal (612), sending 8-bit data (TxD_data) to plurality of multi asynchronous transmitters (614), serializing m-bits data using m-to-n converters (616), determining whether a transmission has occurred (618), sending busy signal when transmission occurs (620), sending TxD_Data 1 signal which is input signal when transmission is not detected (622) and generating TxD output to multiple outputs (624).

The present invention consists of features and a combination of parts hereinafter fully described and illustrated in the accompanying drawings, it being understood that various changes in the details may be made without departing from the scope of the invention or sacrificing any of the advantages of the present invention.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS

To further clarify various aspects of some embodiments of the present invention, a more particular description of the invention will be rendered by references to specific embodiments thereof, which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail through the accompanying drawings where:

FIG. 1 illustrates parallel quantum random number generator (QRNG) having multi random source (MRS) processor.

FIG. 2 illustrates parallel quantum random number generator (QRNG) having multi random processor (MRP) in multi random source (MRS) processor.

FIG. 3 illustrates details of components in multi random processor (MOP) in multi random source (MRS) processor.

FIG. 4 illustrates process of collecting 2-bit and 4-bit data by using serial-to-parallel module.

FIG. 5 illustrates parallel asynchronous transmitter (multi UART) with single m-to-n converter.

FIG. 6 is a flowchart illustrating a method for producing parallel random high speed bits via Quantum Random Number Generator (QRNG) utilizing multi random source (MRS) processor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention provides a method and apparatus for producing parallel random high speed bits via Quantum Random Number Generator (QRNG) utilizing Multi Random Source (MRS) processor. Hereinafter, this specification will describe the present invention according to the preferred embodiments. It is to be understood that limiting the description to the preferred embodiments of the invention is merely to facilitate discussion of the present invention and it is envisioned without departing from the scope of the appended claims.

Reference is first being made to FIG.1. FIG.1 illustrates parallel quantum random number generator (QRNG) having multi random source (MRS) processor. As illustrated in FIG. 1 , quantum random number generator (QRNG) consists of at least one optical system (110) and at least one multi random source (MRS) processor (120). The quantum random number generator (QRNG) can be implemented via embedded system. The optical system further comprising optical component and digital data processor that generates analog signals. The digital data processor which comprises of analog and digital processes (110) will produce sequence of digital signal outputs. The multi random source (MRS) processor (120) generates plurality of multiple outputs of sequence random numbers. The multi random source processor (MRS) (120) will convert digital signal sequence (serial) to n-parallel of random digital signal sequence. The multi random source (MRS) processor (120) will generate n parallel output of random number sequence according to number of inputs. Therefore, number of produced parallel output depends on number of sources (input of multi random source (MRS) processor) used and can be reconfigured based on specific requirement.

Reference is now being made to FIG. 2 and FIG. 3 respectively. FIG. 2 illustrates parallel quantum random number generator (QRNG) having multi random processor (MRP) in multi random source (MRS) processor and FIG. 3 illustrates details of components in multi random processor (MOP) in multi random source (MRS) processor. As illustrated in FIG. 2, the multi random source (MRS) processor comprises at least one multi random processor (MRP) (220) and asynchronous transmitters (230). Multi random processor (MRP) (220) further comprises a plurality of serial to parallel modules (310) having 2" shift register to convert serial data sequence to parallel data sequence and a plurality of digital logical gates to process output of plurality of serial to parallel modules (310) to n- parallel random data sequence.

Multi random processor (MRP) (220) collects m-bit data from multi digital data sequence and thereafter processes the said m-bit data. Multi random processor (MRP) (220) collects m-bits un-random data i.e., 8-bit data from multi digital data sequence produced by optical system (110) using multi serial-to-paralle! module, i.e., a multi 2" shift register in multi random processor (MRP) (220). The parallel 8-bit un-random data which are output of plurality of serial to parallel module (310) will be processed as random digital sources by XOR-ing parallel 8-bit un-random data with Linear Feedback Shift Registers (LFSR) (320). Outputs of multi random processor (MRP) (220) will be sent to multi asynchronous transmitter, such as, a multi Universal Asynchronous Receiver Transmitter (UART) (230) as its random output modules functioned as a serializer. Multi random processor (MRP) (220) converts multi un-random serial data sequence to n-parallel random data sequence wherein multi random processor (MRP) (220) will take an 8-bit data from multi digital data sequence by using multi serial-to-parallel module (, i.e., a multi 2" shift register). Reference is now being made to FIG 4. FIG. 4 illustrates process of collecting 2-bit and 4-bit data by using serial-to-parallel module wherein 2-bit data (410) is collected and saved in 4-bit register A (420) and 4-bit data is collected and saved in 8-bit register B (440) by using multi serial-to-parallel module , such as multi 2" shift register (400). Multi 2" shift register (400) collects 2-bit data and saves the said data in first and second memory of register A, REG A (420). The 2-bit data is shifted to third and fourth memory of REG A for next incoming 2- bit data to occupy first and second memory of REG A. The process (430) will continue until the system is stopped. Once REG A is occupied with 2 x 2 bit data, process for collecting 4-bit data and saving it into the 8-bit register, REG B starts (450). The 4 bit data of REG A will be taken and saved into first till fourth memory of REG B until the next incoming 4 bit data. Upon arrival of new 4-bit data, previous 4-bit data is shifted to fifth till eight memory of REG B (440). Thereafter, new data will replace memory placing of previous 4-bit data. This technique (400) as illustrated in FIG. 4 is faster than collecting 1-bit data and shifting into an 8-bit register. Reference is now being made to FIG. 5. FIG. 5 illustrates parallel asynchronous transmitter (multi UART) with single m-to-n converter. As illustrated in FIG. 5, asynchronous transmitter (230), such as Universal Asynchronous Receiver Transmitter UARTs receives plurality of inputs from multi random processor (MRP) (220) wherein plurality of inputs of asynchronous transmitter (230) includes TxD_data, TxD_start, Clock (clock), and reset. The asynchronous transmitter also has two outputs including a busy and multi TxD (TxD_1 to TxD_n.) Since, n different sources are available, different pattern of multi outputs ( xD^ to TxD_n) will be generated.

Reference is now being made to FIG. 6. FIG. 6 is a flowchart illustrating a method for producing parallel random high speed bits via Quantum Random Number Generator (QRNG) utilizing multi random source (MRS) processor. The at least one optical system (110) generates analog signals (602) and forwards analog signals to analog processor to process the said generated analog signals (604). Thereafter, analog signals are converted to multi random sequence of digital data (606). Subsequently, sequences of digital data are forwarded to multi random processor (MRP) (220) which resides within multi random source (MRS) processor (120).

Multi random processor (MRP) (220) will convert digital data sequence to n-parallel digital data sequence (608). Specifically, multi random processor (MRP) (220) will collect 2-bit data and save the said 2-bit data into 4-bit register (REG A). The multi random processor (MRP) will transmit the said 4-bit data of REG A to 8-bit register (REG B) using serial to parallel module, such as, 2" shift register.

Further, n-parallel digital data sequence which are 8-bit data outputs of serial to parallel modules are processed by XOR-ing with LFSR modules (610). Upon asserting TxD_start signal (612), each multi asynchronous transmitter, such as, multi Universal Asynchronous Receiver Transmitter (UART) will take 8-bit data (614), control data and signals, and serialize the said m-bit (i.e. 8-bit data) using processes of finite state machine and m-to-n converter (616). It is further determined if transmission has occurred (618). Busy signal is asserted and TxD start signal is ignored during transmission (620). Therefore, UART generates start bit, data bits, and stop bits ("busy" signal) by using state machine which resides within multi random source (MRS) processor (120). Assuming that "BaudTick" signal is available, it is asserted at 921600 bits a second. The state machine starts right when TxD_start is asserted, but TxD_Data1 only advances when "BaudTick" is asserted (622). The TxD_1 to Tx_Dn outputs are generated as a serial output through m-to-n converter in asynchronous transmitters (230) (624). Random bits are produced to be parallel to one another. Therefore, digital output is processed by multi random source (MRS) processor (120) that processes digital output sequences it in parallel process. The method and apparatus for producing parallel random high speed bits are applicable for one-time pad encryption in audio-video encryption.

Therefore, the present invention reproduce random bits in parallel by generating n parallel output of sequence random number which increase speed by n times in quantum random number generator (QRNG) utilizing Multi Random Source (MRS) processor.

The present invention may be embodied in other specific forms without departing from its essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore indicated by the appended claims rather than by the foregoing description. All changes, which come within the meaning and range of equivalency of the claims, are to be embraced within their scope.

Claims

An apparatus (100) for producing parallel random high speed bits via Quantum Random Number Generator (QRNG), comprising:

at least one optical system (110) comprising optical component, analog processor, and digital data processor for generating analog signals and converting analog signals to sequence of digital signals; and

at least one multi random source (MRS) processor (120) for generating plurality of multiple output of sequence random number.

The apparatus (100) according to Claim 1 , wherein the at least one multi random source (MRS) processor (120) further comprises:

at least one multi random processor (MRP) (220) for collecting m- bit data from multi digital data sequence and processing m-bit data; and asynchronous transmitters (230) for producing multiple random output.

The apparatus (100) according to Claim 1 , wherein parallel random high speed bits are applicable for one-time pad encryption in audio-video encryption.

The apparatus (100) according to Claim 1 can be implemented via embedded system.

The apparatus (100) according to Claim 2, wherein the at least one multi random processor (MRP) (220) further comprises:

a plurality of serial to parallel modules (310) having 2" shift register to convert serial data sequence to parallel data sequence;

at least one Linear Feedback Shift Registers (LFSR) (320); and a plurality of digital logical gates to process output of plurality of serial to parallel modules (310) to n-parallel random data sequence. The apparatus (100) according to Claim 2, wherein asynchronous transmitter (230) receives plurality of inputs from multi random processor (MRP) (220), the plurality of inputs includes TxD_data, TxD_start, Clock (elk) and Reset (rst).

The apparatus (100) according to Claim 2, wherein outputs of asynchronous transmitter (230) are busy signal and multi true random outputs TxD, wherein TxD is TxD_1 to TxD_n.

The apparatus (100) according to Claim 2, wherein asynchronous transmitter (230) are multi Universal Asynchronous Receiver Transmitter UARTs.

A method (600) for producing parallel random high speed bits via Quantum Random Number Generator (QRNG) utilizing multi random source (MRS) processor comprising steps of:

generating analog signals from at least one optical system quantum random number generator (QRNG) (602);

processing generated analog signals (604);

generating multi random digital data sequence (606);

collecting 2-bit data of digital data sequence and saving the said data into 4-bit register A, collecting 4-bit data of the said register A, transmitting the said 4-bit data to 8-bit register B using serial to parallel module (608);

XOR-ing the 8-bit data with Linear Feedback Shift Register (610); asserting TxD_start signal (612);

sending 8-bit data (TxD_data) to plurality of multi asynchronous transmitters (614);

serializing m-bit data using m-to-n converters (616);

determining whether a transmission has occurred (618);

sending busy signal when transmission occurs (620); sending TxD_Data 1 signal which is input signal when transmission is not detected (622); and

generating TxD output to multiple outputs (624).

The method (600) according to Claim 9 wherein for producing parallel random high speed bits are applicable for one-time pad encryption in audio-video encryption.