WO2012059350A3 - A method of treating a multilayer structure - Google Patents

A method of treating a multilayer structure Download PDF

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Publication number
WO2012059350A3
WO2012059350A3 PCT/EP2011/068502 EP2011068502W WO2012059350A3 WO 2012059350 A3 WO2012059350 A3 WO 2012059350A3 EP 2011068502 W EP2011068502 W EP 2011068502W WO 2012059350 A3 WO2012059350 A3 WO 2012059350A3
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
chemical etch
treating
layer
multilayer structure
Prior art date
Application number
PCT/EP2011/068502
Other languages
French (fr)
Other versions
WO2012059350A2 (en
Inventor
Alexandre Vaufredaz
Original Assignee
Soitec
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec filed Critical Soitec
Publication of WO2012059350A2 publication Critical patent/WO2012059350A2/en
Publication of WO2012059350A3 publication Critical patent/WO2012059350A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

The invention provides a method of treating a multilayer structure (211), comprising a wafer (208) bonded to a substrate (210), the wafer comprising at least one upper layer (202), a lower layer (201) and a buried oxide layer (204) disposed between the upper layer and the lower layer, a bonding oxide layer (206a) also being disposed between the wafer and the substrate, the method comprising a subsequent step of chemical etching of the wafer and, before said subsequent chemical etching step, the following steps in succession; • partial mechanical trimming of the upper layer; • a first preliminary chemical etch; • a first partial deoxidation using a chemical etch with hydrofluoric acid; and • a second preliminary chemical etch; and a second partial deoxidation using a chemical etch with hydrofluoric acid.
PCT/EP2011/068502 2010-11-05 2011-10-24 A method of treating a multilayer structure WO2012059350A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1059135 2010-11-05
FR1059135A FR2967295B1 (en) 2010-11-05 2010-11-05 PROCESS FOR PROCESSING A MULTILAYER STRUCTURE

Publications (2)

Publication Number Publication Date
WO2012059350A2 WO2012059350A2 (en) 2012-05-10
WO2012059350A3 true WO2012059350A3 (en) 2012-11-22

Family

ID=44167962

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2011/068502 WO2012059350A2 (en) 2010-11-05 2011-10-24 A method of treating a multilayer structure

Country Status (3)

Country Link
FR (1) FR2967295B1 (en)
TW (1) TW201232657A (en)
WO (1) WO2012059350A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3003997B1 (en) * 2013-03-29 2015-03-20 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A COMPOSITE STRUCTURE

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917984A (en) * 1995-06-29 1997-01-17 Sumitomo Sitix Corp Bonded soi substrate manufacturing method
FR2880184A1 (en) * 2004-12-28 2006-06-30 Commissariat Energie Atomique Semiconductor structure, e.g. bonded silicon-on-insulator structure, trimming method, involves etching edge of plate after fixing plate on another plate, to form pedestal, and thinning former plate to pedestal, to provide thin part
WO2010026006A1 (en) * 2008-09-02 2010-03-11 S.O.I. Tec Silicon On Insulator Technologies A mixed trimming method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0917984A (en) * 1995-06-29 1997-01-17 Sumitomo Sitix Corp Bonded soi substrate manufacturing method
FR2880184A1 (en) * 2004-12-28 2006-06-30 Commissariat Energie Atomique Semiconductor structure, e.g. bonded silicon-on-insulator structure, trimming method, involves etching edge of plate after fixing plate on another plate, to form pedestal, and thinning former plate to pedestal, to provide thin part
WO2010026006A1 (en) * 2008-09-02 2010-03-11 S.O.I. Tec Silicon On Insulator Technologies A mixed trimming method

Also Published As

Publication number Publication date
TW201232657A (en) 2012-08-01
WO2012059350A2 (en) 2012-05-10
FR2967295A1 (en) 2012-05-11
FR2967295B1 (en) 2013-01-11

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