WO2012050020A1 - Dispositif de traitement de données et procédé de traitement de données - Google Patents

Dispositif de traitement de données et procédé de traitement de données Download PDF

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WO2012050020A1
WO2012050020A1 PCT/JP2011/072952 JP2011072952W WO2012050020A1 WO 2012050020 A1 WO2012050020 A1 WO 2012050020A1 JP 2011072952 W JP2011072952 W JP 2011072952W WO 2012050020 A1 WO2012050020 A1 WO 2012050020A1
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bits
column
code
storage means
address
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PCT/JP2011/072952
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Japanese (ja)
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雄二 篠原
山本　真紀子
横川　峰志
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ソニー株式会社
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6552—DVB-T2
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes

Definitions

  • the present invention relates to a data processing apparatus and a data processing method, and more particularly, to a data processing apparatus and a data processing method capable of improving, for example, tolerance against data errors.
  • LDPC Low Density Parity Check
  • DVB Digital Video Broadcasting
  • S.2 Satellite Digital Broadcasting
  • LDPC codes are also being considered for next-generation terrestrial digital broadcasting.
  • LDPC codes have been found to have performance close to the Shannon limit as the code length is increased, as is the case with turbo codes and the like.
  • the LDPC code has the property that the minimum distance is proportional to the code length, its characteristic is that the block error probability characteristic is good, and furthermore, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed.
  • An advantage is that it hardly occurs.
  • LDPC code is a linear code and does not necessarily need to be binary, but will be described here as being binary.
  • LDPC code is characterized by the fact that the parity check matrix that defines the LDPC code is sparse.
  • a sparse matrix is a matrix in which the number of “1” s in the matrix is very small (a matrix in which most elements are 0).
  • FIG. 1 shows an example of a parity check matrix H of an LDPC code.
  • the weight of each column (column weight) (the number of “1”) (weight) is “3”, and the weight of each row (row weight) is “6”. .
  • a generator matrix G is generated based on the check matrix H, and the generator matrix G is multiplied by binary information bits to generate a codeword (LDPC code). ) Is generated.
  • the generator matrix G is a K ⁇ N matrix
  • the encoding device multiplies the generator matrix G by a bit string (vector u) of information bits made up of K bits to generate a code made up of N bits.
  • Generate the word c ( uG).
  • the code word (LDPC code) generated by this encoding device is received on the receiving side via a predetermined communication path.
  • LDPC code decoding is an algorithm proposed by Gallager called probabilistic decoding (Probabilistic Decoding), which consists of a variable node (also called a message node) and a check node (check node). This can be done by a message passing algorithm based on belief propagation on a so-called Tanner graph.
  • the variable node and the check node are also simply referred to as nodes as appropriate.
  • FIG. 2 shows a procedure for decoding the LDPC code.
  • a real value (reception LLR) expressing the “0” likelihood of the value of the i-th code bit of the LDPC code (1 codeword) received on the receiving side as a log likelihood ratio as appropriate. ) Is also referred to as a received value u 0i . Further, a message output from the check node is u j and a message output from the variable node is v i .
  • step S11 the LDPC code is received, the message (check node message) u j is initialized to “0”, and the counter of the iterative process is used.
  • the variable k taking the integer of is initialized to “0”, and the process proceeds to step S12.
  • step S12 a message (variable node message) v i is obtained by performing the calculation (variable node calculation) shown in Expression (1) based on the received value u 0i obtained by receiving the LDPC code.
  • the message u j is obtained by performing the calculation (check node calculation) shown in Expression (2).
  • Equation (1) and Equation (2) can be arbitrarily selected to indicate the number of “1” s in the vertical direction (column) and horizontal direction (row) of the parity check matrix H, respectively.
  • variable node calculation of Expression (1) the message input from the edge (line connecting the variable node and the check node) to which the message is to be output, respectively.
  • the computation range is 1 to d v -1 or 1 to d c -1.
  • the check node calculation of equation (2) actually creates a table of function R (v 1 , v 2 ) shown in equation (3) defined by one output for two inputs v 1 and v 2 in advance. In addition, this is performed by using it continuously (recursively) as shown in Equation (4).
  • step S12 the variable k is further incremented by “1”, and the process proceeds to step S13.
  • step S13 it is determined whether or not the variable k is larger than a predetermined iterative decoding count C. If it is determined in step S13 that the variable k is not greater than C, the process returns to step S12, and thereafter the same processing is repeated.
  • step S13 determines whether the variable k is larger than C. If it is determined in step S13 that the variable k is larger than C, the process proceeds to step S14, and a message v i as a decoding result to be finally output is obtained by performing the calculation shown in equation (5). And the LDPC code decoding process ends.
  • equation (5) is performed using messages u j from all branches connected to the variable node.
  • FIG. 3 shows an example of a parity check matrix H of a (3, 6) LDPC code (coding rate 1/2, code length 12).
  • the column weight is 3 and the row weight is 6, as in FIG.
  • FIG. 4 shows a Tanner graph of the check matrix H in FIG.
  • a plus “+” represents a check node
  • Check nodes and variable nodes correspond to the rows and columns of the parity check matrix H, respectively.
  • the connection between the check node and the variable node is an edge, and corresponds to “1” of the check matrix element.
  • the branch represents that the sign bit corresponding to the variable node has a constraint condition corresponding to the check node.
  • FIG. 5 shows variable node calculation performed in the variable node.
  • the message v i corresponding to the branch to be calculated is the variable node of the formula (1) using the messages u 1 and u 2 from the remaining branches connected to the variable node and the received value u 0i. It is obtained by calculation. Messages corresponding to other branches are obtained in the same manner.
  • FIG. 6 shows a check node operation performed at the check node.
  • sign (x) is 1 when x ⁇ 0, and ⁇ 1 when x ⁇ 0.
  • Equation (6) can be transformed into Equation (7).
  • the message u j corresponding to the branch to be calculated is the messages v 1 , v 2 , v 3 , v 4 , v from the remaining branches connected to the check node. It is obtained by the check node calculation of Equation (7) using 5 . Messages corresponding to other branches are obtained in the same manner.
  • ⁇ (x) and ⁇ ⁇ 1 (x) are mounted on hardware, they may be mounted using a LUT (Look Up Table), but both are the same LUT.
  • DVB-S.2 ETSI EN 302 307 V1.1.2 (2006-06)
  • LDPC code is used in DVB-S.2 which is a standard for satellite digital broadcasting and DVB-T.2 which is a standard for next-generation terrestrial digital broadcasting.
  • the LDPC code is planned to be used in DVB-C.2, which is the next-generation CATV (Cable Television) digital broadcasting standard.
  • LDPC codes are converted to symbols of orthogonal modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying), and these symbols are signals. It is mapped to a point and transmitted.
  • digital modulation digital modulation
  • QPSK Quadrature Phase Shift Keying
  • the code bits of the LDPC code are exchanged in units of two or more code bits, and the code bit after the exchange is used as a symbol bit.
  • DVB-T.2 is a standard for digital broadcasting for fixed terminals such as television receivers installed in homes and the like, and may not be appropriate for digital broadcasting for portable terminals.
  • the mobile terminal needs to have a smaller circuit scale than the fixed terminal, and it is necessary to reduce power consumption. Therefore, in digital broadcasting for portable terminals, in order to reduce the load necessary for processing such as decoding of LDPC codes in portable terminals, for example, the number of repetitions of LDPC code decoding (repetition decoding number C), LDPC code May be more limited than in the case of digital broadcasting for fixed terminals.
  • the present invention has been made in view of such a situation, and is intended to improve resistance to errors in data such as LDPC codes.
  • the data processing apparatus or the data processing method according to the first aspect of the present invention is written in the column direction of a storage means for storing code bits of an LDPC (Low Density Parity Check) code in the row direction and the column direction,
  • LDPC Low Density Parity Check
  • the code bit of the LDPC code read in the row direction is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, in the column direction of the storage unit
  • Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, and when the code length of the LDPC code is represented as N bits and the predetermined positive integer is represented as b, respectively,
  • the storage means includes: When mb bits are stored in the row direction, N / (mb) bits are stored in the column
  • the storage means has two columns for storing 2 ⁇ 1 bits in the row direction, the rearrangement means, or the The rearranging step sets the address of the first position in the column direction of the storage means to 0, and represents the address of each position in the column direction of the storage means as an integer in ascending order.
  • the first position in the first column Is a data processing apparatus or data processing method in which the address is a position of 0 and the write start position of the second column of the two columns of the storage means is the position of the address 14 .
  • the data processing apparatus or the data processing method according to the second aspect of the present invention is written in the column direction of the storage means for storing the code bits of the LDPC (Low Density Parity Check) code in the row direction and the column direction,
  • the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, and when the code length of the LDPC code is represented as N bits and the predetermined positive integer is represented as b, respectively,
  • the storage means includes: When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of
  • the write start position of the first column of the four columns of the storage means is the position where the address is 0
  • the write of the second column of the four columns of the storage means The starting position is the position where the address is 18
  • the writing start position of the third column of the four columns of the storage means is the position of the address 49
  • the four columns of the storage means This is a data processing apparatus or data processing method in which the write start position of the fourth column is the position where the address is 11.
  • the data processing device or the data processing method according to the third aspect of the present invention is written in the column direction of the storage means for storing the code bits of the LDPC (Low Density Parity Check) code in the row direction and the column direction,
  • the code bit of the LDPC code read in the row direction is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol, in the column direction of the storage unit,
  • Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, and when the code length of the LDPC code is represented as N bits and the predetermined positive integer is represented as b, respectively,
  • the storage means includes: When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb
  • the storage means has 6 columns storing 6 ⁇ 1 bits in the row direction, and the rearranging means or the The rearranging step sets the address of each position in the column direction of the storage unit to 0 in the column direction of the storage unit, and represents the address of each of the six columns of the storage unit when the address of each position in the column direction of the storage unit is expressed in an ascending integer
  • the first position in the first column The position of the address is 0, the writing start position of the second column of the 6 columns of the storage means is the position of the address 0, and the position of the 6 columns of the storage means
  • the write start position of the third column is the position where the address is 32, the write start position of the fourth column of the six columns of the storage means is the position of the address 13, and the storage means Of the six columns, the position where the fifth column starts writing is the position where the address is 8, and the position where the sixth column among the six columns of the storage means starts writing is the address
  • the data processing apparatus or the data processing method according to the fourth aspect of the present invention is written in the column direction of the storage means for storing the code bits of the LDPC (Low Density Parity Check) code in the row direction and the column direction,
  • the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, where the code means of the LDPC code is represented by N bits, and a predetermined positive integer is represented by b, respectively, the storage means,
  • N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of
  • the storage means has 8 columns storing 4 ⁇ 2 bits in the row direction, the rearrangement means, or the The rearranging step sets the address of the first position in the column direction of the storage means to 0, and represents the address of each position in the column direction of the storage means by an integer in ascending order.
  • the first position in the first column The position of the address is 0, the write start position of the second column of the 8 columns of the storage means is the position of the address 3, and the position of the 8 columns of the storage means
  • the write start position of the third column is the position of the address 18
  • the write start position of the fourth column of the 8 columns of the storage means is the position of the address 73
  • the storage means Of the 8 columns the 5th column write start position is the address 8 position
  • the 6th column write start position of the storage means 8 column is the address 14 position
  • the write start position of the seventh column of the eight columns of the storage means is the position of the address 6, and the eighth column of the eight columns of the storage means
  • a data processing device that sets the write start position to the position where the address is 8, or This is a data processing method.
  • the data processing apparatus or the data processing method according to the fifth aspect of the present invention is written in the column direction of the storage means for storing the code bits of the LDPC (Low Density Parity Check) code in the row direction and the column direction,
  • the column direction of the storage means is Reordering means for performing column twist interleaving for changing the writing start position when the code bits of the LDPC code are written for each column of the storage means as a reordering process for reordering the code bits of the LDPC code, or A reordering step, and when the code length of the LDPC code is represented as N bits and the predetermined positive integer is represented as b, respectively,
  • the storage means includes: When mb bits are stored in the row direction, N / (mb) bits are stored in the column direction, and the sign bits of the mb bits read in the row direction of
  • the storage means has 12 columns storing 6 ⁇ 2 bits in the row direction, and the rearranging means or the The rearranging step sets the address of the first position in the column direction of the storage means to 0, and represents the address of each position in the column direction of the storage means as an integer in ascending order.
  • the writing start position of the second column of the 12 columns of the storage means is the position of the address 0, and the position of the 12 columns of the storage means
  • the write start position of the third column is the address 0 position
  • the write start position of the fourth column of the 12 columns of the storage means is the address 0 position
  • the storage means Of the 12 columns the 5th column write start position is the address 32
  • the 6th column write start position of the storage means 12 columns is the address
  • the position of the seventh column of the 12 columns of the storage means is the position where the address is 87
  • the writing start position is the position where the address is 28, and the storage means
  • the write start position of the ninth column of the 12 columns is the position where the address is 31, and the write start position of the 10th column of the 12 columns of the storage means is the position where the address is 23.
  • the start position of the eleventh column of the twelve columns of the storage means is the position where the address is 5, and the write of the twelfth column of the twelve columns of the storage means.
  • the code bits of the LDPC (Low Density Parity Check) code are written in the column direction of the storage means for storing in the row direction and the column direction, and are read out in the row direction.
  • the code bit of the LDPC code is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol
  • the code of the LDPC code in the column direction of the storage means Column twist interleaving for changing the writing start position when bits are written for each column of the storage means is performed as a rearrangement process for rearranging the code bits of the LDPC code.
  • the storage unit stores mb bits in the row direction and N in the column direction. / (mb) bits are stored, and mb code bits read out in the row direction of the storage unit are set to b symbols.
  • the LDPC code is an LDPC code having a code length N of 4320 bits, the m bits is 2 bits, the integer b is 1, and 2 of the LDPC code.
  • the sign bit of the bits are mapped to one of 2 2 signal points prescribed in a predetermined modulation scheme.
  • the storage means has two columns for storing 2 ⁇ 1 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and the column direction of the storage means
  • the write start position of the first column of the two columns of the storage means is the position where the address is 0, and the two addresses of the storage means
  • the start position of writing the second column of the columns is the position where the address is 14.
  • the LDPC code is an LDPC code having a code length N of 4320 bits, the m bits is 2 bits, and the integer b is 2, or the m bits are 4 bits. a bit, and said integer b is 1, if the m bits are 2 bits, the sign bit of the 2 bits of the LDPC code, among the 2 2 signal points prescribed in a predetermined modulation scheme is mapped to one of, if the m bits are 4 bits, the sign bit of the 4 bits of the LDPC code are mapped to one of 2 4 signal points prescribed in a predetermined modulation scheme .
  • the storage means has 4 columns for storing 2 ⁇ 2 bits or 4 ⁇ 1 bits in the row direction, and the address of the head position in the column direction of the storage means is set to 0,
  • the write start position of the first column of the four columns of the storage means is the position where the address is 0,
  • the write start position of the second column of the four columns of the storage means is the position of the address 18, and the write start position of the third column of the four columns of the storage means
  • the address is the 49 position
  • the write start position of the 4th column among the 4 columns of the storage means is the 11 position.
  • the LDPC code is an LDPC code having a code length N of 4320 bits, the m bits is 6 bits, the integer b is 1, and the 6 bits of the LDPC code The code bit is mapped to any one of 26 signal points determined by a predetermined modulation method.
  • the storage means has six columns for storing 6 ⁇ 1 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and the column direction of the storage means
  • the write start position of the first column among the six columns of the storage means is the position where the address is 0, and the six addresses of the storage means
  • the write start position of the second column of the columns is the address 0 position
  • the write start position of the third column of the six columns of the storage means is the position of the address 32.
  • the write start position of the fourth column of the six columns of the storage means is the position of the address 13, and the write position of the fifth column of the six columns of the storage means
  • the starting position is the position where the address is 8, and the storage means 6 6 th writing starting position for the columns of the column address is set to the 0 position.
  • the LDPC code is an LDPC code having a code length N of 4320 bits, the m bits is 4 bits, the integer b is 2, and the LDPC code has 4 bits. code bits are mapped to one of 2 4 signal points prescribed in a predetermined modulation scheme.
  • the storage means has 8 columns for storing 4 ⁇ 2 bits in the row direction, the address of the head position in the column direction of the storage means is set to 0, and the column direction of the storage means
  • the write start position of the first column of the eight columns of the storage means is the position where the address is 0, and the eight addresses of the storage means
  • the write start position of the second column of the columns is the position of the address 3
  • the write start position of the third column of the eight columns of the storage means is the position of the address 18.
  • the write start position of the fourth column of the eight columns of the storage means is the position of the address 73, and the write of the fifth column of the eight columns of the storage means
  • the starting position is the position where the address is 8, and the storage means 8
  • the 6th column write start position is the 14th address
  • the 8th column of the storage means is the 7th column write start position is the 6th address.
  • the position at the beginning of writing of the eighth column among the eight columns of the storage means is the position where the address is 8.
  • the LDPC code is an LDPC code having a code length N of 4320 bits, the m bits is 6 bits, the integer b is 2, and the 6 bits of the LDPC code The code bit is mapped to any one of 26 signal points determined by a predetermined modulation method.
  • the storage means has 12 columns storing 6 ⁇ 2 bits in the row direction, and the address of the head position in the column direction of the storage means is set to 0, and the column direction of the storage means
  • the write start position of the first column among the 12 columns of the storage means is the position where the address is 0, and the 12 addresses of the storage means
  • the write start position of the second column of the columns is the address 0 position
  • the write start position of the third column of the 12 columns of the storage means is the position of the address 0
  • the write start position of the fourth column of the 12 columns of the storage means is the address 0 position
  • the write of the fifth column of the 12 columns of the storage means
  • the starting position is the position where the address is 32
  • the 6th column write start position of the 12 columns is the address 8 position
  • the 7th column write start position of the storage means 12 columns is the address Is the position of 87
  • the write start position of the eighth column of the 12 columns of the storage means is the position
  • a data processing device wherein the code bits of an LDPC (Low Density Parity Check) code are written in the column direction of the storage means for storing the code bits in the row direction and the column direction, and read out in the row direction.
  • LDPC Low Density Parity Check
  • the code bit of the LDPC code is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol
  • the code bit of the LDPC code in the column direction of the storage means Reordering means for performing column twist interleaving for changing the write start position for each column of the storage means as a reordering process for reordering the code bits of the LDPC code.
  • the storage means stores mb bits in the row direction, and
  • N / (mb) bits are stored in the ram direction and the code bits of the mb bits read out in the row direction of the storage means are b symbols
  • the LDPC code has a code length N of 4320 bits a LDPC code
  • the m bits are 2 bits and the integer b is 1, the sign bit of the 2 bits of the LDPC code, among the 2 2 signal points prescribed in a predetermined modulation scheme
  • the storage means has two columns for storing 2 ⁇ 1 bits in the row direction, and the rearrangement means sets the address of the head position in the column direction of the storage means to 0.
  • the write start position of the first column of the two columns of the storage means is the position where the address is 0.
  • the second column of the two columns of the storage means A data processing apparatus comprising a reverse rearrangement unit that performs reverse rearrangement processing for returning the original code bits after the rearrangement processing, which is obtained by a transmission device having an address of 14 as the writing start position is there.
  • a data processing device wherein the code bits of an LDPC (Low Density Parity Check) code are written in the column direction of the storage means for storing the code bits in the row direction and the column direction, and read out in the row direction.
  • LDPC Low Density Parity Check
  • the code bit of the LDPC code is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol
  • the code bit of the LDPC code in the column direction of the storage means Reordering means for performing column twist interleaving for changing the write start position for each column of the storage means as a reordering process for reordering the code bits of the LDPC code.
  • the storage means stores mb bits in the row direction, and
  • N / (mb) bits are stored in the ram direction and the code bits of the mb bits read out in the row direction of the storage means are b symbols
  • the LDPC code has a code length N of 4320 bits
  • the m bits are 2 bits, and the integer b is 2, or the m bits are 4 bits, and the integer b is 1, and the m bits are If it is 2 bits, the sign bit of the 2 bits of the LDPC code are mapped to one of 2 2 signal points prescribed in a predetermined modulation scheme, if the m bits are 4 bits, the sign bit of the 4 bits of the LDPC code are mapped to one of 2 4 signal points prescribed in a predetermined modulation method, wherein the storage unit, 2 ⁇ 2 bits in the row direction, or, 4 ⁇ 1 It has four columns for storing bits, and the sorting means is the storage means.
  • the data processing apparatus includes reverse rearrangement means for performing reverse rearrangement processing for returning the code bits after the rearrangement processing obtained in step 1 to the original order.
  • a data processing device wherein the code bits of an LDPC (Low Density Parity Check) code are written in the column direction of the storage means for storing the code bits in the row direction and the column direction, and read out in the row direction.
  • LDPC Low Density Parity Check
  • the code bit of the LDPC code is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol
  • the code bit of the LDPC code in the column direction of the storage means Reordering means for performing column twist interleaving for changing the write start position for each column of the storage means as a reordering process for reordering the code bits of the LDPC code.
  • the storage means stores mb bits in the row direction, and
  • N / (mb) bits are stored in the ram direction and the code bits of the mb bits read out in the row direction of the storage means are b symbols
  • the LDPC code has a code length N of 4320 bits a LDPC code
  • the m bits are 6 bits and the integer b is 1, the sign bit of the 6 bits of the LDPC code, among the 2 6 signal points prescribed in a predetermined modulation scheme
  • the storage means has 6 columns for storing 6 ⁇ 1 bits in the row direction, and the rearrangement means sets the address of the head position in the column direction of the storage means to 0.
  • the position where the first column of the six columns of the storage means starts writing is the position where the address is 0.
  • the second column of the six columns of the storage means The write start position is the position where the address is 0, and the write start position of the third column of the six columns of the storage means is the position where the address is 32, and the six positions of the storage means
  • the start position of the fourth column of the columns is the position where the address is 13, and the start position of the fifth column of the six columns of the storage means is the position of the address 8.
  • the code bits after the reordering process obtained by the transmitting apparatus having the address at the start of writing of the sixth column of the six columns of the storage means as the original sequence are returned. It is a data processing apparatus provided with the reverse rearrangement means which performs a reverse rearrangement process.
  • a data processing device wherein the code bits of an LDPC (Low Density Parity Check) code are written in the column direction of the storage means for storing the code bits in the row direction and the column direction, and read out in the row direction.
  • the code bit of the LDPC code is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol
  • the code bit of the LDPC code in the column direction of the storage means Reordering means for performing column twist interleaving for changing the write start position for each column of the storage means as a reordering process for reordering the code bits of the LDPC code.
  • the storage means stores mb bits in the row direction, and
  • N / (mb) bits are stored in the ram direction and the code bits of the mb bits read out in the row direction of the storage means are b symbols
  • the LDPC code has a code length N of 4320 bits a LDPC code
  • the m bits are 4 bits and the integer b is 2, the sign bit of the 4 bits of the LDPC code, out of 2 4 signal points prescribed in a predetermined modulation scheme
  • the storage means has 8 columns for storing 4 ⁇ 2 bits in the row direction, and the rearrangement means sets the address of the head position in the column direction of the storage means to 0.
  • the position where the first column of the eight columns of the storage means starts writing is the position where the address is 0.
  • the second column of the eight columns of the storage means The write start position is the position where the address is 3
  • the write start position of the third column of the 8 columns of the storage means is the position of the address 18, and the 8 positions of the storage means
  • the write start position of the fourth column of the columns is the address 73
  • the write start position of the fifth column of the eight columns of the storage means is the position of the address 8.
  • the writing start position of the sixth column of the eight columns of the storage means is the position of the address 14, and the writing start position of the seventh column of the eight columns of the storage means ,
  • the address is 6 position, and the writing start position of the 8th column of the 8 columns of the storage means is obtained by the transmitting apparatus having the address 8 position.
  • Reverse order that performs reverse rearrangement processing to return the sign bit back to the original A data processing apparatus including a replacement unit.
  • a data processing apparatus is a data processing device for writing code bits of an LDPC (Low Density Parity Check) code in the column direction of the storage means for storing the code bits in the row direction and the column direction, and reading the code bits in the row direction.
  • LDPC Low Density Parity Check
  • the code bit of the LDPC code is a symbol, and m code bits of 2 bits or more of the LDPC code are transmitted as one symbol
  • the code bit of the LDPC code in the column direction of the storage means Reordering means for performing column twist interleaving for changing the write start position for each column of the storage means as a reordering process for reordering the code bits of the LDPC code.
  • the storage unit stores mb bits in the row direction, and
  • N / (mb) bits are stored in the column direction and the code bits of the mb bits read in the row direction of the storage means are b symbols
  • the LDPC code has a code length N of 4320 bits a LDPC code
  • the m bits are 6 bits and the integer b is 2, the sign bit of the 6 bits of the LDPC code, among the 2 6 signal points prescribed in a predetermined modulation scheme
  • the storage means has 12 columns storing 6 ⁇ 2 bits in the row direction, and the rearrangement means sets the address of the head position in the column direction of the storage means to 0.
  • the position where the first column of the 12 columns of the storage means starts writing is the position where the address is 0.
  • the second column of the 12 columns of the storage means The ram writing start position is the position where the address is 0, and the writing start position of the third column of the 12 columns of the storage means is the position where the address is 0, and the 12 positions of the storage means
  • the write start position of the fourth column of the columns is the position where the address is 0,
  • the write start position of the fifth column of the 12 columns of the storage means is the position of the address 32
  • the position where the sixth column of the 12 columns of the storage means starts to be written is the position where the address is 8, and the position where the 7th column of the 12 columns of the storage means starts writing.
  • the position is the position where the address is 87
  • the writing start position of the eighth column among the 12 columns of the storage means is the position where the address is 28, and the position of the 12 columns of the storage means
  • the start position of the ninth column is the position where the address is 31.
  • the write start position of the 10th column of the 12 columns of the storage means is the position of the address 23, and the write start position of the 11th column of the 12 columns of the storage means ,
  • the address is 5 position
  • the writing start position of the twelfth column of the 12 columns of the storage means is obtained by the transmitting device having the address position 3. It is a data processing apparatus provided with reverse rearrangement means for performing reverse rearrangement processing for returning code bits to their original order.
  • the reverse rearrangement process for obtaining the original rearranged code bits obtained in the first aspect is performed.
  • the reverse rearrangement process for obtaining the original code bits after the rearrangement process obtained in the second aspect is performed.
  • the reverse rearrangement process for obtaining the original rearranged code bits obtained in the third aspect is performed.
  • the reverse rearrangement process for obtaining the original rearranged code bits obtained in the fourth aspect is performed.
  • the reverse rearrangement process for obtaining the original rearranged code bits obtained in the fifth aspect is performed.
  • the data processing apparatus may be an independent apparatus or an internal block constituting one apparatus.
  • FIG. 3 is a block diagram illustrating a configuration example of a transmission device 11.
  • FIG. 3 is a block diagram illustrating a configuration example of a bit interleaver 116.
  • FIG. It is a figure which shows a check matrix.
  • FIG. 6 is a diagram for explaining processing of a demultiplexer 25.
  • FIG. 6 is a diagram for explaining processing of a demultiplexer 25.
  • FIG. 10 is a flowchart for explaining processing performed by a bit interleaver 116 and a QAM encoder 117. It is a figure which shows the model of the communication path employ
  • An error rate obtained by the simulation is a diagram showing the relationship between the Doppler frequency f d of the flutter.
  • An error rate obtained by the simulation is a diagram showing the relationship between the Doppler frequency f d of the flutter.
  • 3 is a block diagram illustrating a configuration example of an LDPC encoder 115.
  • FIG. 5 is a flowchart for explaining processing of an LDPC encoder 115. [Fig. 38] Fig.
  • Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/4 and the code length 16200. It is a figure explaining the method of calculating
  • Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/4 and the code length 4320.
  • Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with an encoding rate of 1/3 and a code length of 4320.
  • Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 5/12 and the code length 4320.
  • FIG. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/2 and the code length 4320.
  • Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 7/12 and the code length 4320.
  • Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 2/3 and the code length 4320.
  • Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 3/4 and the code length 4320.
  • Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 5/6 and the code length 4320.
  • Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 11/12 and the code length 4320. It is a figure which shows the example of the Tanner graph of the ensemble of a degree sequence that column weight is 3 and row weight is 6. FIG. It is a figure which shows the example of the Tanner graph of a multi-edge type ensemble.
  • Fig. 38 is a diagram illustrating a minimum cycle length and a performance threshold value of a parity check matrix of an LDPC code having a code length 4320.
  • Fig. 38] Fig. 38 is a diagram illustrating a parity check matrix of an LDPC code having a code length of 4320.
  • Fig. 38] Fig. 38 is a diagram illustrating a parity check matrix of an LDPC code having a code length of 4320.
  • FIG. 38 is a diagram illustrating a parity check matrix of an LDPC code having a code length of 4320. It is a figure which shows the number of columns of the memory 31 required for column twist interleaving, and the address of the write start position. It is a figure which shows the simulation result of BER at the time of performing column twist interleaving. It is a figure explaining the exchange process of the present system. It is a figure explaining the exchange process of the present system. It is a figure explaining the exchange process of the present system.
  • FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM and a multiple b is 2.
  • FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM and a multiple b is 2.
  • FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM and a multiple b is 2.
  • FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 64QAM and a multiple b is 2.
  • FIG. 10 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 64QAM and a multiple b is 2.
  • Fig. 11 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 64QAM and the multiple b is 2.
  • FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 5/12 is modulated by 64QAM and a multiple b is 2.
  • Fig. 11 Fig. 11 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 64QAM and a multiple b is 2.
  • FIG. 10 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 64QAM and a multiple b is 2.
  • Fig. 12 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 12 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 11 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 64QAM and a multiple b is 2.
  • Fig. 12 Fig. 12 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 64QAM and a multiple b is 2.
  • FIG. 10 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 2/3 is modulated by 64QAM and a multiple b is 2.
  • FIG. 6 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 3/4 is modulated by 64QAM and a multiple b is 2.
  • Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 64QAM and a multiple b is 2.
  • FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 64QAM and a multiple b is 2.
  • Fig. 10 Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 64QAM and a multiple b is 2.
  • FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 64QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 64QAM and a multiple b is 2.
  • FIG. 5 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 16QAM and a multiple b is 2.
  • FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 16QAM and a multiple b is 2.
  • FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 16QAM and a multiple b is 2.
  • FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 16QAM and a multiple b is 2.
  • FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 16QAM and a multiple b is 2.
  • FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 12 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 16QAM and a multiple b is 2.
  • Fig. 10 Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 16QAM and a multiple b is 2.
  • FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 1/2 is modulated by 16QAM and a multiple b is 2.
  • Fig. 10 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 16QAM and a multiple b is 2.
  • FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 16QAM and a multiple b is 2.
  • FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 16QAM and a multiple b is 2.
  • FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and an encoding rate of 2/3 is modulated by 16QAM and a multiple b is 2.
  • FIG. 3 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 16QAM and a multiple b is 2.
  • FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 16QAM and a multiple b is 2.
  • FIG. 7 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 16QAM and the multiple b is 2.
  • FIG. 11 is a diagram illustrating an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 16QAM and a multiple b is 2.
  • FIG. 4 is a diagram illustrating a code bit group and a symbol bit group when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 16QAM and a multiple b is 2.
  • FIG. 11 is a diagram showing an allocation rule when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 10 is a diagram illustrating code bit replacement according to an allocation rule when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 16QAM and a multiple b is 2.
  • FIG. 7 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 7 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 7 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 64QAM, and a multiple b is 2. [Fig. 10] Fig.
  • FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 64QAM, and a multiple b is 2.
  • FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/4 is modulated by 16QAM, and a multiple b is 2.
  • FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/3 is modulated by 16QAM, and a multiple b is 2.
  • FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 5/12 is modulated by 16QAM, and a multiple b is 2.
  • FIG. 10 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 1/2 is modulated by 16QAM, and a multiple b is 2.
  • FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 7/12 is modulated by 16QAM, and a multiple b is 2.
  • FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 2/3 is modulated by 16QAM, and a multiple b is 2.
  • FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 3/4 is modulated by 16QAM, and a multiple b is 2.
  • FIG. 6 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 5/6 is modulated by 16QAM, and a multiple b is 2.
  • FIG. 11 is a diagram illustrating a BER simulation result when an LDPC code having a code length of 4k and a coding rate of 11/12 is modulated by 16QAM, and a multiple b is 2.
  • Fig. 38 Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 1/2 and the code length 4320.
  • Fig. 38] Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 7/12 and the code length 4320.
  • Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 2/3 and the code length 4320.
  • Fig. 38 is a diagram illustrating an example of a parity check matrix initial value table with the code rate 3/4 and the code length 4320.
  • Fig. 38 is a diagram illustrating a minimum cycle length and a performance threshold value of a parity check matrix of an LDPC code having a code length 4320.
  • Fig. 38] Fig. 38 is a diagram illustrating a parity check matrix of an LDPC code having a code length of 4320. It is a figure which shows the simulation result of BER.
  • FIG. It is a figure which shows a code bit group and a symbol bit group when the 2nd 4k code
  • FIG. It is a figure which shows the allocation rule when the 2nd 4k code
  • FIG. It is a figure which shows replacement
  • FIG. It is a figure which shows a code
  • FIG. It is a figure which shows the allocation rule when the 2nd 4k code
  • FIG. It is a figure which shows replacement
  • FIG. It is a figure which shows a code bit group and a symbol bit group in case the 2nd 4k code of coding rate 2/3 is modulated by 16QAM, and the multiple b is 2.
  • FIG. It is a figure which shows replacement
  • FIG. It is a figure which shows a code bit group and a symbol bit group when the 2nd 4k code
  • FIG. It is a figure which shows the allocation rule in case the 2nd 4k code
  • FIG. It is a figure which shows replacement
  • FIG. 12 is a flowchart for describing processing performed by a QAM decoder 164, a bit deinterleaver 165, and an LDPC decoder 166.
  • FIG. 3 is a block diagram illustrating a configuration example of an LDPC decoder 166.
  • FIG. It is a figure explaining the process of the multiplexer 54 which comprises the bit deinterleaver 165.
  • FIG. It is a figure explaining the process of the column twist deinterleaver.
  • FIG. 165 shows the other structural example of the bit deinterleaver 165.
  • FIG. 7 is a diagram of a transmission system to which the present invention is applied (a system refers to a logical collection of a plurality of devices, regardless of whether or not each configuration device is in the same housing). The structural example of embodiment is shown.
  • the transmission system includes a transmission device 11 and a reception device 12.
  • the transmission device 11 transmits (broadcasts) (transmits) programs for fixed terminals and portable terminals. That is, the transmission device 11 encodes target data to be transmitted, such as image data and audio data as a program for a fixed terminal or a portable terminal, into an LDPC code, for example, a communication channel that is a terrestrial wave 13 to transmit.
  • target data to be transmitted such as image data and audio data as a program for a fixed terminal or a portable terminal
  • an LDPC code for example, a communication channel that is a terrestrial wave 13 to transmit.
  • the receiving device 12 is, for example, a portable terminal, receives an LDPC code transmitted from the transmitting device 11 via the communication path 13, decodes it into target data, and outputs it.
  • the LDPC code used in the transmission system of FIG. 7 exhibits extremely high capability in an AWGN (Additive White Gaussian Noise) channel.
  • AWGN Additional White Gaussian Noise
  • a burst error or erasure may occur in the communication path 13 such as terrestrial waves.
  • echo Orthogonal-Frequency-Division-Multiplexing
  • D / U Desired-to-Undesired-Ratio
  • Desired main path power
  • a burst error may occur due to the state of the wiring from the receiving unit (not shown) such as an antenna that receives a signal from the transmitting device 11 to the receiving device 12 on the receiving device 12 side or the instability of the power supply of the receiving device 12. May occur.
  • the code bit (received value u 0i of the LDPC code) at the variable node corresponding to the column of the parity check matrix H and thus the code bit of the LDPC code. Since the variable node operation of the expression (1) with the addition of) is performed, if an error occurs in the sign bit used for the variable node operation, the accuracy of the required message is reduced.
  • the check node performs the check node calculation of Expression (7) using the message obtained by the variable node connected to the check node, so that a plurality of connected variable nodes ( When the number of check nodes in which the error (including erasure) of the code bits of the LDPC code corresponding to) simultaneously increases, the decoding performance deteriorates.
  • the check node sends a message with an equal probability of a probability of 0 and a probability of 1 to all the variable nodes. return.
  • a check node that returns an equiprobable message does not contribute to one decoding process (one set of variable node calculation and check node calculation), and as a result, requires a large number of repetitions of the decoding process. As a result, the decoding performance deteriorates, and the power consumption of the receiving apparatus 12 that decodes the LDPC code increases.
  • the transmission system of FIG. 7 is designed to improve the tolerance to burst errors and erasures while maintaining the performance on the AWGN communication path.
  • FIG. 8 is a block diagram illustrating a configuration example of the transmission device 11 of FIG.
  • one or more input streams (Input Streams) as target data are supplied to a Mode Adaptation / Multiplexer 111.
  • the mode adaptation / multiplexer 111 selects a mode and multiplexes one or more input streams supplied thereto, and supplies data obtained as a result to a padder 112.
  • the padder 112 performs necessary zero padding (Null insertion) on the data from the mode adaptation / multiplexer 111 and supplies the resulting data to the BB scrambler 113.
  • the BB scrambler 113 performs energy diffusion processing on the data from the padder 112 and supplies data obtained as a result to a BCH encoder 114.
  • the BCH encoder 114 BCH-encodes the data from the BB scrambler 113, and supplies the resulting data to an LDPC encoder 115 as LDPC target data that is an LDPC encoding target.
  • the LDPC encoder 115 performs LDPC encoding on the LDPC target data from the BCH encoder 114 according to a parity check matrix in which a parity matrix that is a part corresponding to the parity bits of the LDPC code has a staircase structure. Output LDPC code as information bits.
  • the LDPC encoder 115 performs LDPC encoding for encoding LDPC target data into an LDPC code such as an LDPC code defined in the DVB-T.2 standard, and outputs the resulting LDPC code. To do.
  • the LDPC code defined in the DVB-S.2 standard is adopted except when the code length is 16200 bits and the coding rate is 3/5. .
  • the LDPC code defined in the DVB-T.2 standard is an IRA (Irregular Repeat Accumulate) code, and the parity matrix in the parity check matrix of the LDPC code has a staircase structure. The parity matrix and the staircase structure will be described later.
  • IRA codes for example, “Irregular Repeat-Accumulate Codes,” H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics-8 , Sept. 2000.
  • the LDPC code output from the LDPC encoder 115 is supplied to the bit interleaver 116.
  • the bit interleaver 116 performs bit interleaving described later on the LDPC code from the LDPC encoder 115, and supplies the LDPC code after the bit interleaving to a QAM encoder (QAM encoder) 117.
  • QAM encoder QAM encoder
  • the QAM encoder 117 maps the LDPC code from the bit interleaver 116 to a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol unit) of the LDPC code and performs orthogonal modulation ( Multilevel modulation).
  • the QAM encoder 117 converts the LDPC code from the bit interleaver 116 into an IQ plane (IQ constellation) defined by an I axis representing an I component in phase with the carrier and a Q axis representing a Q component orthogonal to the carrier. ) Perform the quadrature modulation by mapping to the signal points determined by the modulation method that performs the quadrature modulation of the LDPC code.
  • IQ plane IQ constellation
  • a modulation method of orthogonal modulation performed by the QAM encoder 117 for example, a modulation method including a modulation method defined in the DVB-T standard, that is, for example, QPSK (QuadraturerPhase Shift Keying), 16QAM (Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc.
  • QPSK QuadratturerPhase Shift Keying
  • 16QAM Quadadrature Amplitude Modulation
  • 64QAM 64QAM
  • 256QAM 256QAM
  • 1024QAM 1024QAM
  • 4096QAM a modulation method including a modulation method defined in the DVB-T standard, that is, for example, QPSK (QuadraturerPhase Shift Keying), 16QAM (Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc.
  • Time Interleaver Time Interleaver
  • the time interleaver 118 performs time interleaving (interleaving in the time direction) in units of symbols on the data (symbols) from the QAM encoder 117, and obtains the resulting data as a MISO / MIMO encoder (MISO / MIMO encoder) 119. To supply.
  • the MISO / MIMO encoder 119 performs space-time coding on the data (symbol) from the time interleaver 118 and supplies it to a frequency interleaver 120.
  • the frequency interleaver 120 performs frequency interleaving (interleaving in the frequency direction) for each data (symbol) from the MISO / MIMO encoder 119 and supplies the data to a frame builder / resource allocation unit (Frame Builder & Resource Allocation) 131. To do.
  • the BCH encoder 121 is supplied with control data (signalling) for transmission control such as a preamble called L1 or the like.
  • the BCH encoder 121 performs BCH encoding on the control data supplied thereto in the same manner as the BCH encoder 114, and supplies the resulting data to the LDPC encoder 122.
  • the LDPC encoder 122 performs LDPC encoding on the data from the BCH encoder 121 as LDPC target data in the same manner as the LDPC encoder 115, and supplies the resulting LDPC code to the QAM encoder 123.
  • the QAM encoder 123 converts the LDPC code from the LDPC encoder 122 into a signal point representing one symbol of orthogonal modulation in units of one or more code bits (symbol unit) of the LDPC code.
  • the orthogonal modulation is performed by mapping, and data (symbol) obtained as a result is supplied to the frequency interleaver 124.
  • the frequency interleaver 124 performs frequency interleaving on the data (symbol) from the QAM encoder 123 in units of symbols and supplies the data to the frame builder / resource allocation unit 131.
  • the frame builder / resource allocation unit 131 inserts pilot symbols at necessary positions of the data (symbols) from the frequency interleavers 120 and 124, and from the resulting data (symbols), a predetermined number A frame composed of a number of symbols is constructed and supplied to an OFDM generation unit 132.
  • the OFDM generation unit 132 generates an OFDM signal corresponding to the frame from the frame from the frame builder / resource allocation unit 131, and transmits the OFDM signal via the communication path 13 (FIG. 7).
  • FIG. 9 shows a configuration example of the bit interleaver 116 of FIG.
  • the bit interleaver 116 is a data processing device that interleaves data, and includes a parity interleaver 23, a column twist interleaver 24, and a demultiplexer (DEMUX) 25.
  • the parity interleaver 23 performs parity interleaving for interleaving the parity bits of the LDPC code from the LDPC encoder 115 to the positions of other parity bits, and supplies the LDPC code after the parity interleaving to the column twist interleaver 24.
  • the column twist interleaver 24 performs column twist interleaving on the LDPC code from the parity interleaver 23 and supplies the LDPC code after the column twist interleaving to the demultiplexer 25.
  • the LDPC code is transmitted in the QAM encoder 117 of FIG. 8 by mapping one or more code bits of the LDPC code to a signal point representing one symbol of orthogonal modulation.
  • the column twist interleaver 24 uses a parity interleaver 23 so that a plurality of code bits of the LDPC code corresponding to 1 in any one row of the parity check matrix used in the LDPC encoder 115 are not included in one symbol. As rearrangement processing for rearranging the code bits of the LDPC code, for example, column twist interleaving as described later is performed.
  • the demultiplexer 25 performs an exchange process for exchanging positions of two or more code bits of the LDPC code as a symbol for the LDPC code from the column twist interleaver 24 to obtain an LDPC code with enhanced resistance to AWGN. Then, the demultiplexer 25 supplies two or more code bits of the LDPC code obtained by the replacement process to the QAM encoder 117 (FIG. 8) as a symbol.
  • FIG. 10 shows a parity check matrix H used for LDPC encoding by the LDPC encoder 115 of FIG.
  • LDGM Low-Density Generation Matrix
  • the number of information bits and the number of parity bits in the code bits of one LDPC code are referred to as information length K and parity length M, respectively, and one LDPC.
  • the information length K and the parity length M for an LDPC code having a certain code length N are determined by the coding rate.
  • the parity check matrix H is an M ⁇ N matrix with rows ⁇ columns. Then, the information matrix H A, becomes the matrix of M ⁇ K, the parity matrix H T is a matrix of M ⁇ M.
  • Figure 11 illustrates a parity matrix H T of the parity DVB-T.2 (and DVB-S.2) check matrix H of an LDPC code prescribed in the standard of.
  • the row weight of the parity matrix H T is 1 for the first row and 2 for all the remaining rows.
  • the column weight is 1 for the last column and 2 for all the remaining columns.
  • LDPC codes of the check matrix H the parity matrix H T has a staircase structure can be using the check matrix H, readily produced.
  • an LDPC code (one codeword), together represented by a row vector c, and column vector obtained by transposing the row vector is represented as c T. Further, in the row vector c which is an LDPC code, the information bit portion is represented by the row vector A, and the parity bit portion is represented by the row vector T.
  • FIG. 12 is a diagram for explaining the parity check matrix H of the LDPC code defined in the DVB-T.2 standard.
  • the column weight is X
  • the subsequent K3 column is the column weight 3
  • the subsequent The column weight is 2 for the M-1 column
  • the column weight is 1 for the last column.
  • KX + K3 + M-1 + 1 is equal to the code length N.
  • FIG. 13 is a diagram showing the number of columns KX, K3, and M and the column weight X for each coding rate r of the LDPC code defined in the DVB-T.2 standard.
  • the DVB-T.2 standard specifies LDPC codes with a code length of 64800 bits and 16200 bits.
  • LDPC code having a code length N of 64,800 bits 11 coding rates (nominal rates) 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3 / 4, 4/5, 5/6, 8/9, and 9/10 are defined, and for an LDPC code having a code length N of 16200 bits, 10 coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are specified.
  • the code length N of 64800 bits is also referred to as 64k bits
  • the code length N of 16200 bits is also referred to as 16k bits.
  • the column weight on the head side (left side) tends to be large.
  • the LDPC code corresponding to there is a tendency that the first code bit is more resistant to errors (is more resistant to errors), and the last code bit is more vulnerable to errors.
  • FIG. 14 shows an arrangement on the IQ plane of 16 symbols (corresponding signal points) when 16QAM is performed by the QAM encoder 117 of FIG.
  • a in FIG. 14 shows a 16QAM symbol of DVB-T.2.
  • the 16 symbols are arranged so that the I direction ⁇ Q direction is a 4 ⁇ 4 square shape with the origin of the IQ plane as the center.
  • bit y i + 1 bit from the most significant bit in the bit string represented by one symbol is represented as bit y i
  • the four bits represented by one symbol of 16QAM are bit y 0 in order from the most significant bit. , y 1 , y 2 , y 3 .
  • 4 code bits of the LDPC code is (symbolized) into 4-bit y 0 to y 3 symbol (symbol value).
  • FIG. 14B shows bit boundaries for each of 4 bits (hereinafter also referred to as symbol bits) y 0 to y 3 represented by a 16QAM symbol.
  • the symbol bit y i represented by a symbol is more likely to be erroneous (lower error probability) as there are more symbols far from the bit boundary, and more likely to be erroneous (higher error probability) as there are more symbols near the bit boundary.
  • strong to errors a bit that is hard to error
  • weak to errors a bit that is easy to error
  • 4 symbol bits y 0 to y 3 of a 16QAM symbol 4 symbol bits y 0 to y 3 of a 16QAM symbol .
  • the most significant symbol bit y 0 and the second symbol bit y 1 are strong bits
  • the third symbol bit y 2 and the fourth symbol bit y 3 are weak bits. .
  • 15 to 17 show the arrangement of 64 symbols (corresponding signal points) on the IQ plane when 64QAM is performed by the QAM encoder 117 of FIG. 8, that is, DVB-T.2 16QAM symbols. Is shown.
  • One symbol bit of 64QAM can be expressed as bits y 0 , y 1 , y 2 , y 3 , y 4 , y 5 in order from the most significant bit.
  • the 6 code bits of the LDPC code are the symbol bit y 0 no 6-bit to the symbol y 5.
  • FIG. 15 shows bit boundaries for the most significant symbol bit y 0 and the second symbol bit y 1 among the symbol bits y 0 to y 5 of the 64QAM symbol, and FIG. th symbol bit y 2, the bit boundaries for the fourth symbol bit y 3, respectively, FIG. 17, the fifth symbol bit y 4, the bit boundaries for the sixth symbol bit y 5, respectively, each Show.
  • the symbol bits y 0 of the uppermost bit boundaries for the second symbol bit y 1, respectively, has at one place. Also, as shown in FIG. 16, there are two bit boundaries for each of the third symbol bit y 2 and the fourth symbol bit y 3 , and as shown in FIG. 17, the fifth symbol bit There are four bit boundaries for bit y 4 and sixth symbol bit y 5 .
  • the most significant symbol bit y 0 and the second symbol bit y 1 are strong bits, and the third symbol bits y 2 and 4 th symbol bit y 3 has become a strong bit to the next.
  • the fifth symbol bit y 4 and the sixth symbol bit y 5 are weak bits.
  • the LDPC code output from the LDPC encoder 115 includes a code bit that is resistant to errors and a code bit that is vulnerable to errors.
  • the symbol bits of the orthogonal modulation symbols performed by the QAM encoder 117 include strong bits and weak bits.
  • an interleaver for interleaving the code bits of the LDPC code has been proposed in which the code bits vulnerable to errors of the LDPC code are assigned to the strong bits (symbol bits) of the orthogonal modulation symbol.
  • FIG. 18 is a diagram for explaining the processing of the demultiplexer 25 in FIG.
  • a in FIG. 18 shows a functional configuration example of the demultiplexer 25.
  • the demultiplexer 25 includes a memory 31 and a replacement unit 32.
  • the memory 31 is supplied with the LDPC code from the LDPC encoder 115.
  • the memory 31 has a storage capacity for storing mb bits in the row (horizontal) direction and N / (mb) bits in the column (vertical) direction, and the LDPC supplied thereto The sign bit of the code is written in the column direction, read in the row direction, and supplied to the switching unit 32.
  • N information length K + parity length M
  • m represents the number of code bits of an LDPC code that is one symbol
  • b is a predetermined positive integer, which is a multiple used to multiply m by an integer.
  • the demultiplexer 25 uses the sign bit of the LDPC code as a symbol (symbolizes), and the multiple b represents the number of symbols obtained by the demultiplexer 25 by one-time symbolization.
  • FIG. 18A shows a configuration example of the demultiplexer 25 when the modulation scheme is 64QAM. Therefore, the number m of code bits of the LDPC code that is one symbol is 6 bits.
  • the multiple b is 1, and therefore the memory 31 has a storage capacity of N / (6 ⁇ 1) ⁇ (6 ⁇ 1) bits in the column direction ⁇ row direction.
  • the storage area of the memory 31 extending in the column direction and having a 1-bit row direction is hereinafter referred to as a column as appropriate.
  • the code bits of the LDPC code are written from the top to the bottom (column direction) of the columns constituting the memory 31 from the left to the right columns.
  • the sign bit When writing of the sign bit is completed to the bottom of the rightmost column, the sign bit is changed in units of 6 bits (mb bits) in the row direction from the first row of all the columns constituting the memory 31. It is read out and supplied to the replacement unit 32.
  • the exchanging unit 32 performs an exchanging process of exchanging the positions of the 6-bit code bits from the memory 31, and the 6 bits obtained as a result are replaced with 6 symbol bits y 0 , y 1 , y 2 , y representing one symbol of 64QAM. Output as 3 , y 4 , y 5 .
  • mb bits (6 bits in this case) of code bits are read from the memory 31 in the row direction, and the i-th bit from the most significant bit of the mb bits of code bits read from the memory 31 is read out.
  • bit b i the 6-bit code bits read out from the memory 31 in the row direction are bits b 0 , It can be expressed as b 1 , b 2 , b 3 , b 4 , b 5 .
  • the sign bit in the direction of bit b 0 is a sign bit that is resistant to errors in the relationship of the column weights described in FIGS. 12 and 13, and the sign bit in the direction of bit b 5 is a sign that is vulnerable to errors. It is a bit.
  • the 6-bit code bits b 0 to b 5 from the memory 31 are assigned the error-sensitive code bits to the strong bits of the 64QAM 1-symbol symbol bits y 0 to y 5. As shown in the figure, it is possible to perform a replacement process for replacing the positions of the 6-bit code bits b 0 to b 5 from the memory 31.
  • FIG. 18B shows the first replacement method
  • FIG. 18C shows the second replacement method
  • FIG. 18D shows the third replacement method.
  • FIG. 19 shows a case where the modulation scheme is 64QAM (therefore, the number m of code bits of the LDPC code mapped to one symbol is 6 bits as in FIG. 18) and the multiple b is 2.
  • the demultiplexer 25 and a fourth replacement method are shown.
  • FIG. 19A shows the order of writing LDPC codes to the memory 31.
  • the code bits of the LDPC code are written from the upper side to the lower side (column direction) of the columns constituting the memory 31. Is called.
  • the sign bit When the writing of the sign bit is completed to the bottom of the rightmost column, the sign bit is set in units of 12 bits (mb bits) in the row direction from the first row of all the columns constituting the memory 31. It is read out and supplied to the replacement unit 32.
  • the exchanging unit 32 performs an exchanging process of exchanging the positions of the 12-bit code bits from the memory 31 by the fourth exchanging method, and the 12 bits obtained as a result represent 2 symbols (b symbols) of 64QAM. 12 bits, that is, 6 symbol bit y 0 representing a symbol of 64QAM, y 1, y 2, y 3, y 4, and y 5, 6 symbol bits y 0 representing the next one symbol, y 1, y 2 , y 3 , y 4 , y 5
  • B of FIG. 19 shows a fourth replacement method of the replacement processing by the replacement unit 32 of A of FIG.
  • mb code bits are allocated to mb symbol bits of b consecutive symbols.
  • bit (symbol bit) y i the i + 1-th bit from the most significant bit of the mb bits of b consecutive symbols.
  • parity interleaving by the parity interleaver 23 in FIG. 9 will be described with reference to FIGS.
  • FIG. 20 shows (part of) a Tanner graph of a parity check matrix of an LDPC code.
  • variable nodes corresponding code bits
  • all the check nodes are connected to the check node.
  • a message having a probability that the value is 0 and the probability that the value is 1 is returned to the variable node. For this reason, if a plurality of variable nodes connected to the same check node simultaneously become erasures or the like, the decoding performance deteriorates.
  • LDPC encoder 115 of FIG. 8 outputs, LDPC code prescribed in the standard of DVB-T.2 is the IRA code, parity matrix H T of the parity check matrix H, as shown in FIG. 11 It has a staircase structure.
  • FIG. 21 shows a parity matrix H T having a staircase structure and a Tanner graph corresponding to the parity matrix H T.
  • a of FIG. 21 shows a parity matrix H T having a staircase structure
  • B of FIG. 21 shows a Tanner graph corresponding to the parity matrix H T of A of FIG.
  • parity matrix H T has a staircase structure, in each row (except the first row) first element is adjacent. Therefore, in the Tanner graph of the parity matrix H T, the value of the parity matrix H T corresponding to the columns of two adjacent elements are set to 1, the two variable nodes adjacent, connected to the same check node Yes.
  • the parity bits corresponding to the two adjacent variable nodes mentioned above simultaneously become an error due to a burst error, an erasure, or the like, two variable nodes corresponding to the two parity bits in error (using the parity bit). Since the check node connected to the variable node that seeks the message returns the message having the same probability of 0 and 1 to the variable node connected to the check node, the decoding performance is improved. to degrade. When the burst length (the number of parity bits that continuously cause an error) increases, the number of check nodes that return messages with equal probability increases, and the decoding performance further deteriorates.
  • the parity interleaver 23 (FIG. 9) performs parity interleaving for interleaving the parity bits of the LDPC code from the LDPC encoder 115 to the positions of other parity bits in order to prevent the above-described degradation in decoding performance. .
  • Figure 22 illustrates a parity matrix H T of the parity check matrix H corresponding to the LDPC code after parity interleave to the parity interleaver 23 of FIG. 9 is performed.
  • the information matrix H A of the parity check matrix H corresponding to the LDPC code defined in the DVB-T.2 standard and output from the LDPC encoder 115 has a cyclic structure.
  • a cyclic structure is a structure in which a column matches a cyclic shift of another column.For example, for each P column, the position of 1 in each row of the P column is the first of the P column.
  • a structure in which the column is cyclically shifted in the column direction by a value proportional to the value q obtained by dividing the parity length M is also included.
  • the P column in the cyclic structure is referred to as the number of columns in the cyclic structure unit as appropriate.
  • the LDPC code defined in the DVB-T.2 standard includes two types of LDPC codes having a code length N of 64800 bits and 16200 bits.
  • N 64800 bits
  • 16200 bits 16200 bits.
  • the number P of columns in the unit of the cyclic structure is defined as 360 which is one of the divisors excluding 1 and M among the divisors of the parity length M.
  • the parity interleaver 23 sets the information length to K, sets x to an integer between 0 and less than P, and sets y to an integer between 0 and less than q.
  • the K + qx + y + 1-th code bit is interleaved at the position of the K + Py + x + 1-th code bit.
  • the K + qx + y + 1-th code bit and the K + Py + x + 1-th code bit are both the K + 1-th code bit and the subsequent parity bits, and are therefore parity bits. According to interleaving, the position of the parity bit of the LDPC code is moved.
  • variable nodes connected to the same check node are separated by the number of columns P of the cyclic structure unit, that is, 360 bits here, so the burst length is In the case of less than 360 bits, it is possible to avoid a situation in which a plurality of variable nodes connected to the same check node cause an error at the same time, and as a result, it is possible to improve resistance to burst errors.
  • the LDPC code after parity interleaving that interleaves the K + qx + y + 1-th code bit at the position of the K + Py + x + 1-th code bit is K + qx + of the original parity check matrix H.
  • the pseudo cyclic structure means a structure in which a part except for a part has a cyclic structure.
  • the parity check matrix obtained by performing column replacement equivalent to parity interleaving on the parity check matrix of the LDPC code specified in the DVB-T.2 standard is a 360-row x 360-column portion at the right corner.
  • the shift matrix there is only one element of 1 (it is an element of 0), and in that respect, it is not a (complete) cyclic structure but a pseudo cyclic structure.
  • the conversion check matrix in FIG. 22 replaces rows so that the conversion check matrix is configured with a configuration matrix described later. (Row replacement) is also applied to the matrix.
  • LDPC 8 transmits one or more code bits of the LDPC code as one symbol. That is, for example, when 2 bits of code bits are used as one symbol, QPSK is used as a modulation system, for example. When 4 bits of code bits are used as 1 symbol, a modulation system is used. For example, 16QAM is used.
  • LDPC encoder 115 is output, the parity check matrix H of an LDPC code prescribed in the standard of DVB-T.2, the information matrix H A has a cyclic structure and the parity matrix H T is Has a staircase structure.
  • a cyclic structure (more precisely, a pseudo cyclic structure as described above) also appears in the parity matrix.
  • FIG. 23 shows a conversion check matrix
  • a in FIG. 23 shows a conversion parity check matrix of a parity check matrix H of an LDPC code having a code length N of 64,800 bits and a coding rate (r) of 3/4.
  • FIG. 23B shows processing performed by the demultiplexer 25 (FIG. 9) for the LDPC code of the conversion parity check matrix of FIG. 23A, that is, the LDPC code after parity interleaving.
  • the modulation method is 16QAM, and the code bits of the LDPC code after parity interleaving are written in the column direction in the four columns constituting the memory 31 of the demultiplexer 25.
  • the sign bit written in the column direction in the four columns constituting the memory 31 is read out in units of 4 bits in the row direction to become one symbol.
  • 4-bit code bits B 0 , B 1 , B 2 , and B 3 that are one symbol are code bits corresponding to 1 in any one row of the conversion check matrix of A in FIG.
  • the variable nodes corresponding to the sign bits B 0 , B 1 , B 2 , and B 3 are connected to the same check node.
  • a plurality of code bits corresponding to a plurality of variable nodes connected to the same check node may be one symbol of 16QAM. is there.
  • the column twist interleaver 24 performs a process after parity interleaving from the parity interleaver 23 so that a plurality of code bits corresponding to 1 in any one row of the conversion check matrix are not included in one symbol. Column twist interleaving is performed to interleave the code bits of the LDPC code.
  • FIG. 24 is a diagram for explaining column twist interleaving.
  • FIG. 24 shows the memory 31 of the demultiplexer 25 (FIGS. 18 and 19).
  • the memory 31 stores mb bits in the column (vertical) direction and has a storage capacity for storing N / (mb) bits in the row (horizontal) direction.
  • Consists of The column twist interleaver 24 performs column twist interleaving by controlling the write start position when writing the code bits of the LDPC code in the column direction and reading in the row direction to the memory 31.
  • a plurality of code bits, which are read as one symbol, are read out in the row direction by appropriately changing the write start position at which code bit writing is started for each of a plurality of columns.
  • the sign bit corresponding to 1 in any one row of the conversion parity check matrix is prevented (a plurality of code bits corresponding to 1 in any one row of the parity check matrix are not included in the same symbol.
  • the code bits of the LDPC code are rearranged).
  • the column twist interleaver 24 writes the code bits of the LDPC code from the top to the bottom (column direction) of the four columns constituting the memory 31 (instead of the demultiplexer 25 in FIG. 18) from left to right. Towards the direction column.
  • the column twist interleaver 24 starts from the first row of all the columns constituting the memory 31 in the row direction in units of 4 bits (mb bits).
  • the code bit is read out and output to the switching unit 32 (FIGS. 18 and 19) of the demultiplexer 25 as the LDPC code after column twist interleaving.
  • the address at the top (top) position of each column is 0 and the address at each position in the column direction is expressed as an integer in ascending order
  • the starting position of writing is the position where the address is 0, the second column (from the left) is the starting position of writing, the address is the position 2, and the third column is the starting position of writing.
  • the address is at position 4, and for the fourth column, the write start position is the position at address 7.
  • the writing start position is other than the position where the address is 0
  • the writing start position After writing the sign bit to the lowest position, it returns to the beginning (position where the address is 0), and the writing start position. Writing up to the position immediately before is performed. Thereafter, writing to the next (right) column is performed.
  • FIG. 25 shows the number of columns of the memory 31 required for column twist interleaving and the writing of LDPC codes for 11 coding rates with a code length N of 64,800 as defined in the DVB-T.2 standard. The address of the starting position is shown for each modulation method.
  • the write start position of the first column of the two columns of the memory 31 is the position where the address is 0, and the write start position of the second column is the position where the address is 2.
  • the memory 31 is arranged in the row direction according to FIG. It has 4 columns for storing 2 ⁇ 2 bits and stores 64800 / (2 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 2 position
  • the third column The start position of writing in the column is the position where the address is 4
  • the start position of writing in the fourth column is the position where the address is 7.
  • the multiple b is 2.
  • the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 4 ⁇ 1 bits, and stores 64800 / (4 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 2 position
  • the write start position of the second column is the position where the address is 4
  • the write start position of the fourth column is the position where the address is 7.
  • the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 4 ⁇ 2 bits and stores 64800 / (4 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the second column is the position where the address is 2
  • the start position of the fourth column is the position where the address is 4
  • the start position of the fifth column is the position where the address is 4.
  • the position and the start position of writing in the sixth column are the position where the address is 5
  • the start position of writing in the seventh column is the position where the address is 7, and the starting position of the eighth column is The address is made with 7 positions, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 6 columns for storing 6 ⁇ 1 bits, and stores 64800 / (6 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 2 position
  • the first column write position is the address 5 position
  • the fourth column write start position is the address 9 position
  • the fifth column write start position is the address 10.
  • the position and the position at the beginning of writing in the sixth column are the position where the address is 13, respectively.
  • the memory 31 is arranged in the row direction. It has 12 columns for storing 6 ⁇ 2 bits, and stores 64800 / (6 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • 3 The start position of the second column is the position where the address is 2
  • the start position of the fourth column is the position where the address is 2
  • the start position of the fifth column is the position where the address is 3.
  • the position and the start position of the 6th column are the position where the address is 4, the start position of the 7th column is the position where the address is 4 and the start position of the 8th column is The position where the address is 5 and the start position of writing in the ninth column are the position where the address is 5, and the start position of writing in the 10th column is the position where the address is 7 and the start position of writing in the 11th column The position of is the position of address 8 and the 12th color Position of the writing start is set to the position whose address is 9, are respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 8 ⁇ 1 bits and stores 64800 / (8 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the second column is the position where the address is 2
  • the start position of the fourth column is the position where the address is 4
  • the start position of the fifth column is the position where the address is 4.
  • the position and the start position of writing in the sixth column are the position where the address is 5
  • the start position of writing in the seventh column is the position where the address is 7, and the starting position of the eighth column is The address is made with 7 positions, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 16 columns for storing 8 ⁇ 2 bits, and stores 64800 / (8 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 2 position
  • the start position of the second column is the position where the address is 2
  • the start position of the fourth column is the position where the address is 2
  • the start position of the fifth column is the address where the address is 2.
  • the position and the start position of writing the sixth column are the position where the address is 3
  • the start position of the seventh column is the position where the address is 7
  • the start position of the eighth column is
  • the position where the address is 15 and the start position of the 9th column are the position where the address is 16 and the start position where the 10th column is written are the position where the address is 20 and the start position of the 11th column.
  • the positions of the address 22 and the 12th The start position of the program is the position where the address is 22, the start position of the 13th column is the position where the address is 27, and the start position of the 14th column is the position where the address is 27.
  • the write start position of the 15th column is the position where the address is 28, and the write start position of the 16th column is the position where the address is 32.
  • the memory 31 is arranged in the row direction according to FIG. It has 10 columns for storing 10 ⁇ 1 bits, and stores 64800 / (10 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 3 position
  • the first column write position is the address 6 position
  • the fourth column write start position is the address 8 position
  • the fifth column start position is the address 11
  • the position and the start position of the 6th column are the position of the address 13
  • the start position of the 7th column is the position of the address 15
  • the start position of the 8th column is The address 17 position, the 9th column write start position, the address 18 position, and the 10th column write start position, the address 20 position, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 20 columns for storing 10 ⁇ 2 bits and stores 64800 / (10 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 1 position
  • the start position of the second column is the position where the address is 3
  • the start position of the fourth column is the position where the address is 4
  • the start position of the fifth column is the position where the address is 5.
  • the position and the start position of writing in the sixth column are the position where the address is 6
  • the start position of writing in the seventh column is the position where the address is 6
  • the starting position of the eighth column is
  • the position where the address is 9 and the start position of writing the ninth column are the position where the address is 13, and the start position of writing the tenth column is the position where the address is 14 and the start of writing the eleventh column.
  • the position of is the position of address 14 and the 12th
  • the start position of the program is the position where the address is 16, the start position of the 13th column is the position where the address is 21, and the start position of the 14th column is the position where the address is 21.
  • the 15th column write start position is the address 23
  • the 16th column write start position is the address 25 position
  • the 17th column write start position is the address
  • the 25th position and the 18th column start position are the address 26
  • the 19th column start position are the address 28 and the 20th column start position. Is addressed with 30 positions, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 12 ⁇ 1 bits, and stores 64800 / (12 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • 3 The start position of the second column is the position where the address is 2
  • the start position of the fourth column is the position where the address is 2
  • the start position of the fifth column is the position where the address is 3.
  • the position and the start position of the 6th column are the position where the address is 4, the start position of the 7th column is the position where the address is 4 and the start position of the 8th column is The position where the address is 5 and the start position of writing in the ninth column are the position where the address is 5, and the start position of writing in the 10th column is the position where the address is 7 and the start position of writing in the 11th column The position of is the position of address 8 and the 12th color Position of the writing start is set to the position whose address is 9, are respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 24 columns for storing 12 ⁇ 2 bits, and stores 64800 / (12 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 5 position
  • the start position of the second column is the position where the address is 8
  • the start position of the fourth column is the position where the address is 8
  • the start position of the fifth column is the position where the address is 8.
  • the position and the writing start position of the sixth column are the position where the address is 8
  • the writing start position of the seventh column is the position of the address 10
  • the writing start position of the eighth column is
  • the position where the address is 10 and the start position of the 9th column are the position where the address is 10 and the start position where the 10th column is written are the position where the address is 12 and the start position of the 11th column.
  • the position of is the position of address 13 and the 12th
  • the starting position of the ram writing is the position of address 16, the starting position of the 13th column is the position of address 17, the starting position of the 14th column is the position of address 19
  • the 15th column write start position is the address 21 position
  • the 16th column write start position is the address 22 position
  • the 17th column write start position is the address
  • the position of 23 and the start position of writing of the 18th column are the position of address 26
  • the start position of writing of the 19th column is the position of address 37 and the start position of writing of the 20th column.
  • the position of the address 39 and the start position of the 21st column are the position of the address 40 and the start position of the 22nd column is the position of the address 41 and the position of the 23rd column.
  • the address at the beginning of writing is 41 Position and, writing starting the 24th column position is set to the position whose address is 41, are respectively.
  • FIG. 26 shows the number of columns of the memory 31 required for column twist interleaving and the writing for each LDPC code of 10 coding rates defined in the DVB-T.2 standard and having a code length N of 16200. The address of the starting position is shown for each modulation method.
  • the memory 31 is arranged in the row direction according to FIG. It has two columns that store 2 ⁇ 1 bits and stores 16200 / (2 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position. Is done.
  • the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 2 ⁇ 2 bits, and stores 16200 / (2 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 2 position
  • the writing start position of the second column is the position where the address is 3
  • the writing start position of the fourth column is the position where the address is 3.
  • the memory 31 is arranged in the row direction according to FIG. It has four columns for storing 4 ⁇ 1 bits, and stores 16200 / (4 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 2 position
  • the writing start position of the second column is the position where the address is 3
  • the writing start position of the fourth column is the position where the address is 3.
  • the memory 31 is arranged in the row direction according to FIG. It has 8 columns that store 4 ⁇ 2 bits, and stores 16200 / (4 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the first column write start position is the address 0
  • the fourth column write start position is the address 1 position
  • the fifth column write start position is the address 7.
  • the position and the start position of writing the sixth column are the position where the address is 20, the start position of the seventh column is the position where the address is 20, and the start position of the eighth column is Addresses are made with 21 positions, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 6 columns for storing 6 ⁇ 1 bits, and stores 16200 / (6 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the second column is the position where the address is 2
  • the start position of the fourth column is the position where the address is 3
  • the start position of the fifth column is the position where the address is 7.
  • the position and the position at the beginning of writing in the sixth column are set to the position where the address is 7, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 6 ⁇ 2 bits, and stores 16200 / (6 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the second column is the position where the address is 0
  • the start position of the fourth column is the position where the address is 2
  • the start position of the fifth column is the position where the address is 2.
  • the position of the start position of the 6th column is the position where the address is 2
  • the start position of the 7th column is the position of the address 3
  • the start position of the 8th column is
  • the position where the address is 3 and the start position of the 9th column are the position where the address is 3 and the start position of the 10th column is the position where the address is 6 and the start of writing the 11th column.
  • the position of is the position of address 7 and the 12th color Position of the writing start is set to the position whose address is 7, are respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 8 columns for storing 8 ⁇ 1 bits, and stores 16200 / (8 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the first column write start position is the address 0
  • the fourth column write start position is the address 1 position
  • the fifth column write start position is the address 7.
  • the position and the start position of writing the sixth column are the position where the address is 20, the start position of the seventh column is the position where the address is 20, and the start position of the eighth column is Addresses are made with 21 positions, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 10 columns for storing 10 ⁇ 1 bits, and stores 16200 / (10 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 1 position
  • the start position of the second column is the position where the address is 2
  • the start position of the fourth column is the position where the address is 2
  • the start position of the fifth column is the position where the address is 3.
  • the position of the start position of the 6th column is the position where the address is 3
  • the start position of the 7th column is the position of the address 4
  • the start position of the 8th column is The address 4 position, the 9th column write start position, the address 5 position, and the 10th column write start position are the address 7 position, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 20 columns for storing 10 ⁇ 2 bits, and stores 16200 / (10 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the second column is the position where the address is 0
  • the start position of the fourth column is the position where the address is 2
  • the start position of the fifth column is the position where the address is 2.
  • the position and the start position of writing in the sixth column are the position where the address is 2
  • the start position of writing in the seventh column is the position of address 2
  • the starting position of the eighth column is
  • the position where the address is 2 and the start position of writing the ninth column are the position where the address is 5,
  • the start position of writing the tenth column is the position where the address is 5 and the start of writing the eleventh column.
  • the position of is the position of address 5 and the 12th color
  • the writing start position is the position where the address is 5
  • the writing start position of the 13th column is the position where the address is 5
  • the writing start position of the 14th column is the position where the address is 7
  • the write start position of the 15th column is the position where the address is 7
  • the write start position of the 16th column is the position of address 7
  • the write start position of the 17th column is address 7
  • the position of the 18th column and the start position of the 18th column are the position where the address is 8
  • the start position of the 19th column is the position of the address 8 and the start position of the 20th column is ,
  • the address is 10 positions, respectively.
  • the memory 31 is arranged in the row direction. It has 12 columns for storing 12 ⁇ 1 bits, and stores 16200 / (12 ⁇ 1) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the second column is the position where the address is 0
  • the start position of the fourth column is the position where the address is 2
  • the start position of the fifth column is the position where the address is 2.
  • the position of the start position of the 6th column is the position where the address is 2
  • the start position of the 7th column is the position of the address 3
  • the start position of the 8th column is
  • the position where the address is 3 and the start position of the 9th column are the position where the address is 3 and the start position of the 10th column is the position where the address is 6 and the start of writing the 11th column.
  • the position of is the position of address 7 and the 12th color Position of the writing start is set to the position whose address is 7, are respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 24 columns for storing 12 ⁇ 2 bits, and stores 16200 / (12 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the second column is the position where the address is 0
  • the start position of the fourth column is the position where the address is 0
  • the start position of the fifth column is the position where the address is 0.
  • the position of the start position of the 6th column is the position where the address is 0
  • the start position of the 7th column is the position where the address is 0,
  • the start position of the 8th column is
  • the position where the address is 1 and the start position of writing the ninth column are the position where the address is 1, and the start position of writing the tenth column is the position where the address is 1 and the start of writing the eleventh column.
  • the position of is the position of address 2 and the 12th color
  • the write start position is the position where the address is 2
  • the write start position of the 13th column is the position where the address is 2
  • the write start position of the 14th column is the position where the address is 3
  • the write start position of the 15th column is the position where the address is 7
  • the write start position of the 16th column is the position of address 9
  • the write start position of the 17th column is the address 9
  • the 18th column write start position are the address 9 position
  • the 19th column write start position are the address 10 position
  • the 20th column write start position are
  • the first position is the position where the address is 10.
  • the writing starting position for the 24th column is set to the position whose address is 11, are respectively.
  • FIG. 27 is a flowchart for explaining processing performed by the LDPC encoder 115, the bit interleaver 116, and the QAM encoder 117 of FIG.
  • the LDPC encoder 115 waits for the LDPC target data to be supplied from the BCH encoder 114, encodes the LDPC target data into an LDPC code in step S101, and supplies the LDPC code to the bit interleaver 116. The process proceeds to step S102.
  • step S102 the bit interleaver 116 performs bit interleaving on the LDPC code from the LDPC encoder 115, supplies a symbol obtained by symbolizing the LDPC code after the bit interleaving to the QAM encoder 117, and performs processing.
  • the process proceeds to step S103.
  • the parity interleaver 23 performs parity interleaving for the LDPC code from the LDPC encoder 115, and converts the LDPC code after the parity interleaving into the column twist interleave. Supplied to Lever 24.
  • the column twist interleaver 24 performs column twist interleaving on the LDPC code from the parity interleaver 23 and supplies it to the demultiplexer 25.
  • the demultiplexer 25 replaces the code bits of the LDPC code after the column twist interleaving by the column twist interleaver 24, and performs a replacement process using the replaced code bits as symbol bits (symbol bits) of the symbols.
  • the replacement process by the demultiplexer 25 can be performed according to the first to fourth replacement methods shown in FIGS. 18 and 19 and according to the allocation rule.
  • the allocation rule is a rule for allocating a code bit of an LDPC code to a symbol bit representing a symbol, and details thereof will be described later.
  • the symbol obtained by the replacement process by the demultiplexer 25 is supplied from the demultiplexer 25 to the QAM encoder 117.
  • step S103 the QAM encoder 117 maps the symbol from the demultiplexer 25 to a signal point determined by the modulation method of the orthogonal modulation performed by the QAM encoder 117 and performs orthogonal modulation, and the resulting data is converted into a time interleaver. 118.
  • the parity interleaver 23 that is a block that performs parity interleaving and the column twist interleaver 24 that is a block that performs column twist interleaving are configured separately.
  • the parity interleaver 23 and the column twist interleaver 24 can be integrally configured.
  • both parity interleaving and column twist interleaving can be performed by writing and reading code bits to and from the memory, and an address (write address) for writing code bits is an address for reading code bits. It can be represented by a matrix to be converted into (read address).
  • parity interleaving is performed by converting the sign bit by the matrix, and further, the parity.
  • the result of column twist interleaving of the interleaved LDPC code can be obtained.
  • the demultiplexer 25 can also be configured integrally.
  • the replacement process performed by the demultiplexer 25 can also be represented by a matrix that converts the write address of the memory 31 that stores the LDPC code into a read address.
  • parity interleaving, column twist interleaving, and replacement processing are performed according to the matrix. Can be performed collectively.
  • parity interleaving and column twist interleaving can be performed, or neither can be performed.
  • the simulation was performed using a communication path with flutter with a D / U of 0 dB.
  • FIG. 28 shows a model of the communication path adopted in the simulation.
  • a in FIG. 28 shows a flutter model employed in the simulation.
  • 28B shows a model of a communication path with flutter represented by the model of A in FIG.
  • H represents the flutter model of A in FIG.
  • N represents ICI (Inter Carrier Interference).
  • E [N 2 ] of the power is approximated by AWGN.
  • an error rate obtained by the simulation shows the relationship between the Doppler frequency f d of the flutter.
  • FIG. 29 shows the relationship between the error rate and the Doppler frequency f d when the modulation method is 16QAM, the coding rate (r) is (3/4), and the replacement method is the first replacement method.
  • FIG. 30 shows the relationship between the error rate and the Doppler frequency f d when the modulation method is 64QAM, the coding rate (r) is (5/6), and the replacement method is the first replacement method. Show.
  • the thick line indicates the relationship between the error rate and the Doppler frequency f d when the parity interleaving, the column twist interleaving, and the replacement process are all performed
  • the thin line indicates the parity. interleave, column twist interleave and of the replacement process, in the case of performing only the replacement process, shows the relationship between the error rate and the Doppler frequency f d.
  • the error rate is improved (smaller) when parity interleaving, column twist interleaving, and replacement processing are all performed than when only replacement processing is performed. I understand that.
  • FIG. 31 is a block diagram showing a configuration example of the LDPC encoder 115 of FIG.
  • LDPC encoder 122 of FIG. 8 is similarly configured.
  • the DVB-T.2 standard defines LDPC codes with two code lengths N of 64800 bits and 16200 bits.
  • LDPC codes having a code length N of 64,800 bits eleven coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4 / 5, 5/6, 8/9, and 9/10 are defined, and for LDPC codes with a code length N of 16200 bits, 10 coding rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined (FIGS. 12 and 13).
  • the LDPC encoder 115 performs encoding (error correction coding) using an LDPC code having a code length N of 64,800 bits or 16200 bits for each code length N and each code rate. This can be performed according to the prepared check matrix H.
  • the LDPC encoder 115 includes an encoding processing unit 601 and a storage unit 602.
  • the encoding processing unit 601 includes an encoding rate setting unit 611, an initial value table reading unit 612, a parity check matrix generation unit 613, an information bit reading unit 614, an encoded parity calculation unit 615, and a control unit 616, and an LDPC encoder
  • the LDPC encoding of the LDPC target data supplied to 115 is performed, and the resulting LDPC code is supplied to the bit interleaver 116 (FIG. 8).
  • the coding rate setting unit 611 sets the code length N and coding rate of the LDPC code in accordance with, for example, an operator's operation.
  • the initial value table reading unit 612 reads a parity check matrix initial value table, which will be described later, corresponding to the code length N and the coding rate set by the coding rate setting unit 611 from the storage unit 602.
  • the information bit reading unit 614 reads (extracts) information bits for the information length K from the LDPC target data supplied to the LDPC encoder 115.
  • the encoded parity calculation unit 615 reads the parity check matrix H generated by the parity check matrix generation unit 613 from the storage unit 602, and uses the parity check matrix H to calculate a parity bit for the information bits read by the information bit reading unit 614, A codeword (LDPC code) is generated by calculating based on the formula.
  • LDPC code LDPC code
  • the control unit 616 controls each block constituting the encoding processing unit 601.
  • the storage unit 602 stores, for example, a plurality of parity check matrix initial value tables corresponding to a plurality of coding rates and the like shown in FIGS. 12 and 13 for code lengths N such as 64800 bits and 16200 bits, respectively. Has been.
  • the storage unit 602 temporarily stores data necessary for the processing of the encoding processing unit 601.
  • FIG. 32 is a flowchart for explaining processing of the LDPC encoder 115 of FIG.
  • step S201 the coding rate setting unit 611 determines (sets) a code length N and a coding rate r for performing LDPC coding.
  • step S202 the initial value table reading unit 612 reads, from the storage unit 602, a predetermined parity check matrix initial value table corresponding to the code length N and the coding rate r determined by the coding rate setting unit 611. .
  • the parity check matrix generation unit 613 uses the parity check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612, and the code length N and the coding rate determined by the coding rate setting unit 611.
  • the parity check matrix H of the LDPC code of r is obtained (generated), supplied to the storage unit 602 and stored.
  • step S205 the encoded parity calculation unit 615 sequentially calculates the parity bits of the codeword c that satisfies Expression (8).
  • c represents a row vector as a code word (LDPC code), and c T represents transposition of the row vector c.
  • the information bit portion is represented by the row vector A and the parity bit portion is represented by the row vector T.
  • step S206 the control unit 616 determines whether or not to end LDPC encoding. If it is determined in step S206 that the LDPC encoding is not terminated, that is, for example, if there is still LDPC target data to be LDPC encoded, the process returns to step S201 (or step S204). The processing from S201 (or step S204) to S206 is repeated.
  • step S206 If it is determined in step S206 that the LDPC encoding is to be ended, that is, for example, if there is no LDPC target data to be LDPC encoded, the LDPC encoder 115 ends the processing.
  • a parity check matrix initial value table corresponding to each code length N and each coding rate r is prepared, and the LDPC encoder 115 has a predetermined code length N and a predetermined coding rate r.
  • LDPC encoding is performed using a parity check matrix H generated from a parity check matrix initial value table corresponding to the predetermined code length N and the predetermined coding rate r.
  • the parity check matrix initial value table includes an information matrix H A corresponding to the code length N of the LDPC code (LDPC code defined by the parity check matrix H) and the information length K of the parity check matrix H (FIG. 10). ) Is a table that represents the position of one element for each 360 columns (number of columns P of cyclic structure units), and is created in advance for each check matrix H of each code length N and each coding rate r.
  • FIG. 33 is a diagram illustrating an example of a parity check matrix initial value table.
  • FIG. 33 shows a parity check matrix initial value table for a parity check matrix H defined in the DVB-T.2 standard and having a code length N of 16200 bits and a coding rate r of 1/4.
  • the parity check matrix generation unit 613 obtains the parity check matrix H using the parity check matrix initial value table as follows.
  • FIG. 34 shows a method for obtaining the parity check matrix H from the parity check matrix initial value table.
  • parity check matrix initial value table in FIG. 34 is the parity check matrix initial value for the parity check matrix H defined in the DVB-T.2 standard and having a code length N of 16200 bits and a code rate r of 2/3. Shows the table.
  • the parity check matrix initial value table indicates the position of one element of the information matrix H A (FIG. 10) corresponding to the information length K corresponding to the code length N of the LDPC code and the coding rate r, as 360 columns.
  • This is a table expressed for each (number of columns P of the unit of the cyclic structure), and in the i-th row, the row number of the 1 element of the 1 + 360 ⁇ (i ⁇ 1) -th column of the check matrix H (check matrix H (The row number where the row number of the first row is 0) is arranged by the number of column weights of the 1 + 360 ⁇ (i ⁇ 1) th column.
  • the number of rows k + 1 in the parity check matrix initial value table differs depending on the information length K.
  • Equation (9) The relationship of Equation (9) is established between the information length K and the number k + 1 of rows in the parity check matrix initial value table.
  • 360 in equation (9) is the number of columns P of the unit of the cyclic structure described in FIG.
  • the column weights of the parity check matrix H obtained from the parity check matrix initial value table of FIG. 34 are 13 from the first column to the 1 + 360 ⁇ (3-1) ⁇ 1 column, and 1 + 360 ⁇ (3-1) It is 3 from the column to the Kth column.
  • the first row of the parity check matrix initial value table in FIG. 34 is 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620,2622, which is the parity check matrix H
  • the row number is 0,2084,1613,1548,1286,1460,3196,4297,2481,3369,3451,4620,2622
  • the element of the row is 1 (and other elements) Is 0).
  • 34 is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, which is 361 of the parity check matrix H.
  • the row number is 1,122,1516,3448,2880,1407,1847,3799,3529,373,971,4358,3108, indicating that the element is 1 ing.
  • the parity check matrix initial value table represents the position of one element of the information matrix HA of the parity check matrix H for every 360 columns.
  • the numerical value of the i-th row (i-th from the top) and j-th column (j-th from the left) of the parity check matrix initial value table is represented as h i, j and j items in the w-th column of the parity check matrix H. If the row number of the first element is represented as H wj , the row number H of the first element in the w column, which is a column other than the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H wj can be obtained by Expression (10).
  • mod (x, y) means the remainder of dividing x by y.
  • P is the number of columns of the unit of the cyclic structure described above, and is 360, for example, as described above in the DVB-T.2 standard.
  • the parity check matrix generation unit 613 (FIG. 31) specifies the row number of the 1 element in the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H using the parity check matrix initial value table.
  • the parity check matrix generation unit 613 calculates the row number H wj of the first element of the w column that is a column other than the 1 + 360 ⁇ (i ⁇ 1) column of the parity check matrix H by the formula ( 10) to generate a parity check matrix H in which the element of the row number obtained as described above is 1.
  • LDPC codes with a code length N of 64k bits and 16k bits are defined, but LDPC codes with shorter code lengths are not defined.
  • the LDPC code with a short code length can reduce the memory and delay required when decoding the LDPC code, compared with the LDPC code with a long code length, in digital broadcasting for mobile terminals, May be effective.
  • an LDPC code having a code length shorter than the LDPC code (code length N is 64 kbit and 16 kbit LDPC code) stipulated in DVB-T.2 is used for portable terminals.
  • Digital broadcasting for portable terminals can be performed using the LDPC code for digital broadcasting (hereinafter also referred to as portable LDPC code).
  • parity check matrix H is the same as for LDPC codes specified in DVB-T.2, from the viewpoint of maintaining compatibility with DVB-T.2 as much as possible.
  • the matrix H T has a staircase structure (FIG. 11).
  • the information matrix HA of the parity check matrix H has a cyclic structure, and the number of columns P of the cyclic structure unit is 360 as in the LDPC code defined in DVB-T.2.
  • the code length N of the portable LDPC code is shorter than the LDPC code specified in DVB-T.2, and is cyclic (similar to the LDPC code specified in DVB-T.2).
  • 4320 bits hereinafter also referred to as 4k bits, which is a multiple of the number of columns P of the unit of the structure, is adopted.
  • 35 to 43 are diagrams showing examples of the parity check matrix initial value table of the LDPC code (portable) having a code length N of 4k bits as described above.
  • FIG. 35 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a coding rate r of 1/4.
  • FIG. 36 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 1/3.
  • FIG. 37 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 5/12.
  • FIG. 38 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 1/2.
  • FIG. 39 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a coding rate r of 7/12.
  • FIG. 40 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 2/3.
  • FIG. 41 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 3/4.
  • the LDPC encoder 115 uses a parity check matrix H obtained from the parity check matrix initial value table shown in FIGS. 35 to 43 for digital broadcasting for mobile terminals, and a code length N is 4k bits.
  • the coding rate r is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3/4, 5/6, and 11/12 Encode to any LDPC code.
  • the LDPC code obtained by using the parity check matrix H obtained from the parity check matrix initial value table of FIG. 35 to FIG. 43 is a high-performance LDPC code.
  • a high-performance LDPC code is an LDPC code obtained from an appropriate check matrix H.
  • an appropriate parity check matrix H is an LDPC code obtained from the parity check matrix H with a low E s / N 0 (signal power to noise power ratio per symbol) or E b / N o (per bit). This is a parity check matrix that satisfies a predetermined condition for making BER (Bit Error Rate) smaller when transmitted at a signal power to noise power ratio.
  • An appropriate parity check matrix H can be obtained, for example, by performing a simulation for measuring the BER when LDPC codes obtained from various parity check matrices satisfying a predetermined condition are transmitted at low E s / N o .
  • the predetermined conditions that the appropriate check matrix H should satisfy are, for example, that the analysis result obtained by the code performance analysis method called “Density Evolution” is good, There are no loops, etc.
  • the predetermined condition to be satisfied by the appropriate parity check matrix H can be determined as appropriate from the viewpoints of improving the decoding performance of the LDPC code, facilitating (simplifying) the decoding process of the LDPC code, and the like.
  • 44 and 45 are diagrams for explaining density evolution in which an analysis result as a predetermined condition to be satisfied by an appropriate check matrix H is obtained.
  • Density evolution is a code analysis method that calculates the expected value of the error probability for the entire LDPC code (ensemble) with a code length N of ⁇ characterized by a degree sequence described later. It is.
  • the noise variance when the noise variance is increased from 0, the expected value of the error probability of a certain ensemble is initially 0, but the noise variance is greater than a certain threshold. Then, it is not 0.
  • the expected value of the error probability is not zero, and the threshold of noise variance (hereinafter also referred to as performance threshold) is compared to determine whether the ensemble performance (appropriateness of the check matrix) is good or bad. Can be decided.
  • performance threshold the threshold of noise variance
  • a high-performance LDPC code can be found among the LDPC codes belonging to the ensemble.
  • the above-described degree sequence represents the ratio of variable nodes and check nodes having weights of each value to the code length N of the LDPC code.
  • a regular (3,6) LDPC code with a coding rate of 1/2 is a degree in which the weights (column weights) of all variable nodes are 3 and the weights (row weights) of all check nodes are 6. Belongs to an ensemble characterized by a sequence.
  • FIG. 44 shows a Tanner graph of such an ensemble.
  • Each variable node is connected with three edges equal to the column weight, and therefore there are only 3N branches connected to the N variable nodes.
  • each check node is connected with 6 branches equal to the row weight, and therefore there are only 3N branches connected to N / 2 check nodes.
  • the interleaver randomly reorders 3N branches connected to N variable nodes, and reorders each of the rearranged branches into 3N branches connected to N / 2 check nodes. Connect to one of them.
  • the interleaver through which the branch connected to the variable node and the branch connected to the check node pass is divided into multiple (multi edge), which makes it possible to further characterize the ensemble. Strictly done.
  • FIG. 45 shows an example of a multi-edge type ensemble Tanner graph.
  • the Tanner graph of FIG. 45 there are two branches connected to the first interleaver, c1 check nodes with 0 branches connected to the second interleaver, and two branches connected to the first interleaver.
  • the number of branches connected to the second interleaver is c2 check nodes, the number of branches connected to the first interleaver is 0, and the number of branches connected to the second interleaver is c3. Exists.
  • the performance threshold value is E b / N 0 where the BER begins to drop (becomes smaller) due to multi-edge type density evolution. Finds an ensemble that falls below the specified value, and from among the LDPC codes belonging to that ensemble, the performance of an LDPC code that reduces BER in multiple modulation schemes used in digital broadcasting for mobile terminals, such as 16QAM and 64QAM, Selected as a good LDPC code.
  • a modulation method with a relatively small number of signal points such as QPSK, 16QAM, and 64QAM, is adopted.
  • 35 to 43 described above are parity check matrix initial value tables of LDPC codes having a code length N of 4k bits obtained by the above simulation.
  • the code length N of FIGS. 35 to 43 is 4k bits, and the coding rate r is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3 /. It is a figure which shows the minimum cycle length and performance threshold value of the parity check matrix H calculated
  • the minimum cycle length of the parity check matrix H whose coding rate r is 1/4 and 1/3 is 8 cycles.
  • the minimum cycle length of the parity check matrix H with r 5/12, 1/2, 7/12, 2/3, 3/4, 5/6, and 11/12 is 6 cycles.
  • the performance threshold increases (becomes smaller) as the encoding rate r decreases.
  • FIGS. 35 to 43 are diagrams for explaining a check matrix H (which is also referred to as a check matrix H of a portable LDPC code hereinafter) in FIGS. 35 to 43 (obtained from the check matrix initial value table).
  • H which is also referred to as a check matrix H of a portable LDPC code hereinafter
  • the column weight is X
  • the column weight is Y for the subsequent KY column
  • the column weight is M for the subsequent M-1 column.
  • the column weight is 1, respectively.
  • parity check matrix H of a portable LDPC code having a code length N of 4k As in the parity check matrix defined in DVB-T.2 described in FIGS.
  • the column weight tends to be large, and therefore, the first code bit of the portable LDPC code tends to be more resistant to errors (resistant to errors).
  • LDPC encoder 115 when performing LDPC encoding to a portable LDPC code using parity check matrix H (determined from the parity check matrix initial value table) shown in FIGS.
  • parity check matrix H determined from the parity check matrix initial value table shown in FIGS.
  • the write start position of each column (FIG. 24) of the memory 31 is defined in DVB-T.2. This is different from the writing start position in the case of the existing LDPC code (FIGS. 25 and 26).
  • FIG. 49 is a diagram showing the number of columns of the memory 31 necessary for column twist interleaving and the address of the writing start position for the portable LDPC code.
  • the code length N of FIGS. 35 to 43 is 4k bits
  • the coding rate r is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, Number of columns in memory 31 required for column twist interleaving for 9 types of portable LDPC codes (obtained from parity check matrix H obtained from parity check matrix initial value table) of 9/4, 5/6, and 11/12
  • the address of the writing start position are shown for each modulation method.
  • QPSK QPSK
  • 16QAM 16QAM
  • 64QAM 64QAM
  • the write start position of the first column is the position where the address is 0, and the write start position of the second column is the position where the address is 2. Is done.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • 3 The write start position of the second column is the position where the address is 1
  • the write start position of the fourth column is the position where the address is 0.
  • the writing start position of each of the four columns of the memory 31 is the same as when the multiple b is 2 and QPSK is adopted as the modulation method.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the write start position of the second column is the position where the address is 1
  • the write start position of the fourth column is the position where the address is 0.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 8 position
  • the first column write position is the address 10 position
  • the fourth column write start position is the address 10 position
  • the fifth column write start position is the address 25.
  • the position and the start position of writing the sixth column are the position where the address is 54
  • the start position of the seventh column is the position where the address is 62
  • the start position of the eighth column is Each address is made 69 positions.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the first column is the position where the address is 1
  • the start position of the fourth column is the position where the address is 1
  • the start position of the fifth column is the address where the address is 0.
  • the position and the position at the beginning of writing in the sixth column are set as the position where the address is 0, respectively.
  • the memory 31 is arranged in the row direction according to FIG. It has 12 columns for storing 6 ⁇ 2 bits, and stores 4320 / (6 ⁇ 2) bits in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 2 position
  • the first column write position is the address 10 position
  • the fourth column write start position is the address 12 position
  • the fifth column start position is the address 15
  • the position and the start position of writing in the sixth column are the position where the address is 17,
  • the start position of writing in the seventh column is the position where the address is 20,
  • the starting position of the eighth column is
  • the position of address 21 and the start position of writing the ninth column are the position of address 23 and the start position of the tenth column are the position of address 25 and the start of writing the eleventh column.
  • the position of the address is 26 and the 12th position
  • the writing starting position for the column is set to the position whose address is 30, are respectively.
  • FIG. 50 is a diagram illustrating a BER simulation result when column twist interleaving is performed on a portable LDPC code.
  • the simulation assumes a communication channel (channel) in which Rayleigh fading with an erasure probability of symbol loss of 0.167 is assumed, and a portable LDPC code has a code length N of 4k bits and a coding rate of 2/3 LDPC code (FIG. 40) and QPSK as a modulation method.
  • the horizontal axis represents E s / N 0 (signal power to noise power ratio per symbol), and the vertical axis represents BER.
  • the solid line represents BER when both parity interleaving and column twist interleaving are performed
  • the dotted line represents BER when parity interleaving is performed and column twist interleaving is not performed.
  • a demultiplexer 25 As measures for improving the tolerance to errors, as described above, in addition to a method employing a modulation method with a relatively small number of signal points such as 16QAM and 64QAM, for example, a demultiplexer 25 (FIG. 9). There is a replacement process performed in.
  • the above-described first to fourth replacement methods, DVB-T.2 and the like can be used as the replacement method for replacing the code bits of the LDPC code defined in the DVB-T.2 standard.
  • There is a replacement method defined in the standard but when digital broadcasting for mobile terminals is performed by the above-described LDPC code (portable LDPC code) with a code length N of 4k bits, the code length N is 4k. It is necessary to adopt a replacement process suitable for the LDPC code of bits.
  • the replacement process can be performed according to the assignment rule.
  • the demultiplexer 25 performs a replacement process on the LDPC code defined in DVB-T.2 etc. (hereinafter also referred to as a defined code) in the current method. In this case, the replacement process will be described.
  • FIG. 51 shows an example of replacement processing of the current method when the LDPC code is an LDPC code defined in DVB-T.2 and having a code length N of 64,800 bits and a coding rate of 3/5. Show.
  • a in FIG. 51 is an LDPC code in which the code length N is 64800 bits, the coding rate is 3/5, the modulation method is 16QAM, and the multiple b is 2.
  • An example of the replacement process of the current method is shown.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 7 Sign bit b 1 to symbol bit y 1 Sign bit b 2 to symbol bit y 4 Sign bit b 3 to symbol bit y 2 Sign bit b 4 to symbol bit y 5 Sign bit b 5 to symbol bit y 3 Sign bit b 6 into symbol bit y 6
  • the sign bit b 7 to the symbol bit y 0 Replace each assigned.
  • 51B shows the current scheme when the LDPC code is a defined code with a code length N of 64,800 bits and a coding rate of 3/5, and the modulation scheme is 64QAM and the multiple b is 2. Shows an example of the replacement process.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 11 Sign bit b 1 to symbol bit y 7 Sign bit b 2 to symbol bit y 3 Sign bit b 3 to symbol bit y 10 Sign bit b 4 to symbol bit y 6 Sign bit b 5 to symbol bit y 2 Sign bit b 6 to symbol bit y 9 Sign bit b 7 to symbol bit y 5 Sign bit b 8 to symbol bit y 1 Sign bit b 9 to symbol bit y 8 Sign bit b 10 to symbol bit y 4
  • the sign bit b 11 to the symbol bit y 0 Replace each assigned.
  • 51C shows the current scheme when the LDPC code is a defined code with a code length N of 64,800 bits and a coding rate of 3/5, and the modulation scheme is 256QAM and the multiple b is 2. Shows an example of the replacement process.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 15 Sign bit b 1 to symbol bit y 1 Sign bit b 2 into symbol bit y 13 Sign bit b 3 to symbol bit y 3 Sign bit b 4 to symbol bit y 8 Sign bit b 5 to symbol bit y 11 Sign bit b 6 to symbol bit y 9 Sign bit b 7 to symbol bit y 5 Sign bit b 8 to symbol bit y 10 Sign bit b 9 to symbol bit y 6 Sign bit b 10 to symbol bit y 4 Sign bit b 11 to symbol bit y 7 Sign bit b 12 into symbol bit y 12 The sign bit b 13 into the symbol bit y 2 Sign bit b 14 into symbol bit y 14 The sign bit b 15 to the symbol bit y 0 Replace each assigned.
  • FIG. 52 shows an example of the replacement process of the current method when the LDPC code is a defined code with a code length N of 16200 bits and a coding rate of 3/5.
  • a in FIG. 52 is an LDPC code in which the LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/5, and further, the modulation scheme is 16QAM and the multiple b is 2.
  • the replacement process of the current method is shown.
  • the replacement unit 32 performs replacement to assign the code bits b 0 to b 7 to the symbol bits y 0 to y 7 as in the case of A in FIG.
  • 52B shows an LDPC code in which the code length N is 16200 bits, the code rate is 3/5, the code is 3/5, the modulation method is 64QAM, and the multiple b is 2. Shows an example of the replacement process.
  • the replacement unit 32 performs the replacement for assigning the code bits b 0 to b 11 to the symbol bits y 0 to y 11 as in the case of B in FIG. 51 described above.
  • 52C shows an LDPC code in which the code length N is 16200 bits and the coding rate is 3/5, the modulation method is 256QAM, and the multiple b is 1. An example of a replacement process is shown.
  • the replacement unit 32 Sign bit b 0 to symbol bit y 7 Sign bit b 1 to symbol bit y 3 Sign bit b 2 to symbol bit y 1 Sign bit b 3 to symbol bit y 5 Sign bit b 4 to symbol bit y 2 Sign bit b 5 to symbol bit y 6 Sign bit b 6 to symbol bit y 4
  • the sign bit b 7 to the symbol bit y 0 Replace each assigned.
  • modulation schemes such as QPSK with fewer signal points, 16QAM, 64QAM, etc. are adopted.
  • each of the modulation schemes is 16QAM and 64QAM. The new replacement method will be described.
  • the modulation method is QPSK
  • the 2-bit symbol bits y 0 and y 1 representing the four symbols (signal points) of QPSK do not have superiority or inferiority to the error described with reference to FIGS. Therefore, it is not necessary to perform the replacement process (the resistance to errors does not change even if the replacement process is performed).
  • 53 to 55 are diagrams for explaining the new replacement method.
  • the replacement unit 32 of the demultiplexer 25 performs replacement of the mb bit code bits according to a predetermined allocation rule.
  • Allocation rules are rules for allocating code bits of LDPC codes to symbol bits.
  • a group set that is a combination of a code bit group of a code bit and a symbol bit group of a symbol bit to which a code bit of the code bit group is allocated, and each of the code bit group and the symbol bit group of the group set.
  • the number of code bits and the number of symbol bits (hereinafter also referred to as the number of group bits) are defined.
  • the code bit group is a group that groups the code bits according to the error probability
  • the symbol bit group is a group that groups the symbol bits according to the error probability
  • FIG. 53 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further having a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.
  • the code bit group Gb # i is a group having a better (smaller) error probability of code bits belonging to the code bit group Gb # i as the suffix #i is smaller.
  • the # i + 1 bit from the most significant bit of the mb code bit read out from the memory 31 in the row direction is also expressed as bit b # i, and mb of consecutive b symbols.
  • the # i + 1 bit from the most significant bit of the bit symbols is also expressed as bit y # i.
  • the sign bit group Gb1 includes the sign bit b0
  • the sign bit group Gb2 includes the sign bits b1 and b2
  • the sign bit group Gb3 includes the sign bits b3, b4, b5, b6, b7. , b8, b9, b10, b11 belong respectively.
  • the symbol bit group Gy # i is a group having a better error probability of the symbol bits belonging to the symbol bit group Gy # i as the suffix #i is smaller.
  • symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7
  • symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9
  • symbol bit group Gy3 includes symbols. Bits y4, y5, y10, and y11 belong to each.
  • FIG. 54 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further, the modulation method is 64QAM and the multiple b is 2. Is shown.
  • the combination of the sign bit group Gb1 and the symbol bit group Gy3 is defined as one group set.
  • the number of group bits of the group set is defined as 1 bit.
  • group set information the group set and the number of group bits are collectively referred to as group set information.
  • group set information the group set of the sign bit group Gb1 and the symbol bit group Gy3 and 1 bit that is the number of group bits of the group set are described as group set information (Gb1, Gy3, 1).
  • group set information (Gb1, Gy3, 1), group set information (Gb2, Gy3, 2), (Gb3, Gy3, 1), (Gb3, Gy2, 4), (Gb3, Gy1,4) is specified.
  • the group set information (Gb1, Gy3, 1) means that one bit of the code bit belonging to the code bit group Gb1 is allocated to one bit of the symbol bit belonging to the symbol bit group Gy3.
  • the code bit group is a group that groups the code bits according to the error probability
  • the symbol bit group is a group that groups the symbol bits according to the error probability. Therefore, it can be said that the allocation rule defines a combination of an error probability of a code bit and an error probability of a symbol bit to which the code bit is allocated.
  • the allocation rule that defines the combination of the error probability of the code bit and the error probability of the symbol bit to which the code bit is assigned is, for example, an error resistance (resistance to noise) by simulation or the like that measures BER. Determined to be better.
  • group set information that minimizes the BER (Bit Error Rate), that is, the sign bit group of the sign bit and the symbol bit group of the symbol bit to which the sign bit of the sign bit group is assigned And the number of sign bits and the number of symbol bits (number of group bits) of each group bit set (group set) and the symbol bit group of the group set are defined as allocation rules.
  • the code bits may be exchanged so that the code bits are assigned to the symbol bits.
  • FIG. 55 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 55 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and the modulation method is 64QAM and the multiple b is 2.
  • 54 shows a first example of code bit replacement according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y11 Sign bit b1 to symbol bit y10, Sign bit b2 to symbol bit y4, Sign bit b3 into symbol bit y5 Sign bit b4 to symbol bit y2 Sign bit b5 to symbol bit y3, Sign bit b6 to symbol bit y8 Sign bit b7 to symbol bit y9, Sign bit b8 to symbol bit y6, Sign bit b9 into symbol bit y7 Sign bit b10 to symbol bit y1 Sign bit b11 to symbol bit y0, Replace each assigned.
  • FIG. 55B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further, when the modulation scheme is 64QAM and the multiple b is 2.
  • 54 shows a second example of code bit replacement according to the assignment rule of FIG.
  • the method of allocating the sign bit b # i to the symbol bit y # i shown in A of FIG. 55 and B of FIG. 55 follows the allocation rule of FIG. 54 (observing the allocation rule). ing).
  • FIG. 56 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further having a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.
  • code bit group Gb1 includes code bit b0
  • code bit group Gb2 includes code bits b1 to b3
  • code bit group Gb3 includes code bits b4 to b11.
  • symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7
  • symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9.
  • Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.
  • FIG. 57 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further, when the modulation scheme is 64QAM and the multiple b is 2. Is shown.
  • the group set information (Gb1, Gy1, 1), (Gb2, Gy3, 2), (Gb2, Gy1, 1), (Gb3, Gy3, 2), (Gb3, Gy2, 4), (Gb3, Gy1, 2) is specified.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 2 bits of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit group Gy3 having the third highest error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • FIG. 58 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 58 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further, the modulation method is 64QAM and the multiple b is 2.
  • 57 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, The sign bit b1 is changed to the symbol bit y11. Sign bit b2 to symbol bit y1, Sign bit b3 into symbol bit y10, Sign bit b4 to symbol bit y4, Sign bit b5 to symbol bit y8 Sign bit b6 to symbol bit y2 Sign bit b7 to symbol bit y9, Sign bit b8 to symbol bit y3, Sign bit b9 into symbol bit y7 Sign bit b10 to symbol bit y5 Sign bit b11 to symbol bit y6, Replace each assigned.
  • LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/3, and further when the modulation method is 64QAM and the multiple b is 2.
  • 57 shows a second example of code bit replacement according to the allocation rule of FIG.
  • FIG. 59 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further having a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.
  • code bit b0 belongs to code bit group Gb1
  • code bits b1 to b4 belong to code bit group Gb2
  • code bits b5 to b11 belong to code bit group Gb3.
  • the symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7
  • the symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9.
  • Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.
  • FIG. 60 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further, the modulation method is 64QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy3, 3), (Gb2, Gy1, 1), (Gb3, Gy2, 4), (Gb3, Gy1, 2), (Gb3, Gy3, 1) is defined.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy3 having the third highest error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • FIG. 61 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 61 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further, the modulation method is 64QAM and the multiple b is 2. 60 shows a first example of code bit replacement according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, The sign bit b1 is changed to the symbol bit y11. Sign bit b2 to symbol bit y1, Sign bit b3 into symbol bit y10, Sign bit b4 to symbol bit y4, Sign bit b5 to symbol bit y8 Sign bit b6 to symbol bit y2 Sign bit b7 to symbol bit y9, Sign bit b8 to symbol bit y3, Sign bit b9 into symbol bit y7 Sign bit b10 to symbol bit y5 Sign bit b11 to symbol bit y6, Replace each assigned.
  • FIG. 61B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further, when the modulation scheme is 64QAM and the multiple b is 2.
  • 60 shows a second example of code bit replacement according to the allocation rule of FIG.
  • FIG. 62 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.
  • code bit b0 belongs to code bit group Gb1
  • code bits b1 to b5 belong to code bit group Gb2
  • code bits b6 to b11 belong to code bit group Gb3.
  • symbol bits y0, y1, y6, and y7 are included in symbol bit group Gy1
  • symbol bits y2, y3, y8, and y9 are included in symbol bit group Gy2, as in B of FIG.
  • Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.
  • FIG. 63 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 64QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy1, 3), (Gb2, Gy1, 1), (Gb2, Gy2, 1), (Gb3, Gy2, 3), (Gb3, Gy1, 2) and (Gb3, Gy3, 1) are defined.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy3 having the third highest error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • the group set information (Gb2, Gy2, 1) one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • the group set information (Gb3, Gy2, 3) 3 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • the group set information (Gb3, Gy1, 2) 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • FIG. 64 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 64 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, the modulation method is 64QAM and the multiple b is 2.
  • 63 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, The sign bit b1 is changed to the symbol bit y11. Sign bit b2 to symbol bit y1, Sign bit b3 into symbol bit y10, Sign bit b4 to symbol bit y4, Sign bit b5 to symbol bit y8 Sign bit b6 to symbol bit y2 Sign bit b7 to symbol bit y9, Sign bit b8 to symbol bit y3, Sign bit b9 into symbol bit y7 Sign bit b10 to symbol bit y5 Sign bit b11 to symbol bit y6, Replace each assigned.
  • 64B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 64QAM and the multiple b is 2.
  • 63 shows a second example of code bit replacement according to the assignment rule of FIG.
  • FIG. 65 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further the modulation method is 64QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • the code bit group Gb1 includes the code bit b0
  • the code bit group Gb2 includes the code bits b1 to b6
  • the code bit group Gb3 includes the code bits b7 to b11.
  • symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7
  • symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9.
  • Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.
  • FIG. 66 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further the modulation scheme is 64QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy3, 3), (Gb2, Gy1, 1), (Gb2, Gy2, 2), (Gb3, Gy2, 2), (Gb3, Gy1, 2) and (Gb3, Gy3, 1) are defined.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy3 having the third highest error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • FIG. 67 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 67 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further, the modulation method is 64QAM and the multiple b is 2.
  • 66 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, The sign bit b1 is changed to the symbol bit y11. Sign bit b2 to symbol bit y1, Sign bit b3 into symbol bit y10, Sign bit b4 to symbol bit y4, Sign bit b5 to symbol bit y8 Sign bit b6 to symbol bit y2 Sign bit b7 to symbol bit y9, Sign bit b8 to symbol bit y3, Sign bit b9 into symbol bit y7 Sign bit b10 to symbol bit y5 Sign bit b11 to symbol bit y6, Replace each assigned.
  • FIG. 67B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further, when the modulation scheme is 64QAM and the multiple b is 2.
  • 66 shows a second example of exchanging code bits according to the allocation rule of FIG.
  • FIG. 68 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, when the modulation scheme is 64QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bit group Gb1 includes code bit b0
  • code bit group Gb2 includes code bits b1 to b7
  • code bit group Gb3 includes code bits b8 to b11.
  • symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7
  • symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9.
  • Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.
  • FIG. 69 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, the modulation scheme is 64QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy2, 1), (Gb2, Gy2, 1), (Gb2, Gy3, 3), (Gb2, Gy1, 3), (Gb3, Gy3, 1), (Gb3, Gy2, 2) and (Gb3, Gy1, 1) are defined.
  • 3 bits of the code bit of the code bit group Gb2 having the second best error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • one bit of the sign bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy3 having the third highest error probability.
  • 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • FIG. 70 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 70 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, the modulation method is 64QAM and the multiple b is 2.
  • 69 shows a first example of code bit replacement according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y2 Sign bit b1 into symbol bit y8 Sign bit b2 to symbol bit y5 Sign bit b3 to symbol bit y11, Sign bit b4 to symbol bit y0, Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y1 Sign bit b7 to symbol bit y10 Sign bit b8 to symbol bit y4, Sign bit b9 to symbol bit y9, Sign bit b10 to symbol bit y3, Sign bit b11 to symbol bit y7 Replace each assigned.
  • FIG. 70B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 2/3, and further, when the modulation scheme is 64QAM and the multiple b is 2.
  • 69 shows a second example of code bit replacement according to the allocation rule of FIG. 69.
  • Sign bit b0 to symbol bit y2 Sign bit b1 into symbol bit y8 Sign bit b2 to symbol bit y11
  • Sign bit b3 into symbol bit y5 Sign bit b4 to symbol bit y0
  • Sign bit b5 to symbol bit y6 Sign bit b6 to symbol bit y1
  • Sign bit b8 to symbol bit y4 Sign bit b9 to symbol bit y3
  • Sign bit b10 into symbol bit y9, Sign bit b11 to symbol bit y7 Replace each assigned.
  • FIG. 71 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation scheme is 64QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bit group Gb1 includes code bit b0
  • code bit group Gb2 includes code bits b1 to b8
  • code bit group Gb3 includes code bits b9 to b11.
  • symbol bit group Gy1 includes symbol bits y0, y1, y6, and y7
  • symbol bit group Gy2 includes symbol bits y2, y3, y8, and y9.
  • Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.
  • FIG. 72 shows an allocation rule when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation scheme is 64QAM and the multiple b is 2. Is shown.
  • the group set information (Gb1, Gy2, 1), (Gb2, Gy2, 1), (Gb2, Gy3,4), (Gb2, Gy1, 3), (Gb3, Gy2, 2), (Gb3, Gy1, 1) is defined.
  • FIG. 73 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 73 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation method is 64QAM and the multiple b is 2.
  • 72 shows a first example of exchanging code bits according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y2 Sign bit b1 into symbol bit y8 Sign bit b2 to symbol bit y5 Sign bit b3 to symbol bit y11, Sign bit b4 to symbol bit y0, Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y1 Sign bit b7 to symbol bit y10 Sign bit b8 to symbol bit y4, Sign bit b9 to symbol bit y9, Sign bit b10 to symbol bit y3, Sign bit b11 to symbol bit y7 Replace each assigned.
  • 73B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further, when the modulation scheme is 64QAM and the multiple b is 2.
  • 72 shows a second example of code bit replacement in accordance with the allocation rule of FIG.
  • Sign bit b0 to symbol bit y2 Sign bit b1 into symbol bit y8 Sign bit b2 to symbol bit y4, Sign bit b3 into symbol bit y10, Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y0, Sign bit b6 to symbol bit y6, Sign bit b7 to symbol bit y11, Sign bit b8 to symbol bit y5 Sign bit b9 to symbol bit y3, Sign bit b10 into symbol bit y9, Sign bit b11 to symbol bit y7 Replace each assigned.
  • FIG. 74 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further having a modulation scheme of 64QAM and a multiple b of 2. A group and a symbol bit group are shown.
  • code bits b0 and b1 belong to code bit group Gb1
  • code bits b2 to b9 belong to code bit group Gb2
  • code bits b10 and b11 belong to code bit group Gb3, respectively.
  • symbol bit group Gy1 includes symbol bits y0, y1, y6, y7
  • symbol bit group Gy2 includes symbol bits y2, y3, y8, y9.
  • Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.
  • FIG. 75 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further having a modulation scheme of 64QAM and a multiple b of 2. Is shown.
  • group set information (Gb1, Gy2, 2), (Gb2, Gy3,4), (Gb2, Gy1, 3), (Gb2, Gy2, 1), (Gb3, Gy2, 1), (Gb3, Gy1, 1) is defined.
  • the group set information (Gb1, Gy2, 2) 2 bits of the code bit of the code bit group Gb1 having the first highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • the group set information (Gb2, Gy3,4) 4 bits of code bits of the code bit group Gb2 having the second highest error probability are allocated to 4 bits of symbol bits of the symbol bit group Gy3 having the third highest error probability.
  • 3 bits of the code bit of the code bit group Gb2 having the second best error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to
  • FIG. 76 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 76 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further, the modulation method is 64QAM and the multiple b is 2. 75 shows a first example of exchanging code bits according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y2 Sign bit b1 into symbol bit y8 Sign bit b2 to symbol bit y5 Sign bit b3 to symbol bit y11, Sign bit b4 to symbol bit y0, Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y1 Sign bit b7 to symbol bit y10 Sign bit b8 to symbol bit y4, Sign bit b9 to symbol bit y9, Sign bit b10 to symbol bit y3, Sign bit b11 to symbol bit y7 Replace each assigned.
  • 76B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further when the modulation scheme is 64QAM and the multiple b is 2.
  • 75 shows a second example of code bit replacement according to the assignment rule of FIG.
  • Sign bit b0 to symbol bit y8 Sign bit b1 to symbol bit y2 Sign bit b2 to symbol bit y4, Sign bit b3 into symbol bit y10, Sign bit b4 to symbol bit y6, Sign bit b5 to symbol bit y0, Sign bit b6 to symbol bit y1 Sign bit b7 to symbol bit y11, Sign bit b8 to symbol bit y5 Sign bit b9 to symbol bit y9, Sign bit b10 to symbol bit y3, Sign bit b11 to symbol bit y7 Replace each assigned.
  • FIG. 77 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further, the modulation method is 64QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bit b0 belongs to code bit group Gb1
  • code bits b1 to b10 belong to code bit group Gb2
  • code bit b11 belongs to code bit group Gb3.
  • symbol bits y0, y1, y6, and y7 are included in symbol bit group Gy1
  • symbol bits y2, y3, y8, and y9 are included in symbol bit group Gy2, as in B of FIG.
  • Symbol bits y4, y5, y10, and y11 belong to the symbol bit group Gy3, respectively.
  • FIG. 78 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further the modulation scheme is 64QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy2, 1), (Gb2, Gy2, 3), (Gb2, Gy3,4) (Gb2, Gy1, 3), (Gb3, Gy1, 1) are defined. Has been.
  • the group set information (Gb1, Gy2, 1) 1 bit of the code bit of the code bit group Gb1 having the first highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • the group set information (Gb2, Gy2, 3) 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • the group set information (Gb2, Gy3,4) 4 bits of code bits of the code bit group Gb2 having the second highest error probability are allocated to 4 bits of symbol bits of the symbol bit group Gy3 having the third highest error probability.
  • 3 bits of the code bit of the code bit group Gb2 having the second best error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • 1 bit of the sign bit of the code bit group Gb3 having the third highest error probability and 1 bit of the symbol bit of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to
  • FIG. 79 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 79 is a portable LDPC code whose LDPC code has a code length N of 4320 bits and a coding rate of 11/12, and further, the modulation method is 64QAM and the multiple b is 2.
  • 78 shows a first example of exchanging code bits according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y2 Sign bit b1 into symbol bit y8 Sign bit b2 to symbol bit y5 Sign bit b3 to symbol bit y11, Sign bit b4 to symbol bit y0, Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y1 Sign bit b7 to symbol bit y10 Sign bit b8 to symbol bit y4, Sign bit b9 to symbol bit y9, Sign bit b10 to symbol bit y3, Sign bit b11 to symbol bit y7 Replace each assigned.
  • 79B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further, when the modulation scheme is 64QAM and the multiple b is 2.
  • 78 shows a second example of code bit replacement in accordance with the assignment rule of FIG.
  • Sign bit b0 to symbol bit y2 Sign bit b1 to symbol bit y3, Sign bit b2 into symbol bit y10
  • Sign bit b3 to symbol bit y4 Sign bit b4 to symbol bit y6, Sign bit b5 to symbol bit y1, Sign bit b6 to symbol bit y0, Sign bit b7 to symbol bit y11, Sign bit b8 to symbol bit y5
  • Sign bit b9 to symbol bit y8 Sign bit b10 into symbol bit y9, Sign bit b11 to symbol bit y7 Replace each assigned.
  • FIG. 80 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/4, and further having a modulation scheme of 16QAM and a multiple b of 2. A group and a symbol bit group are shown.
  • code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.
  • code bit group Gb1 includes code bit b0
  • code bit group Gb2 includes code bit b1
  • code bit group Gb3 includes code bits b2 to b7.
  • symbol bits y0, y1, y4, and y5 belong to symbol bit group Gy1
  • symbol bits y2, y3, y6, and y7 belong to symbol bit group Gy2, respectively.
  • FIG. 81 shows an allocation rule when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 1/4, and further the modulation scheme is 16QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy2, 1), (Gb2, Gy2, 1), (Gb3, Gy2, 2), (Gb3, Gy1, 4) are defined.
  • FIG. 82 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 82 is a case where the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 1/4, and the modulation scheme is 16QAM and the multiple b is 2.
  • 81 shows a first example of code bit replacement according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y7 Sign bit b1 to symbol bit y6, Sign bit b2 to symbol bit y4, Sign bit b3 into symbol bit y3 Sign bit b4 to symbol bit y2 Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y1 Sign bit b7 to symbol bit y0, Replace each assigned.
  • B in FIG. 82 is a portable LDPC code with an LDPC code having a code length N of 4320 bits and an encoding rate of 1/4, and further, when the modulation scheme is 16QAM and the multiple b is 2.
  • 81 shows a second example of code bit replacement according to the allocation rule of FIG.
  • Sign bit b0 to symbol bit y7 Sign bit b1 to symbol bit y6, Sign bit b2 to symbol bit y1, Sign bit b3 to symbol bit y2 Sign bit b4 to symbol bit y3, Sign bit b5 to symbol bit y4, Sign bit b6 to symbol bit y0, Sign bit b7 to symbol bit y5, Replace each assigned.
  • FIG. 83 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further when the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • the sign bit group Gb1 includes the sign bit b0
  • the sign bit group Gb2 includes the sign bit b1
  • the sign bit group Gb3 includes the sign bit b2
  • the sign bit group Gb4 includes the sign bit. Bits b3 to b7 belong to each.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.
  • FIG. 84 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further, when the modulation scheme is 16QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy2, 1), (Gb2, Gy2, 1), (Gb3, Gy1, 1), (Gb4, Gy2, 2), (Gb4, Gy1, 3) It is prescribed.
  • FIG. 85 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 85 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 1/3, and further, the modulation method is 16QAM and the multiple b is 2.
  • 84 shows a first example of exchanging code bits according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y7 Sign bit b1 to symbol bit y6, Sign bit b2 to symbol bit y4, Sign bit b3 into symbol bit y3 Sign bit b4 to symbol bit y2 Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y1 Sign bit b7 to symbol bit y0, Replace each assigned.
  • B in FIG. 85 is a portable LDPC code in which the LDPC code has a code length N of 4320 bits and a coding rate of 1/3, and the modulation scheme is 16QAM, and the multiple b is 2.
  • 84 shows a second example of code bit replacement according to the allocation rule of FIG.
  • FIG. 86 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 5/12, and further when the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bits read from the memory 31 are divided into four code bit groups Gb1, Gb2, Gb3, Gb1, as shown in FIG. Can be grouped into Gb4.
  • the sign bit group Gb1 includes the sign bit b0
  • the sign bit group Gb2 includes the sign bits b1 and b2
  • the sign bit group Gb3 includes the sign bit b3
  • the sign bit group Gb4 includes the sign bit b3.
  • the code bits b4 to b7 belong respectively.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.
  • FIG. 87 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further has a modulation scheme of 16QAM and a multiple b of 2. Is shown.
  • the group set information (Gb1, Gy1, 1), (Gb2, Gy1, 1), (Gb2, Gy2, 1), (Gb3, Gy2, 1), (Gb4, Gy1, 2), (Gb4, Gy2, 2) is specified.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • 2 bits of the code bit of the code bit group Gb4 having the fourth highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • 2 bits of the sign bit of the code bit group Gb4 having the fourth highest error probability and 2 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to
  • FIG. 88 shows an example of exchanging code bits according to the allocation rule of FIG.
  • 88A shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further, the modulation method is 16QAM and the multiple b is 2.
  • 87 shows a first example of exchanging code bits according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y2 Sign bit b3 into symbol bit y6 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • 88B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/12, and further when the modulation method is 16QAM and the multiple b is 2.
  • 87 shows a second example of code bit replacement according to the assignment rule of FIG.
  • FIG. 89 shows a code bit when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. 89A according to the difference in error probability. Can be grouped.
  • the code bit group Gb1 includes the code bit b0
  • the code bit group Gb2 includes the code bits b1 to b3
  • the code bit group Gb3 includes the code bits b4 to b7.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.
  • FIG. 90 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 16QAM and the multiple b is 2. Is shown.
  • the group set information (Gb1, Gy2, 1), (Gb2, Gy2, 2), (Gb2, Gy1, 1), (Gb3, Gy2, 1), (Gb3, Gy1, 3) It is prescribed.
  • the group set information (Gb1, Gy2, 1) 1 bit of the code bit of the code bit group Gb1 having the first highest error probability is assigned to 1 bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • the group set information (Gb2, Gy2, 2) 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • the group set information (Gb3, Gy1, 3) 3 bits of the code bit of the code bit group Gb3 having the third highest error probability, and 3 bits of the symbol bits of the symbol bit group Gy1 having the highest error probability It is stipulated to be assigned to
  • FIG. 91 shows an example of exchanging code bits according to the assignment rule of FIG.
  • a in FIG. 91 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, the modulation method is 16QAM and the multiple b is 2.
  • 90 shows a first example of code bit replacement in accordance with the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y7 Sign bit b1 to symbol bit y6, Sign bit b2 to symbol bit y4, Sign bit b3 into symbol bit y3 Sign bit b4 to symbol bit y2 Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y1 Sign bit b7 to symbol bit y0, Replace each assigned.
  • 91B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 1/2, and further, when the modulation scheme is 16QAM and the multiple b is 2.
  • 90 shows a second example of code bit replacement according to the assignment rule of FIG.
  • FIG. 92 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and an encoding rate of 7/12, and further when the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • the sign bit group Gb1 includes the sign bit b0
  • the sign bit group Gb2 includes the sign bits b1 to b3
  • the sign bit group Gb3 includes the sign bit b4
  • the sign bit group Gb4 includes the sign bit b4.
  • the code bits b5 to b7 belong respectively.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.
  • FIG. 93 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 7/12, and further, when the modulation scheme is 16QAM and the multiple b is 2. Is shown.
  • the group set information (Gb1, Gy1, 1), (Gb2, Gy1, 1), (Gb2, Gy2, 2), (Gb3, Gy1, 1), (Gb4, Gy1, 1), (Gb4, Gy2, 2) is specified.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • one bit of the code bit of the code bit group Gb4 having the fourth highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 2 bits of the sign bit of the code bit group Gb4 having the fourth highest error probability and 2 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to
  • FIG. 94 shows an example of exchanging code bits in accordance with the assignment rule of FIG.
  • a in FIG. 94 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further the modulation method is 16QAM and the multiple b is 2.
  • 93 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y2 Sign bit b3 into symbol bit y6 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • FIG. 94B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 7/12, and further when the modulation method is 16QAM and the multiple b is 2.
  • 93 shows a second example of code bit replacement according to the assignment rule of FIG.
  • FIG. 95 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 2/3, and further when the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bits read out from the memory 31 are divided into four code bit groups Gb1, Gb2, Gb3, Gb1, as shown in FIG. Can be grouped into Gb4.
  • the sign bit group Gb1 includes the sign bit b0
  • the sign bit group Gb2 includes the sign bits b1 to b4
  • the sign bit group Gb3 includes the sign bit b5
  • the sign bit group Gb4 includes the sign bit b5.
  • the code bits b6 and b7 belong respectively.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.
  • FIG. 96 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, when the modulation scheme is 16QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy1, 2), (Gb2, Gy2, 2), (Gb3, Gy1, 1), (Gb4, Gy2, 2) It is prescribed.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 2 bits of the sign bit of the code bit group Gb4 having the fourth highest error probability and 2 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability It is stipulated to be assigned to
  • FIG. 97 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 97 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, and further, the modulation method is 16QAM and the multiple b is 2.
  • 96 shows a first example of exchanging code bits in accordance with the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y2 Sign bit b3 into symbol bit y6 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • FIG. 97B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 2/3, a modulation scheme of 16QAM, and a multiple b of 2.
  • 96 shows a second example of code bit replacement according to the assignment rule of FIG.
  • FIG. 98 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 3/4, and the modulation method is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.
  • code bit b0 belongs to code bit group Gb1
  • code bits b1 to b5 belong to code bit group Gb2
  • code bits b6 and b7 belong to code bit group Gb3, respectively.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.
  • FIG. 99 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation scheme is 16QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy1, 3), (Gb2, Gy2, 2), (Gb3, Gy2, 2) are defined.
  • the group set information (Gb1, Gy1, 1) one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • the group set information (Gb2, Gy1, 3) 3 bits of the code bit of the code bit group Gb2 having the second best error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • the group set information (Gb2, Gy2, 2) 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • FIG. 100 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 100 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 3/4, and further, the modulation method is 16QAM and the multiple b is 2.
  • FIG. 99 shows a first example of code bit replacement according to the assignment rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y2 Sign bit b3 into symbol bit y6 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • B in FIG. 100 is a portable LDPC code in which the LDPC code has a code length N of 4320 bits and a coding rate of 3/4, and the modulation scheme is 16QAM and the multiple b is 2. 99 shows a second example of code bit replacement according to the allocation rule of FIG.
  • FIG. 101 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and a coding rate of 5/6, and the modulation scheme is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bits read out from the memory 31 are divided into five code bit groups Gb1, Gb2, Gb3, Gb1, as shown in FIG. Can be grouped into Gb4 and Gb5.
  • the sign bit group Gb1 includes the sign bit b0
  • the sign bit group Gb2 includes the sign bit b1
  • the sign bit group Gb3 includes the sign bits b2 to b5
  • the sign bit group Gb4 includes the sign bit b1.
  • the code bit b6 belongs to the code bit group Gb5, and the code bit b7 belongs to the code bit group Gb5.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.
  • FIG. 102 shows an allocation rule when the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further having a modulation scheme of 16QAM and a multiple b of 2. Is shown.
  • the group set information (Gb1, Gy1, 1), (Gb2, Gy1, 1), (Gb3, Gy2, 2), (Gb3, Gy1, 2), (Gb4, Gy2, 1), (Gb5, Gy2, 1) is specified.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • 2 bits of the code bit of the code bit group Gb3 having the third highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • FIG. 103 shows an example of exchanging code bits in accordance with the assignment rule of FIG.
  • a in FIG. 103 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further, the modulation method is 16QAM and the multiple b is 2.
  • 102 shows a first example of code bit replacement according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y2 Sign bit b3 into symbol bit y6 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • FIG. 103B shows a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and a coding rate of 5/6, and further when the modulation scheme is 16QAM and the multiple b is 2.
  • 102 shows a second example of code bit replacement according to the assignment rule of FIG.
  • FIG. 104 shows a code bit when the LDPC code is a portable LDPC code with a code length N of 4320 bits and an encoding rate of 11/12, and further when the modulation scheme is 16QAM and the multiple b is 2. A group and a symbol bit group are shown.
  • code bits read from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.
  • code bit group Gb1 includes code bit b0
  • code bit group Gb2 includes code bits b1 to b6
  • code bit group Gb3 includes code bit b7.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7. Belong to each.
  • FIG. 105 shows an allocation rule when the LDPC code is a portable LDPC code with a code length N of 4320 bits and an encoding rate of 11/12, and further the modulation scheme is 16QAM and the multiple b is 2. Is shown.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy2, 3), (Gb2, Gy1, 3), (Gb3, Gy2, 1) is defined.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 3 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • 3 bits of the code bit of the code bit group Gb2 having the second best error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • FIG. 106 shows an example of exchanging code bits according to the assignment rule of FIG.
  • a in FIG. 106 is a case where the LDPC code is a portable LDPC code having a code length N of 4320 bits and an encoding rate of 11/12, and further, the modulation scheme is 16QAM and the multiple b is 2.
  • 105 shows a first example of exchanging code bits according to the allocation rule of FIG.
  • the demultiplexer 25 uses the column direction ⁇
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y2 Sign bit b3 into symbol bit y6 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • B in FIG. 106 is an LDPC code in which the code length N is 4320 bits and the code rate is 11/12 portable LDPC code, and the modulation scheme is 16QAM and the multiple b is 2.
  • 105 shows a second example of code bit replacement according to the assignment rule of FIG.
  • FIGS. 124A and 124B show simulation results of BER (Bit ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ Error Rate) when the replacement process of the new replacement method is performed and when the replacement process is not performed.
  • the code length N is 4320, and the coding rate is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3/4, 5 /.
  • the BER is shown when 64QAM is adopted as a modulation method for portable LDPC codes (FIGS. 35 to 43) of 6, 11/12.
  • the code length N is 4320, and the coding rate is 1/4, 1/3, 5/12, 1/2, 7/12, 2/3, 3/4, 5/6,
  • the BER is shown for 11/12 portable LDPC codes and 16QAM is used as the modulation method.
  • the multiple b is 2.
  • the horizontal axis represents E s / N 0 (signal power to noise power ratio per symbol), and the vertical axis represents BER.
  • a circle ( ⁇ ) represents the BER when the replacement process of the new replacement method is performed, and the asterisk represents the BER when the replacement process is not performed.
  • a dedicated bit allocation pattern can be employed for the LDPC code.
  • the bit allocation pattern implemented in the transmission apparatus 11 can be reduced.
  • the code bit b0 shown in A of FIGS. 58, 61, 64, and 67 is used.
  • the replacement unit 32 performs the replacement process for the code bit read from the memory 31, but the replacement process is performed in the memory 31. This can be done by controlling the writing and reading of the sign bit for.
  • the replacement process can be performed, for example, by controlling the address (read address) from which the code bits are read so that the code bits are read from the memory 31 in the order of the code bits after the replacement.
  • DVB-T.2 For an LDPC code having a code length of 4k bits (hereinafter, also referred to as a first 4k code) obtained using a parity check matrix obtained from the parity check matrix initial value table of FIGS. 35 to 43, DVB-T.2 From the standpoint of maintaining the affinity with the PSB as much as possible, 360 as specified in DVB-T.2 is used as the number of columns P of the unit of the cyclic structure, as in the LDPC code specified in DVB-T.2. It has been adopted.
  • FIGS. 125 to 128 are diagrams showing examples of a parity check matrix initial value table of a second 4k code that is a portable LDPC code having a code length of 4k bits, which is different from the first 4k code.
  • FIG. 125 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 1/2.
  • 126 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 7/12.
  • 127 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 2/3.
  • 128 shows a parity check matrix initial value table for a parity check matrix H having a code length N of 4k bits and a code rate r of 3/4.
  • parity matrix of the parity check matrix obtained from the parity check matrix initial value table of FIGS. 125 to 128 has a staircase structure (FIG. 11).
  • the second 4k code which is an LDPC code having a 4k-bit code length obtained using the parity check matrix obtained from the parity check matrix initial value table of FIGS. 125 to 128, is defined in DVB-T.2. Similar to the LDPC code, the information matrix of the check matrix H has a cyclic structure.
  • the number P of units of the cyclic structure unit is not 360, but 72, which is one of the divisors of 360.
  • LDPC encoder 115 uses a parity check matrix obtained from the parity check matrix initial value table shown in FIGS. 125 to 128, and has a code length N of 4k bits and a coding rate r of 1/2. , 7/12, 2/3, and 3/4, LDPC encoding to any second 4k code can be performed.
  • the LDPC encoder 115 sets the number of columns P of the cyclic structure as 72 instead of 360, from the parity check matrix initial value table shown in FIGS. 125 to 128, as in the case described in FIG. A parity check matrix is obtained, and LDPC encoding to the second 4k code is performed using the parity check matrix.
  • the second 4k code (the check matrix initial value table) in FIGS. 125 to 128 was obtained by performing a simulation similar to the simulation for obtaining the first 4k code in FIGS.
  • an ensemble in which the performance threshold at which Eb / N 0 starts to decrease (becomes smaller) due to multi-edge type density evolution is equal to or less than a predetermined value is found. From among the LDPC codes belonging to the ensemble, an LDPC code that reduces the BER in a plurality of modulation schemes used in digital broadcasting for mobile terminals, such as 16QAM and 64QAM, was selected as a high-performance LDPC code.
  • the number of signal points such as QPSK, 16QAM, 64QAM, and the like is compared in order to improve tolerance to errors, similarly to the simulation for obtaining the first 4k code.
  • FIG. 129 is obtained from the parity check matrix initial value tables of the second 4k codes of the four types of coding rates r of 1/2, 7/12, 2/3, and 3/4 in FIGS. 125 to 128. It is a figure which shows the minimum cycle length and performance threshold value of the check matrix which are calculated
  • the minimum cycle length of the parity check matrix obtained from the parity check matrix initial value table of FIGS. 125 to 128 is all 6 cycles, and cycle 4 does not exist.
  • the performance threshold increases (becomes smaller) as the encoding rate r decreases.
  • FIG. 130 is a diagram for explaining the parity check matrix (of the second 4k code obtained from the parity check matrix initial value table) in FIGS. 125 to 128.
  • the column weight of the KX column from the first column is X
  • the subsequent KY The column weight of the column is Y
  • the column weight of the subsequent M-1 column is 2
  • the column weight of the last column is 1.
  • the weights X and Y are as shown in FIG.
  • the second 4k code parity check matrix is the same as the parity check matrix defined in DVB-T.2 described with reference to FIGS. 12 and 13 and the first 4k code parity check matrix.
  • the column weight tends to be larger in the column, and therefore, the first code bit of the second 4k code tends to be more resistant to errors (tolerant to errors).
  • FIG. 131 is a diagram showing a result of BER simulation performed on the second 4k code.
  • the horizontal axis represents E s / N 0 (signal power to noise power ratio per symbol), and the vertical axis represents BER.
  • the second 4k code is better than the first 4k code. It has been confirmed that the BER is improved. Therefore, according to the second 4k code, tolerance against errors can be improved.
  • the replacement unit 32 performs a replacement process (in the new replacement method) performed by the replacement unit 32 in order to further improve the resistance to errors.
  • the replacement process will be described.
  • FIG. 132 shows a code bit group and a symbol bit group when the LDPC code is a second 4k code with a coding rate of 1/2, the modulation scheme is 16QAM, and the multiple b is 2. Show.
  • code bits read out from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.
  • code bit group Gb1 includes code bit b0
  • code bit group Gb2 includes code bits b1 to b3
  • code bit group Gb3 includes code bits b4 to b7.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7, respectively.
  • FIG. 133 shows an allocation in the case where the LDPC code is a second 4k code having a code length N of 4320 bits and a coding rate of 1/2, a modulation scheme of 16QAM, and a multiple b of 2. Shows the rules.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy1, 2), (Gb2, Gy2, 1), (Gb3, Gy1, 1), (Gb3, Gy2, 3) It is prescribed.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • the group set information (Gb3, Gy2, 3) 3 bits of the sign bit of the code bit group Gb3 having the third highest error probability, and 3 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability Assigning to, Is stipulated.
  • FIG. 134 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 134 is an allocation rule in FIG. 133 when the LDPC code is a second 4k code with a coding rate of 1/2, the modulation scheme is 16QAM, and the multiple b is 2.
  • 1 shows a first example of exchanging code bits according to FIG.
  • the demultiplexer 25 has (4320 / column direction ⁇ column direction).
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y1, Sign bit b3 into symbol bit y6 Sign bit b4 to symbol bit y2 Sign bit b5 to symbol bit y5 Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • B in FIG. 134 follows the allocation rule in FIG. 133 when the LDPC code is the second 4k code with a coding rate of 1/2, the modulation scheme is 16QAM, and the multiple b is 2. 2 shows a second example of exchanging code bits.
  • FIG. 135 shows code bit groups and symbol bit groups when the LDPC code is a second 4k code with a coding rate of 7/12, the modulation scheme is 16QAM, and the multiple b is 2. Show.
  • the sign bit group Gb1 contains the sign bit b0
  • the sign bit group Gb2 contains the sign bits b1 to b3
  • the sign bit group Gb3 contains the sign bit b4
  • the sign bit group Gb4 contains the sign bit b4.
  • the code bits b5 to b7 belong respectively.
  • symbol bits y0, y1, y4, and y5 belong to symbol bit group Gy1
  • symbol bits y2, y3, y6, and y7 belong to symbol bit group Gy2, respectively.
  • FIG. 136 shows an allocation in the case where the LDPC code is a second 4k code having a code length N of 4320 bits and a coding rate of 7/12, a modulation scheme of 16QAM, and a multiple b of 2. Shows the rules.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy1, 2), (Gb2, Gy2, 1), (Gb3, Gy1, 1), (Gb4, Gy2, 3) It is prescribed.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • the group set information (Gb4, Gy2, 3) 3 bits of the sign bit of the code bit group Gb4 having the fourth highest error probability and 3 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability Assigning to, Is stipulated.
  • FIG. 137 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 137 is an allocation rule in FIG. 136 when the LDPC code is the second 4k code with a coding rate of 7/12, the modulation scheme is 16QAM, and the multiple b is 2.
  • 1 shows a first example of exchanging code bits according to FIG.
  • the demultiplexer 25 has (4320 / column direction ⁇ column direction).
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y5 Sign bit b3 to symbol bit y2 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • B in FIG. 137 follows the allocation rule in FIG. 136 when the LDPC code is the second 4k code with a coding rate of 7/12, the modulation scheme is 16QAM, and the multiple b is 2. 2 shows a second example of exchanging code bits.
  • the replacement unit 32 follows the allocation rule of FIG. Sign bit b0 to symbol bit y1 Sign bit b1 into symbol bit y5 Sign bit b2 to symbol bit y4, Sign bit b3 to symbol bit y2 Sign bit b4 to symbol bit y0, Sign bit b5 to symbol bit y3, Sign bit b6 to symbol bit y6, Sign bit b7 into symbol bit y7 Replace each assigned.
  • FIG. 138 shows a code bit group and a symbol bit group when the LDPC code is a second 4k code with a coding rate of 2/3, the modulation scheme is 16QAM, and the multiple b is 2. Show.
  • the sign bit group Gb1 contains the sign bit b0
  • the sign bit group Gb2 contains the sign bits b1 to b4
  • the sign bit group Gb3 contains the sign bit b5
  • the sign bit group Gb4 contains the sign bit b5.
  • the code bits b6 and b7 belong respectively.
  • symbol bit group Gy1 includes symbol bits y0, y1, y4, and y5
  • symbol bit group Gy2 includes symbol bits y2, y3, y6, and y7, respectively.
  • FIG. 139 shows an allocation when the LDPC code is a second 4k code with a code length N of 4320 bits and a coding rate of 2/3, a modulation scheme of 16QAM, and a multiple b of 2. Shows the rules.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy1, 3), (Gb2, Gy2, 1), (Gb3, Gy2, 1), (Gb4, Gy2, 2) It is prescribed.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is represented by the symbol bit group having the first error probability. Assigning to 1 bit of Gy1 symbol bit, According to the group set information (Gb2, Gy1, 3), 3 bits of the code bit of the code bit group Gb2 having the second best error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy1 having the best error probability. thing, According to the group set information (Gb2, Gy2, 1), one bit of the sign bit of the code bit group Gb2 having the second highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • one bit of the code bit of the code bit group Gb3 having the third highest error probability is assigned to one bit of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • the group set information (Gb4, Gy2, 2) 2 bits of the sign bit of the code bit group Gb4 having the fourth highest error probability and 2 bits of the symbol bits of the symbol bit group Gy2 having the second highest error probability Assigning to, Is stipulated.
  • FIG. 140 shows an example of exchanging code bits according to the allocation rule of FIG.
  • a in FIG. 140 is the allocation rule in FIG. 139 when the LDPC code is the second 4k code with a coding rate of 2/3, the modulation scheme is 16QAM, and the multiple b is 2.
  • 1 shows a first example of exchanging code bits according to FIG.
  • the demultiplexer 25 has (4320 / column direction ⁇ row direction).
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y5 Sign bit b3 to symbol bit y2 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • 140B corresponds to the allocation rule in FIG. 139 when the LDPC code is the second 4k code with a coding rate of 2/3, the modulation scheme is 16QAM, and the multiple b is 2. 2 shows a second example of exchanging code bits.
  • Sign bit b0 to symbol bit y4 Sign bit b1 to symbol bit y0, Sign bit b2 to symbol bit y1, Sign bit b3 to symbol bit y7
  • Sign bit b4 to symbol bit y5 Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y3, Sign bit b7 to symbol bit y2
  • Sign bit b0 to symbol bit y4 Sign bit b1 to symbol bit y0
  • Sign bit b2 to symbol bit y1 Sign bit b3 to symbol bit y7
  • Sign bit b4 to symbol bit y5 Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y3, Sign bit b7 to symbol bit y2
  • Sign bit b0 to symbol bit y4 Sign bit b1 to symbol bit y0, Sign
  • FIG. 141 shows a code bit group and a symbol bit group when the LDPC code is a second 4k code with a coding rate of 3/4, the modulation scheme is 16QAM, and the multiple b is 2. Show.
  • code bits read out from the memory 31 are divided into three code bit groups Gb1, Gb2, and Gb3 as shown in FIG. Can be grouped.
  • code bit group Gb1 includes code bit b0
  • code bit group Gb2 includes code bits b1 to b5
  • code bit group Gb3 includes code bits b6 and b7.
  • symbol bits y0, y1, y4, and y5 belong to symbol bit group Gy1
  • symbol bits y2, y3, y6, and y7 belong to symbol bit group Gy2, respectively.
  • FIG. 142 shows an allocation in the case where the LDPC code is a second 4k code having a code length N of 4320 bits and a coding rate of 3/4, a modulation scheme of 16QAM, and a multiple b of 2. Shows the rules.
  • group set information (Gb1, Gy1, 1), (Gb2, Gy1, 3), (Gb2, Gy2, 2), (Gb3, Gy2, 2) are defined.
  • one bit of the code bit of the code bit group Gb1 having the highest error probability is allocated to one bit of the symbol bit of the symbol bit group Gy1 having the highest error probability.
  • 3 bits of the code bit of the code bit group Gb2 having the second best error probability are allocated to 3 bits of the symbol bit of the symbol bit group Gy1 having the best error probability.
  • 2 bits of the code bit of the code bit group Gb2 having the second highest error probability are allocated to 2 bits of the symbol bit of the symbol bit group Gy2 having the second highest error probability.
  • FIG. 143 shows an example of exchanging code bits according to the assignment rule of FIG.
  • a in FIG. 143 is the allocation rule in FIG. 142 when the LDPC code is the second 4k code with a coding rate of 3/4, the modulation scheme is 16QAM, and the multiple b is 2.
  • 1 shows a first example of exchanging code bits according to FIG.
  • the demultiplexer 25 has (4320 / column direction ⁇ column direction).
  • the replacement unit 32 Sign bit b0 to symbol bit y0, Sign bit b1 into symbol bit y4 Sign bit b2 to symbol bit y5 Sign bit b3 to symbol bit y2 Sign bit b4 to symbol bit y1, Sign bit b5 to symbol bit y6, Sign bit b6 to symbol bit y3, Sign bit b7 into symbol bit y7 Replace each assigned.
  • FIG. 143 B in FIG. 143 follows the assignment rule in FIG. 142 when the LDPC code is the second 4k code with a coding rate of 3/4, the modulation scheme is 16QAM, and the multiple b is 2. 2 shows a second example of exchanging code bits.
  • resistance to errors can be improved by performing the replacement process using the new replacement method as described above.
  • bit allocation patterns corresponding to the number (type) of the second 4k codes having different coding rates can be obtained. There is a need to install the transmitter 11, and it may be necessary to change (switch) the bit allocation pattern for each type of LDPC code having a different coding rate.
  • the bit allocation pattern implemented in the transmission apparatus 11 can be reduced.
  • the code bits b0 to b7 shown in FIG. 132A are replaced with the symbol bits y0, y4, y1, y6, y2, y5, y3, y7, respectively.
  • the bit allocation pattern assigned to For the second 4k codes with coding rates of 7/12, 2/3, and 3/4, the code bits b0 to b7 shown in FIG. 137, FIG. 140, and FIG. Bit allocation pattern to be assigned to symbol bits y0, y4, y5, y2, y1, y6, y3, y7, By adopting each of them, it is only necessary to mount two patterns of bit allocation patterns in the transmission device 11.
  • LDPC encoder 115 when performing LDPC encoding to the second 4k code using the parity check matrix (obtained from the parity check matrix initial value table) shown in FIGS. 125 to 128
  • the write start position of each column (FIG. 24) of the memory 31 is defined in DVB-T.2. This is different from the writing start position in the case of the LDPC code (FIGS. 25 and 26) and the writing start position in the case of the first 4k code (FIG. 49).
  • FIG. 144 is a diagram showing the number of columns of the memory 31 necessary for column twist interleaving and the address of the writing start position for the second 4k code.
  • FIG. 144 four types (check matrixes) of FIGS. 125 to 128, in which the code length N is 4k bits and the coding rate r is 1/2, 7/12, 2/3, and 3/4.
  • the code length N is 4k bits
  • the coding rate r is 1/2, 7/12, 2/3, and 3/4.
  • the second 4k code obtained from the parity check matrix obtained from the initial value table
  • the number of columns of the memory 31 necessary for column twist interleaving and the address of the writing start position are indicated for each modulation method.
  • QPSK, 16QAM, and 64QAM which have a relatively small number of signal points, are employed as the modulation method, as in the first 4k code.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 14 position. Is done.
  • the multiple b is 2 and QPSK is adopted as the modulation scheme
  • the multiple b is 1 and the modulation scheme is 1 even when the bit number m of one symbol is 2 bits.
  • the write start position of the first column of the four columns of the memory 31 has an address of 0
  • the position and the start position of the second column are the position where the address is 18, the start position of the third column is the position where the address is 49, and the start position of the fourth column is Addresses are made with 11 positions, respectively.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • 3 The start position of the second column is the position where the address is 32
  • the start position of the fourth column is the position where the address is 13
  • the start position of the fifth column is the position where the address is 8.
  • the position and the position at the beginning of writing in the sixth column are set as the position where the address is 0, respectively.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 3 position
  • the first column write position is the position where the address is 18, the fourth column start position is the address 73
  • the fifth column start position is the address 8.
  • the position and the start position of writing the sixth column are the position where the address is 14, the start position of the seventh column is the position where the address is 6, and the start position of the eighth column is Each address is made with 8 positions.
  • the memory 31 stores 6 ⁇ 2 bits in the row direction. 12 columns and 4320 / (6 ⁇ 2) bits are stored in the column direction.
  • the first column write start position is the address 0 position
  • the second column write start position is the address 0 position
  • the start position of the second column is the position where the address is 0
  • the start position of the fourth column is the position where the address is 0
  • the start position of the fifth column is the position where the address is 32.
  • the position and the start position of writing the sixth column are the position where the address is 8
  • the start position of the seventh column is the position where the address is 87
  • the start position of the eighth column is
  • the address 28 position and the 9th column start writing position are the address 31 position and the 10th column writing start position are the address 23 and 11th column start writing.
  • the position of is the position of address 5 and the 12th
  • the starting position for writing the ram is the position with address 3 respectively.
  • FIG. 145, FIG. 146, FIG. 147, and FIG. 148 are diagrams showing the results of BER and FER (Frame Error Rate) simulations performed on the second 4k code.
  • the horizontal axis represents E s / N 0 (signal power to noise power ratio per symbol), and the vertical axis represents BER and FER.
  • FIG. 145 shows the BER (solid line) and FER (dotted line) of the second 4k code with a coding rate r of 1/2
  • FIG. 146 shows the second 4k code with a coding rate r of 7/12.
  • FIG. 147 shows the BER (solid line) and FER (dotted line) of the second 4k code with a coding rate r of 2/3
  • FIG. 148 shows the second 4k with a coding rate r of 3/4. It represents the BER (solid line) and FER (dotted line) of the code.
  • a communication path (Rayleigh channel) where Rayleigh fading has an erasure probability of 0.25, where a symbol is erased, and a communication path where Rayleigh fading has an erasure probability of 0.209, is simulated in FIG.
  • a communication path in which Rayleigh fading with an erasure probability of 0.167 is assumed, and in the simulation of FIG. 148, a communication path in which Rayleigh fading with an erasure probability of 0.125 is assumed.
  • the multiple b is set to 2, and 16QAM is adopted as the modulation method, and 50 times is adopted as the number of iterations C.

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Abstract

La présente invention porte sur un dispositif de traitement de données et un procédé de traitement de données qui sont aptes à améliorer la tolérance par rapport à des erreurs. Un code LDPC ayant une longueur de code de 4 320 bits est écrit dans la direction de colonne et lu dans la direction de rangée d'une mémoire (31). Deux, quatre ou six bits de code lu dans la mémoire (31) est défini comme étant un symbole et est mappé à 22, 24 ou 26 points de signal. Un entrelaceur à vrillage de colonne réalise un entrelacement à vrillage de colonne, afin de changer, pour chaque colonne de la mémoire (31), la position de début d'écriture lorsqu'un bit de code est écrit dans la direction de colonne de la mémoire (31) en tant que processus de transposition dans lequel des bits de code d'un code LDPC sont transposés, de sorte qu'une pluralité des bits de code correspondant à « 1 » existant dans n'importe quelle ligne d'une matrice de contrôle du code LDPC ne soient pas inclus dans un symbole unique. La présente invention peut être appliquée, par exemple, lorsqu'un code LDPC est transmis.
PCT/JP2011/072952 2010-10-14 2011-10-05 Dispositif de traitement de données et procédé de traitement de données WO2012050020A1 (fr)

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US10797828B2 (en) 2013-12-17 2020-10-06 Huawei Technologies Co.,Ltd. Data receiving method and device, and data sending method and device
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