WO2012040946A1

WO2012040946A1 - Liquid crystal display panel and manufacturing method thereof

Info

Publication number: WO2012040946A1
Application number: PCT/CN2010/078435
Authority: WO
Inventors: 林师勤; 贺成明
Original assignee: 深圳市华星光电技术有限公司
Priority date: 2010-09-28
Filing date: 2010-11-04
Publication date: 2012-04-05
Also published as: CN102023445A

Abstract

A liquid crystal display panel and manufacturing method thereof are provided. Transparent electrode layers (222b, 522b) are provided on thin film transistors (100, 400) as the shift register (50) while transparent electrode layers (222a, 522a) as the pixel electrodes are provided, and the transparent electrode layers (222b, 522b) can shield the influence on the thin film transistors (100, 400) caused by the common voltage of the common voltage electrode layer. Therefore, the I-V characteristic graph of the thin film transistors (100, 400) can not be shifted due to the common voltage of the common voltage electrode layer, the power consumption at work can be reduced, and the using life of the thin film transistors can be improved, while the problem of the abnormal picture display caused by the failure of the power supply chip due to excessive current can be avoided.

Description

Liquid crystal display panel and method of manufacturing the same

The invention relates to a liquid crystal display panel and a manufacturing method thereof, in particular to a displacement register formed by directly covering an amorphous silicon thin film transistor with a conductive layer to isolate the voltage of the glass substrate from the amorphous silicon thin film transistor. Liquid crystal display panel and its manufacturing method. The liquid crystal display panel of the dragon conventional liquid crystal display comprises a plurality of pixels, and each pixel comprises three pixel units respectively representing three primary colors of red, green and blue (RGB). When the scan signal outputted by the gate driver causes the thin film transistors of the pixel units of each column to be sequentially turned on, the source driver outputs corresponding data signals to an entire column of pixel units to charge them to respective required voltages to display different Grayscale. The gate driver outputs the scan signals in a row and a column to turn on the thin film transistors of the pixel cells of each column, and then the pixel drivers of each column are charged and discharged by the source driver. In this way, until all the pixel units of the liquid crystal display panel are charged, charging is started from the first column. In current liquid crystal display panel designs, the gate driver includes a shift register for outputting a scan signal to the liquid crystal display panel at regular intervals. However, for gate drivers using amorphous silicon thin film process technology, the shift register can be directly applied to a glass substrate. However, after the liquid crystal display panel is lit, the performance of the liquid crystal display panel is often abnormal due to the shift of the IV characteristic curve. One of the reasons is the thin film crystal of the shift register. The body tube will be affected by the voltage of the glass substrate of the upper substrate, so that the opening voltage of the thin film transistor

(threshold voltage) offset. This affects the effective operation of the thin film transistor, which in turn affects the lifetime of the thin film transistor. Moreover, the degree of shift of the I-V characteristic curve is also easy to cause the power supply chip on the circuit board to malfunction due to excessive current, causing the screen display to be abnormal. Summary of the invention

In view of the above, the present invention provides a liquid crystal display panel and a method of fabricating the same, which directly covers a shift register formed by an amorphous silicon thin film transistor by using a conductive layer to isolate the influence of the voltage of the glass substrate on the amorphous silicon thin film transistor. .

According to an embodiment of the invention, a liquid crystal display panel has a display area and a non-display area, and the liquid crystal display panel further includes a glass substrate, a plurality of first thin film transistors, a plurality of second thin film transistors, and a passivation layer. a first transparent electrode layer and a second transparent electrode layer. The plurality of first thin film transistors are located on the non-display area corresponding to the glass substrate, and include a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and the semiconductor layer a layer and a source and a drain on the insulating layer. The plurality of second thin film transistors are located on the display area corresponding to the glass substrate, and include a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and the semiconductor layer And a source and a drain on the insulating layer. The passivation layer is located on a source and a drain of the first thin film transistor and a source and a drain of the second thin film transistor. The first transparent electrode layer is located above the first thin film transistor via the passivation layer. The second transparent electrode layer is electrically connected to the drain or the source of the second thin film transistor through a connection hole formed in the passivation layer.

According to an embodiment of the invention, the first thin film transistor has at least one connection hole formed in The insulating layer corresponds to a source or a drain of the first thin film transistor, and a source or a drain of the first thin film transistor is connected to a gate of another first thin film transistor through the connection hole or Source or drain.

According to an embodiment of the present invention, the first thin film transistor has at least one connection hole formed under the insulating layer corresponding to a source or a drain of the first thin film transistor, and the liquid crystal display panel further includes at least a signal layer is formed under the connection hole, and a source or a drain of the first thin film transistor is connected to a gate or a source of another first thin film transistor through the connection hole and the signal layer or Drain.

According to an embodiment of the present invention, there is provided a method of fabricating a liquid crystal display panel, the liquid crystal display panel comprising a display area and a non-display area, comprising the steps of: providing a glass substrate; forming a first metal layer The glass substrate is characterized in that: the method further comprises: forming a gate of the plurality of first thin film transistors for the non-display area and the plurality of display regions in the first metal layer a gate of the second thin film transistor; forming an insulating layer on the gate of the first thin film transistor and the gate of the second thin film transistor; forming a semiconductor layer on the insulating layer; forming the first thin film transistor a source and a drain, a source and a drain of the second thin film transistor on the semiconductor layer and the insulating layer; forming a passivation layer at a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor; and forming a transparent conductive layer on the passivation layer and etching the transparent conductive layer with a mask to form a first transparent electrode layer and a second a transparent electrode layer electrically connected to a drain or a source of the second thin film transistor, wherein the first transparent electrode layer is located in the first thin film transistor via the passivation layer on.

Compared with the prior art, the liquid crystal display panel of the present invention and the method of fabricating the same have a first transparent electrode layer disposed above the first thin film transistor as a shift register, and the first transparent electrode layer can shield the common of the common voltage electrode layer The effect of voltage on the first thin film transistor. So thin The characteristic curve of the film transistor ι-ν is not offset by the common voltage of the common voltage electrode layer, which not only reduces the power consumption during operation, but also increases the service life of the thin film transistor, and also prevents the power chip from malfunctioning due to excessive current. , causing the screen to display an abnormal problem.

In order to make the above description of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of a shift register of the present invention.

2 to 7 are schematic views showing a process of a liquid crystal display panel according to a first embodiment of the present invention. Fig. 8 is a view showing the configuration of a liquid crystal display panel of a first embodiment of the present invention.

9 to 13 are schematic views showing a process of a liquid crystal display panel according to a second embodiment of the present invention. Figure 14 is a structural view of a liquid crystal display panel of a second embodiment of the present invention. detailed description

The following description of the various embodiments is provided to illustrate the specific embodiments of the invention. Directional terms as used in the present invention, such as "upper", "lower", "previous", "rear", "left", "right", "top", "bottom", "horizontal", "vertical", etc. , just refer to the direction of the additional schema. Therefore, the directional terminology is used to describe and understand the invention, and not to limit the invention.

Please refer to FIG. 1 to FIG. 8. FIG. 1 is a circuit diagram of a shift register 50 of the present invention. The shift register 50 illustrated in FIG. 1 is merely illustrative of the present invention and is not intended to limit the present invention. Other shift registers to which the present invention is applied are also within the scope of the present invention. 2 to 7 are schematic diagrams showing the process of the liquid crystal display panel 10 according to the first embodiment of the present invention, and FIG. 8 is a liquid crystal display of the present invention. A structural view of the panel 10. The liquid crystal display panel 10 of the present invention includes a display area and a non-display area. The display area includes a plurality of thin film transistors 200 for use as pixel electrode switching switches. The non-display area includes a shift register 50 for outputting a scan signal every other time period. The shift register 50 is composed of a plurality of thin film transistors, wherein the source of the thin film transistor 100 is connected to the gate of the thin film transistor 300, or the gate of one thin film transistor is connected to the drain of another thin film transistor (Fig. Show). In the present embodiment, the thin film transistor 100 of the shift register 50 and the thin film transistor 200 of the display area responsible for switching can be formed on the glass substrate 202. At the same time, the source of the thin film transistor 100 is directly connected to the gate of the thin film transistor 300 (or the drain 100 of the thin film transistor is connected to the gate of another thin film transistor) without passing through a transparent conductive layer (ITO). . The manufacturing procedure will be explained below.

As shown in FIG. 2, a glass substrate 202 is first provided as a lower substrate, and then a metal thin film deposition process is performed to form a first metal layer (not shown) on the surface of the glass substrate 202, and a first mask is used. A Photo Etching Process (PEP) is performed to etch the gate 111 and the gate 211, the storage capacitor lower electrode 311, and the signal layers 212 and 213. The signal layers 212, 213 are the medium for conducting electrical signals, and the signal layers 212, 213 may also be the gates of another first thin film transistor.

Next, as shown in FIG. 3, a gate insulating layer 210 is then deposited to cover the gate electrode 111, the gate electrode 211, the lower electrode 311, and the signal layers 212, 213. An amorphous silicon (a-Si) layer is continuously deposited on the gate insulating layer 210, and a second lithography is performed by the second mask to form an island semiconductor layer 114, 214 or other conformal gate 111. The structure of the gate 211 pattern. Next, as shown in FIG. 4, a third lithography etching is performed using a third mask to remove the gate insulating layer 210 to form a plurality of connection holes over the signal layers 212, 213.

As shown in FIG. 5, a second metal layer covering the entire surface is formed on the gate insulating layer 210. The fourth lithography is performed by using the fourth mask to define the source 216 and the drain 218 and the source 116 and the drain 118, respectively. At this time, the source 116 is connected to the signal layer 212 through the connection hole, or is drained. The pole 118 connects the signal layer 213 through the connection hole. Signal layers 212 and 213 may also be electrically coupled to the source or drain or gate of another first thin film transistor (not shown) of the non-display area. Therefore, the signal layers 212 and 213 can electrically connect the source 116 or the drain 118 of the first thin film transistor 100 to the gate, source or drain of the other first thin film transistor of the shift register 50 or as a conductive current. The medium of the signal:

As shown in FIG. 6, a passivation layer 220 is deposited, and the source 116, 216 and the drains 118, 218 and the gate insulating layer 210 are covered, and the fifth mask is used to perform the fifth lithography. The etch is used to remove a portion of the passivation layer 220 over the drain 218 up to the surface of the drain 218 (or source 216) to form a plurality of connection holes over the drain 218 (or source 216).

As shown in FIG. 7, a transparent conductive layer (ITO) is formed on the passivation layer 220, and then the transparent conductive layer is etched by a sixth mask to form transparent electrode layers 222a and 222b. The transparent electrode layer 222a is formed in advance. A plurality of connection holes are electrically connected to the drain 218 (or the source 216) of the second thin film transistor 200 as a pixel electrode. The transparent electrode layer 222b is located above the thin film transistor 100, and is separated from the source electrode 116 and the drain 118 of the thin film transistor 100 by the passivation layer 220 to avoid short circuit. Finally, an alignment film 224 is formed on the transparent electrode layers 222a, 222b and the passivation layer 220. The alignment film 224 is used to align liquid crystal molecules in the same direction.

Referring to FIG. 8, after the thin film transistor 100, the thin film transistor 200, and the storage capacitor Cs are completed on the glass substrate 202 as the lower substrate, the liquid crystal layer 250 is first implanted and covered with a black matrix 242. And a glass substrate 270 of a color filter 244. Another transparent electrode layer 240 overlies the black matrix layer 242 and the color filter 244, and is overlaid Another alignment film 224 is covered. The transparent electrode layer 240 acts as a common voltage electrode layer to which a common constant voltage is applied. The liquid crystal molecules of the liquid crystal layer 250 control the direction of rotation according to the voltage difference between the data voltage of the transparent electrode layer 222a (pixel electrode) and the common voltage of the transparent electrode layer 240, in order to determine the degree of penetration of the light. The purpose of the transparent electrode layer 222b is to serve as a shield to prevent the thin film transistor 100 from being affected by the common voltage of the transparent electrode layer 240 to cause IV characteristic curve drift.

Referring to FIG. 9 to FIG. 14, FIG. 9 to FIG. 14 are schematic diagrams showing the process of the liquid crystal display panel 20 according to the second embodiment of the present invention. The shift register 50 is composed of a plurality of thin film transistors, wherein the source of the thin film transistor 400 is connected to the gate of the thin film transistor 300, or the gate of one thin film transistor is connected to the drain of another thin film transistor (Fig. Show). The liquid crystal display panel 20 of the present invention can be formed on the glass substrate 402 by a thin film transistor 400 (shown in Fig. 14) of the shift register and a thin film transistor 500 (shown in Fig. 14) for switching the display area. At the same time, the source of the thin film transistor 400 is directly connected to the gate of the thin film transistor 300 (or the drain of one thin film transistor is connected to the gate of the other thin film transistor) without passing through the transparent conductive layer (ITO). . The manufacturing procedure will be explained below.

As shown in FIG. 9, a glass substrate 402 is first provided as a lower substrate, and then a metal thin film deposition process is performed to form a first metal layer (not shown) on the surface of the glass substrate 402, and a first mask is used. The first lithography is performed to etch the gate 411 and the gate 511, the lower electrode 611 of the storage capacitor Cs, and the signal layers 512 and 513.

Next, as shown in FIG. 10, a gate insulating layer 510 is then deposited to cover the gate electrode 411, the gate electrode 511, the storage capacitor lower electrode 611, and the signal layers 512 and 513. A second lithography etching is performed using the second mask to remove the gate insulating layer 510 to form a plurality of connection holes over the signal layers 512 and 513. Next, as shown in FIG. 11, an amorphous silicon (a-Si) layer and a second metal layer are successively deposited on the gate insulating layer 510, and a third mask is used to perform a third lithography etching to define respectively. The semiconductor layers 414, 514, the source 516, the drain 518, the source 416 and the drain 418, at this time, the signal layer 512 is connected to the source 416, and the signal layer 513 is connected to the drain 418. The source 416 and the drain 418 are located above the semiconductor layer 414, and the source 516 and the drain 518 are located above the semiconductor layer 514. Since the thickness of the semiconductor layer 514 is very thin, the source 416 and the signal layer 512 of the upper and lower layers of the semiconductor layer 414 are in an on state, and the drain 418 and the signal layer 513 are in an on state. That is, the signal layers 512, 513 can electrically connect the source 416 or the drain 418 of the first thin film transistor 400 to the gate, drain or source of other thin film transistors (such as the thin film transistor 300 of FIG. 1) or It is used as a medium for conducting electrical signals.

As shown in FIG. 12, a passivation layer 520 is deposited, and the source electrodes 416, 516 and the drain electrodes 418, 518 and the gate insulating layer 510 are covered, and the fourth mask is used to perform the fourth lithography etching to remove A portion of the passivation layer 520 over the drain 518 is up to the surface of the drain 518 (or source 516) to form a plurality of connection holes over the drain 518 (or source 516).

As shown in FIG. 13, a transparent conductive layer (ITO) is formed on the passivation layer 520 by lithography, and then a fifth mask is used to etch the transparent conductive layer to form a transparent electrode layer 522a. 522b. The transparent electrode layer 522a is electrically connected to the drain 518 (or the source 516) through a plurality of connection holes formed in advance. The transparent electrode layer 522a electrically connected to the drain 518 (or the source 516) serves as a pixel electrode. The transparent electrode layer 522b is located above the thin film transistor 400, and is separated from the source electrode 416 and the drain 418 of the thin film transistor 400 by the transparent electrode layer 522b to avoid short circuit. Finally, an alignment film 524 is formed on the transparent electrode layers 522a, 522b and the passivation layer 520. The alignment film 524 is used to connect the liquid crystal molecules in the same direction. Referring to FIG. 14, FIG. 14 is a configuration diagram of a liquid crystal display panel 20 according to a second embodiment of the present invention. After the thin film transistor 400, the thin film transistor 500, and the storage capacitor Cs are completed on the glass substrate 402 as the lower substrate, the liquid crystal layer 550 is first implanted and covered with a black matrix 542 and a color filter ( Color filter) 544 glass substrate 570. Another transparent electrode layer 540 overlies the black matrix layer 542 and the color filter 544, and overlies another alignment film 524. The transparent electrode layer 540 acts as a common voltage electrode layer to which a common voltage is applied. The liquid crystal molecules of the liquid crystal layer 550 control the direction of rotation according to the voltage difference between the pixel electrode of the transparent electrode layer 522a and the transparent electrode layer 540, thereby determining the degree of light penetration. The purpose of the transparent electrode layer 522b is to serve as a shield to prevent the thin film transistor 400 from being affected by the common voltage of the transparent electrode layer 540 to cause IV characteristic curve drift.

In the above, although the present invention has been disclosed in the above preferred embodiments, the preferred embodiments are not intended to limit the invention, and those skilled in the art can, without departing from the spirit and scope of the invention, Various modifications and refinements are made, and the scope of the invention is defined by the scope of the claims.

Claims

The present invention claims a liquid crystal display panel, the liquid crystal display panel comprising a display area and a non-display area, wherein the liquid crystal display panel further comprises:

a glass substrate;

a plurality of first thin film transistors, located on the non-display area corresponding to the glass substrate, comprising a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and the semiconductor layer and a source and a drain on the insulating layer and at least one connection hole, the connection hole being formed under the insulating layer corresponding to a source or a drain of the first thin film transistor; and a plurality of second thin film transistors Located on the display area corresponding to the glass substrate, comprising a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and the semiconductor layer and the insulating layer Source and drain;

a passivation layer, located at a source and a drain of the first thin film transistor, and a source and a drain of the second thin film transistor;

a first transparent electrode layer is disposed on the first thin film transistor via the passivation layer; and a second transparent electrode layer is electrically connected to the second through a connection hole formed in the passivation layer The drain or source of the thin film transistor.

The liquid crystal display panel according to claim 1, wherein a source or a drain of the first thin film transistor is connected to a gate or a source or a drain of another first thin film transistor through the connection hole.

The liquid crystal display panel according to claim 1, wherein the liquid crystal display panel further comprises at least one signal layer formed under the connection hole, and the source or the drain of the first thin film transistor is transparent. The connection hole and the signal layer are connected to a gate or a source or a drain of another first thin film transistor.

A liquid crystal display panel, the liquid crystal display panel comprising a display area and a non-display area, The indication is that: the liquid crystal display panel further comprises:

a glass substrate;

a plurality of first thin film transistors, located on the non-display area corresponding to the glass substrate, comprising a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and the semiconductor layer And a source and a drain on the insulating layer;

a plurality of second thin film transistors, located on the corresponding display area of the glass substrate, comprising a gate electrode, an insulating layer on the gate electrode, a semiconductor layer on the insulating layer, and the semiconductor layer and a source and a drain on the insulating layer;

The liquid crystal display panel according to claim 4, wherein the first thin film transistor has at least one connection hole formed in the insulating layer corresponding to a source or a drain of the first thin film transistor Below, a source or a drain of the first thin film transistor is connected to a gate or a source or a drain of another first thin film transistor through the connection hole.

The liquid crystal display panel according to claim 4, wherein the first thin film transistor has at least one connection hole formed in the insulating layer corresponding to a source or a drain of the first thin film transistor The liquid crystal display panel further includes at least one signal layer formed under the connection hole, and a source or a drain of the first thin film transistor is connected to the signal layer through the connection hole and another A gate or source or drain of a thin film transistor.

A method of manufacturing a liquid crystal display panel, comprising: a display area and a non-display area, comprising the steps of: providing a glass substrate; forming a first metal layer on the glass substrate, The feature is that: the method further comprises: Forming a gate of the plurality of first thin film transistors for the non-display area and a gate of the plurality of second thin film transistors for the display area in the first metal layer;

Forming an insulating layer on a gate of the first thin film transistor and a gate of the second thin film transistor; forming a semiconductor layer on the insulating layer;

Forming a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor on the semiconductor layer and the insulating layer;

Forming a passivation layer on a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor;

Forming a transparent conductive layer on the passivation layer and etching the transparent conductive layer with a mask to form a first transparent electrode layer and a second transparent electrode layer, the second transparent electrode layer and the second thin film The drain or source of the transistor is electrically connected, and the first transparent electrode layer is located above the first thin film transistor via the passivation layer.

8. The method according to claim 7, wherein the method further comprises etching the insulating layer to form a connection hole under the source or the drain of the first thin film transistor.

9. The method according to claim 8, wherein: in forming the semiconductor layer, a source and a drain of the first thin film transistor, and a source and a drain of the second thin film transistor Contains:

Depositing an amorphous silicon layer on the insulating layer and etching to form a first semiconductor layer and a second semiconductor layer of a specific shape;

Forming a second metal layer on the insulating layer and the first and second semiconductor layers, and etching the second metal layer to form a source and a drain of the first thin film transistor, the second a source and a drain of the thin film transistor, and a source or a drain of the first thin film transistor is connected to a gate of another first thin film transistor through the connection hole.

10. The method according to claim 8, wherein: in forming the semiconductor layer, a source and a drain of the first thin film transistor, and a source and a drain of the second thin film transistor Contains:

Depositing an amorphous silicon layer and a second metal layer on the insulating layer;

Simultaneously etching the amorphous silicon layer and the second metal layer to form the first semiconductor layer, the second semiconductor layer, the source and drain of the first thin film transistor, and the second thin film transistor a source and a drain, and a source or a drain of the first thin film transistor is connected to a gate of another first thin film transistor through the connection hole.

11. The method according to claim 7, wherein: the method further comprises:

Forming a lower electrode of a storage capacitor and a signal layer located in the non-display area in the first metal layer;

Forming the insulating layer on a lower electrode of the storage capacitor and the signal layer; and

Etching the insulating layer to form a plurality of connection holes over the signal layer, the signal layer being electrically connected to a gate of another first thin film transistor, the signal layer being connected to the first thin film transistor through the connection hole Source or drain.

12. The method according to claim 7, wherein: the method further comprises:

Etching the insulating layer to form a plurality of connection holes over the signal layer, the signal layer electrically connecting a source or a drain of the first thin film transistor to the other first through the connection hole The source or drain of the thin film transistor.

13. The method according to claim 11, wherein the step of forming a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor further comprises: Depositing an amorphous silicon layer on the insulating layer and etching to form a first semiconductor layer and a second semiconductor layer of a specific shape;

Forming a second metal layer on the insulating layer and the first and second semiconductor layers, and etching The second metal layer forms a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor, and a drain or a source of the first thin film transistor passes through the connection The aperture and the signal layer are connected to the gate or drain or source of another thin film transistor.

14. The method according to claim 12, wherein the step of forming a source and a drain of the first thin film transistor, a source and a drain of the second thin film transistor further comprises: Depositing an amorphous silicon layer on the insulating layer and etching to form a first semiconductor layer and a second semiconductor layer of a specific shape;

Forming a second metal layer on the insulating layer and the first and second semiconductor layers, and etching the second metal layer to form a source and a drain of the first thin film transistor, the second a source and a drain of the thin film transistor, and a drain or a source of the first thin film transistor is connected to a gate or a drain or a source of another thin film transistor through the connection hole and the signal layer.