WO2012013514A1

WO2012013514A1 - Electronic component and method for producing an electronic component

Info

Publication number: WO2012013514A1
Application number: PCT/EP2011/062082
Authority: WO
Inventors: Bernd Barchmann; Gertrud KRÄUTER; Klaus Müller; Reinhard Streitel
Original assignee: Osram Opto Semiconductors Gmbh
Priority date: 2010-07-26
Filing date: 2011-07-14
Publication date: 2012-02-02
Also published as: TW201222899A; DE102010038405A1

Abstract

The invention relates to an electronic component (100a, 100b, 200), in particular an optoelectronic component. The electronic component comprises a substrate (124, 224) having at least one semiconductor chip contact layer (110a, 110b, 210). A semiconductor chip (102, 202) is disposed on the semiconductor chip contact layer (110a, 110b, 210). A connection layer (106, 206) comprising pores is disposed between the semiconductor chip contact layer (110a, 110b, 210) and a contact surface (104, 204) of the semiconductor chip (102, 202) facing the substrate (124, 224).

Description

ELE KT RONIC COMPONENT AND METHOD FOR PRODUCING AN ELECTRONIC COMPONENT

DESCRIPTION

The present invention relates to an electronic component, in particular an optoelectronic

Component, and a method for producing such a device.

Electronic components, in particular optoelectronic components, with a semiconductor chip generate heat during operation, which reduces the efficiency of the electronic component. Especially with optoelectronic

The components of the upper power class can

thermal management be problematic.

An object of the invention is to provide an electronic component in which the heat generated in the semiconductor chip can be dissipated quickly to the substrate.

This object is achieved by an electronic component according to independent claim 1 and by a method for producing an electronic component

Component solved according to the independent claim 11.

Further developments and advantageous embodiments of the electronic component and the method for

Production of the electronic component are given in the dependent claims.

Exemplary embodiment forms Various embodiments have an electronic component in which the heat generated in the semiconductor chip can be quickly dissipated to the substrate.

The electronic component has a substrate with at least one semiconductor chip contact layer. On the semiconductor chip contact layer, a semiconductor chip is arranged. Between the semiconductor chip contact layer and a substrate facing the contact surface of the semiconductor chip is having a pore

Connecting layer arranged.

The semiconductor chip contact layer may be a metallized layer that is electrically and / or thermally conductive. For example, the semiconductor chip contact layer has gold. Depending on the embodiment, the semiconductor chip contact layer may be in a measurable thickness or as a surface with a nearly

vanishing thickness.

In a preferred embodiment, this is

electronic component an optoelectronic

Component. The in optoelectronic component

arranged semiconductor chip may be based on a III-V compound semiconductor material. The

Semiconductor chips have at least one active zone that emits electromagnetic radiation. The active zones may have pn junctions, double heterostructure,

Multiple quantum well structure (MQW), single quantum well structure (SQW). Quantum well structure means: quantum wells (3-dim), quantum wires (2-dim) ui quantum dots (1-dim). The semiconductor chip can, for example, as

Surface emitter, especially as so-called

Thin-film chip or be designed as a volume emitter, in particular as a sapphire volume emitter. The thin-film chip is for example from the

Publication WO2005081319A1 known. During the production of the optoelectronic component, in particular of a component with a metal-containing mirror layer, the growth substrate of the

Dissolved semiconductor layer sequence, such are produced by peeling off the growth substrate

Components also referred to as thin-film components. The radiation-emitting semiconductor component has herein a stack of different I I I-V nitride semiconductor layers, in particular gallium nitride layers. The thin-film component is designed without a radiation-absorbing substrate and a reflector is applied directly on the GaN semiconductor body from the stack of different I I I-V nitride semiconductor layers.

The sapphire volume emitter is known, for example, from the patent DE102006015788A1. In this case, sapphire can be used as the growth substrate for the semiconductor layer sequence. Unlike the thin-film chip, the sapphire bulk emitter does not have the growth substrate at the end of the manufacturing process

Semiconductor layer sequence detached. The (growth) substrate is transparent to radiation generated in the active zone. This facilitates the radiation extraction from the semiconductor chip through the substrate. The semiconductor chip is thus as Volume radiator formed. In the case of a volume emitter, in contrast to a surface emitter, a significant proportion of radiation is coupled out of the semiconductor chip via the substrate. The surface luminance at the outcoupling surfaces of the semiconductor chip is reduced in the case of a volume radiator with respect to a surface radiator.

The disclosures of the publications WO2005081319A1 and

DE102006015788A1 are hereby incorporated by reference into the disclosure of the present application.

In a preferred embodiment, the voided compound layer is thermally conductive. This is particularly advantageous since, as a result, the heat generated in the semiconductor chip is applied particularly quickly to the substrate

can be dissipated. As a semiconductor chip, a

Sapphire volume emitter can be used in which the pore-containing compound layer is used only for thermal contact.

In a further preferred embodiment, the connecting layer having pores is thermally conductive and at the same time electrically conductive. This is special

advantageous because in addition to the heat dissipation one of the two electrical contacts of the semiconductor chip is realized. As a semiconductor chip, a thin-film chip can be used.

In a preferred embodiment, the pore-containing compound layer consists of silver. As a result, the thermal conductivity with respect to bonding layers of adhesive, in particular silver conductive adhesive, or solder can be increased. The pore-containing silver layer is free from organic compounds. It is also clear

cheaper (factor 10) than a Au80Sn20 solder consisting of 80% by weight of gold and 20% by weight of tin. The pore-containing compound layer of silver has a thermal conductivity between 80 W / m * K and 300 W / m * K. The fewer pores in the

Bonding layer are present and the smaller the pores, the higher the thermal conductivity.

The thermal conductivity of electrically conductive adhesive is between 1.5 W / m * K and 20 W / m * K. The

Depending on the type of solder used, the thermal conductivity of solder is between 50 and 60 W / m * K. As Lot can one

Tin-containing alloy, e.g. SnAgCu, to be used. Alternatively, Au80Sn20 can be used as solder. The melting temperature of Au80Sn20 is about 280 ° C.

In other words, a core idea of the invention, the previously used Silberleitkleber or the previously used Lot between the semiconductor chip and the

Replacing the semiconductor chip contact layer on the substrate with a silver layer.

It is particularly advantageous that the pore-containing silver layer is produced at about 250 ° C by a sintering process. The melting point of silver is

much higher, at about 960 ° C. In other words, the liquid phase is bypassed during sintering. The pore-containing silver layer remains at the later

Surface mounting of electronic components on a printed circuit board (SMT assembly) stable and does not melt. After assembling the printed circuit boards with electronic components, the components in the soldered so-called reflow process. In this case, a maximum temperature of 260 ° C is reached. If a chip-based alloy is a tin-based alloy (except Au80Sn20) in one

Soldering process is used, melts the chip plaque during surface mounting. This leads to a

Undefined microstructural state of the chip card and can result in thermal problems and reliability problems. Alternatively, a lot of Au80Sn20 could be used. Au80Sn20 has a melting point of about 280 ° C, so no re-melting in the

Surface mounting done. One disadvantage of using Au80Sn20 as solder is the high price, since the gold content is about 80 percent by weight. Another disadvantage is that Au80Sn20 is processed as chip chip at about 300 ° C. At this temperature, case plastics can discolour premold housings, resulting in a significant reduction in the reflectivity of these case plastics.

In a preferred disclosed embodiment, the pore-containing compound layer of silver has a thickness between about 1 μπι and about 50 μπι, preferably between 5 μπι and 30 μπι on. Because of the high thermal conductivity of the pore-containing silver layer, the thickness of the pore-containing silver layer, in contrast to the thickness of the previously used silver-conductive adhesive, is a less relevant parameter. This allows a simple

Processing with relatively large tolerances. At the

Silver conductive adhesive, however, increases strongly with the layer thickness of the thermal resistance. Therefore, the glue must be processed as thinly as possible. Typically, the thickness of the Silberleitklebers 3 μπι to 5 μπι. Even layer thicknesses of 10 μπι are problematic

with regard to the removal of the heat generated by the semiconductor chip.

In a preferred embodiment, the pore-containing compound layer of silver has pores with it

Pore sizes between about 50 nm and about 1000 nm. The small size of the pores is advantageous because with

decreasing pore size the thermal conductivity of the

Silver layer increases. Likewise, the lowest possible pore density is advantageous. The lower the pore density, the lower the thermal resistance.

In a preferred embodiment, the voided compound layer is gold. This is

advantageous because gold has similar favorable properties as silver and also not oxidized. As a result, the thermal and electrical conductivity remains constant in the long term.

In a preferred embodiment, the substrate is a leadframe. The leadframe can be made of copper with a thermal conductivity of about 300 W / m * K. The copper can be silvered on its surface to the

To increase reflectivity for the emitted from the semiconductor chip electromagnetic radiation. The copper may also be gold plated to make the leadframe more stable to oxidation and to remove the copper ions from

Keep semiconductor chip away.

In a preferred embodiment, the leadframe is cast in a premold housing. The premold housing is a Spritzverguss. The injection molding takes place at about 350 ° C and 800 to 2000 bar. The premold is from one Plastic, in particular a polymer, and has a reflectivity of up to 95%. The premold has a white color. The premold has several functions. He holds the two parts of the leadframe together. It has a cavity, on the bottom of which the semiconductor chip is arranged. The side walls of the cavity serve as a reflector for the emitted from the semiconductor chip

electromagnetic radiation. The cavity of the premold provides space for a grout and prevents

lateral course of the potting. The potting may have a phosphor. Overall, the premold housing with leadframe can be processed very simply and cost-effectively.

Because of the limited thermal stability of

Polymers, it is necessary when using a premold housing that the short-term

Working temperature does not exceed 260 ° C. This condition can be met with the sintering process according to the invention, with which the pore-containing silver layer is produced.

In a preferred embodiment, the substrate is a ceramic. As a ceramic aluminum oxide (Al ₂ O ₃ ) with a thermal conductivity of about 20 W / m * K,

Aluminum nitride (A1N) with a thermal conductivity of about 170 W / m * K or boron nitride (BN) with a

Thermal conductivity of about 220 W / m * K are used. The use of a ceramic substrate is special

advantageous because ceramic largely

temperature insensitive. The invention is particularly advantageous for

Optoelectronic components of the upper power classes with an energization of more than 300 mA. For example, the inventive pores having

Bonding layer for the following OSRAM OS products are used. Leadframe and premold package components such as Advanced Power TOPLED (Plus), Golden Dragon (Plus), Platinum Deagon or Diamond Dragon.

Components with a ceramic substrate, such as the Oslon.

In a preferred embodiment, the Advanced Power TOPLED has a pore-containing silver interconnect layer over one

Bonding layer of conductive adhesive, the thermal resistance by up to 40%. This causes the luminous flux to increase by about 4%. This can be explained by the improved heat dissipation from the

Semiconductor chip to the leadframe of the phosphor is heated less. The lower the temperature of the

Phosphorus is, the higher its efficiency.

Various embodiments of the method for

Producing an electronic component with a voided connecting layer between

Semiconductor chip and substrate have at least the following process steps:

First, a substrate with at least one

Semiconductor chip contact layer provided. A paste is passed through the semiconductor chip contact layer

Dispensing or screen printing or stamping or

Stencil printing or jetting applied. The paste includes silver particles, organic solvent and an organic matrix in which the silver particles

are embedded. The silver particles have a size of less than 5 μπι. This is particularly advantageous because subsequent sintering at low temperatures of less than about 250 ° C provides better results the smaller the silver particles are. The silver particles are in the form of flocs or beads before the sintering step. After application of the paste, the semiconductor chip is pressed onto the paste, which is also called Die Attach. Finally, the paste

sintered to burn out the organic matrix. The end product formed between the semiconductor chip and the semiconductor chip contact layer on the substrate, a thermally conductive, voided compound layer of silver.

In a particularly advantageous manner

Sintering process produces round and small pores, which are also distributed evenly in the connecting layer. In a preferred embodiment, the sintering of the paste takes place in a circulating air oven under normal atmosphere for about 20 minutes at less than 250.degree. This

Low-temperature sintering is particularly advantageous in premold housings, since the

Do not discolour housing plastics.

In a preferred disclosed embodiment is after the

Pressing the semiconductor chip on the paste and prior to the sintering step carried out an annealing step. The annealing is carried out in a convection oven at normal atmosphere for about 10 minutes at about 150 ° C. The annealing step is used for expelling the organic solvent from the paste. The use of an organic solvent is particularly advantageous because it has a high vapor pressure. It evaporates even at low temperatures

In a preferred embodiment, the mold is attached to the substrate after the sintering step

Semiconductor chip with a potting material, in particular a silicone or a resin, potted.

In a preferred embodiment, after the casting of the semiconductor chip, a primary optic, in particular a lens, is placed on the casting.

KU RZ E B E S C H R E I U N G D E R I C H N U N G E N

Various embodiments of the solution according to the invention are explained in more detail below with reference to the drawings.

Figure la shows a section through an electronic

Component with a leadframe as a substrate;

Figure lb shows a section through an electronic

Component with a leadframe as a substrate;

Figure 2 shows a section through an electronic

Component with a ceramic substrate;

FIG. 3 shows a flow chart of the

Production method of the electronic component according to the invention. EXAMINATION EXAMPLES

The same, similar or equivalent elements are provided in the figures with the same reference numerals. The figures and the proportions of the elements shown in the figures with each other are not to be considered to scale. Rather, individual can

Elements for better representability and for better understanding to be shown exaggerated or reduced.

Figure la shows a sectional view through a

electronic component 100a. The electronic

Component 100a may be an optoelectronic device. The electronic component 100a includes

Substrate 124, on which a semiconductor chip contact layer 110a is provided. The semiconductor chip contact layer 110a comprises an electrically conductive and / or heat-conducting material. The material can be gold. The semiconductor chip contact layer 110a has a thickness between 0.5 μπι and 5μπι. On the semiconductor chip contact layer 110a is a

Semiconductor chip 102 is arranged. Between the

Semiconductor chip contact layer 110 a and the substrate 124 facing contact surface 104 of the semiconductor chip 102 is a voided compound layer 106 is disposed. The voided interconnect layer 106 is electrically conductive and / or thermally conductive. The

Pore-containing bonding layer 106 may be made of silver. It has a thickness between about 1 μπι and about 50 μπι, preferably between 5 μπι and 30 μπι on. The pore-containing compound layer 106 of silver has over its entire volume, pores 108 having pore sizes between about 50 nm and about 1000 nm.

The voided compound layer 106 of silver has a thermal conductivity between 80 W / m * K and 300 W / m * K.

Alternatively, the voided interconnect layer 106 may also be gold.

The substrate 124 is a leadframe cast in a premold housing 118. The premold housing 118 forms a cavity. The bottom of the cavity is formed by the leadframe 124. The semiconductor chip 102 is arranged on the leadframe 124. The surface of the semiconductor chip 102 facing away from the leadframe 124 is electrically conductively connected to a bonding pad 126a on the leadframe via a contact pad 112 and a bonding wire 116. The gold bonding pad 126a has a thickness of between 0.5 μπι and 5 μπι. The semiconductor chip 102 is potted by a planar volume casting 120. On the potting 120 is a primary optic 122 in the form of a lens

arranged.

Figure lb shows a sectional view through a

electronic component 100b. The embodiment of Figure lb is identical to the embodiment of Figure la, except that the semiconductor chip contact layer 110b and the bonding pad 126b have a vanishing thickness. In other words, the voided silver interconnection layer 106 directly adjoins

Leadframe 124 on. Analogously, the bonding wire 116 is directly applied to the leadframe 124. The shown in Figure lb

Embodiment is advantageous because the thermal and electrical connection between the leadframe 124 and the semiconductor chip 102 is immediate, that is mediated only by the connecting layer 106 having the pores. This leads to a particularly good heat dissipation from

Semiconductor chip 102 to the leadframe 124th

Figure 2 shows a sectional view through a

electronic device 200. In contrast to FIGS. 1a and 1b, the substrate 224 is a ceramic. The core of the invention, namely the optimized heat transfer from the semiconductor chip 202 to the substrate 224 via the connecting layer 206 made of silver having the pores, is also based on the exemplary embodiment of FIG. Of the

Semiconductor chip 202 is connected via its contact surface 204 with the voided connecting layer 206 made of silver. The voided interconnect layer 206 is electrically and thermally conductive

Semiconductor chip contact layer 210 connected. Unlike in FIG. 1b, in the exemplary embodiment of FIG. 2 a conductive semiconductor chip contact layer 210 with non-negligible thickness is absolutely necessary, since the ceramic substrate 224 is an electrical insulator. The second electrical contact is made by the bonding wire 216, the contact pad 212 on the side facing away from the substrate 224 of the semiconductor chip 202 with the

Bondpad 226 on the ceramic 224 connects. Of the

Semiconductor chip 202 is cast in a potting 220. On the potting a primary optics 222 is arranged in the form of a lens. Through the ceramic substrate 224 vias 230, 232 are arranged, which are filled with electrically conductive material. In electrical connection with the vias 230, 232 are on the semiconductor chip 202 opposite side of the substrate 224 metallized

Contact layers 234, 236 arranged. These

Contact layers 234, 236 are for example for

Contacting provided on a printed circuit board. The heat generated in the semiconductor chip 202 is primarily dissipated to the ceramic 224.

FIG. 3 shows a flow chart for producing an electronic, in particular an optoelectronic, component. The manufacturing process can be broken down into steps S1 to S7.

In step S1, a substrate 124, 224 with at least one semiconductor chip contact layer 110a, 110b, 210 is provided.

In step S2, a paste is applied to the semiconductor chip contact layer 110a, 110b, 210 by dispensing or

Screen printing or stamping or stencil printing or jetting applied. The paste comprises silver particles, organic solvent and an organic matrix. The silver particles are in the organic matrix

embedded, creating at least a minimal

Cohesion between the silver particles is given.

In step S3, the semiconductor chip 102, 202 is pressed onto the paste. The paste is compacted.

In optional step 4, the paste for annealing the organic solvent from the paste is annealed. The annealing is carried out in a convection oven under normal atmosphere for about 10 minutes at about 150 ° C.

In step S5, the paste is sintered, resulting in a voided bonding layer 106, 206. The Sintering takes place in a convection oven under normal atmosphere for about 20 minutes at about 250 ° C. In the sintering step, the organic matrix is burned out. The porosity and the volume of the connecting layer 106, 206 are reduced significantly. In addition, form

so-called sintering necks, the strength of the

Increase connection layer 106, 206. The sintered necks are formed by surface diffusion between the

Sintered particles. In step S6, the attached to the substrate

Semiconductor chip 102, 202 with a potting material, in particular a silicone or a resin encapsulated.

In step S7, a primary optic 122, 222,

in particular a lens, on the potting 120, 220th

placed.

The optoelectronic device has become the

Illustration of the underlying idea described with reference to some embodiments. The

Embodiments are not specific

Characteristic combinations limited. Although some

Features and configurations only in connection with a particular embodiment or individual

Embodiments have been described, they can each with other characteristics of others

Embodiments are combined. It is also conceivable to omit or add in individual embodiments illustrated features or special embodiments, as far as the general technical teaching is realized. Reference sign list

100a electronic component

100b electronic component

102 semiconductor chip

104 contact surface of the semiconductor chip

106 pore-containing compound layer of silver

108 pores in the tie layer

110a semiconductor chip contact layer on leadframe 110b semiconductor chip contact layer on leadframe

112 contact pad

116 bonding wire

118 premold case

120 potting

122 Primary optics

124 leadframe

126a bond pad on leadframe

126b bond pad on leadframe

200 electronic component

202 semiconductor chip 204 contact surface of the semiconductor chip

206 pore silver compound layer

208 pores in the tie layer

210 semiconductor chip contact layer on ceramic 212 contact pad

216 bonding wire

220 potting

222 primary optics

224 ceramics

226 Bondpad on ceramic

230 electrically conductive via

232 electrically conductive via

234 metallized contact layer

236 metallized contact layer

Claims

PAT EN TAN SPRU

1. Electronic component (100a, 100b, 200), in particular optoelectronic component, with:

a substrate having at least one semiconductor chip contact layer,

- At least one on the semiconductor chip contact layer (110a, 110b, 210) arranged

Semiconductor chip (102, 202),

- Wherein between the semiconductor chip contact layer (110 a, 110 b, 210) and the substrate (124, 224) facing contact surface (104, 204) of the

Semiconductor chips (102, 202) a voided compound layer (106, 206) is arranged.

2. The electronic component according to claim 1, wherein the voided connecting layer (106, 206) is electrically conductive and / or thermally conductive.

3. The electronic component according to claim 1 or 2, wherein the voided connecting layer (106, 206) consists of silver.

4. The electronic component according to claim 3, wherein the void having connecting layer (106, 206) made of silver has a thickness between about 1 μπι and about 50 μπι, preferably between 5 μπι and 30 μπι.

5. Electronic component according to claim 3 or 4, wherein the voided connecting layer (106,

206) of silver has pores (108, 208) with pore sizes between about 50 nm and about 1000 nm.

6. Electronic component according to one of claims 3 to 5, wherein the pores having

Connecting layer (106, 206) made of silver one

Thermal conductivity between about 80 W / m * K and about 300 W / m * K has.

7. An electronic device according to claim 1 or 2, wherein the voided compound layer consists of gold.

8. The electronic component according to one of the preceding claims, wherein the substrate (124) is a leadframe.

9. Electronic component according to claim 8, wherein the leadframe (124) is cast in a premold housing.

10. The electronic component according to one of claims 1 to 7, wherein the substrate (224) a

Ceramics is.

11. A method for producing an electronic component (100a, 100b, 200), in particular an optoelectronic component, having at least the following steps:

- Providing a substrate (124, 224) with

at least one semiconductor chip contact layer (110a, 110b, 210),

Applying a paste comprising silver particles, organic solvent and an organic matrix to the semiconductor chip contact layer (110a, 110b, 210),

- Pressing the semiconductor chip (102, 202) on the

Paste, - sintering the paste to burn off the organic matrix.

12. A method according to the preceding claim, wherein the sintering of the paste is carried out at about 250 ° C for about 20 minutes.

13. The method according to claim 11 or 12, wherein an annealing step for expelling the organic

Solvent after pressing the semiconductor chip (102, 202) is performed on the paste and before the sintering step.

14. A process according to claim 13, wherein the annealing is carried out at about 150 ° C for about 10 minutes.