WO2012002428A1 - Storage device, method for determining de-allocation priority order, and program - Google Patents

Abstract

Disclosed is a storage device which temporarily stores data recorded in a storage medium and which comprises: a cache with smaller latency than the storage medium; and a unit for determining the de-allocation priority order which increases the de-allocation priority order of data at the time the cache is replaced the longer the data length of the data stored in the cache.

Description

Storage device, release priority determination method and program

The present invention relates to a storage device having a cache, a data release priority determination method and a program for performing replacement in the cache.

With the development of information communication technology, the amount of data handled by an information processing system has increased, and the demand for immediate processing has increased. For this reason, the performance of the storage device is also improved so that a large amount of data can be processed in parallel and in a short time.
For example, an SSD (Solid State Drive, hereinafter referred to as a flash memory) that can read and write faster than a hard disk (Hard Disk Drive; HDD) that is widely used as a large-capacity storage medium. Simply referred to as “SSD”). The SSD is a storage medium using a flash memory. Since the SSD does not have a physically movable part such as a magnetic head or a platter, it does not require a seek time or a platter rotation waiting time when the magnetic head moves. For this reason, SSDs have very low latency and high throughput compared to hard disks.
Therefore, by replacing the storage medium in the storage device from the hard disk to the SSD, the latency of the storage device can be greatly reduced. In addition, since the SSD consumes less power than the hard disk, power saving of the storage device can also be achieved.

However, SSDs have a higher price per storage capacity than hard disks. For this reason, if all the storage media in the storage device are replaced from the hard disk to the SSD, the cost increases significantly.
Therefore, it is conceivable to use an SSD as a large-capacity cache memory for the hard disk. An SSD is more expensive than a hard disk of the same capacity, but is cheaper than a DRAM (Dynamic Random Access Memory) generally used as a cache memory. Since the SSD is a non-volatile storage medium unlike the DRAM, there is an advantage that the data is not lost even when the power of the storage device is cut off and the power of the battery is not present.
On the other hand, SSD is faster than hard disk but slower than DRAM. Therefore, in order to obtain higher speed than when SSD is simply used as a cache, DRAM is a higher cache (for example, a primary cache) and SSD is a lower cache (a hard disk lower than DRAM). It is conceivable to use in combination as a cache closer to the cache (for example, a secondary cache). Thereby, a large-capacity and high-speed cache can be realized at a relatively low cost.

In a storage device having a cache, such as a hard disk having a cache, there are several methods (policies) for selecting data to be released when the cache has insufficient free space and data replacement is performed. It is known (replacement of data is to release already stored data and store new data).
For example, in LRU (Least Recently Used), which is described in Patent Document 1, data with a long unused time, that is, data with the oldest access time is preferentially released. In LFU (Least Frequently Used), data with low usage frequency (access frequency) is preferentially released.

If these methods are used, an improvement in hit rate can be expected especially when the frequency of use for each data is almost fixed. That is, it is conceivable that data with a long unused time has a low use frequency and a long time until it is used in the future. Thus, by preferentially releasing data with a long unused time using LRU, it can be expected that data with a short time until future use remains in the cache and the hit rate is improved. In addition, it is considered that data with low use frequency is low in use frequency in the future, that is, the probability of being used within a certain time is low. Therefore, it is expected that data with high probability of being used within a predetermined time remains in the primary storage medium by preferentially releasing data with low usage frequency using LFU, and the hit rate is improved.

Japanese Unexamined Patent Publication No. 2008-21314

However, methods such as LRU and LFU cannot perform appropriate replacement according to the characteristics of the access performance of the storage medium. For example, a hard disk has a delay due to seek time and rotation latency each time it accesses a discontinuous block (access to a discontinuous block means access to a block located at a distant address on the storage medium. In the case of a hard disk, it is generally an access to a block that is physically separated on the platter.) When there is a data read request from the outside, this delay may increase the time required for access. However, in the methods such as LRU and LFU, no consideration is given to this delay.

The present invention has been made in consideration of such circumstances. An example of an object of the present invention is to select and store data to be stored in a cache according to the access performance characteristics of the storage medium, and to improve the hit rate in the cache, a release priority determination method, and a program Is to provide.

This invention was made to solve the above-mentioned problems. A storage device according to one embodiment of the present invention temporarily stores data stored in a storage medium, and has a cache with lower latency than the storage medium and the longer the data length of the data stored in the cache, Includes a release priority determining unit that increases the release priority of the data when performing replacement.

According to one aspect of the present invention, there is provided a release priority order determination method for temporarily storing data stored in a storage medium, wherein the cache performs replacement in a storage device including a cache having a latency lower than that of the storage medium. The release priority order determination method of the method further comprises increasing the release priority order of the data when the cache performs replacement as the data length of the data stored in the cache is longer.

A program according to one aspect of the present invention temporarily stores data stored in a storage medium, and a release priority order when the cache performs replacement in a storage device including a cache having a latency lower than that of the storage medium The higher the data length of the data stored in the cache, the higher the release priority of the data when the cache performs the replacement is executed.

According to the present invention, the data to be stored in the cache can be selected and stored according to the access performance characteristics of the storage medium, and the hit rate in the cache can be improved.

1 is a configuration diagram illustrating a schematic configuration of a computer network system including a storage device according to an embodiment of the present invention. It is a block diagram which shows schematic structure of the memory | storage device in one Embodiment of this invention. In one Embodiment of this invention, it is a figure which shows the example of the performance information table which a performance information storage part memorize | stores. In one Embodiment of this invention, it is a figure which shows the example of the SSD cache management table which a data information storage part memorize | stores. In one Embodiment of this invention, it is a figure which shows the example of the SSD cache management table which a data information storage part memorize | stores. FIG. 4 is a diagram illustrating an example of a DRAM cache management table stored in a data information storage unit in the embodiment of the present invention. In one Embodiment of this invention, it is a figure which shows the example of the hard disk management table which a data information storage part memorize | stores. FIG. 6 is a diagram illustrating an example of a read request transmitted from a host in an embodiment of the present invention. FIG. 6 is a diagram illustrating an example of a write request transmitted from a host in an embodiment of the present invention. 6 is a flowchart illustrating a processing procedure of the storage device when a read request from a host is received in an embodiment of the present invention. 6 is a flowchart illustrating a processing procedure of the storage device when a write request from a host is received in an embodiment of the present invention. FIG. 10 is a flowchart showing a processing procedure for storing data selected as a release target in step S162 in FIG. 8 and step S212 in FIG. 9 in an SSD cache or a hard disk as necessary. FIG. 10 is a flowchart showing a processing procedure for storing data selected as a release target in step S162 in FIG. 8 and step S212 in FIG. 9 in an SSD cache or a hard disk as necessary. FIG. 10 is a diagram showing information stored in a DRAM cache management table before a read request T process in an embodiment of the present invention. FIG. 6 is a diagram showing information stored in an SSD cache management table before a read request T process in an embodiment of the present invention. FIG. 6 is a diagram illustrating an example of a series of processing requests transmitted from a host to a storage device in an embodiment of the present invention. FIG. 10 is a diagram illustrating information stored in a DRAM cache management table after a read request T process in an embodiment of the present invention. FIG. 10 is a diagram illustrating information stored in an SSD cache management table after processing a read request T in an embodiment of the present invention. FIG. 10 is a diagram illustrating information stored in a DRAM cache management table after processing a read request X in an embodiment of the present invention. FIG. 10 is a diagram showing information stored in an SSD cache management table after processing a read request X in an embodiment of the present invention. FIG. 10 is a diagram illustrating information stored in a DRAM cache management table after a read request Y process in an embodiment of the present invention. FIG. 10 is a diagram illustrating information stored in an SSD cache management table after a read request Y process in an embodiment of the present invention. FIG. 6 is a diagram showing information stored in a DRAM cache management table after processing a read request Z in an embodiment of the present invention.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a configuration diagram showing a schematic configuration of a computer network system including a storage device according to an embodiment of the present invention. The computer network system shown in FIG. 1 includes one or more hosts 10, a storage device 20, and a network 30.
The host 10 transmits a write request or a read request (hereinafter, the write request and the read request are collectively referred to as a “processing request”) to the storage device 20, and is read based on the read request. Receive data.
The storage device 20 stores data based on a write request from the host 10 and returns data based on a read request.
The network 30 connects the host 10 and the storage device 20 and transmits a processing request transmitted from the host 10 to the storage device 20 and a processing result transmitted from the storage device 20 to the host 10.
The connection configuration between the host 10 and the storage device 20 is not limited to the configuration via the network shown in FIG. The host 10 and the storage device 20 may be directly connected. The storage device 20 may be incorporated in the host 10.

FIG. 2 is a configuration diagram showing a schematic configuration of the storage device 20. In FIG. 2, the storage device 20 includes a hard disk (storage medium) 210, an SSD cache (cache) 220, a DRAM cache (upper cache) 230, an access processing unit 240, a storage medium performance measurement unit 250, and performance information. A storage unit 260, a release priority order determination unit 270, and a data information storage unit 280 are provided.
The hard disk 210 stores data written by the access processing unit 240. As described above, when data is read from the hard disk 210, a delay occurs due to seek time and rotation waiting time for each data. The memory space of the hard disk 210 is divided into blocks, and an address is assigned to each block. The address of the hard disk 210 is also used as an address when accessing the storage device 20 from the outside of the storage device 20, that is, an address of a virtual memory space of the storage device 20 (hereinafter referred to as “virtual address”). That is, the address of the hard disk 210 matches the virtual address. The hard disk 210 and the management means of the hard disk 210 use existing technology.
The number of hard disks included in the storage device 20 is not limited to one shown in FIG. 1, and may be two or more. The number of SSD caches 220 included in the storage device 20 is not limited to one as shown in FIG. 1 and may be two or more.

The SSD cache 220 and the DRAM cache 230 constitute a two-layer cache for the hard disk 210.
The SSD cache 220 is a cache configured by SSD (SSD configured by flash memory as described above). The SSD cache 220 functions as a secondary cache for the hard disk 210. The SSD cache 220 has a higher throughput than the hard disk 210. Since the SSD cache 220 does not particularly have a physically movable part such as a magnetic head or a platter, the latency is very small. The memory space of the SSD cache is divided into blocks having the same size as the blocks of the hard disk 210, and an address is assigned to each block.
The DRAM cache 230 has a higher read / write speed than the SSD cache 220. The DRAM cache 230 functions as a primary cache higher than the SSD cache 220. The memory space of the DRAM cache 230 is divided into blocks having the same size as the blocks of the hard disk 210, and an address is assigned to each block. The DRAM cache 230 and the management means of the DRAM cache 230 use existing technology.

In this embodiment, a write-back method (Write Back Algorithm) is adopted as a data update method of the SSD cache 220 and the DRAM cache. However, the scope of application of the embodiment of the present invention is not limited to this, and can also be applied to a cache in which data is updated by a write-through method (Write Through Algorithm).

In response to a processing request transmitted from the host 10 (FIG. 1), the access processing unit 240 reads / writes data from / to the hard disk 210, the SSD cache 220, and the DRAM cache 230, and stores data in the data information storage unit 280. Update the data. In addition, the access processing unit 240 returns the processing result to the host 10.
The storage medium performance measurement unit 250 accesses the hard disk 210 and the SSD cache 220 in advance for consecutive blocks as pre-processing in which the storage device 20 performs processing according to a processing request from the host 10. The access speed (throughput) and the delay time (latency) for each of the case of the case and the case of discrete access, and for each of the case of reading (Read) and the case of writing (Write) Measure access performance characteristics including The storage medium performance measurement unit 250 writes the measured data in the performance information storage unit 260. The performance information storage unit 260 stores the access performance characteristics measured by the storage medium performance measurement unit 250. Access to consecutive blocks means access to blocks located at adjacent addresses on the storage medium. In the case of a hard disk, access is to a block that is physically close to the platter.
When the access performance characteristics of the hard disk 210 and the SSD cache 220 are known, the performance information storage unit 260 may store these known access performance characteristics in advance. This eliminates the need for the storage device 20 to include the storage medium performance measurement unit 250, thereby simplifying the device configuration.

The release priority order determination unit 270 uses the access performance characteristics of the hard disk 210 and the SSD cache 220 stored in the performance information storage unit 260 to store data stored in the SSD cache 220 and data released from the DRAM cache 230. The release priority index value is calculated. The release priority determining unit 270 determines the release priority of each data based on the calculated release priority index value. This release priority indicates the priority that is released from the SSD cache 220 when replacing in the SSD cache 220 (the priority that is written to the SSD cache 220 for data released from the DRAM cache 230).

The data information storage unit 280 stores an SSD cache management table indicating the address, access frequency, and the like of each data stored in the SSD cache 220. Further, the data information storage unit 280 stores a DRAM cache management table indicating the address, access frequency, etc. of each data stored in the DRAM cache 230. Further, the data information storage unit 280 stores a hard disk management table indicating the address, access frequency, etc. of each data stored in the hard disk 210.
The SSD cache 220 may store the SSD cache management table. Similarly, the DRAM cache 230 may store a DRAM cache management table. Similarly, the hard disk 210 may store a hard disk management table.
In particular, when the SSD cache 220 stores the SSD cache management table, the DRAM cache 230 stores the DRAM cache management table, and the hard disk 210 stores the hard disk management table, the storage device 20 includes a data information storage unit. It is not necessary to have 280.

Next, the data structure of data stored in the performance information storage unit 260 and the data information storage unit 280 will be described with reference to FIGS.
FIG. 3 is a diagram illustrating an example of the performance information table stored in the performance information storage unit 260. As shown in FIG. 3, the performance information table stores the delay time and access speed of the hard disk 210 and the SSD cache 220. As the delay time, latency (delay time at the beginning of access) is stored. As the access speed, the speed at the time of accessing a continuous block is stored. In the present embodiment, it is assumed that the hard disk 210 and the SSD cache 220 have the same delay time and access speed when reading data and when writing data. For this reason, the performance information table stores data common to reading and writing. If the values differ between reading and writing, the performance information storage unit 260 stores data for each.

4A and 4B are diagrams showing examples of the SSD cache management table stored in the data information storage unit 280. FIG. As shown in FIG. 4A, the SSD cache management table includes a “Dirty flag (Dirty flag)” field, a “Start address (SSD)” field, a “Start address (virtual)” field, and a “Data length” field. And “access frequency” column. The SSD cache management table stores information on each column for each data on the SSD cache 220.

In the “Dirty flag” column, a Dirty flag indicating whether or not the data stored in the hard disk 210 needs to be updated is stored. As the value of the Dirty flag, the data on the SSD cache 220 (hereinafter referred to as “the relevant data” in the description of FIGS. 4A and 4B), when there is a new write request from the host 10, “1” indicating that updating is necessary is stored. On the other hand, when there is no unreflected write request in the hard disk 210, “0” indicating that there is no need to update the Dirty flag is stored.
In the “start address (SSD)” column, the start address (hereinafter referred to as “start address (SSD)”) of the data in the address of the SSD memory space (hereinafter referred to as “SSD address”). Stored.

In the “start address (virtual)” column, the start address (hereinafter referred to as “start address (virtual)”) of the data in the virtual address (address of the storage device 20) is stored.
In the “data length” column, the data length of the data is stored in the notation of the number of blocks.
The “access frequency” column stores the access frequency (the number of accesses within the latest fixed time) for the data from the host 10.
As shown in FIG. 4B, in the SSD cache management table, instead of the access frequency, the LRU order, that is, the order of the longest elapsed time from the last processing request for the data from the host 10 to the present is shown. It may be stored.

FIG. 5 is a diagram illustrating an example of a DRAM cache management table stored in the data information storage unit 280. As shown in FIG. 5, the DRAM cache management table includes a “Dirty flag” field, a “start address (DRAM)” field, a “start address (virtual)” field, a “data length” field, and an “access frequency”. "Column. The DRAM cache management table stores information on each column for each data on the DRAM cache 230.
In the “Dirty flag” column, a Dirty flag indicating whether or not the data stored in the hard disk 210 needs to be updated is stored, as described with reference to FIG. 4A.
In the “first address (SSD)” column, data on the DRAM cache 230 at the address of the SSD memory space (hereinafter referred to as “SSD address”) (hereinafter, “the relevant data” in the description of FIG. 5). The first address (hereinafter referred to as “first address (DRAM)”) is stored.

In the “start address (virtual)” column, the start address (virtual) of the data is stored.
In the “data length” column, the data length of the data is stored in the notation of the number of blocks.
The “access frequency” column stores the access frequency for the data from the host 10.
The replacement policy applied to the DRAM cache 230 is not limited to LFU. Further, information stored in the DRAM cache management table is not limited to access frequency information. For example, LRU may be applied to the DRAM cache 230. In this case, the DRAM cache management table includes an LRU order information field instead of the access frequency field, and stores the information.

FIG. 6 is a diagram illustrating an example of a hard disk management table stored in the data information storage unit 280. As shown in FIG. 6, the hard disk management table includes a “start address (virtual)” column, a “data length” column, and an “access frequency” column. The hard disk management table stores information in each column for each data on the hard disk 210.
The “start address (virtual)” column stores the start address (virtual) of data on the hard disk in the virtual address (hereinafter referred to as “the data” in the description of FIG. 6). As described above, the memory space address of the hard disk 210 matches the virtual address, and the head address (virtual) also indicates the head address in the hard disk 210.

In the “access frequency” column, the access frequency for the data from the host 10 is stored. When a replacement policy other than LFU is applied to the SSD cache 220 and the DRAM cache 230, the hard disk management table stores data according to the policy. For example, when the LRU is applied to the SSD cache 220 and the DRAM cache 230, the hard disk management table includes an LRU order information field instead of the access frequency field, and stores the information.

As described above, the address of the hard disk 210 matches the virtual address of the storage device 20. Therefore, it is not necessary to store the correspondence between the address of the hard disk 210 and the virtual address of the storage device 20 in the hard disk management table. Therefore, when it is not necessary to store information (access frequency or LRU order information) according to the replacement policy for the data stored in the hard disk 210, the hard disk management table is unnecessary.
For example, when the access frequency after being stored in the SSD cache management table is stored as data in the access frequency column of the SSD cache management table, the access frequency at the time when the data is stored in the hard disk 210 is unnecessary. . In this case, the data information storage unit 280 can be prevented from storing the hard disk management table, and the necessary storage capacity can be reduced.

If the address of the hard disk 210 does not match the virtual address, the hard disk management table is used to store the correspondence between the address of the hard disk 210 and the virtual address regardless of whether or not information corresponding to the replacement policy needs to be stored. Necessary. That is, when the storage device 20 writes data to the hard disk 210, the storage device 20 associates the data writing position on the hard disk 210 (that is, the address of the hard disk 210) with the virtual address included in the external write request. Stored in the hard disk management table. When the storage device 20 receives a read request for designating data by a virtual address from the outside, the storage device 20 searches the hard disk management table based on the virtual address, acquires the address of the hard disk 210, and stores the hard disk based on the acquired address. Read data from 210.
However, in this embodiment, since the address of the hard disk 210 and the virtual address of the storage device 20 match as described above, it is not necessary to store the correspondence between the address of the hard disk 210 and the virtual address. Therefore, when it is not necessary to store information according to the replacement policy, the hard disk management table is unnecessary.

The replacement policy applied to the SSD cache 220 and the replacement policy applied to the DRAM cache 230 may be different. In this case, the SSD cache management table, DRAM cache management table, and hard disk management table store data according to both policies. For example, when the LRU is applied to the SSD cache 220 and the LFU is applied to the DRAM cache 230, the SSD cache management table, the DRAM cache management table, and the hard disk management table are respectively an access frequency column and an LRU order. And an information column for storing the information.

The data in the access frequency column of each table in the data information storage unit 280 is periodically updated by the access processing unit 240. For example, the data information storage unit 280 stores an access history (processing request history from the host 10) for each data. The access processing unit 240 updates the data in the access frequency column based on the access history.

7A and 7B are diagrams illustrating examples of processing requests transmitted from the host 10. FIG. FIG. 7A shows an example of a read request. FIG. 7B shows an example of a write request. As shown in FIGS. 7A and 7B, the processing request includes a head address (virtual) and a data length. The head address (virtual) and the data length are used by the access processing unit 240 to specify data to be processed.

Next, the operation of the storage device 20 will be described with reference to FIGS.
FIG. 8 is a flowchart showing a processing procedure of the storage device 20 when a read request from the host 10 (FIG. 1) is received. Each time the storage device 20 receives a read request from the host 10, the storage device 20 performs the process of FIG.
When receiving a read request from the host 10, the access processing unit 240 first attempts to read data from the DRAM cache 230. First, the access processing unit 240 searches the DRAM cache management table stored in the data information storage unit 280. Specifically, the access processing unit 240 reads the head address (virtual) and the data length from the read request, and searches the DRAM cache management table for a line where the head address (virtual) and the data length match (above, Step S101).

Then, the access processing unit 240 determines whether or not the data requested to be read exists on the DRAM cache 230. Specifically, the access processing unit 240 determines that the data requested to be read exists in the DRAM cache 230 when a matching line is found in the search performed in step S101. On the other hand, the access processing unit 240 determines that it does not exist when no matching row is found in the search performed in step S101. If a line that matches only the start address and does not match the data length is found, the requested data is considered as data stored in the storage device 20. Therefore, the access processing unit 240 transmits (replies) an error message to the host 10 and ends the process of FIG. 8 (step S102).

If it is determined in step S102 that the read requested data exists in the DRAM cache 230 (step S102: YES), the access processing unit 240 reads the read requested data from the DRAM cache 230 and obtains a result for the read request. The data is transmitted (returned) to the host 10 as data. Specifically, the access processing unit 240 stores an area (one piece of data in the DRAM cache 230) indicated by the head address (DRAM) and the data length stored in the matching row in the search performed in step S101. A set of blocks used for storage is referred to as one “area” (the same applies hereinafter), and data is read out and transmitted to the host 10 (step S111). Thereafter, the process of FIG.

On the other hand, when it is determined that the data requested to be read does not exist in the DRAM cache (step S102: NO), the access processing unit 240 next tries to read the data from the SSD cache 220. First, the access processing unit 240 searches the SSD cache management table stored in the data information storage unit 280. Specifically, as in step S101, a search is made for a line having the same start address (virtual) and data length (step S121).
Then, the access processing unit 240 determines whether or not the data requested to be read exists on the SSD cache 220. Specifically, as in step S102, if a matching line is found in the search performed in step S103, it is determined that data exists. On the other hand, if no matching line is found in the search performed in step S103, it is determined that the line does not exist. If only a head address matches and a line whose data length does not match is found, an error message is transmitted to the host 10 as in step S102, and the process of FIG. 8 is terminated (step S122).

When it is determined in step S122 that the data requested to be read exists on the SSD cache 220 (step S122: YES), the access processing unit 240 reads the data requested to be read from the SSD cache 220 and obtains a result for the read request. The data is transmitted (returned) to the host 10 as data. Specifically, as in step S111, the access processing unit 240 stores the area on the SSD cache 220 indicated by the head address (SSD) and the data length stored in the line matched in the search performed in step S121. The data is read out from the host and transmitted to the host 10 (step S131). Thereafter, the process proceeds to step S151.

On the other hand, when it is determined in step S122 that the data requested to be read does not exist on the SSD cache 220 (step S122: NO), the access processing unit 240 reads the data requested to be read from the hard disk 210, and reads the read request. Is transmitted (returned) to the host 10 as result data. Specifically, since the address on the hard disk 210 matches the virtual address, the access processing unit 240 stores the head address (virtual) and the data length stored in the line matched in the search performed in step S121. The data is read from the area on the hard disk 210 shown and transmitted to the host 10 (step S141).

The access processing unit 240 that has transmitted the data to the host 10 in step S131 or step S141 stores the data read in that step (hereinafter referred to as “storage target data” in the description of FIG. 8) in the DRAM cache 230. Process to store.
In the present embodiment, as a replacement policy for the DRAM cache 230, a policy is employed in which data received from the host 10 is always stored in the DRAM cache 230. However, the scope of application of the embodiment of the present invention is not limited to this. For example, the access frequency of data that has received a processing request is compared with the access frequency of each data on the DRAM cache 230, and data having a lower access frequency than the data that has received the processing request is released from the DRAM cache 230. Thus, it may be determined whether or not it is possible to secure the capacity of the data for which the processing request has been received. In this case, the access processing unit 240 performs the following process only when it is determined that the data capacity can be secured. On the other hand, if the access processing unit 240 determines that the data capacity cannot be secured, the access processing unit 240 accesses the data that has received the processing request (the data on the SSD cache 220 or the hard disk 210 corresponding to the data that has received the processing request). Only the frequency is updated, and the replacement of the DRAM cache 230 is not performed, and the processing of FIG.

In the process of storing the storage target data in the DRAM cache 230, the access processing unit 240 first acquires the free capacity on the DRAM cache 230. For example, the access processing unit 240 sums the values in the data length column of the DRAM cache management table stored in the data information storage unit 280 and subtracts the obtained value from the total capacity of the DRAM cache 230 to calculate the free capacity. (Step S151).
Then, the access processing unit 240 compares the data length of the storage target data with the free capacity of the DRAM cache 230 and determines whether or not there is free capacity in the DRAM cache 230 that can store the storage target data. (Step S152).
If the access processing unit 240 determines that there is free space in the DRAM cache 230 that can store the storage target data (step S152: YES), the access processing unit 240 proceeds to step S163.

On the other hand, when it is determined in step S152 that there is no free space in the DRAM cache 230 that can store the storage target data (step S152: NO), the access processing unit 240 releases it to secure the free space. Select data. Specifically, the access processing unit 240 refers to the DRAM cache management table stored in the data information storage unit 280 until the total data length becomes greater than or equal to the data length of the storage target data in order of increasing access frequency. Data on the DRAM cache 230 is selected (step S161).
Next, the access processing unit 240 performs processing for storing each of the data selected in step S161 in the SSD cache 220 or the hard disk 210 as necessary. Details of this processing will be described later. Thereafter, the access processing unit 240 releases the data selected in step S161 and secures a free capacity capable of storing the storage target data. (The above is step S162).
Then, the access processing unit 240 writes the storage target data to the DRAM cache 230 (step S163). Thereafter, the process of FIG.

FIG. 9 is a flowchart showing a processing procedure of the storage device 20 when a write request from the host 10 (FIG. 1) is received. Each time the storage device 20 receives a write request from the host 10, the storage device 20 performs the processing of FIG.
Steps S201 to S213 in FIG. 9 are the same as steps S151 to S163 in FIG. In steps S201 to S213, the data requested to be written by the host 10 corresponds to the storage target data in steps S151 to S163.
The case where the data requested to be written is new data, that is, the case where the area indicated by the head address and the data length included in the write request is an empty area on the hard disk 210 will be described. In this case, the access processing unit 240 secures the free area on the hard disk 210 as an area for storing data requested to be written, and then performs the process of FIG.
When a release request (write request with a data length of 0) is received from the host 10, the access processing unit 240 releases the corresponding area in each of the DRAM cache 230, the SSD cache 220, and the hard disk 210. Then, the SSD cache management table and the DRAM cache management table stored in the data information storage unit 280 are updated.

10 and 11 are data selected as a release target in step S162 (FIG. 8) and step S212 (FIG. 9) (hereinafter referred to as “selected data (DRAM)” in the description of FIGS. 9 and 10). ) Is a flowchart showing a processing procedure for storing in the SSD cache 220 or the hard disk 210 as necessary.
10 and 11, the access processing unit 240 first starts a loop L1 in which processing is performed on each of the selected data (DRAM) in descending order of access frequency. The reason for processing in the order of the high access frequency is to eliminate the waste of the selected data (DRAM) written in the SSD cache being freed (swapped out) when processing the other selected data (DRAM). (Step S301).

The access processing unit 240 determines whether to store the selected data (DRAM) in the SSD cache 220 based on the free space on the SSD cache 220 and the release priority of each data on the SSD cache 220.
Specifically, the access processing unit 240 first acquires the free capacity on the SSD cache 220. For example, the access processing unit 240 totals the values in the data length column of the SSD cache management table stored in the data information storage unit 280 and subtracts the obtained value from the total capacity of the SSD cache 220 to calculate the free capacity. (Step S302).
Next, the access processing unit 240 compares the data length of the storage target data with the free capacity of the SSD cache 220 to determine whether or not the free capacity capable of storing the storage target data exists on the SSD cache 220. Determination is made (step S303). If the access processing unit 240 determines that there is free space in the SSD cache 220 where the storage target data can be stored (step S303: YES), the access processing unit 240 proceeds to step S331.

On the other hand, if it is determined in step S303 that there is no free space in the SSD cache 220 that can store the storage target data (step S303: NO), the access processing unit 240 determines that the release priority order determining unit 270 , Request release priority determination. The release priority order determination unit 270 then selects data (DRAM) to be processed in the loop L1 (hereinafter referred to as “loop L1 data” in the description of FIGS. 9 and 10) and the SSD cache 220. For each of the above data, the release priority order is determined and output to the access processing unit 240. A method for determining the release priority will be described later.
The release priority order determination unit 270 may calculate the release priority order for each data on the SSD cache 220 before the start of the loop L1. As a result, it is not necessary to repeatedly calculate the release priority, and the amount of calculation can be reduced (step S311).

The access processing unit 240 that has received the output of the release priority order selects data to be released from the data on the SSD cache 220 and the loop L1 data (step S312).
Specifically, the process of step S312 is as follows.
First, the access processing unit 240 totals the data lengths of data having a higher release priority than the loop L1 data among the data on the SSD cache 220 (step S401).
The access processing unit 240 determines whether the total data length is less than or equal to the data length of the loop L1 data (step S402). When determining that the total data length is equal to or less than the data length of the loop L1 data, the access processing unit 240 selects the loop L1 data as data to be released (step S411). On the other hand, if the access processing unit 240 determines that the total data length is greater than the data length of the loop L1 data in step S402, the access processing unit 240 converts the data on the SSD cache to the data length in descending order of release priority. Selection is made until the total value + the free space on the SDD cache becomes longer (larger) than the data length of the loop L1 data (step S412). Above, the process of step S312 is complete | finished and it progresses to step S313.

Next, the access processing unit 240 starts a loop L2 for performing processing on each of the data selected in step S312 (hereinafter referred to as “selected data (SSD)” in the description of FIGS. 10 and 11) ( Step S313). In this loop, the access processing unit 240 updates the data selected by the write request from the host 10 among the selected data (SSD) (that is, the selected data (SSD) in which the Dirty flag is set). ) Only to the hard disk 210.
In the process of the loop L2, first, the access processing unit 240 refers to the SSD cache management table or the DRAM cache management table stored in the data information storage unit 280, and selects the selected data (the processing target in the loop L2 ( SSD) (hereinafter, referred to as “loop L2 data” in the description of FIGS. 10 and 11), the value of the Dirty flag is read (step S314). Next, the access processing unit 240 determines whether or not the Dirty flag is set (that is, whether or not the read value is “1”) based on the value of the read Dirty flag (step S315). . If the access processing unit 240 determines that the Dirty flag is not set (step S315: NO), the access processing unit 240 proceeds to step S322.

On the other hand, if the access processing unit 240 determines in step S315 that the Dirty flag is set (step S315: YES), the loop L2 data is written to the hard disk 210, that is, the loop L2 data on the hard disk 210 is written. Update (step S321).
The access processing unit 240 determines whether or not the processing of the loop L2 has been completed for all the selected data (SSD). If the access processing unit 240 determines that there is unprocessed selected data (SSD), the access processing unit 240 returns to step S313 and continues the processing of the loop L2. On the other hand, if the access processing unit 240 determines that the processing of the loop L2 has been completed for all the selected data (SSD), the access processing unit 240 ends the loop L2 (step S322).

Next, the access processing unit 240 determines whether the data selected in step S312 is data on the SSD cache (step S323). If the access processing unit 240 determines that the data selected in step S312 is not the data on the SSD cache (that is, the loop L1 data is selected) (step S323: YES), the access processing unit 240 proceeds to step S333. In this case, the loop L1 data is not written to the SSD cache 220.
On the other hand, when it is determined in step S323 that the data selected in step S312 is data on the SSD cache (step S323: YES), the access processing unit 240 converts each data selected in step S312 to the SSD. Release from cache. Further, the access processing unit 240 updates the SSD cache management table, that is, deletes information on data released from the SSD cache from the SSD cache management table (step S331).

Then, the access processing unit 240 writes the loop L1 data, that is, the data released from the DRAM cache 230 to the SSD cache 220. Further, the access processing unit 240 updates the SSD cache management table, that is, provides a row corresponding to the data written in the SSD cache 220 in the SSD cache management table, and writes the information of each item (step S332). .
The access processing unit 240 determines whether or not the processing of the loop L1 has been completed for all the selected data (DRAM). If the access processing unit 240 determines that there is unprocessed selected data (DRAM), the access processing unit 240 returns to step S301 and continues the processing of the loop L1. On the other hand, if the access processing unit 240 determines that the processing of the loop L1 has been completed for all the selected data (DRAM), the access processing unit 240 ends the loop L1 (step S333).

The access processing unit 240 releases all selected data (DRAM) from the DRAM cache 230. Further, the access processing unit 240 updates the DRAM cache management table, that is, deletes information on the data released from the DRAM cache from the DRAM cache management table (step S334). Thereafter, the processes in FIGS. 10 and 11 are terminated.

A method in which the release priority determining unit 270 determines the release priority in step S311 will be described. The release priority order determination unit 270 increases the release priority order for data having a longer data length.
For example, the release priority determining unit 270 assigns release priorities to the data for which the release priority is to be determined in order of increasing data length. As will be described later, since the access processing unit 240 preferentially releases data with a high release priority from the SSD cache 220, data with a short data length tends to remain in the SSD cache 220. Data with a short data length is data in which the ratio of delay time (latency) at the initial stage of access to the entire time required for access is large. That is, data with a short data length has a large ratio of the time required to read data when the data is read from the hard disk 210 to the time required to read the data when the data is read from the SSD cache 220. In this regard, data with a short data length is data that has a large cost when no hit is made on the SSD cache 220. By storing such data in the SSD cache 220, the reduction rate due to the use of the cache increases in the response time from when the storage device 20 receives the read request from the host 10 to when all the data is transmitted. I can expect.
As described above, the hard disk 210 and the SSD cache 220 can be appropriately replaced according to the access performance characteristics of the storage medium.

The method by which the release priority order determination unit 270 determines the release priority order is not limited to the above-described method of assigning the release priority order in descending order of the data length.
For example, the release priority order determination unit 270 may calculate the release priority index value R based on the formula (1) and assign the release priority order in ascending order of the release priority index value R.
R = F / L ... Formula (1)
Here, “F” indicates the access frequency to the data for which the release priority order is determined. “L” indicates the data length of the data.
By determining the priority order in this way, data with a longer data length is given a higher release priority order. Therefore, as with the case where the release priority order is assigned in order of the longer data length, no hit was made on the SSD cache 220. In this case, data with a large cost can be left in the SSD cache 220. In addition, when the priority order is determined in this way, data with a lower access frequency is given a higher release priority order, so that data with a higher access frequency can remain in the SSD cache 220. As a result, an improvement in hit rate can be expected.
As described above, the hit rate can be improved while performing appropriate replacement of the hard disk 210 and the SSD cache 220 in accordance with the storage medium access performance characteristics.

The release priority order determination unit 270 may calculate the release priority index value Q based on the formula (2), and assign the release priority order in ascending order of the release priority index value Q.
Q = R / L (2)
Here, “R” indicates the priority of the LRU replacement of the data for which the release priority is to be determined, that is, the oldest access time. “L” indicates the data length of the data.
When the access frequency for each data is almost fixed, the higher the priority of LRU replacement, the lower the access frequency. Therefore, when the release priority is assigned in ascending order of the release priority index value Q, the cost of not hitting on the SSD cache 220 is the same as in the above case where the release priority is assigned based on the formula (1). Large data can remain in the SSD cache 220. In addition, when assigning release priorities in ascending order of the release priority index value Q, data with lower access frequency is given higher release priorities, so that data with higher access frequency can remain in the SSD cache 220.
As described above, the hit rate can be improved while appropriately replacing the hard disk 210 and the SSD cache 220 according to the access performance characteristics of the storage medium.

The release priority order determination unit 270 may calculate the release priority index value using the delay time and access speed of the hard disk 210 and the SSD cache 220 stored in the performance information storage unit 260.
For example, first, the data length of the target data for determining the release priority is set to “L”. The access frequency for the data is “F”. It is assumed that the data reading speed and writing speed of the hard disk 210 are both “s _h ”. It is assumed that the data read speed and write speed of the SSD cache 220 are both “s _s ”. It is assumed that the delay time of the hard disk 210 is “a _h ” for both reading and writing. Assume that the delay time of the SSD cache 220 is 0 (that is, there is no delay time).

In this case, when the data is read from the SSD cache 220, the read time from when the read request is received until all the data is read is calculated by Expression (3).
L / s _s Formula (3)
When data is read from the hard disk 210, the read time from receipt of a read request until reading of all data is calculated by equation (4).
a _h + L / s _h ... Formula (4)
Therefore, the ratio obtained by dividing the read time when data is read from the SSD cache 220 by the read time when data is read from the hard disk 210 is expressed by Equation (5).
(L / s _s ) / (a _h + L / s _h ) (5)
Data with a smaller value has a higher read time reduction rate when read from the SSD cache 220 than when read from the hard disk 210. In this regard, the smaller the value calculated by the equation (5), the higher the cost when no hit is made on the SSD cache 220.

Therefore, the release priority order determination unit 270 calculates the release priority index value P of Expression (6) obtained by multiplying Expression (5) by the access frequency F, and sets the release priority order in ascending order of the release priority index value P. You may make it attach.
P = ((L / s _s ) / (a _h + L / s _h )) F (6)
By determining the priority order in this way, data having a large cost when no hit is made on the SSD cache 220 can be left in the SSD cache 220. In addition, when assigning release priorities in ascending order of the release priority index value P, data with lower access frequency is given higher release priorities, so that data with higher access frequency can remain in the SSD cache 220.

As described above, the hit rate can be improved while appropriately replacing the hard disk 210 and the SSD cache 220 according to the access performance characteristics of the storage medium.
Equation (6) can be transformed into Equation (7).
P = ((1 / s _s ) / (a _h / L + 1 / s _h )) F (7)
Therefore, the release priority index value P decreases as the value of L increases. That is, the longer the data length, the higher the release priority.

The timing at which the release priority determining unit 270 determines the release priority is not limited to the timing at which step S311 is executed. For example, the release priority determination unit 270 may periodically determine the release priority of each data, and the access processing unit 240 may use the release priority. In this case, it is not necessary for the access processing unit 240 to wait for the release priority determination by the release priority determination unit 270 in step 311 and the processing time can be shortened.

Next, an operation example of the storage device 20 will be described with reference to FIGS.
In the following, it is assumed that the hard disk 210 is divided into blocks and addresses are assigned in order from 0 for each block. The hard disk 210 is assumed to store one piece of data in consecutive blocks. Assume that the capacity of the hard disk is sufficiently large with respect to the amount of data to be written, and the problem of fragmentation does not occur.
Assume that the delay time when accessing discontinuous blocks of the hard disk 210 is 20 ms (milliseconds) for both reading and writing. It is assumed that the reading speed when accessing consecutive blocks after starting reading is 50000 blocks per second.

The SSD cache 220 is divided into blocks of the same size as the hard disk 210, and the number of blocks is 10,000.
It is assumed that the delay time when accessing discontinuous blocks in the SSD cache 220 is 0 ms regardless of reading or writing. Therefore, it is assumed that there is no delay in reading or writing due to fragments. Assume that the reading speed when accessing consecutive blocks after starting reading is 100,000 blocks per second.

The DRAM cache 230 is divided into blocks of the same size as the hard disk 210 and the number of blocks is 1000. LRU is used as a policy for determining data to be replaced on the DRAM cache 230.
Assume that the address space of the entire storage device 20 matches the address space of the block of the hard disk 210.

FIG. 12 is a diagram showing information stored in the DRAM cache management table at the start of a series of processes to be described later (hereinafter referred to as “process start time”). In order to simplify the description, it is assumed that one piece of data is stored in successive blocks on the DRAM cache 230, and an area is designated by a head address and a data length. As described above, since the delay time (latency) of the DRAM cache 230 is 0, even when one piece of data is stored in discontinuous blocks on the DRAM cache 230, the operation timing of the storage device 20 is as follows. It is the same as the description.

In the following, among the areas on the DRAM cache 230 in the state of FIG. 12, the area of 10 blocks from the start address “910” is referred to as an area “A”. An area of 30 blocks from the start address “880” is referred to as an area “B”. An area of 500 blocks from the start address “380” is referred to as an area “C”. The number of blocks in use in the state of FIG. 12 is 920 blocks obtained by adding the data length “10” to the start address “910” of the area A. Therefore, the free capacity is 80 blocks obtained by subtracting 920 blocks from 1000 blocks, which is the capacity of the DRAM cache 230.
Of the data shown in FIG. 12, the data in the area A has the highest release priority, that is, the access frequency is low, and then the data in the area B, the data in the area C,. Suppose it is expensive.

FIG. 13 is a diagram showing information stored in the SSD cache management table at the start of processing. As with the DRAM cache 230, one piece of data is stored in successive blocks on the data information storage unit 280, and an area is designated by a head address and a data length. Similar to the DRAM cache 230, the SSD cache 220 has a delay time (latency) of 0. Therefore, even when one piece of data is stored in a discontinuous block on the SSD cache 220, the operation timing of the storage device 20 is as follows. It is the same as that of description.
Hereinafter, the areas on the SSD cache 220 in the state of FIG. 13 are referred to as areas “P”, “Q”,. The number of blocks in use in the state of FIG. 13 is 9980 blocks obtained by adding the data length “200” to the start address “9780” of the area U. Therefore, the free capacity is 20 blocks obtained by subtracting 9980 blocks from 10,000 blocks, which is the capacity of the SSD cache 220.
The data shown in FIG. 13 has a high release priority in the order of low access frequency, that is, data in the region U, data in the region T,.

FIG. 14 is a diagram illustrating an example of a series of processing requests transmitted from the host 10 (FIG. 1) to the storage device 20. Processing is performed in the order of the arrow α shown in FIG. A read request T shown in FIG. 14 (read request shown in a row with a symbol T) is a read request for data stored in the area T on the SSD cache 220 in the state shown in FIG.
On the other hand, read requests X, Y, and Z are requests for reading data stored in areas X, Y, and Z on hard disk 210, respectively. These data are not stored on the DRAM cache 230 in the state of FIG. 12 or on the SSD cache 220 in the state of FIG. 13 but are stored on the hard disk 210.

When a read request T is transmitted from the host 10 to the storage device 20, the access processing unit 240 first refers to the DRAM cache management table on the data information storage unit 280 and stores data in the region T in the DRAM cache 230. Is stored. Here, the data of the region T is not stored in the DRAM cache 230 (FIG. 12).
Therefore, the access processing unit 240 refers to the SSD cache management table on the data information storage unit 280 and determines whether or not the data in the region T is stored in the SSD cache 220. The SSD cache 220 stores data of the area T (FIG. 13). Therefore, the access processing unit 240 reads the data in the region T from the SSD cache 220 and transmits the read data to the host 10 that is the transmission source of the read request T as a result of the read request T.

Thereafter, the access processing unit 240 updates the access frequency of the area T stored in the SSD cache management table stored in the data information storage unit 280. Specifically, the access processing unit 240 adds 1 to the access frequency “999” of the region T to obtain “1000”.
FIG. 16 shows information stored in the SSD cache management table after a series of processing for the read request T is performed.
Since the free capacity of the DRAM cache 230 is 80 blocks at the start of processing (FIG. 12), the data in the region T (80 blocks) can be stored in the DRAM cache 230 without releasing other data. Therefore, the access processing unit 240 writes the data in the area T into the DRAM cache 230. As a result, the free capacity of the DRAM cache 230 becomes 0 blocks.
FIG. 15 shows information stored in the DRAM cache management table after a series of processes for the read request T is performed.

When a read request X is transmitted from the host 10 to the storage device 20 following the read request T, the access processing unit 240 determines whether or not the data in the area X is stored in the DRAM cache 230. Here, the data of the area X is not stored in the DRAM cache 230 (FIG. 15).
Therefore, the access processing unit 240 determines whether or not the data of the area X is stored in the SSD cache 220. Here, the data of the area X is not stored on the SSD cache 220 (FIG. 16).
Therefore, the access processing unit 240 reads the data in the area X from the hard disk 210 and transmits the read data to the host 10 that is the transmission source of the read request X as a result of the read request X.

Thereafter, the access processing unit 240 stores the data of the area X in the DRAM cache 230. Since the free capacity of the DRAM cache 230 is 0 block (FIG. 15), the data in the area X cannot be stored in the DRAM cache 230 as it is. Therefore, the access processing unit 240 releases the data of the area A having the highest release priority among the areas on the DRAM cache 230 from the DRAM cache 230 and writes the data of the area X.
At this time, the access processing unit 240 determines whether to write the data of the area A to be released to the SSD cache 220. Referring to the SSD cache management table on the data information storage unit 280, the free space of the SSD cache 220 is 20 blocks (FIG. 16), and the data in the area A (10 blocks) is stored without releasing other data. Is possible. Therefore, the access processing unit 240 writes the data of the area A into the SSD cache 220. As a result, the free space of the SSD cache 220 becomes 10 blocks.
FIG. 17 shows information stored in the DRAM cache management table after a series of processing for the read request X is performed. FIG. 18 shows information stored in the SSD cache management table after a series of processing for the read request X is performed.

When a read request Y is transmitted from the host 10 following the read request X, the access processing unit 240 determines whether data in the area Y is stored in the DRAM cache 230. The DRAM cache 230 stores no data in the area Y (FIG. 17).
Therefore, the access processing unit 240 determines whether or not the data of the area Y is stored in the SSD cache 220. Here, the data of area Y is not stored on the SSD cache 220 (FIG. 18).

Therefore, the access processing unit 240 reads the data in the area Y from the hard disk 210 and transmits the read data to the host 10 that is the transmission source of the read request Y as a result of the read request Y.
Thereafter, the access processing unit 240 stores the data of the area Y in the DRAM cache 230. Since the free capacity of the DRAM cache 230 is 0 block (FIG. 17), the data in the area X cannot be stored in the DRAM cache 230 as it is. Therefore, the access processing unit 240 releases the data in the area B having the highest data replacement priority from the area on the DRAM cache 230 from the DRAM cache 230 and writes the data in the area Y.

At this time, the access processing unit 240 determines whether to write the data of the area B to be released to the SSD cache 220 (FIG. 11: Steps S302 to 312). Referring to the SSD cache management table on the data information storage unit 280, the free space of the SSD cache 220 is 10 blocks (FIG. 18), and 30 blocks of data in the area B are stored on the SSD cache 220. Data needs to be released. Therefore, the release priority order determination unit 270 calculates the release priority order for each piece of data on the SSD cache 220 and determines the data to be released (FIG. 11: step S331). The release priority order determination unit 270 calculates the index value F / L based on the reference count F of each data stored in the SSD cache management table and the data length L of each data, and the calculated index value is low. The release priority is assigned in order from the data.

At this time, the data in the areas P, Q, R, S, T, U, and A exist in the SSD cache 220 (FIG. 18). The index values of these data are calculated as follows. The index value of P is 50000/5000 = 10. The index value of Q is 36000/3000 = 12. The index value of R is 10800/1200 = 9. The index value of S is 5500/500 = 11. The index value of T is (999 + 1) /80=12.5 because it is accessed once in the present embodiment. The index value of U is 50/200 = 0.25. The index value of A is 500/10 = 50. When the index value is calculated for the data in the area B released from the DRAM cache 230, 900/30 = 30. Therefore, the release priority order determination unit 270 assigns the highest release priority order to the data in the area U having the smallest index value. Since the data length of the area U is 200 blocks, by releasing the data in the area U, it is possible to store data up to 210 blocks in total with the current free capacity. Therefore, it is not necessary to replace the data other than the area U in order to store the data of the area B (20 blocks). Therefore, the access processing unit 240 determines the data in the area U as a release target.

The access processing unit 240 reads the value of the Dirty flag from the SSD cache management table for the data in the area U to be released (FIG. 11: step S314). Here, the Dirty flag is set (FIG. 18). Therefore, the access processing unit 240 writes the data of the area U to the hard disk 210 (FIG. 11: Step S321). Thereafter, the access processing unit 240 releases the data of the area U from the SSD cache 220 and deletes the information of the area U included in the SSD cache management table of the data information storage unit 280 (FIG. 11: Step S331).

Thereafter, the access processing unit 240 adds area B data information to the SSD cache management table on the data information storage unit 280, and stores the area B data in the SSD cache 220 (FIG. 11: step S332). As a result, the free capacity of the SSD cache 220 becomes 10 + 200−30 = 180 blocks.
FIG. 20 shows information stored in the SSD cache management table after a series of processing for the read request Y is performed.
Thereafter, the data in the area B is released from the DRAM cache 230 (FIG. 11: Step S334), and the data in the area Y is newly stored in the DRAM cache 230 (FIG. 8: Step S163). The free capacity of the DRAM cache 230 is 10 blocks.
FIG. 19 shows information stored in the DRAM cache management table after a series of processing for the read request Y is performed.

When a read request Z is transmitted from the host 10 following the read request Y, the access processing unit 240 determines whether or not the data in the area Z is stored in the DRAM cache 230. The DRAM cache 230 does not store area Z data.
Therefore, the access processing unit 240 determines whether or not the data of the area Z is stored in the SSD cache 220. Data of the area Z is not stored on the SSD cache 220. Therefore, the access processing unit 240 reads the data in the area Z from the hard disk 210 and transmits the read data to the read request Z transmission source host 10 as a result of the read request Z.

After that, the access processing unit 240 stores the data of the area Z in the DRAM cache 230. Since the free space of the DRAM cache 230 is 10 blocks (FIG. 19), the data in the area X cannot be stored in the DRAM cache 230 as it is. Therefore, the access processing unit 240 releases the data in the area C having the highest release priority among the areas on the DRAM cache 230 from the DRAM cache 230 and writes the data in the area Z.

At this time, the access processing unit 240 determines whether or not to write the data of the area C to be released to the SSD cache 220. Referring to the SSD cache management table on the data information storage unit 280, the free space of the SSD cache 220 is 180 blocks (FIG. 20), and in order to store 500 blocks of data in the area C, the SSD cache 220 Data needs to be released. Therefore, the release priority order determination unit 270 calculates the release priority order for each piece of data on the SSD cache 220 and determines the data to be released (FIG. 11: step S331).

At this time, the data in the areas P, Q, R, S, T, B, and A exist in the SSD cache 220 (FIG. 20). These index values are calculated as follows. The index value of P is 50000/5000 = 10. The index value of Q is 36000/3000 = 12. The index value of R is 10800/1200 = 9. The index value of S is 5500/500 = 11. The index value of T is 1000/80 = 12.5. The index value of A is 500/10 = 50. The index value of B is 900/30 = 30. On the other hand, when the index value is obtained for the data in the area C released from the DRAM cache 230, the index value of C is 2000/500 = 4. Thus, the data with the smallest index value is not the data stored in the SSD cache 220 but the data in the area C released from the DRAM cache 230. The release priority determining unit 270 assigns the highest release priority to the data in the area C having the smallest index value. Thereby, the access processing unit 240 does not release the data stored in the SSD cache 220 and does not store the data in the area C in the SSD cache 220 (FIG. 11: Step S323: NO).

Since the Dirty flag of the data in area C is 0 (FIG. 19), the access processing unit 240 does not write the data in area C to the hard disk 210 (FIG. 11: Step S315: NO). Thereafter, the access processing unit 240 releases the data in the area C from the DRAM cache 230 (FIG. 11: step S334), and writes the data in the area Z into the DRAM cache 230 (FIG. 8: step S163).
FIG. 21 shows information stored in the DRAM cache management table after a series of processing for the read request Z is performed.
Thus, the storage device 20 ends the processing for the processing instructions T, X, Y, and Z shown in FIG.

As described above, the release priority determining unit 270 increases the release priority of data when the SSD cache 220 performs replacement as the data length of the data stored in the SSD cache 220 is longer. Short data can be preferentially left in the SSD cache 220. This data with a short data length is data with a large ratio of latency (delay time at the beginning of access) in the read time, and the read time reduction rate by storing in the cache is high.
On the other hand, when a read request is received for data with a long data length released from the SSD cache 220, the storage device 20 reads the data from the hard disk 210 and sends a reply. At this time, in the data having a long data length, the ratio of the latency in the reading time is small, and the increase in the reading time due to the latency is relatively small.

In this way, the storage device 20 preferentially leaves data with a short data length in the SSD cache 220 and reads data with a long data length from the hard disk 210. As a result, an increase in reading time due to latency can be suppressed, and reading speed can be improved.
In particular, the longer the data length of the data stored in the SSD cache 220, the higher the release priority of the data when the SSD cache 220 performs the replacement. Can be preferentially released, and further, not stored in the SSD cache. Thereby, the utilization efficiency of the SSD cache 220 can be improved. Further, it is possible to prevent data having a short data length from being evicted from the SSD cache 220 due to replacement.

In particular, stream data is generally data with a low access frequency and a long data length. By using the above method of increasing the release priority as the data length is longer, the stream data is not stored in the SSD cache 220 or is released preferentially, thereby improving the hit rate in the SSD cache 220. be able to.
Furthermore, stream data is normally accessed in order from the beginning of the data, and is accessed by accessing consecutive blocks. For this reason, the decrease in access speed due to the stream data not hitting the cache is smaller than other data. By increasing the release priority of the stream data and preferentially storing other data in the SSD cache 220, the access speed of the storage device 20 can be improved.

The release priority determination unit 270 also replaces the SSD cache 220 as the data length of the data stored in the SSD cache 220 is longer and the elapsed time from the last access to the data is longer. Increase the release priority when doing it. Therefore, it is possible to improve the hit rate while performing appropriate replacement according to the latency of the storage medium.

In addition, the release priority determination unit 270 increases the release priority when the SSD cache 220 performs replacement as the data length of the data stored in the SSD cache 220 is longer and the access frequency to the data is higher. To do. Therefore, it is possible to improve the hit rate while performing appropriate replacement according to the latency of the storage medium.

Further, by providing the SSD cache 220 as a secondary cache and providing the DRAM cache 230 as a primary cache, a large-capacity and high-speed cache can be realized at a relatively low cost.

The embodiment of the present invention can also be applied to a storage device having a one-layer cache. In this case, the access processing unit 240 performs processing excluding processing for the DRAM cache 230 in response to a processing request from the host 10. Specifically, steps S121 to S141 (FIG. 8) and steps S302 to S332 (FIGS. 10 and 11) are executed for the read request, and steps S302 to S332 (FIG. 10) are executed for the write request. , 11).

The series of processes in the storage device 20 described above may be stored in a computer-readable recording medium in the form of a program. The above processing may be performed by the computer reading and executing this program. That is, each process in the storage device 20 may be realized by a central processing unit such as a CPU reading the above program into a main storage device such as a ROM or RAM, and executing information processing and calculation processing. .

As described above, the embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design changes and the like without departing from the gist of the present invention.

This application claims priority based on Japanese Patent Application No. 2010-155102 filed on July 1, 2010, the entire disclosure of which is incorporated herein.

The present invention is suitable for use in a storage device, a release priority determination method, and a program.

10 host 20 storage device 210 hard disk 220 SSD cache 230 DRAM cache 240 access processing unit 250 storage medium performance measurement unit 260 performance information storage unit 270 release priority order determination unit 280 data information storage unit 30 network

Claims (8)

1. Temporarily storing data stored in a storage medium, a cache having a lower latency than the storage medium; and
   A release priority determining unit that increases the release priority of the data when the cache performs replacement, as the data length of the data stored in the cache is longer;
   A storage device comprising:
2. The release priority determination unit increases the release priority when the cache performs replacement as the elapsed time from the last access to the data is longer for the data stored in the cache. Item 4. The storage device according to Item 1.
3. 3. The release priority determination unit according to claim 1, wherein for the data stored in the cache, the release priority when the cache performs replacement increases as the access frequency to the data decreases. Storage device.
4. The storage device according to any one of claims 1 to 3, further comprising an upper cache that is an upper cache than the cache.
5. The storage device according to any one of claims 1 to 4, wherein the storage medium is a hard disk.
6. The storage device according to any one of claims 1 to 5, wherein the cache is configured by a storage medium including a nonvolatile semiconductor.
7. A storage device that temporarily stores data stored in a storage medium and includes a cache having a latency lower than that of the storage medium, and a release priority determination method when the cache performs replacement,
   A release priority determination method comprising: increasing the release priority of data when the cache performs replacement as the data length of data stored in the cache is longer.
8. A computer that temporarily stores data stored in a storage medium and has a cache having a smaller latency than the storage medium, and determines a release priority when the cache performs replacement.
   A program for executing an increase in the release priority of the data when the cache performs replacement as the data length of the data stored in the cache is longer.

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