WO2012000907A1 - A method of treating a multilayer structure with hydrofluoric acid - Google Patents

A method of treating a multilayer structure with hydrofluoric acid Download PDF

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Publication number
WO2012000907A1
WO2012000907A1 PCT/EP2011/060643 EP2011060643W WO2012000907A1 WO 2012000907 A1 WO2012000907 A1 WO 2012000907A1 EP 2011060643 W EP2011060643 W EP 2011060643W WO 2012000907 A1 WO2012000907 A1 WO 2012000907A1
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WIPO (PCT)
Prior art keywords
wafer
oxide layer
bonding
layer
multilayer structure
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PCT/EP2011/060643
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French (fr)
Inventor
Alexandre Vaufredaz
Fleur Guittard
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Soitec
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Publication of WO2012000907A1 publication Critical patent/WO2012000907A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Definitions

  • the present invention relates to the field of producing multilayer semiconductor structures (also known as multilayer semiconductor wafers) produced by
  • Such a layer transfer is obtained by bonding, for example by direct wafer bonding, of a first wafer (or initial substrate) onto a second wafer (or final substrate) , the first wafer generally being thinned after bonding.
  • the transferred layer may also comprise all or part of a component or a plurality of microcomponents .
  • SOS silicon on sapphire
  • SOI silicon on insulator
  • the invention addresses the problem of unwanted fragments of material that appear on the exposed surface of the transferred layer during the manufacture of a multilayer structure, for example of the SOS type. This phenomenon of contamination has been observed following a technical step involving chemically etching at least a portion of a multilayer SOS structure. This technical step may correspond, for example, to chemical etching carried out on the first wafer of a multilayer SOS
  • the technique frequently used during manufacture of multilayer structures for the purpose of cleaning the surface of a transferred layer after a chemical etching step consists in carrying out a step of rinsing (or cleaning) using a pressure jet .
  • a step of rinsing or cleaning
  • pressurized jet of water (or any rinsing solution) is manually applied to the surface of the wafer to be cleaned.
  • the present invention proposes a method of treating a multilayer structure, the multilayer structure comprising a wafer bonded to a substrate at a bonding interface , a bonding oxide layer being disposed between the wafer and the substrate, the method
  • a step of partially deoxidizing the bonding oxide layer of the multilayer structure by hydrofluoric acid chemical etching in order to eliminate a peripheral portion of the bonding oxide layer • before the chemical etching step, a step of partially deoxidizing the bonding oxide layer of the multilayer structure by hydrofluoric acid chemical etching in order to eliminate a peripheral portion of the bonding oxide layer .
  • the method of the invention can be used to eliminate a peripheral portion of the bonding oxide layer of a multilayer structure, for example of the SOS type, from which portion fragments may be detached during a subsequent chemical etching step and thus contaminate the surface of the structure.
  • the invention can be used to minimize the source of the oxide fragments that might contaminate the exposed surface of a multilayer structure during a subsequent technical step carried out using chemical etching .
  • the method of the invention is applicable when the multilayer structure has a surface energy of less than 1 J/m 2 at the bonding interface.
  • the wafer may include microcomponents .
  • microcomponents means any devices or motifs resulting from technical steps carried out on the wafers of a multilayer structure. In particular, they may be active or passive components, simple contact points or interconnections.
  • the chemical etching step corresponds to a step of chemically thinning the wafer .
  • the chemical etching step may be carried out with a solution of TMAH and/or a solution of KOH.
  • the treatment method of the invention may also comprise a step of mechanically thinning the wafer, the step of partially deoxidizing the bonding oxide layer being carried out after the mechanical thinning step.
  • the step of partially deoxidizing the bonding oxide layer may also comprise immersing at least a portion of the multilayer structure in a hydrofluoric acid solution, preferably in a concentration of 10% by weight or less for a period in the range 60 s [seconds] to 400 s.
  • the use of a 10% or less hydrofluoric acid solution means that the rate of etching of the exposed portion of the bonding oxide layer located at the periphery of the multilayer structure is controlled in a manner that is optimized.
  • the bonding oxide layer may be formed from a layer of silicon dioxide (SiO?) -
  • the substrate is formed from a material that can resist the chemical etching step, such as sapphire, or is coated with a layer of nitride or a layer of oxide that can resist the chemical etching step.
  • Said oxide layer may, for example, be of the order of 200 A [angstroms] thick.
  • the wafer is a SOI type wafer or a wafer comprising a stack of layers comprising a buried oxide layer, the method comprising the following steps in succession, after the step of partially deoxidizing the bonding layer and before the step of chemically etching the wafer:
  • peripheral portion of the buried oxide layer is also a source of oxide fragments that might contaminate the surface of the multilayer structure during a subsequent chemical etching step.
  • This implementation is advantageous insofar as it can eliminate said peripheral portion and thus minimize the source of oxide fragments that can be deposited on the 'wafer during a chemical thinning step, for example.
  • the preliminary chemical etching step may be carried out with a solution of TMAH or a solution of KOH, the duration of the preliminary chemical etching step preferably being 20 minutes or less.
  • the step of partially deoxidizing the buried layer may be carried out with an etching solution with a hydrofluoric acid concentration of 10% by weight or less , the deoxidation step being carried out for a period that is preferably in the range 200 s to 600 s .
  • the invention also provides a method of
  • the wafer is a SOI type wa er or a wafer comprising a stack of layers comprising a buried oxide layer, the manufacturing method being characterized in that it comprises eliminating a peripheral portion of a layer of the wafer interposed between the bonding oxide layer and the buried oxide layer and a peripheral portion of the buried oxide layer .
  • Figures 3A to 31 diagrammatically represent a treatment method and a method of manufacture in
  • the present invention is of general application to partially deoxidizing a multilayer structure in order to minimize the source of the fragments of material that might appear on the exposed surface of the structure during the course of its fabrication.
  • a SOS multilayer structure is produced by bonding a first wafer to a second wafer, or substrate, formed from sapphire and constituting the support for the first wafer, a bonding oxide layer being present between the two wafers .
  • the wafers composing a multilayer structure are generally in the form of wafers with a generally circular contour that may have various diameters, in particular diameters of 100 mm [millimeter] , 150 um, 200 mm, or 300 mm.
  • the wafers may have any shape, such as a wafer with a rectangular shape, for example .
  • These wafers preferably have a chamfered side, namely a side comprising an upper chamfer and a lower chamfer .
  • Said chamfers generally have a rounded shape .
  • the wafers may have chamfers or edge roundings with different shapes, such as a beveled shape. The role of such chamfers is to facilitate
  • a SOS multilayer structure 111 is formed by assembling a first wafer 108 with a second wafer (or substrate) 110 formed from
  • the first wafer 108 corresponds to a SOI structure comprising a buried oxide layer 104 interposed between two layers of silicon (i.e. the upper layer 101 and the lower layer 102).
  • the first and second wafers 108 and 110 in this example have the same diameter. However, they could have different diameters.
  • the whole surface of the first wafer 108 is oxidized before bonding to the second wafer 110.
  • This oxidation is carried out by means of a heat treatment in an oxidizing medium so that an oxide layer 106 (termed a bonding oxide layer) can be formed over the whole surface of the first wafer 108 before bonding to the second wafer 110.
  • the oxide layer 106 is a layer of S1O 2 .
  • a bonding oxide layer 106 thus exists at the bonding interface between the first wafer 108 and the substrate 110 and permits better bonding therebetween .
  • a bonding oxide layer may be deposited on the face to be assembled (termed the bonding face) of the first wafer 108 before bonding to the second wafer 110.
  • the first wafer 108 has a chamfered side, namely a side comprising an upper chamfer 107a and a lower chamfer 107b.
  • the second wafer 110 has a side comprising an upper chamfer 109a and a lower chamfer 109b.
  • the first wafer 108 and the substrate 110 are assembled using the direct wafer bonding technique known to the skilled person.
  • bonding techniques may be used, however, such as anodic bonding, metallic bonding or bonding with adhesive bonding.
  • the attractive forces between the two surfaces are then large enough to bring about direct wafer bonding (bonding induced by the set of attractive forces (van der Waals forces) of electronic interaction between atoms or molecules on the two surfaces to be bonded) .
  • the first wafer 108 may include microcomponents (not shown in the figures ) at its face for bonding with the second wafer 110 , especially for 3D-integration, which requires transferring one or more layers of microcomponents onto a final support , or for circuit transfer such as, for example, in the
  • the multilayer structure 111 undergoes a moderate reinforcing anneal of the bonding interface (for example 100 °C to 400 °C for 2 hours), which is intended to strengthen the bond between the first wafer 108 and the second wafer 110 (step E12 ) ,
  • thinning of the first wafer 108 is generally carried out in order to form a transferred layer with a predetermined thickness (for example
  • This thinning operation generally includes a chemical etching step.
  • the thinning step in this example comprises two distinct sub-steps.
  • the first wafer 108 is initially mechanically thinned using a grinder or any other tool that can mechanically wear away the material of the first wafer 108 (sub-step E13 ) .
  • This first thinning sub-step can eliminate the ma or portion of the upper la er 102 so as to retain only a residual layer 112 ( Figure 1C ) .
  • a second thinning sub-step is carried out , corresponding to chemically etching the residual layer 112 (sub-step E14).
  • This second sub-step consists in placing the multilayer structure 111 in a bath comprising an etching solution 120 ( Figure ID) .
  • the etching solution used is a solution of TMAH that can etch the silicon of the first wafer 108.
  • Other chemical attack solutions may be
  • ⁇ or a solution of KOH may be used, for example.
  • the buried oxide layer 104 interposed between the layers 101 and 102 of the first wafer 108 act as a stop layer during chemical etching that is then interrupted at the oxide layer 104.
  • the chemical etching can then ⁇ 211mi.Tl Q.t €2 11 * 1 €S T €5S 3L3.TJ.ci1 112 »
  • fragments of material 118 were present on the exposed surface of the first wafer 108. These fragments 118 typically have dimensions of more than 2 um.
  • step E12 for moderately annealing the bonding interface to strengthen it, an annular portion at the periphery of the first wafer 108 located in the vicinity of the lower chamfer 107b is bonded poorly to the second wafer 110 (bonding may even be completely absent ) .
  • the Applicant has observed that during the chemical etching (E14 ) of the thinning step, the etching solution 120 has a tendency to etch the sides of the first wafer 108 and the bonding oxide layer 106 laterally . This lateral etching action causes uncontrolled fracturing of the bonding oxide layer 106, more particularly at the peripheral portion of the oxide layer 106 that is exposed to attack by the etching solution 120 ,
  • This fracturing phenomenon thus causes the formation of debris or oxide fragments 118 (here of Si0 2 )
  • the oxide, silicon and/or circuit fragments originating from the sides of the first wafer 108 might also pollute the exposed surface of the wafer.
  • the Applicant has developed a treatment method of eliminating a peripheral portion of the bonding oxide layer 106 of the multilayer structure 111.
  • Figures 3A and 3B show a multilayer structure 211 identical to the structure 111 shown in Figure 1C, namely a multilayer SOS structure obtained at the end of steps of bonding (Ell), annealing (E12) and mechanical thinning (E13) as described above.
  • Figure 3B shows, in more detail, the structure 211 illustrated in Figure 3A at the peripheral side of the wafers 208 and 210.
  • the multilayer structure 211 under consideration is constituted by a first wafer 208 bonded to a second wafer (or substrate) 210 formed from
  • the first wafer 208 is a SOI structure: it is constituted by a buried oxide layer 204 (identical to the layer 104) interposed between two layers of silicon, namely an upper layer 212 that has been mechanically thinned, termed the residual layer (identical to the layer 112), and a lower layer 201 (identical to the layer 101) .
  • the thickness of the bonding oxide layer 206 at the bonding interface is approximately 500 A.
  • the lower layer 201 and residual layer 212 respectively have thicknesses of 750 A and 65 um.
  • the buried oxide layer 204 in this example has a thickness of approximately 2000 A.
  • 210 is not necessarily formed from sapphire.
  • the wafer 210 may, for example, be formed from silicon.
  • the invention is more generally applicable to multilayer structures obtained by bonding, and in particular to those with a low surface energy ⁇ less than 1 J/m 2 ) at their bonding interface.
  • FIG. 1A and IB other implementations may be carried out to provide a bonding oxide layer between the wafers 208 and 210. It is thus possible to form a bonding oxide layer on the bonding surface of the first wafer 208 and/or on the bonding surface of the second wafer 210, before bonding the two wafers.
  • the substrate 210 is formed from silicon for example, it is possible to oxidize the whole surface of the substrate before bonding with the first wafer 208, taking care that the oxide layer formed is sufficiently thick to resist etches carried out in the treatment process of the invention.
  • deoxidizing the bonding oxide layer 206 is carried out on the multilayer structure 211, During this step E20 , the multilayer structure 211 is placed in an etching solution 222 comprising hydrofluoric acid (HF) ( Figure 3C) .
  • etching solution 222 comprising hydrofluoric acid (HF)
  • the hydrofluoric acid initially attacks the bonding oxide layer 206 at its exposed portion in the vicinity of the periphery of the wafers .
  • the etching solution 222 is
  • Step E20 for partial deoxidation can thus eliminate the peripheral portion of the bonding o ide layer 206 from which fragments may become detached during subsequent chemical etching and might contaminate the surface of the structure ( Figure 3D) .
  • the etching solution 222 has a concentration of HF by weight (denoted C HFI ) of 10% and step E20 for partially deoxidizing the bonding oxide layer 206 consists in immersing the multilayer structure 211 in said etching solution 222 for a time Tl preferably in the range 60 s to 400 s. In this example, Tl is fixed at 70 seconds .
  • concentration C HFI of HF can be envisaged, however .
  • concentration C HFI is preferably 10% (by weight) or less . It is in fact necessary for the concentration of HF to be moderate so that etching is relatively slow and so that :
  • C HPI etching procedure
  • the time Tl during which the multilayer structure 211 is exposed to the action of etching by the solution 222 is then selected as a function of the selected concentration C HFI , in order to control the quantity of bonding oxide layer 206 that is eliminated at the
  • the hydrofluoric acid infiltrates the bonding interface between the wafers 208 and 210 too deeply, thus degrading the quality of the bond between said two wafers .
  • a step E26 for chemical etching (more specifically E26a for the first implementation described here) is carried out .
  • said step E26 is carried out after the partial deoxidation step E20 .
  • this etching solution may, for example, comprise a TMAH or a KOH solutio .
  • the etching solution 220 is a solution of TMAH diluted to 25 % and heated to a temperature of approximately 80°C.
  • the buried oxide layer 204 then acts as a stop layer for the e ching action of the solution 220.
  • T2 is, for example, in the range 3 to 4 hours, and is preferably 3h45.
  • the bonding oxide layer 206 at the wafer side 208 is the source of the formation of fragments of oxide that might contaminate the surface of the multilayer structure 211 during a chemical etching step. Eliminating a peripheral portion of this oxide layer 206 (i.e. the exposed
  • step E20 means that the oxide fragments that might be deposited on the exposed surface of the structure 211 during step E26 can be very significantly reduced.
  • the invention can advantageously be used to minimize the source of oxide fragments that might contaminate the exposed surface of the multilayer
  • the second chemical etching step E26 does not necessarily correspond to a step of chemically thinning the first wafer 208 , but may correspond to any technical step involving a chemical etch.
  • Such a step may, for example, be carried out with a solution of ⁇ or a solution of KOH and may, for example, be intended for the formation of one or more microcomponents (in the first wafer 208, for example).
  • no treatment is carried out on the multilayer structure 211 between the partial deoxidation step E20 and the chemical etching step E26a .
  • treatment means any technical step intended to modify the characteristics of said multilayer structure. Such a technical step may, for example, involve a chemical etch, the deposition of materials, doping, etc.
  • a preliminary chemical etching step E22 is carried out after step E20 for partially deoxidizing the bonding oxide layer 206.
  • the multilayer structure 211 is immersed in an etching solution for a time T3.
  • said etching solution has the same characteristics as those of the solution 220 described above: a solution of TMAH diluted to 25% and heated to a temperature of approximately 80°C is used.
  • the preliminary chemical etching step E22 can be used to eliminate the exposed side of the lower layer 201, i.e. the peripheral portion that is no longer protected by the subjacent bonding oxide layer 206
  • the etching time T3 is selected such that it is 20 min or less, and is preferably in the range 5 min to 20 min.
  • the residual upper layer 212 is altered little or not at all by the etching action of the TMAH solution.
  • the time T3 is relatively short ( ⁇ 20 min) .
  • the residual layer 212 is very thick compared with the oxide layer 206.
  • the etching action on the residual layer 212 is negligible during the etching step E22.
  • the residual layer 212 thus retains a thickness of approximately 65 ⁇ im at the end of s ep E2 .
  • step E24 for partially deoxidizing the buried oxide layer 204 is carried out by hydrofluoric acid etching. More precisely, this s ep E24 consists in immersing the multilayer structure 211 in an etching solution
  • the etching solution used has , for example, the same characteristics as those of the solution 222 used during the first HF etching step E20.
  • step E22 for preliminary chemical etching advantageously opens an attack surface on a peripheral portion of the buried oxide layer 204.
  • the step E24 for partial deoxidation thus means that the exposed side of the buried oxide layer 204 , i.e. the peripheral portion that is no longer protected by the subjacent lower layer 201 ( Figure 3H) , can be eliminated.
  • the concentration C H F4 is preferably 10% by weight or less .
  • the concentration C3 ⁇ 4F4 must be sufficiently moderate for the progress of deoxidation during step E24 to be precisely controlled and to avoid any unbending at the bonding interface of the two wafers 208 and 210.
  • the time T4 is defined as a function of the selected concentration C H F ⁇ T4 is in the range 200 to 600
  • T4 is preferably fixed at approximately 280 seconds .
  • step E24 for partially deoxidizing the buried oxide layer 204 the step E26 for chemical etching as described above (more specifically denoted E26b in this second
  • the step E26 in this example corresponds to a step of chemically thinning the first wafer 208. At the end of this chemical etching step, the residual upper layer 212 is eliminated completely
  • the step E20 carried out in the second implementation can advantageously eliminate the exposed portion of the bonding oxide layer 206 located at the periphery of the wafer. Elimination of this portion of the oxide layer 206 means that the fragments of oxide that might be deposited on the exposed surface of the multilayer structure 211 during the chemical etching step E26 can be significantly reduced.
  • the partial deoxidation step E24 carried out in this second implementation can also eliminate a peripheral portion of the buried oxide layer 204.
  • the Applicant has demonstrated that the exposed portion of this oxide layer 204 is also a source of oxide fragments when the
  • multilayer structure 211 undergoes chemical etching (such as, for example, during a chemical thinning step) .
  • This second implementation thus produces results that are even better than for the first implementation , since it can further reduce the quantity of oxide fragments that might contaminate the exposed surface of the multilayer
  • a rinsing step is generally carried out after the chemical etching step E26.
  • the treatment method of the invention is also advantageous in that its application parameters (in
  • step E20 and optionally steps E22 and E24 may in fact be integrated into a conventional method of manufacturing a multilayer structure, for exam le of the SOS type, before a chemical etching step E26.
  • the sapphire substrate 210 is advantageous in that it is capable of resisting successive chemical etches , optionally during steps E22 and E24 for the second implementation of the invention. It should also be noted that the sapphire subs trate 210 may contain di f ferent types of impurities in the form of traces ( itanium, iron, vanadium, etc.) in any concentrations.
  • the substrate 210 may be formed from a material other than sapphire, provided that it is
  • the substrate 210 may be formed from any material coated with a protective layer (formed from oxide or nitride, for example) that is sufficiently thick not to be completely eliminated at the end of the various etches carried out in the method of the invention.
  • the substrate 210 may, for example, be covered with an oxide layer with a thickness of the order of 2000 A.
  • this mechanical thinning step E13 causes large mechanical stresses on the multilayer structure 211 and in general results in enlargement of the ring that is not bonded or poorly bonded at the bonding interface between the two wafers 208 and 210.
  • step E13 before step E20 means that access of the hydrofluoric acid to the bonding interface between the two wafers 208 and 210 is optimized i order to maximize the elimination of potential sources of contamination .
  • the treatment method of the invention is applicable to all types of multilayer structure obtained by bonding, and more particularly to multilayer SOS structures with wafers that have chamfered sides (or edge roundings of any shape) and/or that cannot be heated to high

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Abstract

The invention provides a method of treating a multilayer structure (211), the multilayer structure (211) comprising a wafer (208) bonded to a substrate (210) at a bonding interface, a bonding oxide layer (206) being disposed between the wafer (208) and the substrate (210), the method comprising at least one step of chemically etching the wafer (208), the method further comprising, before the chemical etching step, a step of partially deoxidizing the bonding oxide layer (206) of the multilayer structure (211) by hydrofluoric acid chemical etching in order to eliminate a peripheral portion of the bonding oxide layer (206).

Description

Title of the invention
A METHOD OF TREATING A MULTILAYER STRUCTURE WITH HYDROFLUORIC ACID Background of the invention
The present invention relates to the field of producing multilayer semiconductor structures (also known as multilayer semiconductor wafers) produced by
transferring at least one layer onto a final substrate, Such a layer transfer is obtained by bonding, for example by direct wafer bonding, of a first wafer (or initial substrate) onto a second wafer (or final substrate) , the first wafer generally being thinned after bonding. The transferred layer may also comprise all or part of a component or a plurality of microcomponents .
More particularly, the present invention is
applicable to multilayer structures obtained by bonding and having a low surface energy (less than 1 J/m2 [Joule per square meter]) at the bonding interface, such as structures of the SOS (silicon on sapphire) type. The term "SOS" designates multilayer structures comprising a first silicon wafer transferred onto a crystalline sapphire substrate AI2O3) . SOS is a technique from the SOI (silicon on insulator) family. SOS technology is in particular used in radiofrequency applications because it performs well, especially as regards electrical
insulation and heat dissipation.
The invention addresses the problem of unwanted fragments of material that appear on the exposed surface of the transferred layer during the manufacture of a multilayer structure, for example of the SOS type. This phenomenon of contamination has been observed following a technical step involving chemically etching at least a portion of a multilayer SOS structure. This technical step may correspond, for example, to chemical etching carried out on the first wafer of a multilayer SOS
3 t-Cl_iC-1X XT€2 cLl_JlXT11*1Cj" c3. ti* 1X*-LX ULΏ-Cf £51€~ » More particularly, said problem of contamination has been observed when it has not been possible to completely stabilize the bonding interface between the two wafers of the multilayer SOS structure.
The technique frequently used during manufacture of multilayer structures for the purpose of cleaning the surface of a transferred layer after a chemical etching step consists in carrying out a step of rinsing (or cleaning) using a pressure jet . In general , a
pressurized jet of water (or any rinsing solution) is manually applied to the surface of the wafer to be cleaned.
However, the Applicant has established that the efficiency of that technique is limited, since it can be used to eliminate only part of the fragments present on the surface of the wafer to be cleaned. Further, that rinsing technique requires human intervention, which limits industrialization of the rinsing step.
Thus , there is currently a need for a method that can prevent such fragments of material from contaminating a multilayer structure, in particular of the SOS type, during its manufacture .
Object and summary of the invention
To this end, the present invention proposes a method of treating a multilayer structure, the multilayer structure comprising a wafer bonded to a substrate at a bonding interface , a bonding oxide layer being disposed between the wafer and the substrate, the method
comprising at least one step of chemically etching the wafer and being characterized in that it also comprises :
• before the chemical etching step, a step of partially deoxidizing the bonding oxide layer of the multilayer structure by hydrofluoric acid chemical etching in order to eliminate a peripheral portion of the bonding oxide layer . Advantageously, the method of the invention can be used to eliminate a peripheral portion of the bonding oxide layer of a multilayer structure, for example of the SOS type, from which portion fragments may be detached during a subsequent chemical etching step and thus contaminate the surface of the structure.
In particular, the invention can be used to minimize the source of the oxide fragments that might contaminate the exposed surface of a multilayer structure during a subsequent technical step carried out using chemical etching .
In particular, the method of the invention is applicable when the multilayer structure has a surface energy of less than 1 J/m2 at the bonding interface.
Further, the wafer may include microcomponents .
In this document, the term "microcomponents" means any devices or motifs resulting from technical steps carried out on the wafers of a multilayer structure. In particular, they may be active or passive components, simple contact points or interconnections.
In a particular implementation of the invention, the chemical etching step corresponds to a step of chemically thinning the wafer .
Further, when the thinned wafer is formed from silicon, the chemical etching step may be carried out with a solution of TMAH and/or a solution of KOH.
The treatment method of the invention may also comprise a step of mechanically thinning the wafer, the step of partially deoxidizing the bonding oxide layer being carried out after the mechanical thinning step.
The step of partially deoxidizing the bonding oxide layer may also comprise immersing at least a portion of the multilayer structure in a hydrofluoric acid solution, preferably in a concentration of 10% by weight or less for a period in the range 60 s [seconds] to 400 s.
The use of a 10% or less hydrofluoric acid solution means that the rate of etching of the exposed portion of the bonding oxide layer located at the periphery of the multilayer structure is controlled in a manner that is optimized.
The bonding oxide layer may be formed from a layer of silicon dioxide (SiO?) -
In a particular implementation of the invention, the substrate is formed from a material that can resist the chemical etching step, such as sapphire, or is coated with a layer of nitride or a layer of oxide that can resist the chemical etching step. Said oxide layer may, for example, be of the order of 200 A [angstroms] thick.
In accordance with a particular implementation, the wafer is a SOI type wafer or a wafer comprising a stack of layers comprising a buried oxide layer, the method comprising the following steps in succession, after the step of partially deoxidizing the bonding layer and before the step of chemically etching the wafer:
• a step of preliminary chemical etching in order to eliminate a peripheral portion of a layer of the wafer interposed between the bonding oxide layer and the buried oxide layer; and
• a step of partially deoxidizing the buried layer by hydrofluoric acid etching to eliminate a peripheral portion of the buried oxide layer.
The Applicant has demonstrated that the peripheral portion of the buried oxide layer is also a source of oxide fragments that might contaminate the surface of the multilayer structure during a subsequent chemical etching step. This implementation is advantageous insofar as it can eliminate said peripheral portion and thus minimize the source of oxide fragments that can be deposited on the 'wafer during a chemical thinning step, for example.
Furthermore , the preliminary chemical etching step may be carried out with a solution of TMAH or a solution of KOH, the duration of the preliminary chemical etching step preferably being 20 minutes or less. Further, the step of partially deoxidizing the buried layer may be carried out with an etching solution with a hydrofluoric acid concentration of 10% by weight or less , the deoxidation step being carried out for a period that is preferably in the range 200 s to 600 s .
The invention also provides a method of
manufacturing a multilayer structure, comprising the following steps in succession :
• forming a bonding oxide layer on at least one wafer or substrate;
• bonding the wafer onto the substrate by means of the bonding oxide layer in order to form the multilayer structure;
• annealing the multilayer structure;
* mechanically thinning the wafer; and
• chemically thinning the wafer;
said method being characterized in that it further comprises eliminating a peripheral portion of the bonding oxide layer in accordance with a treatment method
according to one of the implementations mentioned above.
In a particular implementation, the wafer is a SOI type wa er or a wafer comprising a stack of layers comprising a buried oxide layer, the manufacturing method being characterized in that it comprises eliminating a peripheral portion of a layer of the wafer interposed between the bonding oxide layer and the buried oxide layer and a peripheral portion of the buried oxide layer .
Brief description of the drawings
Other characteristics and advantages of the present invention become apparent from the following description made with reference to the accompanying drawings that illustrate an example and is not in any way limiting in scope . In the figures :
» Figures 1A to ID are sectional views
diagrammatically representing a known method of producing a SOS type multilayer structure; • Figure 2 represents, in the form of a flowchart, the principal steps in the method illustrated in
Figures 1A to ID;
• Figures 3A to 31 diagrammatically represent a treatment method and a method of manufacture in
accordance with a first implementation (E20 , E26a) and a second implementation (E20, E22 , E24 , E26b) of the invention; and
art , the principal steps in the method of the invention in accordance with first and second implementations
illustrated in Figures 3A to 31.
Detailed description of an implementation of the
invention
The present invention is of general application to partially deoxidizing a multilayer structure in order to minimize the source of the fragments of material that might appear on the exposed surface of the structure during the course of its fabrication.
Particularly, but not exclusively, the invention is of application to SOS type multilayer structures. A SOS multilayer structure is produced by bonding a first wafer to a second wafer, or substrate, formed from sapphire and constituting the support for the first wafer, a bonding oxide layer being present between the two wafers .
The wafers composing a multilayer structure are generally in the form of wafers with a generally circular contour that may have various diameters, in particular diameters of 100 mm [millimeter] , 150 um, 200 mm, or 300 mm. However, the wafers may have any shape, such as a wafer with a rectangular shape, for example .
These wafers preferably have a chamfered side, namely a side comprising an upper chamfer and a lower chamfer . Said chamfers generally have a rounded shape . However, the wafers may have chamfers or edge roundings with different shapes, such as a beveled shape. The role of such chamfers is to facilitate
manipulation of the wafers and prevent breakage that could occur if these sides protruded out; such breakages would be sources of contamination by particles at the wafer surfaces .
An example of a known method of manufacturing a SOS multilayer structure is described here with reference to Figures 1A to ID and 2.
As can be seen in Figures 1A to ID, a SOS multilayer structure 111 is formed by assembling a first wafer 108 with a second wafer (or substrate) 110 formed from
In this example, the first wafer 108 corresponds to a SOI structure comprising a buried oxide layer 104 interposed between two layers of silicon (i.e. the upper layer 101 and the lower layer 102).
The first and second wafers 108 and 110 in this example have the same diameter. However, they could have different diameters.
In the example described here, the whole surface of the first wafer 108 is oxidized before bonding to the second wafer 110. This oxidation is carried out by means of a heat treatment in an oxidizing medium so that an oxide layer 106 (termed a bonding oxide layer) can be formed over the whole surface of the first wafer 108 before bonding to the second wafer 110.
In the present example, the oxide layer 106 is a layer of S1O2. A bonding oxide layer 106 thus exists at the bonding interface between the first wafer 108 and the substrate 110 and permits better bonding therebetween .
In a first alternative, a bonding oxide layer may be deposited on the face to be assembled (termed the bonding face) of the first wafer 108 before bonding to the second wafer 110. In another alternative, before bonding the two wafers 108 and 110, it is possible to form a bonding oxide layer on the bonding face of the substrate 110 or alternatively to form a bonding oxide layer on the bonding face of each of the two wafers 108 and 110.
The above alternatives mean that, as in the example of Figure IB, a bonding oxide layer can be interposed between the two wafers 108 and 110 before bonding.
Further, the first wafer 108 has a chamfered side, namely a side comprising an upper chamfer 107a and a lower chamfer 107b. In the same manner, the second wafer 110 has a side comprising an upper chamfer 109a and a lower chamfer 109b.
In the example described here, the first wafer 108 and the substrate 110 are assembled using the direct wafer bonding technique known to the skilled person.
Other bonding techniques may be used, however, such as anodic bonding, metallic bonding or bonding with adhesive bonding.
It should be recalled that the principle of bonding by direct wafer bonding is based on bringing two surfaces into direct contact, i.e. without using a specific material (adhesive, wax, solder, etc.). Such an
operation requires that the surfaces to be bonded be sufficiently smooth, free of particles or of
contamination and that they be brought sufficiently close together to allow contact to be initiated, typically to a distance of less than a few nanometers. The attractive forces between the two surfaces are then large enough to bring about direct wafer bonding (bonding induced by the set of attractive forces (van der Waals forces) of electronic interaction between atoms or molecules on the two surfaces to be bonded) .
It should be understood that the first wafer 108 may include microcomponents (not shown in the figures ) at its face for bonding with the second wafer 110 , especially for 3D-integration, which requires transferring one or more layers of microcomponents onto a final support , or for circuit transfer such as, for example, in the
manufacture of back-lit imaging devices . Once bonding step Ell has been carried out, the multilayer structure 111 undergoes a moderate reinforcing anneal of the bonding interface ( for example 100 °C to 400 °C for 2 hours), which is intended to strengthen the bond between the first wafer 108 and the second wafer 110 (step E12 ) ,
After this anneal, thinning of the first wafer 108 is generally carried out in order to form a transferred layer with a predetermined thickness (for example
approximately 60 μπι [micrometer] ) on the 'wafer support 110. This thinning operation generally includes a chemical etching step.
However, the Applicant has observed the appearance of unwanted fragments of materials on the exposed surface of the first wafer 108 following a thinning step
involving a chemical phase.
An in-depth study has brought the mechanism for formation of these fragments to light. The formation mechanism is described in more detail with reference to Figures 1C and ID, which illustrate an example of the step of thinning the first wafer 108.
The thinning step in this example comprises two distinct sub-steps. The first wafer 108 is initially mechanically thinned using a grinder or any other tool that can mechanically wear away the material of the first wafer 108 (sub-step E13 ) . This first thinning sub-step can eliminate the ma or portion of the upper la er 102 so as to retain only a residual layer 112 (Figure 1C ) .
Next , a second thinning sub-step is carried out , corresponding to chemically etching the residual layer 112 (sub-step E14). This second sub-step consists in placing the multilayer structure 111 in a bath comprising an etching solution 120 (Figure ID) . In the exam le described here , the etching solution used is a solution of TMAH that can etch the silicon of the first wafer 108. Other chemical attack solutions , however , may be
envisaged; they are in particular selected as a function of the composition of the first wafer to be thinned. For silicon wafers that are to be thinned, a solution of ΤΜΆΗ or a solution of KOH may be used, for example.
The buried oxide layer 104 interposed between the layers 101 and 102 of the first wafer 108 act as a stop layer during chemical etching that is then interrupted at the oxide layer 104. The chemical etching can then ΐ211mi.Tl Q.t€2 11*1€S T€5S 3L3.TJ.ci1
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However, the Applicant has observed that at the end of the chemical etching step, fragments of material 118 were present on the exposed surface of the first wafer 108. These fragments 118 typically have dimensions of more than 2 um.
A study has shown that these fragments of material are debris originating from the sides of the first wafer.
More precisely, because of the presence of chamfered sides on the first and second wafers, the bonding force in the vicinity of the periphery of the two wafers is limited. Despite step E12 for moderately annealing the bonding interface to strengthen it, an annular portion at the periphery of the first wafer 108 located in the vicinity of the lower chamfer 107b is bonded poorly to the second wafer 110 (bonding may even be completely absent ) .
The Applicant has observed that during the chemical etching (E14 ) of the thinning step, the etching solution 120 has a tendency to etch the sides of the first wafer 108 and the bonding oxide layer 106 laterally . This lateral etching action causes uncontrolled fracturing of the bonding oxide layer 106, more particularly at the peripheral portion of the oxide layer 106 that is exposed to attack by the etching solution 120 ,
This fracturing phenomenon thus causes the formation of debris or oxide fragments 118 (here of Si02)
originating at least in part from this peripheral portion of the bonding oxide layer 106. These oxide fragments will then be deposited in part on the exposed surface of the first thinned wafer 108 (Figure ID) during the chemical etching of E14,
It should be noted that under the action of the lateral etching by the etching solution 120» the oxide, silicon and/or circuit fragments originating from the sides of the first wafer 108 might also pollute the exposed surface of the wafer.
Thus, the Applicant has developed a treatment method of eliminating a peripheral portion of the bonding oxide layer 106 of the multilayer structure 111.
An example of carrying out the treatment method of the invention, and more generally an example of carrying out the manufacturing method of the invention is
described below with reference to Figures 3A to 31 and 4.
Figures 3A and 3B show a multilayer structure 211 identical to the structure 111 shown in Figure 1C, namely a multilayer SOS structure obtained at the end of steps of bonding (Ell), annealing (E12) and mechanical thinning (E13) as described above.
Figure 3B shows, in more detail, the structure 211 illustrated in Figure 3A at the peripheral side of the wafers 208 and 210.
More precisely, the multilayer structure 211 under consideration is constituted by a first wafer 208 bonded to a second wafer (or substrate) 210 formed from
sapphire, a bonding oxide layer 206 having been formed (by oxidation) over the whole surface of the first wafer 208 before bonding to the second wafer 210. In this example, the first wafer 208 is a SOI structure: it is constituted by a buried oxide layer 204 (identical to the layer 104) interposed between two layers of silicon, namely an upper layer 212 that has been mechanically thinned, termed the residual layer (identical to the layer 112), and a lower layer 201 (identical to the layer 101) .
In the example considered here, the thickness of the bonding oxide layer 206 at the bonding interface is approximately 500 A. In addition, the lower layer 201 and residual layer 212 respectively have thicknesses of 750 A and 65 um. The buried oxide layer 204 in this example has a thickness of approximately 2000 A.
However, it should be noted that the second wafer
210 is not necessarily formed from sapphire.
Alternatively, the wafer 210 may, for example, be formed from silicon. As indicated above, the invention is more generally applicable to multilayer structures obtained by bonding, and in particular to those with a low surface energy {less than 1 J/m2) at their bonding interface.
Further, as indicated above with reference to
Figures 1A and IB, other implementations may be carried out to provide a bonding oxide layer between the wafers 208 and 210. It is thus possible to form a bonding oxide layer on the bonding surface of the first wafer 208 and/or on the bonding surface of the second wafer 210, before bonding the two wafers. Thus, when the substrate 210 is formed from silicon for example, it is possible to oxidize the whole surface of the substrate before bonding with the first wafer 208, taking care that the oxide layer formed is sufficiently thick to resist etches carried out in the treatment process of the invention.
More precisely, once the mechanical thinning step E13 has been carried out, a step E20 of partially
deoxidizing the bonding oxide layer 206 is carried out on the multilayer structure 211, During this step E20 , the multilayer structure 211 is placed in an etching solution 222 comprising hydrofluoric acid (HF) (Figure 3C) .
When the multilayer structure 211 is immersed in the etching solution 222 , the hydrofluoric acid initially attacks the bonding oxide layer 206 at its exposed portion in the vicinity of the periphery of the wafers . During this step E20 , the etching solution 222 is
introduced between the wafers 208 and 211 at the ring of the bonding interface, i.e. at the chamfered sides of the two wafers that have a poor bonding interface (or total absence of bonding) . Step E20 for partial deoxidation can thus eliminate the peripheral portion of the bonding o ide layer 206 from which fragments may become detached during subsequent chemical etching and might contaminate the surface of the structure (Figure 3D) .
In this example, the etching solution 222 has a concentration of HF by weight (denoted CHFI ) of 10% and step E20 for partially deoxidizing the bonding oxide layer 206 consists in immersing the multilayer structure 211 in said etching solution 222 for a time Tl preferably in the range 60 s to 400 s. In this example, Tl is fixed at 70 seconds .
It should be noted that other concentrations CHFI of HF can be envisaged, however . The concentration CHFI is preferably 10% (by weight) or less . It is in fact necessary for the concentration of HF to be moderate so that etching is relatively slow and so that :
• the progress of deoxidation during step E20 can be precisely controlled; and
· unwanted lateral etching can be limited.
Further, an excessive concentration, CHPI, may render the HF etching procedure difficult to control and may result in unwanted unbending.
The time Tl during which the multilayer structure 211 is exposed to the action of etching by the solution 222 is then selected as a function of the selected concentration CHFI , in order to control the quantity of bonding oxide layer 206 that is eliminated at the
periphery. In fact , if the multilayer structure
undergoes a HF attack for an excessive time Tl, the hydrofluoric acid infiltrates the bonding interface between the wafers 208 and 210 too deeply, thus degrading the quality of the bond between said two wafers .
In accordance with a first implementation of the invention, after the partial deoxidation step E20 , a step E26 for chemical etching (more specifically E26a for the first implementation described here) is carried out . In the example described here, said step E26
corresponds to a chemical thinning step that is intended to i-21 ~Lmin.cit £ ttc» x Gsiciu.S 1 1¾^*i2i 2 -L 2 *
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identical to the etching solution 120 described with reference to Figure ID (Figure 3E) . As indicated above, when silicon wafers are to be thinned, this etching solution may, for example, comprise a TMAH or a KOH solutio .
In the example described here, the etching solution 220 is a solution of TMAH diluted to 25 % and heated to a temperature of approximately 80°C.
The buried oxide layer 204 then acts as a stop layer for the e ching action of the solution 220. The time T2
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212 I S eliminated at the end of step E26 (Figure 3F) . T2 is, for example, in the range 3 to 4 hours, and is preferably 3h45.
As explained above, the Applicant has observed that the bonding oxide layer 206 at the wafer side 208 is the source of the formation of fragments of oxide that might contaminate the surface of the multilayer structure 211 during a chemical etching step. Eliminating a peripheral portion of this oxide layer 206 (i.e. the exposed
portion) during the HF etching step E20 means that the oxide fragments that might be deposited on the exposed surface of the structure 211 during step E26 can be very significantly reduced.
In addition, the invention can advantageously be used to minimize the source of oxide fragments that might contaminate the exposed surface of the multilayer
structure 211 during a subsequent etching step such as the step E26 , for example,
However, it should be understood that the second chemical etching step E26 does not necessarily correspond to a step of chemically thinning the first wafer 208 , but may correspond to any technical step involving a chemical etch. Such a step may, for example, be carried out with a solution of ΤΜΆΗ or a solution of KOH and may, for example, be intended for the formation of one or more microcomponents (in the first wafer 208, for example).
In accordance with a particular implementation of the first implementation described above, no treatment is carried out on the multilayer structure 211 between the partial deoxidation step E20 and the chemical etching step E26a . The term "treatment" as used here means any technical step intended to modify the characteristics of said multilayer structure. Such a technical step may, for example, involve a chemical etch, the deposition of materials, doping, etc. In accordance with a second implementation of the invention, after step E20 for partially deoxidizing the bonding oxide layer 206, a preliminary chemical etching step E22 is carried out.
During said step E22, the multilayer structure 211 is immersed in an etching solution for a time T3. In the present example, said etching solution has the same characteristics as those of the solution 220 described above: a solution of TMAH diluted to 25% and heated to a temperature of approximately 80°C is used.
The preliminary chemical etching step E22 can be used to eliminate the exposed side of the lower layer 201, i.e. the peripheral portion that is no longer protected by the subjacent bonding oxide layer 206
(Figure 3G) . Elimination of this annular portion of the lower layer 201 is possible since the step E20 has already opened a peripheral attack surface on the lower layer 201.
The etching time T3 is selected such that it is 20 min or less, and is preferably in the range 5 min to 20 min.
It should be noted that during said step E22 for preliminary chemical etching, the residual upper layer 212 is altered little or not at all by the etching action of the TMAH solution. The time T3 is relatively short (< 20 min) . Furthermore , the residual layer 212 is very thick compared with the oxide layer 206. As a result , it may be assumed that the etching action on the residual layer 212 is negligible during the etching step E22. In the example considered here, the residual layer 212 thus retains a thickness of approximately 65 \im at the end of s ep E2 .
In this same second implementation, after step E22 , a step E24 for partially deoxidizing the buried oxide layer 204 is carried out by hydrofluoric acid etching. More precisely, this s ep E24 consists in immersing the multilayer structure 211 in an etching solution
containing hydrofluoric acid at a concentration of CHF4 (defined by weight) for a time T4. The etching solution used has , for example, the same characteristics as those of the solution 222 used during the first HF etching step E20.
It should be noted that the preceding step E22 for preliminary chemical etching advantageously opens an attack surface on a peripheral portion of the buried oxide layer 204. The step E24 for partial deoxidation thus means that the exposed side of the buried oxide layer 204 , i.e. the peripheral portion that is no longer protected by the subjacent lower layer 201 (Figure 3H) , can be eliminated.
The concentration CHF4 is preferably 10% by weight or less . In the same manner as for CHFI during step E20, the concentration C¾F4 must be sufficiently moderate for the progress of deoxidation during step E24 to be precisely controlled and to avoid any unbending at the bonding interface of the two wafers 208 and 210. Furthermore, the time T4 is defined as a function of the selected concentration CHF · T4 is in the range 200 to 600
seconds , for example. When CKF4 - 10% (by weight) , T4 is preferably fixed at approximately 280 seconds . In accordance with this second implementation, after step E24 for partially deoxidizing the buried oxide layer 204, the step E26 for chemical etching as described above (more specifically denoted E26b in this second
implementation) is carried out.
As explained above, the step E26 in this example corresponds to a step of chemically thinning the first wafer 208. At the end of this chemical etching step, the residual upper layer 212 is eliminated completely
(Figure 31) .
In the same manner as for the first implementation, the step E20 carried out in the second implementation can advantageously eliminate the exposed portion of the bonding oxide layer 206 located at the periphery of the wafer. Elimination of this portion of the oxide layer 206 means that the fragments of oxide that might be deposited on the exposed surface of the multilayer structure 211 during the chemical etching step E26 can be significantly reduced.
The partial deoxidation step E24 carried out in this second implementation can also eliminate a peripheral portion of the buried oxide layer 204. The Applicant has demonstrated that the exposed portion of this oxide layer 204 is also a source of oxide fragments when the
multilayer structure 211 undergoes chemical etching (such as, for example, during a chemical thinning step) . This second implementation thus produces results that are even better than for the first implementation , since it can further reduce the quantity of oxide fragments that might contaminate the exposed surface of the multilayer
structure 211 during a chemical etching step.
It should be noted that in general, a rinsing step is generally carried out after the chemical etching step E26.
The treatment method of the invention is also advantageous in that its application parameters (in
particular CHFI , Tl and T2 , and optionally T3 , T4 and 0Η?4 for the second implementation) can be controlled and are reproducible. This technique can thus be optimized and automated for industrial purposes. The step E20 and optionally steps E22 and E24 may in fact be integrated into a conventional method of manufacturing a multilayer structure, for exam le of the SOS type, before a chemical etching step E26.
The sapphire substrate 210 is advantageous in that it is capable of resisting successive chemical etches , optionally during steps E22 and E24 for the second implementation of the invention. It should also be noted that the sapphire subs trate 210 may contain di f ferent types of impurities in the form of traces ( itanium, iron, vanadium, etc.) in any concentrations.
However, the substrate 210 may be formed from a material other than sapphire, provided that it is
resistant to the chemical attacks mentioned above.
Alternatively, the substrate 210 may be formed from any material coated with a protective layer (formed from oxide or nitride, for example) that is sufficiently thick not to be completely eliminated at the end of the various etches carried out in the method of the invention. The substrate 210 may, for example, be covered with an oxide layer with a thickness of the order of 2000 A.
Furthermore, it should be noted that while it is not obligatory, it is preferable to carry out the mechanical thinning step E13 before the step E20 for partially deoxidizing the bonding oxide layer 206. The Applicant has observed that this mechanical thinning step E13 causes large mechanical stresses on the multilayer structure 211 and in general results in enlargement of the ring that is not bonded or poorly bonded at the bonding interface between the two wafers 208 and 210.
Carrying out step E13 before step E20 (regardless of the implementation) means that access of the hydrofluoric acid to the bonding interface between the two wafers 208 and 210 is optimized i order to maximize the elimination of potential sources of contamination .
The treatment method of the invention is applicable to all types of multilayer structure obtained by bonding, and more particularly to multilayer SOS structures with wafers that have chamfered sides (or edge roundings of any shape) and/or that cannot be heated to high
temperatures to stabilize the bonding interface properly .

Claims

1. A method of treating a multilayer structure (211), said multilayer structure comprising a wafer (208) bonded to a substrate (210) at a bonding interface, a bonding oxide layer (206 } being disposed between the wafer and the substrate, the method comprising at least one step (E26) for chemically etching said wafer and being
characterized in that it also comprises :
before the chemical etching step, a step (E20) for partially deoxidizing the bonding oxide layer of the multilayer structure by hydrofluoric acid chemical etching in order to eliminate a peripheral portion of said bonding oxide layer ,
2. A method according to claim 1, wherein the multilayer structure has a surface energy of less than 1 J/m2 at the bonding interface .
3. A method according to claim 2 or claim 3 , wherein said wafer comprises microcomponents .
4. A method according to any one of claims 1 to 3 , wherein the chemical etching step (E26 ) corresponds to a step of chemically thinning said wafer .
5. A method according to any one of claims 1 to 4 , wherein the chemical etching step is carried out using a solution of TMAH or a solution of KOH.
6. A method according to any one of claims 1 to 5 , further comprising a step (E13 ) for mechanically thinning said wafer, the step of partially deoxidizing the bonding oxide layer being carried out after said mechanical thinning step .
7. A method according to any one of claims 1 to 6 , wherein the step of partially deoxidizing the bonding oxide layer comprises immersing at least a portion of the multilayer structure in a hydrofluoric acid solution (222), in a concentration of 10% by weight or less for a period in the range 60 s to 400 s.
8. A method according to any one of claims 1 to 7 , wherein said bonding oxide layer is a layer of silicon dioxide (Si02) .
9. A method according to any one of claims 1 to 8, wherein the substrate is capable of resisting a chemical etching step or is coated with a layer of nitride or a layer of oxide capable of resisting the chemical etching s e .
10, A method according to any one of claims 1 to 9 , wherein said wafer is a SOI type wafer or a wafer
comprising a stack of layers comprising a buried oxide layer, said method comprising the following steps in succession, after the step of partially deoxidizing the bonding layer and before the step of chemically etching the wafer:
• a step (E22 ) for preliminary chemical etching in order to eliminate a peripheral portion of a layer (201) of said wafer interposed between the bonding oxide layer (206) and said buried oxide layer (204); and
• a step (E24 ) for partially deoxidizing the buried layer by hydrofluoric acid etching to eliminate a
peripheral portion of said buried oxide layer .
11. A method according to claim 10 , wherein the
preliminary chemical etching step (E22 ) is carried out with a solution of TMAH or a solution of KOH, the
duration of said preliminary chemical etching step being 20 minutes or less .
12. A method according to claim 10 or claim 11, wherein the step (E24 ) for partially deoxidizing the buried layer is carried out with an etching solution having a
hydrofluoric acid concentration of 10% by weight or less, said deoxidation step being carried out for a period in the range 200 s to 600 s.
13. A method of manufacturing a multilayer structure (211) , comprising the following steps in succession:
· forming a bonding oxide layer (206) on at least one wafer (208) or substrate (210);
• bonding (Ell) the wafer onto said substrate by means of the bonding oxide layer in order to form said multilayer structure;
· annealing (E12 ) said multilayer structure;
• mechanically thinning (E13 ) the wafer; and
• chemically thinning (E14) the wafer;
said method being characterized in that it further comprises eliminating a peripheral portion of said bonding oxide layer in accordance with the treatment method defined in any one of claims 1 to 12.
14. A method according to claim 13 , wherein the wafer is a SOI type wafer or a wafer comprising a stack of layers comprising a buried oxide layer, characterized in that it comprises eliminating a peripheral portion of a layer (201 ) of the wafer interposed between the bonding oxide layer (206) and the buried oxide layer (204) and a peripheral portion of said buried oxide layer (204 ) .
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FR1002734A FR2962141A1 (en) 2010-06-30 2010-06-30 METHOD FOR DEOXIDIZING A MULTILAYER STRUCTURE WITH FLUORHYDRIC ACID
FR1057456A FR2962258B1 (en) 2010-06-30 2010-09-17 PROCESS FOR TREATING A MULTILAYER STRUCTURE WITH FLUORHYDRIC ACID
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