WO2012000708A1

WO2012000708A1 - Circuit arrangement for a digital input

Info

Publication number: WO2012000708A1
Application number: PCT/EP2011/057512
Authority: WO
Inventors: Harald Karl; Rainer Viertler
Original assignee: Siemens Aktiengesellschaft
Priority date: 2010-06-29
Filing date: 2011-05-10
Publication date: 2012-01-05
Also published as: DE102010030656A1

Abstract

The invention relates to a circuit arrangement for a digital input of an electronic device. The circuit arrangement comprises a rectifier for rectifying the current flow, a self-conducting field effect transistor, a blocking member for blocking the current flow below a circuit threshold of an input voltage (U), and a separator for galvanically separating the digital input from at least one further component of the electronic device, said component being coupled to the digital input.

Description

description

Circuit arrangement for a digital input The invention relates to a circuit arrangement for a digital input of an electronic device.

Digital inputs in automation devices in industry or power engineering are operated with different nominal voltages and alternating and direct voltages, which are typically in the range between 24 V DC and 230 V AC. They are also often subject to high demands on their electromagnetic compatibility and their relevant immunity to interference.

US 4,275,307 A discloses an input circuit for a digital system having a rectifier, a dynamic current limiting circuit, a plurality of Zener diodes, and a light emitting element.

From JP 6-177736 A, DE 34 19 227 AI and US 5 909 660 A input circuits are known, each having at least one self-conducting MOSFET (= metal-oxide-semiconductor field effect ^¬ transistor) to limit the current and a series-switched to Having light-emitting element for galvanic isolation of ^¬ the input circuit.

US Pat. Nos. 5,672,919 and DE 10 2007 025 243 B3 disclose digital input circuits which each contain a rectifier, a separating element for the galvanic isolation of the input circuit, a blocking element for the voltage-dependent blocking of the current flow and a self-conducting field-effect transistor for limiting the current. Further input circuits with optocouplers for their galvanic isolation are known from US 5 539 352 A, JP 7-46111 A, JP 2-135819 A, US 4 197 471 A and GB 1 403 110 A. It is an object of the invention to provide an improved formwork ^¬ processing arrangement for a digital input of an electronic device, which is particularly suitable for a wide input voltage range.

The object is achieved by the features of claim 1. An ^¬ .

Advantageous embodiments of the invention are the subject of the dependent claims.

The inventive circuit arrangement for a digital ^¬ input of an electronic device comprises at least one rectifier for rectifying a current flow through the circuit arrangement, a downstream rectifier self-conducting field-effect transistor is a downstream of the self-conducting field-effect transistor blocking member for blocking the current flow below a switching threshold of a one ^¬ output voltage, and the Blocking member downstream isolator for galvanic isolation of the digital input of we ^¬ least one coupled to him another component of the electronic device.

The most essential component of the circuit arrangement according to the invention is the self-conducting field effect transistor. Such transistors can be obtained with very high blocking voltages and thus enable a regulation of the current flow through the circuit arrangement in a wide input voltage range, which can cover in particular the entire range between 24 V DC and 230 V AC. This advantageously enables the construction of a digital input for such a wide input voltage range, for otherwise various conventional digital inputs for each ^¬ parts of this Eingangsspannungbe- would have to be rich provided.

The other components of the circuit advantageously allow rectification of the current flow through the Circuitry for their protection against harmful input voltages wrong polarity and as polarity reversal in DC operation of the circuit, the realization of a switching threshold of the circuit as a function of the input signal strength, and the galvanic isolation of the digital input coupled with him further compo ^¬ len of the electronic device.

The rectifier is preferably a semiconductor diode or a bridge rectifier.

In this case, a bridge rectifier by its full-wave rectification of the electric current allows a faster response of the digital input to AC input voltages than the semiconductor diode, and is therefore preferably for appli ^¬ tions provided in which such a rapid response is advantageous. Otherwise, the use of a semi-conductor diode ^¬ is preferred as the rectifier, since it is less expensive realized sierbar over the use of a bridge rectifier and reduces the total power loss of the digital input. The bridge rectifier causes a current flow both at a positive and a negative input voltage and thus at an applied AC input voltage for both half-waves of the input voltage.

In one embodiment of the self-conducting field-effect transistor is a depletion metal oxide semiconductor field effect transistor ^¬. Preferably have a control terminal and a source terminal of the self-conducting metal oxide semiconductor Feldef ^¬ fekttransistors a current control resistance verbun ^¬. The current control resistor ensures when current flows for a voltage at the control terminal of the field effect transistor, which adjusts the current according to the characteristic of the Feldef ^¬ fekttransistors. The field effect transistor acts as a dynamic current source of the Schaltungsanord ^¬ tion.

In an alternative embodiment, the self-conducting field effect transistor is a self-conducting junction field effect transistor.

The blocking member is preferably ausgebil ^¬ det as a Zener diode.

This advantageously enables a simple and cost-effective implementation of a switching threshold of the digital input.

The isolator is preferably designed as an optocoupler.

This advantageously enables reliable electrical isolation of the digital input from the components of the electronic device coupled to it.

An embodiment of the circuit arrangement according to the invention provides at least one protective element for protection against input interference voltages. As a result, requirements for immunity to interference of the digital input can advantageously be met.

In this case, a protective element is preferably a suppressor diode or a varistor for protecting against input voltages exceeding a protection threshold.

As a result, the circuit arrangement and especially the field effect transistor contained in it can be protected against harmful overvoltages. This is particularly advantageous because field effect transistors can easily be destroyed by overvoltages. Alternatively or additionally, the circuit arrangement can have at least one interference suppression capacitor as a protective element against input voltages whose frequency exceeds a protective frequency.

As a result, the circuit arrangement can be advantageously protected against harmful high-frequency voltages.

A further embodiment of the circuit arrangement provides for a first bypass capacitor electrically connected in parallel with the current control ^resistor .

This embodiment is particularly advantageous if the circuit arrangement is preceded by a relay. With such a relay, over time, the relay contacts may be oxidized, thereby affecting the reliability of the overall circuit consisting of the relay and the circuitry. Through the first bypass capacitor of Stromsteue- is briefly approximately resistance at least partially bypassed, thereby setting a higher current flow, which advantageously allows for Rei ^¬ nigung of the relay contacts after the switching of the relay.

Another embodiment of the circuit arrangement provides for the current control resistor electrically geschal ^¬ ended bypass optocoupler before.

This allows the electric current through the circuit arrangement ^¬ each case only for a certain time interval to allow flie- SEN and thereby reduce their total power dissipation advantageously, said current circuits are brought about by the Überbrückungsoptokoppler.

A further embodiment of the circuit arrangement provides a second bypass capacitor electrically connected in parallel with the isolator and / or a third bypass capacitor. In this case, the third bypass capacitor is electrically parallel to a self-conducting Field effect transistor, the blocking member and the separator ent ^¬ held part of the circuit connected.

By the second or third bypass capacitor transient spikes (known as spikes), steep rising edges and half-waves of input voltages ^¬ kön- NEN advantageously be smoothed.

Further advantages, features and details of the invention are described below with reference to embodiments with reference to drawings. Showing:

1 shows a first circuit arrangement for a digital input of an electronic device according to the prior art,

2 shows a second circuit arrangement for a digital input of an electronic device according to the prior art, FIG 3 shows a first embodiment of a erfindungsge ^¬ MAESSEN circuit arrangement for a digital input of an electronic device,

4 shows a second embodiment of a erfindungsge ^¬ MAESSEN circuit arrangement for a digital input of an electronic device,

5 shows a third embodiment of a erfindungsge ^¬ MAESSEN circuit arrangement for a digital input of an electronic device,

6 shows a fourth exemplary embodiment of a circuit arrangement according to the invention for a digital input of an electronic device,

7 shows a fifth embodiment of a erfindungsge ^¬ MAESSEN circuit arrangement for a digital input of an electronic device, and

8 shows a sixth embodiment of a fiction, ^¬ contemporary circuit arrangement for a digital input of an electronic device. Corresponding parts are provided in all figures with the same reference numerals.

FIG. 1 shows a first conventional circuit arrangement for a digital input of an electronic device, for example an automation device used in industry or energy technology. The circuit arrangement comprises a semiconductor diode D, a of the semiconductor diode D downstream Zener diode V _z, a Zener diode _Vz downstream resistor R _v and a series resistor R _v downstream optocoupler 0 _T with a light emitting diode L as an optical transmitter and a photo-transistor PT as an optical Receiver.

The semiconductor diode D is used to rectify a current flow through the circuit arrangement, the zener diode V _z de ^¬ defines a switching threshold of the digital input, the Vorwi ^¬ resistance R _v limits the electrical current flow through the light emitting diode L of the optocoupler 0 _T , and the optocoupler 0 _T. separating the digital input electrically isolated from at least one coupled thereto further component of the electronic device, for example a microprocessor, which processes input signals received via the digital input, wherein the further device with the phototransistor PT is we ^¬ nigstens ver ^¬ prevented.

Such a circuit arrangement has the disadvantage that it can be used only for a relatively small range of input voltages U applied to the digital input. Namely, by the series resistor R _v , the current flowing through the light emitting diode L increases by a factor of 10 when the input voltage U increases 10 times, for example, and the total power loss of the digital input in this example increases by a factor of 100. FIG second conventional circuit arrangement for a digital input of an electronic device. In this case, a current-limiting diode CLD (current limiting diode) replaces the series resistor R _{v of} the circuit arrangement shown in FIG. Order. The constant-current diode CLD stabilizes the electrical current ^¬ rule from a certain stabilization value of the input voltage U by keeping the current at higher input voltages U almost constant. Compared with the circuit arrangement shown in FIG. 1, this has the advantage that, starting from the stabilization value, the total power loss of the circuit arrangement only increases linearly with the input voltage U and no longer quadratically as in the case of the circuit arrangement illustrated in FIG. The disadvantage, however, is that commercially available current-regulating diodes CLD tolerate only a maximum supply voltage of about 100 V and thus are not suitable for a larger input voltage range. Figure 3 shows a first embodiment of a circuit arrangement according OF INVENTION ^¬ dung for a digital input of an electronic device. It differs from the conventional circuit arrangements shown in Figures 1 and 2 by a self-conductive metal oxide semiconductor field effect transistor M, hereinafter referred to as MOSFET M, which is arranged between the semiconductor diode D and the zener diode V _z ^¬ and the series resistor R _v the Darge in Figure 1 ^¬ presented first conventional circuit arrangement or the constant-current diode replaced CLD the embodiment shown in Figure 2 the second conventional circuit arrangement. The MOSFET M has a control terminal G _M (gate), a source terminal S _M (source), a drain terminal D _M (drain) and a substrate terminal B _M (bulk) and is formed as an n-channel metal oxide semiconductor field effect transistor , Here, the drain port D _M directly to the semiconductor diode D is verbun ^¬, the source terminal S _M is connected to the substrate terminal B _M, and the control terminal G _M is connected via a current ^¬ control resistor R _B to the source terminal S _M and di ^¬ rectly with connected to the zener diode V _z .

The current control resistor R _B provides at current flow for ei ^¬ ne negative voltage at the control terminal G _{M of} the MOSFET M and thereby adjusts the current corresponding to the characteristic of MOSFET M on. The MOSFET M thus acts as a dynamic current source of the circuit arrangement. The Zener diode _Vz be ^¬ acts as in the conventional circuit arrangements according to Figures 1 and 2 to set a switching threshold of the circuit arrangement, from which it is SENS ^¬ Lich for input signals. The semiconductor diode D protects the electronic circuit from harmful input voltages U.

Compared to the circuit arrangements illustrated in FIGS. 1 and 2, the circuit arrangement shown in FIG. 3 has the advantage that metal oxide semiconductor field effect transistors with relatively high blocking voltages can be obtained and a wide input voltage range can be covered by a circuit arrangement according to FIG. 3, in particular between a DC input voltage U of 24 V up to an AC input voltage U of 230 V.

As a MOSFET M, for example, an under

http: // ww. datasheetcatalog. org / datasheet / s iemens / BSPI 35. pdf described metal oxide semiconductor field effect transistor or similar n-channel small transistors with high dynamic resistances.

Instead of the MOSFET M, another self-conducting field-effect transistor, for example a self-conducting junction field-effect transistor, can also be used correspondingly.

Figure 4 shows a second embodiment of a circuit arrangement according OF INVENTION ^¬ dung for a digital input egg nes electronic device. It differs from the circuit arrangement shown in Figure 3 only in that the semiconductor diode D is replaced by a bridge rectifier B. Compared to the embodiment illustrated in FIG. 3, this circuit ^arrangement allows a faster response of the digital input to alternating input voltages U by means of a two-way ^{rectification of} the electric current. and is therefore to be preferred to the circuit of Figure 3 in cases where such a rapid response is advantageous. However, it causes a higher Gesamtver ^¬ loss performance of the digital input as a comparable circuit shown in Figure 3, since the bridge rectifier B causes a current flow at both a positive and a negative input voltage U and thus at an applied AC input voltage U both half-waves of the input voltage U cause a current flow.

Figure 5 shows a third embodiment of a circuit arrangement according OF INVENTION ^¬ dung for a digital input of an electronic device. This exemplary embodiment is a first embodiment of the circuit arrangement illustrated in FIG. 3 by adding various respectively optional protective elements for protecting the circuit from high or high-frequency input voltages U.

These protective elements are a suppressor diode V _T , suppression capacitors C _x , C _Y and at least one additional protection element R _z , L _z .

The suppressor diode V _T is arranged in the circuit elekt ^¬ rically between the outputs of the semiconductor diode D and the optocoupler 0 _T. It serves to protect against a threshold voltage exceeding input voltages U, which could damage the MOSFET M.

Decoupling capacitors C _x, C _Y are so-called each X or Y capacitors electrically ver to the input of Halbleiterdio- de D, possibly via an additional protecting member R _z, L _z, and / or to the output of the optocoupler 0 _T ^{¬ are} bound. They protect the circuit from input voltages U whose frequency exceeds a protection frequency.

The additional protection elements R _z , L _z are a protective resistor R _{z connected} upstream of the semiconductor diode D and a ballast protection element L _z which is connected upstream of the interference suppression capacitors C _x , C _Y may be an electrical resistance or an inductive electrical component. In this case, the protective resistor R _z serves primarily to divide the total power loss on the MOSFET M and the protective resistor R _z and thereby relieve the MOSFET M.

This third embodiment can be varied by ressordiode depending on the requirements to the circuit arrangement at least one of the decoupling capacitors C _x, C _Y and / or the Supp- V _T and / or at least one of the additional protection ^¬ members R _z, L _z is omitted.

Figure 6 shows a fourth embodiment of a circuit arrangement according OF INVENTION ^¬ dung for a digital input egg nes electronic device, which is a second embodiment of the circuit arrangement shown in FIG. 3 In this embodiment, a first bypass capacitor C _{s is} electrically connected in parallel with the current control resistor R _B.

This fourth embodiment is particularly advantageous ^¬ way, when the circuit arrangement for reducing the total power loss of the digital input, a non dargestell ^¬ tes, the digital input Feeding electromechanical relay is connected upstream. In such a relay in Lau ^¬ fe time at the relay contacts oxidation problems occurring defects ^¬ th that of the reliability of the relay and

Circuit arrangement affect existing overall circuit. Such oxidation problems are advantageously reduced by the first bypass capacitor C _s , since it allows a higher current to flow for a short time to the switching point of the relay, thereby enabling a cleaning of the relay contacts. Because of the bypass capacitor C _s , the voltage at the control terminal G _{M of} the MOSFET M is momentarily reduced after the relay has been switched, which results in a higher current flow. Figure 7 shows a fifth embodiment of a circuit arrangement according OF INVENTION ^¬ dung for a digital input of an electronic device which is a third embodiment of the circuit arrangement shown in FIG. 3 This design provides for a training to the current control resistor R _B connected electrically in parallel Überbrückungsoptokoppler 0 _D and the latter and the current control resistor R _B pre ^¬ switched resistor R _v before. This allows to make the electric current only for one by the properties of the components of the circuit arrangement flow predeterminable time interval and advantageously reduce the total loss ^¬ power by the resulting pulse / pause ratio. Here, the Überbrückungsoptokoppler 0 _D, enables the power circuits by the electrical resistance of _v formed from him, the current control ^¬ resistor R _B and the series resistor R part scarf ^¬ processing with respect to the current control resistor R _B and the control terminal G _M of the MOSFET M the resulting current flow reduced. In this case, _D are most Überbrückungsoptokoppler 0 only relatively small switching voltages, for example in the range of a few volts, thereby can be advantageously used cost Stan ^¬ dardbauteile. Figure 8 shows a sixth embodiment of a circuit arrangement according OF INVENTION ^¬ dung for a digital input of an electronic device which is a fourth embodiment of the circuit arrangement shown in FIG. 3 This refinement provides a second bridging capacitor C _P i electrically connected in parallel with the light-emitting diode L of the optocoupler O _T , a series resistor R _V arranged between the semiconductor diode D and the MOSFET M, and a third bypass capacitor C _P 2, the third bridging capacitor C _P 2 The capacitor C _P 2 is electrically connected in parallel with the part of the circuit ^arrangement formed by the MOSFET M, the Zener diode V _z and the light-emitting diode L. By means of the bypass capacitors C _P i, C _P 2, voltage ^peaks , steep switching edges and half-waves of input voltages can advantageously be used. gen U intercepted and the input signal thus entprellt who ^¬ . Also, the sixth embodiment can be varied ^¬ the by either the second bypass capacitors C _P i or the third bypass capacitor C _P 2 and the current limiting resistor R _v may be omitted.

The exemplary embodiments illustrated in FIGS. 3 to 8 can also be suitably combined. For example, in the exemplary embodiments shown in FIGS. 5 to 8, the semiconductor diode D can be replaced by a bridge ^rectifier B as in FIG. 4 and / or the exemplary embodiments illustrated in ^FIGS . 6 to 8 can be used around protective elements V _T , C _x , C _Y , R _z and / or L _{z are expanded} as in FIG.

Claims

claims

1. Circuit arrangement for a digital input of an electronic device, comprising at least

a rectifier for rectifying a current flow through the circuit arrangement,

- A downstream of the rectifier blocking member for blocking the current flow below a switching threshold of an input voltage (U), and

- a downstream of the blocking member separating member for electrical isolation ^¬ the digital input of at least one further component coupled to it of the electronic device,

characterized by a downstream of the rectifier and the blocking member upstream self-conducting

Field effect transistor and by a suppressor diode (V _T ) or a varistor as a protective member for protection against a protection threshold exceeding input voltages (U).

2. Circuit arrangement according to claim 1,

characterized in that the rectifier is a semicon ^¬ terdiode (D).

3. Circuit arrangement according to claim 1,

characterized in that the rectifier is a bridge rectifier (B).

4. Circuit arrangement according to one of the preceding claims,

characterized in that the self-conducting field effect ^¬ transistor is a normally-on metal oxide semiconductor field effect transistor (M).

5. Circuit arrangement according to claim 4,

characterized in that a control terminal (GM) and a source terminal (S _M) of the self-conductive metal oxide semi-conductor field effect transistor ^¬ (M) via a current control Resistance (R _B ) are connected.

6. Circuit arrangement according to claim 5,

characterized by a first bypass capacitor (C _s ) electrically connected in parallel with the current control resistor (R _B ).

7. Circuit arrangement according to claim 5 or 6,

characterized by a bypass coupler (0 _D ) electrically connected in parallel with the current control resistor (R _B ).

8. Circuit arrangement according to one of claims 1 to 3, characterized in that the self-conducting field effect transistor is a self-conducting junction field effect transistor.

9. Circuit arrangement according to one of the preceding claims,

characterized in that the blocking member is a Zener diode (V _z ).

10. Circuit arrangement according to one of the preceding claims,

characterized in that the separating member is an opto ^¬ ler (0 _T).

11. Circuit arrangement according to one of the preceding claims,

characterized by at least one suppressor capacitor (C _x , C _y ) as a protective member before input voltages (U) whose frequency exceeds a protective frequency.

12. Circuit arrangement according to one of the preceding claims, characterized by a to the isolator elek ^¬ trically connected in parallel second bypass capacitor (C _PI ).

13. Circuit arrangement according to one of the preceding claims, characterized by a third Überbrückungskon- capacitor (Cp _2), which is electrically connected in parallel to a contained the self-conductive field effect transistor ^¬, the blocking member and the partition member portion of the circuit arrangement.