WO2012000354A1

WO2012000354A1 - Storing and forwarding system and message storing method thereof

Info

Publication number: WO2012000354A1
Application number: PCT/CN2011/074521
Authority: WO
Inventors: 周昶; 陈红旗; 缪欣; 张兰君
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-06-29
Filing date: 2011-05-23
Publication date: 2012-01-05
Also published as: CN101883041B; CN101883041A

Abstract

A storing and forwarding system and message storing method thereof are disclosed in the present invention. Wherein, the method comprises: the storing and forwarding system receives a message (S402); the storing and forwarding system determines that the byte number L of the payload of the message is within a preset threshold range and the value of L mod M is not zero (S404), and wherein, the M is the storage burst read-write byte number of a main storage controller which is a dynamic random access memory; the message is divided into two segments, the first segment of the message is stored into an auxiliary storage controller, and the other segment of the message is segmented and stored into the main storage controller sequentially in the storage processes of N times(S406), and wherein the byte number of the first segment of the message is the remainder part of the L/M, and the N is the integer part of the L/M. With the invention, the requirement for the bandwidth of the main storage controller can be reduced, and the message forwarding efficiency is improved.

Description

The present invention relates to the field of network communication memory management technologies, and in particular to a store-and-forward system and a message storage method thereof. BACKGROUND OF THE INVENTION The data rate of Internet Bone Network has almost doubled every six to nine months. At the same time, the requirements for the quality of the Internet and the demand for data are also increasing. Most of the processing of packets on the network by the network device is to use the store-and-forward method. That is, the packet is first cached in the message memory, and the information such as the exit and format of the packet is calculated and processed, so all the reports are sent. The write and read operations are performed at least once, and these operations are done in the memory controller. At present, the off-chip memory mainly includes static random access memory (Sram) and dynamic random access memory (Dram), from speed and capacity. And cost considerations, message cache mainly uses DRAM. Dram is accessed according to a certain burst length. Therefore, due to the impact of the number of bursts, the actual bandwidth requirement of the storage controller is higher than theoretical. For example, for a Dram with a bit width of 64 bits and a burst length of 8, each burst read or write is 64 bytes. For a message that needs to buffer 65 bytes, it needs to be twice. Burst read and write operations complete the store and forward of a message. Figure 1 is the corresponding relationship between the theoretically forwarded packet length and the maximum required bandwidth. Figure 2 is the corresponding relationship between the packet length and the maximum required bandwidth forwarded in actual use. By comparison, it can be seen that the actual length of the packet is longer. The small range of demand for memory controller bandwidth jumps a lot, and the actual bandwidth requirements are higher than the theoretical bandwidth requirements. In a Dram-based store-and-forward system, when the number of bytes of the message payload that needs to be stored and forwarded is L, the number of bytes of the storage burst read and write of the system Dram is M, because the memory is subjected to bursts of bytes. Restriction, the efficiency of message forwarding varies with the number of bytes of the message and the number of bursts of bytes. Wherein, when L is an integer multiple of M, the efficiency is N = 100%. When L is not an integer multiple of M, the efficiency is N = L / ( M * ( L \ M + 1 )) * 100% Dram completes a read or write operation and needs to be precharged, enabled, read or written. Therefore, the higher the length of Dram burst read and write, the higher the read and write efficiency of Dram. In the above formula, the inventor has found that the smaller the message payload L is, the larger the number of memory burst read and write bytes M of the system Dram is, the lower the packet forwarding efficiency of the system is. If L>=M, then L=M+1, the packet forwarding efficiency of the system is also low. SUMMARY OF THE INVENTION A main object of the present invention is to provide a store-and-forward system and a message storage method thereof to solve at least the problem of low efficiency of system message forwarding. According to an aspect of the present invention, a packet storage method for a store-and-forward system is provided, including: a store-and-forward system receives a message; and the store-and-forward system determines that the number L of bytes of the payload of the packet is within a preset threshold range. The value of L mod M is not zero, wherein M is the storage burst read and write byte number of the primary storage controller, and the primary storage controller is dynamic random access memory; the message is divided into two segments, The first segment of the packet is stored in the secondary storage controller, and the other segment of the packet is sequentially stored in the primary storage controller in the N-time storage process, wherein the number of bytes of the first segment of the packet is The remainder of L / M, where N is the integer part of L/M. The first paragraph above is obtained from the first section of the article. The first segment of the message is obtained from the end of the message. The above M is 64 bytes and the threshold range is [M+1, M+8]. The above M is 64 bytes, and the threshold range is [M*2+l, M*2 + 4]. The secondary storage controller is a synchronous static random access memory (SSRAM). The secondary storage controller is Dram, and the storage burst read/write byte number of the secondary storage controller is less than or equal to M. According to another aspect of the present invention, a storage and forwarding system is provided, including: a receiving module, configured to receive a message that needs to be stored and forwarded; and a determining module, configured to determine whether a byte number L of the payload of the message is Within the threshold range and the value of L mod M is not zero, if yes, triggering the splitting module, where M is the number of read and write bytes of the storage burst of the primary storage controller; the splitting module is set to divide the packet into Two segments, where the number of bytes of the first segment of the message is L mod M; the primary storage controller is Dram, The second segment of the packet is sequentially segmented and stored in the process of storing the second segment of the packet, wherein N is an integer part of L/M; and the secondary storage controller is configured to store the first segment of the packet. . The above secondary storage controller is an SSRAM. The secondary storage controller is Dram, and the storage burst read/write byte number of the secondary storage controller is less than or equal to M. According to the present invention, by adding a secondary storage controller, the packet generating the read/write efficiency loss portion is stored in the secondary storage controller, thereby reducing the bandwidth requirement of the primary storage controller and improving the efficiency of packet forwarding. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are set to illustrate,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, In the drawings: FIG. 1 is a corresponding relationship between a packet length and a maximum required bandwidth according to a theoretical calculation; FIG. 2 is a corresponding relationship between a packet length and a maximum required bandwidth in actual use in the related art; FIG. 4 is a flowchart of a packet storage method of a store-and-forward system according to Embodiment 2 of the present invention; FIG. 5 is a schematic diagram of a technical solution provided by Embodiment 2 of the present invention. Schematic diagram of the correspondence between the packet length and the maximum required bandwidth. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. FIG. 3 is a schematic structural diagram of a store-and-forward system according to a first embodiment of the present invention. The store-and-forward system includes: a receiving module 10, a determining module 20, a dividing module 30, a main storage controller 40, and a secondary storage controller 50. The receiving module 10 is configured to receive a packet that needs to be stored and forwarded. The determining module 20 is configured to determine whether the number L of the payload of the packet is less than a threshold, and the value of L mod M is not zero. The triggering module 30 is triggered, wherein the M is the storage burst read/write byte number of the main storage controller 40; the splitting module 30 is configured to divide the packet into two segments, wherein the first segment of the message The number of sections is L mod M; the main storage controller 40 is Dram, and is set to store the second segment of the packets in sequence during the storage of the second segment of the message N times, where N is L/M The integer portion; the secondary storage controller 50 is configured to store the first segment of the message. For example, if M = 64 bytes, the above threshold range may be one or both of the following: [ M+1 , M+8 ]; [ M*2+l , M*2+4 ]. It should be noted that, in practical applications, the setting of the threshold range is not limited thereto, and the purpose of setting the threshold range is to digest the read/write efficiency loss due to the storage burst read/write bytes of the main storage controller 40. , can be set according to empirical values or experimental data. In the related art, the message that needs to be stored and forwarded is stored in a storage controller. In the case that the storage controller is Dram, due to the limitation of the storage burst read and write bytes of the storage controller, if necessary The number of bytes of the packet to be forwarded and forwarded is not a multiple of the number of bytes of the burst read and write, but only a small fraction of the number of bytes of the burst read and write, which will result in lower packet forwarding efficiency. Increase the need for the maximum bandwidth of the storage controller. In the foregoing storage and forwarding system provided by the embodiment of the present invention, a secondary storage controller 50 is added, which is configured to store a small number of packets in the packet that are more than a multiple of the number of stored burst read/write bytes, thereby improving The overall read and write efficiency of the system reduces the bandwidth requirements of the primary storage controller. Preferably, secondary storage control 50 may be a storage controller that does not store a burst read/write byte limit, such as an SRAM. Preferably, since the number of bytes of the message stored by the secondary storage control 50 is not large, the capacity of the secondary storage control 50 does not need to be too large. Therefore, the secondary storage control 50 can be a synchronous SRAM (Synchronous SRAM, referred to as SSRAM), thereby reducing the cost. . Preferably, the secondary storage controller 50 can also be a DRAM, and the number of storage burst bytes is shorter, at least smaller than the number of storage burst read and write bytes of the primary storage controller 40, so as to ensure the overall reading of the system. Write efficiency has improved. The second embodiment of the present invention is described in conjunction with the storage and forwarding system provided by the first embodiment of the present invention. 4 is a flowchart of a message storage method of a store-and-forward system according to a second embodiment of the present invention. The method mainly includes the following steps (step S402 - step S406): Step S402: The store-and-forward system receives a message; for example, a receiving module 10: Receive a message to be processed; Step S404, the store-and-forward system determines that the number L of the payload of the message is within a preset threshold range, and the value of L mod M is not zero, wherein M is dominant The storage controller 40 stores the number of read and write bytes of the burst, and the primary storage controller 40 is Dram; for example, M = 64 bytes, and the threshold range may be [M + 1 , M+8 ]; or, the threshold range is also Can be [ M*2 + l , M*2+4 ]. According to the reading and writing efficiency X = L / (M * (L \ M + 1)) * 100%, at L > = M, L = M + 1 is the lowest point of system efficiency. When L is a multiple of M, the change in the number of L bytes has a relatively small effect on the storage and forwarding efficiency of the packet. Therefore, in the embodiment of the present invention, the message with a longer payload number L is still Processed according to the existing method. Step S406, the packet is divided into two segments, and the first segment of the packet is stored in the secondary storage controller 50, and another segment of the packet is sequentially stored in the primary storage controller in the N-time storage process. 40, wherein the number of bytes of the first paragraph is L mod M, and N is an integer part of L/M. For example, the first segment of the packet may be obtained from the header of the packet, or may be obtained from the end of the packet. When the first segment of the packet is obtained from the header of the packet, the packet is stored in the secondary storage controller 50, and the first packet is obtained from the end of the packet. At the time of forwarding, after reading and forwarding the second segment of the packet stored in the primary storage controller 40, the packet stored in the secondary storage controller 50 is read. When the second segment of the message is stored, if N>1, the second segment of the packet is sequentially segmented in the N-th storage process of the segment, that is, the packet is first intercepted from the second segment. The data of the number of bytes M is stored in the main storage controller 40. After the data stored in the main storage controller 40 is forwarded, the next segment of the message is intercepted from the second segment of the message. The data is stored in the main storage controller 40, and then the data stored in the main storage controller 40 is forwarded, and then the data of the next segment of the number M is stored in the main storage controller 40, and so on, until the second The segment messages are all forwarded. FIG. 5 is a schematic diagram of the correspondence between the packet length and the maximum bandwidth requirement of the primary storage controller after using the technical solution provided by the embodiment of the present invention. As shown in FIG. 5, the technical solution provided by the embodiment of the present invention can be reduced. The primary storage controller bandwidth requirements. In the related art, the message that needs to be stored and forwarded is stored in a storage controller. In the case that the storage controller is Dram, due to the limitation of the storage burst read and write bytes of the storage controller, if necessary The number of bytes of the packet to be forwarded and forwarded is not a multiple of the number of bytes of the burst read and write, but only a small fraction of the number of bytes of the burst read and write, which will result in lower packet forwarding efficiency. Increase the need for the maximum bandwidth of the storage controller. In the message storage method of the storage and forwarding system provided by the embodiment of the present invention, a small portion of the message that is larger than a multiple of the number of stored burst read/write bytes is stored in the secondary storage controller 50, thereby It can improve the overall reading and writing efficiency of the system and reduce the bandwidth requirement of the main storage controller 40. Embodiment 3 In the third embodiment of the present invention, taking a 10 Gigabit Ethernet forwarding as an example, as shown in Table 1, the number of storage burst read and write bytes of the main storage controller 40 is 64 bytes, and the forwarding traffic is In the shortest packet change, the packet full traffic is 7.619G, the required read/write bandwidth is 7.619G, and the 4艮 text is 69 bytes. For 7.753G, the required read and write bandwidth is 14.382G. Table 1.

In-chip adjustment after adjustment

DRAM

Bao Chang 艮文 3⁄4 L amount 4 艮 text rate 净 payload literacy with Dram cry DRAM burst read

(bytes) (G bps) (MPPS) long width (G) read and write total band width write times

(Bytes) number of times (G)

64 7.619 14.881 60 1 7.619 1 7.619

65 7.647 14.706 61 1 7.529 1 7.529

66 7.674 14.535 62 1 7.442 1 7.442

67 7.701 14.368 63 1 7.356 1 7.356

68 7.727 14.205 64 1 7.273 1 7.273

69 7.753 14.045 65 2 14.382 1 7. 191

70 7.778 13.889 66 2 14.222 1 7. 1 1 1

71 7.802 13.736 67 2 14.066 1 7.033

72 7.826 13.587 68 2 13.913 1 6.957

73 7.849 13.441 69 2 13.763 1 6.882

74 7.872 13.298 70 2 13.617 1 6.809

75 7.895 13. 158 71 2 13.474 1 6.737

76 7.917 13.021 72 2 13.333 1 6.667

77 7.938 12.887 73 2 13. 196 1 6.598

78 7.959 12.755 74 2 13.061 1 6.53 1

79 7.980 12.626 75 2 12.929 1 6.465

127 8.639 8.503 123 2 8.707 2 8.707

128 8.649 8.446 124 2 8.649 2 8.649

129 8.658 8.389 125 2 8.591 2 8.591

130 8.667 8.333 126 2 8.533 2 8.533

131 8.675 8.278 127 2 8.477 2 8.477

132 8.684 8.224 128 2 8.421 2 8.421

133 8.693 8.170 129 3 12.549 2 8.366

134 8.701 8.117 130 3 12.468 2 8.312

135 8.710 8.065 131 3 12.387 2 8.258

136 8.718 8.013 132 3 12.308 2 8.205

137 8.726 7.962 133 3 12.229 2 8.153

138 8.734 7.911 134 3 12.152 2 8.101

139 8.742 7.862 135 3 12.075 2 8.050

140 8.750 7.813 136 3 12.000 2 8.000

141 8.758 7.764 137 3 11.925 3 11.925

142 8.765 7.716 138 3 11.852 3 11.852

143 8.773 7.669 139 3 11.779 3 11.779

144 8.780 7.622 140 3 11.707 3 11.707

145 8.788 7.576 141 3 11.636 3 11.636

146 8.795 7.530 142 3 11.566 3 11.566

147 8.802 7.485 143 3 11.497 3 11.497

148 8.810 7.440 144 3 11.429 3 11.429

149 8.817 7.396 145 3 11.361 3 11.361

150 8.824 7.353 146 3 11.294 3 11.294

151 8.830 7.310 147 3 11.228 3 11.228

152 8.837 7.267 148 3 11.163 3 11.163

153 8.844 7.225 149 3 11.098 3 11.098

154 8.851 7.184 150 3 11.034 3 11.034

155 8.857 7.143 151 3 10.971 3 10.971

156 8.864 7.102 152 3 10.909 3 10.909

157 8.870 7.062 153 3 10.847 3 10.847

158 8.876 7.022 154 3 10.787 3 10.787 In the embodiment of the present invention, the threshold range includes: [69, 84] and [133, 144], that is, in the embodiment of the present invention, the length of the file is 69 bytes to 84. Bytes and contents of 133 to 140 bytes of tail less than 64 bytes are stored in the secondary storage controller 50 (for example, SSRAM), and the requirement for the primary storage controller 40 is reduced to 7.191G at 69 bytes, the system is the largest. The bandwidth required is reduced from 14.382G to 12.190G. From the above description, it can be seen that, in the embodiment of the present invention, by adding a secondary storage controller 50, a message that generates a read/write efficiency loss portion is stored in the secondary storage controller 50, thereby reducing the The bandwidth requirement of the storage controller 40 improves the efficiency of packet forwarding. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module. Thus, the invention is not limited to any specific combination of hardware and software. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A packet storage method for a store-and-forward system, including:

The store-and-forward system receives a message;

The storage and forwarding system determines that the number L of the payload of the packet is within a preset threshold range, and the value of L mod M is not zero, where M is a storage burst read and write of the primary storage controller. The number of bytes, the primary storage controller is a dynamic random access memory Dram;

And dividing the packet into two segments, storing the first segment of the packet in the secondary storage controller, and storing another segment of the packet in the N storage process, and sequentially storing the packet in the primary storage. In the controller, the number of bytes of the message in the first segment is a remainder of L / M, and N is an integer part of L/M.

2. The method according to claim 1, wherein the first segment of the message is obtained from a header of the message.

3. The method according to claim 1, wherein the first segment of the message is obtained from a tail of the message.

4. The method of claim 1, wherein M is 64 bytes and the threshold range is [M+1, M+8].

5. The method according to claim 1, wherein M is 64 bytes, and the threshold range is

[ M*2+l , M*2 + 4 ].

The method according to any one of claims 1 to 5, wherein the secondary storage controller is a synchronous static random access memory (SSRAM).

The method according to any one of claims 1 to 5, wherein the secondary storage controller is Dram, and the number of storage burst read/write bytes of the secondary storage controller is less than or equal to M.

8. A store-and-forward system, including:

a receiving module, configured to receive a message that needs to be stored and forwarded;

a determining module, configured to determine whether the number L of the payload of the packet is within a threshold range and the value of L mod M is not zero, and if so, triggering the splitting module, where M is the primary storage controller Store the number of burst read and write bytes; a segmentation module, configured to divide the packet into two segments, where the number of bytes of the packet in the first segment is L mod M;

The primary storage controller is Dram, and is configured to sequentially store the second segment of the message in the process of storing the second segment of the message N times, where N is an integer of L/M section;

The secondary storage controller is configured to store the message in the first segment.

9. The system of claim 8, wherein the secondary storage controller is a SSRAM.

10. The system according to claim 8, wherein the secondary storage controller is Dram, and the number of storage burst read/write bytes of the secondary storage controller is less than or equal to M.