WO2011162720A1

WO2011162720A1 - A light collecting device

Info

Publication number: WO2011162720A1
Application number: PCT/SG2011/000215
Authority: WO
Inventors: Gang Zhang; Guo-Qiang Patrick Lo; Jun-Shuai Li; She-Mein Wong; Heng-Meng Wong; Hong-yu YU; Dim-Lee Kwong
Original assignee: Agency For Science, Technology And Research; Nanyang Technological University
Priority date: 2010-06-23
Filing date: 2011-06-16
Publication date: 2011-12-29

Abstract

Embodiments provide a light collecting device. The light collecting device may comprise a semiconductor nanowire array which comprises a plurality of semiconductor nanowires. The light collecting device may also comprise a supporting structure supporting the semiconductor nanowire array. Each semiconductor nanowire may be divided into a plurality of nanowire areas. The diameter of each semiconductor nanowire may change from nanowire area to nanowire area, however remains at least substantially constant within each of the nanowire areas.

Description

A LIGHT COLLECTING DEVICE

[00011 The present application claims the benefit of the USA provisional patent application 61/357,577 (filed on 23 June 2010), the entire contents of which are incorporated herein by reference for all purposes.

Technical Field

[0002] Various embodiments relate generally to a light collecting device. For example, the light collecting device may be used as a solar cell.

Background

[0003] The Sun deposits 120,000 terawatts (TW) of power per year onto the Earth's surface, which is far more than enough to provide the 13 TW of total power that is currently used by the planet's population or the 30 TW that will probably be needed by 2050. The development of affordable photovoltaic (solar) cells is therefore one of the most promising long-term solutions to solve the energy crisis. The light-harvesting process to convert solar energy to electricity has two key steps that determine the overall efficiency of the process: light absorption, and charge collection.

[0004] Traditionally, silicon thin films are used as photovoltaic cells. However, the overall efficiency is not as high as expected. Recently, silicon nanowires (SiNWs) arrays have been suggested as a promising candidate for solar energy harvesting. SiNWs are of outstanding interest as one of the promising building material systems for future nanoscale electronic and optoelectronic devices due to their compatibility with silicon-based technology. SiNW photovoltaic cells may have a short collection length for excited carriers, leading to significant improvement in carrier collection efficiency. Besides high carrier collection efficiency, to increase the overall efficiency, it is important that the semiconductors used are able to capture a large fraction of the solar energy across the whole solar spectrum.

[0005] With the fasi and progressive research in experiment, more and more theoretical efforts have been made to understand optical absorption in SiNW arrays. Hu and Chen [cf. 1] have studied the optical absorption in SiNW arrays using a transfer matrix method. They found that in the high photon energy regime, SiNW arrays have higher absorbance than their thin film counterparts. Moreover, Li et al. [c 2] have demonstrated that SiNW arrays together with a thin film as the substrate layer have much higher optical absorption efficiency than both thin films and pure SiNW arrays.

[0006] High optical absorption is the challenge in photovoltaic research with less material available optically for the cost consideration. Although some research has been performed, there is still space to enhance the absorption efficiency, and in turn to increase the overall efficiency of SiNW based solar cells further.

Summary of the Invention

[0007] Various embodiments provide a light collecting device which may achieve an improved light absorption efficiency, compared to known light collecting devices. Various embodiments of the light collecting device may be used as a solar cell.

[0008] The light collecting device may comprise a semiconductor nanowire array which comprises a plurality of semiconductor nanowires. The light collecting device may further comprise a supporting structure supporting the semiconductor nanowire array. Each nanowire may be divided into a plurality of nanowire areas. The diameter of each nanowire may change from nanowire area to nanowire area, however remains at least substantially constant within each of the nanowire areas.

Brief Description of the Drawings

[0009] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

FIG 1 (a) shows a side view of a silicon nanowire (SiNW) array where each SiNW in the array has a uniform diameter along the length of the respective SiNW;

FIG. 1 (b) shows a perspective view of a structure which comprises a SiNW array supported by a substrate where each SiNW in the array has a uniform diameter along the length of the respective SiNW;

FIG. 1 (c) shows a side view of a structure which comprises a SiNW array supported by a substrate where each SiNW in the array has a uniform diameter along the length of the respective SiNW;

FIGs. 2 (a) and (b) shows the reflection and transmission spectra of a SiNW array with substrate structure as shown in FIGs. 1 (b) and (c) with different periodicities;

FIG. 3 shows the scattering of incident light in a nanowire array resulting in a longer optical path and thus in an enhanced light absorption;

FIG. 4 (a) shows a structure which comprises a uniform diameter SiNW array supported by a substrate and which may be used as a solar cell; FIG. 4 (b) shows the absorbance of uniform diameter SiNW arrays with SiNW diameters of 20, 50, and 80 nm, respectively;

FIG. 4 (c) shows the ultimate efficiency versus diameters of SiNWs in the SiNW arrays; FIG. 5 (a) shows a SiNW array with a diameter of 50 nm for each SiNW in the array; FIG. 5 (b) shows a SiNW array with a diameter of 100 nm for each SiNW in the array; FIG. 5 (c) shows a SiNW array with a diameter of 200 nm for each SiNW in the array; FIG. 6 (a) shows a perspective view of an inhomogeneous-diameter semiconductor nanowire array with a supporting structure according to one embodiment;

FIG 6 (b) shows a top view of the inhomogeneous-diameter semiconductor nanowire in the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (c) shows a side view of a semiconductor nanowire in the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (d) shows a side view of a semiconductor nanowire in the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (e) shows a side view of a semiconductor nanowire in the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (f) shows a top view of a semiconductor nanowire in the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (g) shows a top view of a semiconductor nanowire in the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (h) shows a top view of a semiconductor nanowire in the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment; FIG. 6 (i) shows a top view of the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (j) shows a top view of the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (k) shows a top view of the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (1) shows a top view of the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 6 (m) shows a top view of the semiconductor nanowire array shown in FIG. 6 (a) according to one embodiment;

FIG. 7 shows a table illustrating the ultimate efficiency for SiNW arrays having SiNWs with different geometries; and

FIG. 8 shows a fabrication process for an inhomogeneous-diameter SiNW according to one embodiment.

Description

[0010] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0011] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration"; Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0012] A simple and effective approach to enhance the ultimate efficiency of silicon rianowire arrays for photovoltaic application is provided. The proposed solution may increase the optical absorption by using inhomogeneous-diameter SiNWs. This may allow a high absorption over the whole solar spectrum, and yield maximum attainable total ultimate efficiency. It may reduce the transmission of low energy photons, and the reflection of photons in high energy range. Moreover, high efficient solar cells based on SiNW arrays with inhomogeneous-diameter SiNWs may also have the advantage of light mass over bulk solar cells. This method is very attractive due to its compatibility with the present silicon-based technology.

[0013] In this context, the ultimate efficiency refers to the optical-electrical conversion capability for all the incident photons onto a solar device, provided that those incident photons with an energy above or equal to E_g (bandgap of the semiconductors) may be trapped by the solar device. The photon energy may be converted into one electron-hole pair with the energy of E_g, arid the excess energy above E_g may be lost as heat. The electron-hole pair may be completely extracted for electrical energy output, i.e. the electron-hole pair generated may be converted to electrical current. In other words, when calculating the ultimate efficiency, the internal quantum efficiency is set as 1, i.e., if the incident photon has an energy equal to or above E_g, an electron-hole pair is generated. If the incident photon has an energy less than E_g, the photon energy will not be converted to electrical energy but will be lost as heat. Hence, the ultimate efficiency is typically never higher than 50%, because the photon energy to electron- hole pair generation is not perfect, as determined by the bandgap. For instance, if the photon energy is less than the bandgap, no charges will be generated, and the photon energy is only converted into heat. For the photons with energies larger than the bandgap, the energy portion equal to the bandgap may result in one electron-hole pair, and the extra portion may be wasted into heat. ; Different structure and different materials may be used to convert photons with different energies to generate electrical energy with different conversion efficiencies.

[0014] Embodiments provide a light collecting device. In one embodiment, the light collecting device may comprise a semiconductor nanowire array which comprises a plurality of semiconductor nanowires. The light collecting device may further comprise a supporting structure supporting the semiconductor nanowire array. In one embodiment, each semiconductor nanowire may be divided into a plurality of nanowire areas. The diameter of each semiconductor nanowire may change from nanowire area to nanowire area, however remains at least substantially constant within each of the nanowire areas.

[0015] In one embodiment, the light collecting device may comprise a semiconductor nanowire array which comprises a plurality of semiconductor nanowires. The diameter of each semiconductor nanowire of the semiconductor nanowire array may change at least one discrete interval along the length of the respective nanowire. The light collecting device may further comprise a supporting structure which supports the semiconductor nanowire array.

[0016] The light collecting device as described herein may be comprised in or used as a solar cell. [0017] In one embodiment, the supporting structure may comprise a semiconductor layer or a metallic layer or a combination of a metallic layer and a semiconductor layer. First ends of the semiconductor nanowires may be connected to the supporting structure.

[0018] ; In one embodiment, the supporting structure comprises a substrate supporting the semiconductor layer or the metallic layer or the combination of the semiconductor layer and the metallic layer.

[0019] In one embodiment, the semiconductor nanowires are silicon nanowires. It should however be noted that the semiconductor nanowires may be Germanium, Gallium Arsenide, Indium Phosphide nanowires etc. In one embodiment, for each semiconductor nanowire, each seiriiconductor area may comprise a different semiconductor material from that comprised in another semiconductor area.

[0020] In one embodiment, the semiconductor layer is a silicon layer.

[0021] In one embodiment, each nanowire area of the corresponding nanowire has an at least substantially cylindrical shape.

[0022] In one embodiment, the semiconductor nanowires respectively extend along a direction aligned at least substantially perpendicular to the supporting structure.

[0023] In one embodiment, the diameter of each semiconductor nanowire increases along a direction pointing towards the supporting structure.

[0024] In one embodiment, each semiconductor nanowire of the semiconductor nanowire array has at least substantially the same shape and the same alignment with regard to the supporting structure.

[0025] In one embodiment, the number of nanowire areas per nanowire ranges between 2 and 6. [0026] In one embodiment, each semiconductor nanowire comprises 3 nanowire areas having nanowire diameters of about 20 nm, 50 nm, and 80 nm, respectively. It should be noted that the range of diameters of each nanowire area is not so limited. For example, the diameter of each nanowire area may range between around 100 nm to around 500 nm.

[0027] In one embodiment, a cross-sectional shape of each nanowire area is respectively concentric or point symmetrical with respect to a longitudinal central axis of the corresponding semiconductor nanowire. In other words, each nanowire area in a semiconductor nanowire may be aligned along the same longitudinal central axis.

[0028] In one embodiment, the length of the nanowire areas increases or decreases or remains constant along a direction pointing towards the supporting structure.

[0029] In one embodiment, the cross-sectional shape of the nanowire areas is circular, polygonal, or elliptical. In one embodiment, the cross-sectional shape of the nanowire areas is hexagonal or octagonal.

[0030] In one embodiment, the plurality of semiconductor nanowires is arranged in a two- dimensional lattice pattern of semiconductor nanowires.

[0031] In one embodiment, the distances between a semiconductor nanowire to another semiconductor nanowire in the semiconductor nanowire array may vary according to the design requirement for optimization of the light collecting device's overall light collection efficiency and the charge collection efficiency.

[0032] In one embodiment, the lattice pattern is a square lattice pattern.

[0033] In one embodiment, a lattice spacing of the lattice pattern ranges between about 100 nm and about 600 nm. [0034] In one embodiment, the plurality of semiconductor nanowires is arranged as a rectangular lattice pattern, a hexagonal lattice pattern, a rhombic lattice pattern, a parallelogrammic lattice pattern, or an irregular pattern.

[0035] In one embodiment, the semiconductor nanowire array may comprise a plurality of sub-arrays. The semiconductor nanowires in each sub-array may be arranged in a regular pattern.

In one embodiment, the semiconductor nanowires in a sub-array may be arranged in different egular pattern from that in another sub array. In one embodiment, the semiconductor nanowires in two sub-arrays may be arranged in a similar pattern, but one sub-array may be disjointed or disoriented with respect to the other sub-array.

[0036] In one embodiment, the semiconductor nanowire may include a combination of various patterns. For example, locally with one regular patterns, but globally, with various patterns regularity (such as a single crystalline versus a poly-crystalline concept). This provides the flexibility of design and implementation in the future.

[0037] In one embodiment, the plurality of semiconductor nanowires of the semiconductor nanowire array is made of an intrinsic semiconductor and/or doped semiconductor.

[0038] In one embodiment, the plurality of semiconductor nanowires of the semiconductor nanowire array and the semiconductor film are made of an intrinsic semiconductor and/or doped semiconductor.

[0039] In one embodiment, each semiconductor nanowire of the semiconductor nanowire array may comprise an at least substantially cylindrical doped semiconductor core. The doped semiconductor core may be covered across the length and the end that is not connected to the supporting structure by a plurality of semiconductor layers. [0040] In one embodiment, the semiconductor core may be p-doped, and the plurality of semiconductor layers may comprise an intrinsic-type layer and n-type layer to form p-i-n junctions.

[0041] . ^' In one embodiment, the semiconductor core may be p-doped, and the plurality of semiconductor layers may comprise an intrinsic-type layer, n-type layer and p-type layer to form p-i-n-p-i-n junctions.

[0042] In one embodiment, the semiconductor core may be n-doped and the plurality of semiconductor layers may comprise an intrinsic-type layer and p-type layer to form n-i-p junctions.

[0043] In one embodiment, the semiconductor core may be n-doped, and the plurality of semiconductor layers may comprise an intrinsic-type layer, p-type layer and n-type layer to form n-i-p-n-i-p junctions.

[0044] In one embodiment, for each semiconductor nanowire, the semiconductor material contained in a nanowire area is different from that contained in at least one other nanowire area.

[0045] FIG. 1 (a) shows the side view of a pure silicon nanowire (SiNW) array 110 which comprises a plurality of SiNWs 11 1 for solar cell application [cf. 1]. Each SiNW 111 in the array 110 has a uniform diameter along the length of the respective SiNW. Reference [1] shows that in a high frequency regime, SiNW arrays have higher absorbance than their thin film counterparts, which is the commonly used structure for commercial products now. However, in a low frequency regime, SiNW arrays have a lower absorbance than that of thin film solar cells.

[0046] FIG. 1 (b) illustrates a perspective view of a structure 120 of a combination of a SiNW array 121 with a thin film 122 as a substrate which may enhance the optical absorption [cf- 2]. [0047] FIG. 1 (c) illustrates the side view of the structure 120 comprising the SiNW array 121 and the substrate 122. In this example, the height of each SiNW 111 is 1000 nm, and the thickness of the substrate 122 is 800 nm. The diameter 123 of each SiNW 11 1 is equal to the spacing 124 The periodicity of the SiNW array 121 is the sum of the diameter of each SiNW

11 1 and the spacing, i.e., the ratio of diameter to periodicity is 0.5.

[0048] Generally, the optical absorpt ion may be suppressed by reflection and transmission.

[0049] FIG. 2 (a) and FIG. 2 (b) respectively show the simulation results of the reflectance and transmission of SiNW arrays with a thin film as a substrate (e.g., see FIGs. 1 (b) and (c)). In the simulation, the ratio of diameter to periodicity is set to be 0.5. From the analysis in reflectance and transmittance shown in FIGs. 2 (a) and (b), it can be seen that for a low energy photon, transmission is the dominating source for energy loss, and hence a large periodicity (i.e., using SiNWs with large diameters) may benefit the absorption. However, in a high energy range, reflection is the major factor which suppresses absorption. Thus, a small periodicity (i.e., using SiNWs with small diameters) is preferred in high photon energy range.

[0050] FIG. 3 illustrates the scattering of the incident light 302 by the NW (nanowire) array which comprises a plurality of NWs 301. The high absorption in NW arrays, compared to thin films, may be well understood from the point of view of wave optics. The enhanced scattering to the incident light 302 may result in a longer optical path and thus in an enhanced light absorption. The strong scattering occurs when the wavelength of incident light is comparable with the array periodicity (the sum of the diameter 311 of each NW and the spacing 312).

Similarly, as shown earlier in relation to FIGs. 2 (a) and (b), for low energy photons, a large diameter or periodicity can improve the absorption. However, in a high energy range, a small diameter or periodicity can improve the absorption. [0051] FIG. 4 (a) illustrates a structure 400 which may be used as a solar cell. The structure 400 comprises a SiNW array 401 comprising a plurality of SiNWs 410, and the SiNW array 401 is supported by a substrate 402. In this example, the top portion of each SiNW 410 comprises a planar pn junction 403. Each SiNW 410 in the SiNW array 401 may comprise a metal top contact 404, and the substrate 402 may further comprise a metal back contact 405. In this example, each SiNW 410 in the SiNW array has a uniform diameter along the length of the SiNW, and each SiNW 410 has the same diameter.

[0052] FIG. 4 (b) shows the absorbance of SiNW arrays each of which comprises uniform

SiNW diameters of 20, 50, and 80 nm, respectively with the array periodicity of 100 nm.

[0053] As shown in FIG. 4 (b), in SiNW arrays with large SiNW diameter (e.g., D=80 nm, corresponding to a high filling ratio), the absorbance in a high energy range (e.g., above 3 eV) is relatively low due to the increased reflectance. However, in SiNW arrays with small diameter (e.g., D=20 nm), the small filling ratio leads to a high transmittance (low absorptance) in a low energy range (e.g., below 2.5 eV). Thus, there may be one optimal SiNW diameter (such as 50 nm) which may balance the absorption over the whole solar spectrum, and yield high attainable total ultimate efficiency.

[0054] The ultimate efficiency may be calculated from the following g equation

where E_g is the bandgap of the semiconductor; E is the photon energy; 1(E) is the solar energy density spectrum at AMI .5G; and <x(E) is the absorption spectrum.

[0055] ; FIG. 4 (c) shows the ultimate efficiency for the SiNW arrays each of which comprises a plurality of SiNWs of the same dimensions with different SiNW diameters, with a fixed lattice period of 100 nm. The ultimate efficiency increases with the NW diameter, reaching a maximum value of 33,9 % with the optimal diameter being 47 nm, then decreases with the increase of the NW diameter. Thus, the ultimate efficiency of a SiNW array solar cell may be increased by optimizing the diameter of the SiNWs in the SiNW array. However, there is still space to enhance the efficiency further.

[0056] Experimental technology has been developed to control the growth of SiNWs not only in various growth orientations, but also with various diameters (e.g. FIGs. 5 (a) - (c)) and cross sectional shapes.

[0057] FIGs. 5 (a) - (c) show the experimental results for fabricating SiNW arrays with

SiNWs having different diameters. FIG. 5 (a) shows the SEM image of the SiNW array 510, wherein the diameter of each SiNW 511 in the array 510 is around 50 nm. FIG. 5 (b) shows the SEM image of the SiNW array 520, wherein the diameter of each SiNW 521 in the array 520 is around 100 nm. FIG. 5 (c) shows the SEM image of the SiNW array 530 wherein the diameter of each SiNW 531 in the array 530 is around 200 nm.

[0058] SiNWs having different diameters have an advantage regarding the optical absorption in different wavelength ranges. In one embodiment, inhomogeneous-diameter SiNWs are provided to; be used to enhance the absorption over the whole solar spectrum and to yield maximum attainable total ultimate efficiency.

[0059] FIG. 6 (a) illustrates a light collecting device 600 according to one embodiment.

[0060] The light collecting device 600 comprises a semiconductor nanowire (NW) array which comprises a plurality of semiconductor nanowires 601. The light collecting device 600 may also comprise a supporting structure 602 supporting the semiconductor nanowire array. Each nanowire 601 may be divided into a plurality of nanowire areas, wherein the diameter of each nanowire 601 may change from nanowire area to nanowire area. The diameter may remain at least substantially constant within each of the nanowire areas.

[0061] In this example, each nanowire 601 is divided into three nanowire areas in the nanowire array, i.e., nanowire areas 603, 604, and 605. In each of the nanowire areas 603, 604, and 605, the diameter remains at least substantially constant. For each nanowire 601, the diameter of the nanowire 601 in one nanowire area is different from that in another nanowire area. In this particular example, the diameter of each semiconductor nanowire 601 increases along a direction pointing towards the supporting structure 602. That is, the diameter of the nanowire area 603 of the nanowire 601 is larger than that of the nanowire area 604. The diameter of the nanowire area 604 of the nanowire 601 is larger than that of the nanowire area 605. For example, the diameter of the nanowire areas 603, 604, and 605 may be 80 nm, 50 nm, and 20 nm, respectively.

[0062] It should however be noted that the number of nanowire areas in each nanowire 601 is not limited to three. For example, the number of nanowire areas in each nanowire 601 in the nanowire array in the light collecting device as described herein may range between 2 and 6.

[0063] In one embodiment, each semiconductor nanowire 601 in the nanowire array of the light collecting device 600 at least substantially has the same shape and the same alignment with regard to the supporting structure 602. That is, each nanowire 601 in the nanowire array may have the same number of nanowire areas (e.g., three nanowire areas 603, 604, and 605), and the same stacking arrangement with reference to the supporting structure 602. For example, each nanowire area 603 of the nanowires 601 in the nanowire array may have the same length and the same diameter. Similarly, each nanowire area 604 of the nanowires 601 in the nanowire array may have the same length and the same diameter, and each nanowire area 605 of the nanowires

601 in the nanowire array may have the same length and the same diameter.

[0064] The supporting structured 602 may comprise a semiconductor layer or a metallic layer or a combination of a metallic layer and a semiconductor layer, wherein first ends 606 of the semiconductor nanowires 601 are connected to the supporting structure. The supporting structure

602 may comprise a substrate supporting the semiconductor layer or the metallic layer or the combination of the metallic layer and the semiconductor layer. In one embodiment, the semiconductor nanowires are silicon nanowires. In one embodiment, the semiconductor layer is a silicon layer.

[0065] In one embodiment, for each semiconductor nanowire 601, each semiconductor area may comprise a different semiconductor material from that comprised in another semiconductor area. For example, in a semiconductor nanowire 601, the semiconductor material in the nanowire area 603 may be different from that in the nanowire area 604 or 605. As the different semiconductor materials have different energy bandgaps, the use of different semiconductor materials in different nanowire areas may result in a higher efficiency. The semiconductor material contained in each nanowire area may be, for example, Si, Ge, A1P, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, InSb, or a combination of two or more of these semiconductor materials.

[0066] In one embodiment, each nanowire area has an at least substantially cylindrical shape. For example, each of the nanowire areas 603, 604, and 605 may have an at least substantially cylindrical shape.

[0067] In one embodiment, the semiconductor nanowires 601 respectively extend along a direction aligned at least substantially perpendicular to the supporting structure 602. [0068] In one embodiment, a cross-sectional shape of each nanowire area is respectively concentric or point symmetrical with respect to a longitudinal central axis of the corresponding semiconductor nanowire. In other words, each nanowire area in a semiconductor nanowire is aligned along the same longitudinal central axis. FIG. 6 (b) illustrates the top view of the semiconductor NW 601 according to an exemplary embodiment. For example, the cross- sectional shape of the respective nanowire area 603, 604, and 605 is concentric with respect to the longitudinal central axis 620 of the corresponding semiconductor NW 601.

[0069] In one embodiment, the length of the nanowire areas increases or decreases or remains constant along a direction pointing towards the supporting structure 602.

[0070] FIG. 6(C) illustrates a side view of a semiconductor NW 601 as shown in FIG. 6(a) according to an exemplary embodiment. In this exemplary embodiment, the lengths of nanowire areas 603, 604, and 605 are the same.

[0071] FIG. 6 (d) illustrates a side view of a semiconductor NW 601 as shown in FIG. 6(a) according to an exemplary embodiment. In this exemplary embodiment, the length of the nanowire areas 603, 604, and 605 increases along a direction pointing towards the supporting structure 602.

[0072] FIG. 6(e) illustrates a side view of a semiconductor NW 601 as shown in FIG. 6 (a) according to an exemplary embodiment. In this exemplary embodiment, the length of the nanowire areas 603, 604, and 605 decreases along a direction pointing towards the supporting structure 602.

[0073] In one embodiment, the cross-sectional shape of the semiconductor nanowire areas is circular, polygonal, or elliptical. In one embodiment, the cross-sectional shape of the semiconductor nanowire areas is hexagonal or octagonal [0074] FIG. 6 (f) illustrates a top view of the semiconductor NW 601 shown in FIG. 6 (a) according to one exemplary embodiment. As can be seen, the cross-sectional shape of the semiconductor nanowire areas 603, 604, and 605 is elliptical.

[0075] FIG. 6 (g) illustrates a top view of the semiconductor NW 601 shown in FIG. 6 (a) according to one exemplary embodiment. As can be seen, the cross-sectional shape of the semiconductor nanowire areas 603, 604, and 605 is hexagonal.

[0076] FIG. 6 (h) illustrates a top view of the semiconductor NW 601 shown in FIG. 6 (a) according to one exemplary embodiment. As can be seen, the cross-sectional shape of the semiconductor nanowire areas 603, 604, and 605 is octagonal.

[0077] In one embodiment, the plurality of semiconductor nanowires is arranged in a two- dimensional lattice pattern of semiconductor nanowires. In one embodiment, the lattice pattern is a square lattice pattern. For example a lattice spacing of the lattice pattern may range between about 100 nm and about 600 nm.

[0078] FIG. 6 (i) illustrates the top view of a semiconductor nanowire array shown in FIG. 6 (a) according to one exemplary embodiment. The semiconductor nanowires 601 in the array are arranged in a two-dimensional square lattice pattern in this exemplary embodiment. The lattice spacing 630 may range between around 100 nm to around 600 nm.

[0079] In another embodiment, the plurality of semiconductor nanowires is arranged as a rectangular lattice pattern, a hexagonal lattice pattern, a rhombic lattice pattern, a parallelogrammic lattice pattern, or an irregular pattern.

[0080] FIG. 6 0) illustrates the top view of a semiconductor nanowire array shown in FIG. 6

(a) according to one exemplary embodiment. The semiconductor nanowires 601 in the array are arranged in a two-dimensional rectangular lattice pattern in this exemplary embodiment. [0081] FIG. 6 (k) illustrates the top view of a semiconductor nanowire array shown in FIG. 6 (a) according to one exemplary embodiment. The semiconductor nanowires 601 in the array are arranged in a two-dimensional hexagonal lattice pattern in this exemplary embodiment.

[0082] FIG. 6 (1) illustrates the top view of a semiconductor nanowire array shown in FIG. 6 (a) according to one exemplary embodiment. The semiconductor nanowires 601 in the array are arranged in a two-dimensional rhombic lattice pattern in this exemplary embodiment.

[0083] FIG. 6 (m) illustrates the top view of a semiconductor nanowire array shown in FIG. 6 (a) according to one exemplary embodiment. The semiconductor nanowires 601 in the array are arranged in a two-dimensional parallelogrammic lattice pattern lattice pattern in this exemplary embodiment.

[0084] In one embodiment, the plurality of semiconductor nanowires of the semiconductor nanowire array is made of intrinsic semiconductor and/or doped semiconductor.

[0085] In one embodiment, the plurality of semiconductor nanowires of the semiconductor nanowire array and the semiconductor film are made of intrinsic semiconductor and/or doped semiconductor.

[0086] In one embodiment, the semiconductor core is p-doped and the plurality of semiconductor layers comprises an intrinsic-type layer and an n-type layer to form p-i-n junctions. In one embodiment, the semiconductor core is p-doped and the plurality of semiconductor layers comprises an intrinsic-type layer, an n-type layer and a p-type layer to form p-i-n p-i-n junctions.

[0087] In an alternative embodiment, the semiconductor core is n-doped, and the plurality of semiconductor layers comprises an intrinsic-type layer and a p-type layer to form n-i-p junctions. In one embodiment, the semiconductor core is n-doped, and the plurality of semiconductor layers comprises an intrinsic-type layer, a p-type layer and an n-type layer to form n-i-p-n-i-p junctions.

[0088] In one embodiment, the light collecting device 600 as described herein is used as a solar cell.

[0089] FIG. 7 illustrates the table 700 showing the ultimate efficiency of the inhomogeneous-diameter SiNWs having diameters of 80 nm, 50 nm, 20 nm, along a direction pointing away from the supporting structure. And the absorbance is compared with those of SiNWs having uniform diameters of 20, 50, and 80 nm, respectively. A comparison is also made between the inhomogeneous-diameter SiNWs and that of SiNWs with diameter of 47 nm, which yields the maximum absorption efficiency for uniform diameter SiNWs. As can be seen, the SiNW array with inhomogeneous-diameter SiNWs has the advantages of high optical absorption efficiency in both high and low energy range.

[0090] The nanowire arrays having a plurality of nano wires each having an inhomogeneous- diameter and having two to six nanowire areas were tested, and the simulation results show that the impact of number of nanowire areas on the ultimate efficiency is slight.

[0091] FIG. 8 illustrates the direct fabrication of a nanowire with three nanowire areas on metal substrate which is cost effective and simple. Firstly, a metal substrate 801 is provided. Then a first nanowire area 802 is grown on the substrate 801. Further, a second nanowire area 803 is grown on the first nanowire area 802. Thereafter, a third nanowire area 804 is grown on the second nanowire area 803.

[0092] Overall, a novel approach of using the light collecting devices as described herein for solar cell application is provided. The light collecting device may improve the device performances such as optical absorption efficiency over whole solar spectrum, leading to higher ultimate efficiency. By using inhomogeneous-diameter SiNWs in the light collecting device, significant increase in optical absorption efficiency is observed than those of SiNWs with uniform diameter. The fabrication of the light collecting device may be achieved at low cost due to the simple design and is compatible with silicon-based CMOS technology. Hence, the light collecting device with inhomogeneous diameter SiNWs is especially attractive for industry production. Further, it may have a lighter mass than pure SiNW with uniform diameter yielding maximum ultimate efficiency, although that efficiency is less than the one attained with this propose.

[0093] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

[0094] In this document, the following documents are cited:

1. "Analysis of Optical Absorption in Silicon Nanowire Arrays for Photovoltaic Applications", L. Hu and G. Chen, Nano Letters, 7, 3249 (2007).

2. "Si Nanopillar Array Optimization on Si Thin Films for Solar Energy Harvesting", J.S. Li, H.Y. Yu, S.M. Wong, G. Zhang, X.W. Sun, G. Q. Lo, D.L. Kwong, Applied Physics Letters, 95, 033102 (2009).

Claims

Claims What is claimed is:

1. A light collecting device, comprising:

a semiconductor nanowire array which comprises a plurality of semiconductor nanowires,

a supporting structure supporting the semiconductor nanowire array, wherein each semiconductor nanowire is divided into a plurality of nanowire areas, wherein the diameter of each semiconductor nanowire changes from nanowire area to nanowire area, however remains at least substantially constant within each of the nanowire areas.

2. The device as claimed in claim 1, wherein the supporting structure comprises a semiconductor layer or a metallic layer or a combination of a metallic layer and a semiconductor layer, wherein first ends of the semiconductor nanowires are connected to the supporting structure.

3. The device as claimed in claim 2, wherein the supporting structure comprises a substrate supporting the semiconductor layer or the metallic layer or the combination of the metallic layer and the semiconductor layer.

4. The device as claimed in claim 1, wherein the semiconductor nanowires are silicon nanowires.

5. The device as claimed in claim 2, wherein the semiconductor layer is a silicon layer.

6. The device as claimed in claim 1, wherein each nanowire area has an at least substantially cylindrical shape.

The device as claimed in claim 1, wherein the semiconductor nanowires respectively extend along a direction aligned at least substantially perpendicular to the supporting structure.

The device as claimed in claim 1 , wherein the diameter of each semiconductor increases along a direction pointing towards the supporting structure.

9. The device as claimed in claim 1, wherein each semiconductor nanowire in the nanowire array has at least substantially the same shape and the same alignment with regard to the supporting structure.

10. The device as claimed in claim 1, wherein the number of nanowire areas per nanowire ranges between 2 and 6.

11. The device as claimed in claim 10, wherein each semiconductor nanowire comprises 3 nanowire areas having nanowire diameters of about 20 nm, 50 nm, and 80 nm, respectively.

12. The: device as claimed in any of claims 9-1 1, wherein a cross-sectional shape of each nanowire area is respectively concentric or point symmetrical with respect to a longitudinal central axis of the corresponding semiconductor nanowire.

13. The device as claimed in any of claims 9-11, wherein the length of the nanowire areas increases or decreases or remains constant along a direction pointing towards the supporting structure.

14. The device as claimed in claim 1, wherein the cross-sectional shape of the nanowire areas is Circular, polygonal, or elliptical.

15, The device as claimed in claim 14, wherein the cross-sectional shape of the nanowire areas is hexagonal or octagonal.

16. The device as claimed in claim 1, wherein the plurality of semiconductor nanowires is arranged in a two-dimensional lattice pattern of semiconductor nanowires.

17. The device as claimed in claim 16, wherein the lattice pattern is a square lattice pattern.

18. The device as claimed in claim 17, wherein a lattice spacing of the lattice pattern ranges between about 100 nm and about 600 run.

19. The device as claimed in claim 16, wherein the plurality of semiconductor nanowires is arranged as a rectangular lattice pattern, a hexagonal lattice pattern, a rhombic lattice pattern, or a parallelogrammic lattice pattern.

20. The device as claimed in claim 1, wherein the plurality of semiconductor nanowires of the semiconductor nanowire is made of intrinsic semiconductor and/or doped semiconductor.

The device as claimed in claim 2, wherein the plurality of semiconductor nanowires the semiconductor nanowire array and the semiconductor layer are made of intrinsic semiconductor and/or doped semiconductor,

22. ; The device as claimed in claim 2, wherein each semiconductor nanowire of the semiconductor nanowire array comprises an at least substantially cylindrical doped semiconductor core, covered across the length and the end that is not connected to the supporting structure by a plurality of semiconductor layers.

23. The device as claimed in claim 22, wherein the semiconductor core is p-doped, and the plurality of semiconductor layers comprises an intrinsic-type layer and an n-type layer to form p- i-n junctions

24. The device as claimed in claim 22, wherein the semiconductor core is p-doped, and the plurality of semiconductor layers comprises an intrinsic-type layer, an n-type layer and a p-type layer to form p-i-n-p-i-n junctions.

25. The device as claimed in claim 22, wherein the semiconductor core is n-doped, and the plurality of semiconductor layers comprises an intrinsic-type layer and a p-type layer to form n-i- p junctions.

26. The device as claimed in claim 22, wherein the semiconductor core is n-doped, and the plurality of semiconductor layers comprises an intrinsic-type layer, a p-type layer and an n-type layer to form n-i-p-n-i-p junctions.

27. The device as claimed in claim 1, wherein for each semiconductor nanowire, the semiconductor material contained in a nanowire area is different from that contained in at least one other nanowire area.

28. A solar cell, comprising a device as claimed in any of claims 1-27.