WO2011157031A1

WO2011157031A1 - Clock adjustment method and line card for synchronous digital hierarchy (sdh) system

Info

Publication number: WO2011157031A1
Application number: PCT/CN2010/079363
Authority: WO
Inventors: 彭成
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-06-13
Filing date: 2010-12-01
Publication date: 2011-12-22
Also published as: CN101882967B; CN101882967A

Abstract

A clock adjustment method for a Synchronous Digital Hierarchy (SDH) system is disclosed in the present invention. The method includes that: a line card detects that a clock selection from clock cards changes; then the line card switches the clock by using a task with a low priority, in order to switch to the changed clock for the SDH system. A line card for an SDH system is also disclosed in the present invention. The present invention achieves the effect of smoothly switching the clock in the SDH system.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical synchronous digital transmission technology, and in particular to a clock adjustment method and a line card for a Synchronous Digital Hierarchy (SDH) system. BACKGROUND OF THE INVENTION In an SDH communication system, clock switching and phase adjustment are important because the instability of the clock source affects the service. The current clock chip generally integrates clock selection, clock adjustment, and clock output functions. It can complete the clock adjustment after clock switching, and then output the adjusted clock for use by other modules in the system. FIG. 1 shows a schematic diagram of clock adjustment for an SDH system according to the related art. The left side is the clock card (Clock Card), including the clock card 1 and the clock card 2, respectively providing two system clocks to the right line card (Linecard-N, there are 4 multi-line cards in the system need to use the clock, The figure shows that the clock module 3 of one of the line cards performs clock selection and frequency multiplication and then outputs. In addition, the two system clocks generated by the clock card 1 and the clock card 2 are respectively divided by the frequency dividing modules 1 and 2. The system frame header 1 and the system frame header 2 are generated, and are also sent to the system frame header selection module 4 of the line card for selection. The clock output from the clock module 3 passes through the system frame header regeneration module 5 to generate a regenerated frame header for use by the service processing on the line card. If the regenerative frame header exceeds a certain threshold of the selected system frame header, it will be adjusted by adjusting the system frame header after the regenerated frame header exceeds a certain threshold of the system frame header, and performing in the software background. The phase of the clock is adjusted so that the regenerated frame header is realigned with the system frame header. In the above process, the clock card 1 and the clock card 2 respectively provide two system clocks to the clock module 3 of the Linecard-N line card for clock selection and multiplication, and the two system clocks are respectively divided by the frequency generation system. Frame header 1 and system frame header 2 are also sent to the line card for selection. The output clock will generate a regenerated frame header for use by the line processing on the line card. If the regenerated frame header exceeds the threshold of the selected system frame header, then the adjusted replay frame header is realigned with the system frame header. But the inventor found that for a large SDH system, if this method is used, once When a clock switch occurs, all modules that use the clock will complete the clock switch at the same time, which will impact the service of the entire system and affect the stability of the entire system. SUMMARY OF THE INVENTION In order to solve the problem of instability caused by clock switching to the entire SDH system, the present invention proposes a clock adjustment method for an SDH system and a line card. According to an aspect of the present invention, a clock adjustment method for a synchronous digital series SDH system is provided, comprising: a line card detecting a change in clock selection from a clock card; and a line card processing a clock using a low priority task Switch to switch the SDH system to the changed clock. According to another aspect of the present invention, a line card for synchronizing a digital series SDH system is provided, comprising: a detecting module for detecting a change in clock selection from a clock card; and a switching module for using low The priority task handles the clock switch to switch the SDH system to the changed clock. The clock adjustment method and the line card set the clock switching to the priority of the clock, so that the other tasks of the system can be preferentially executed, so that the clock switching does not preempt the CPU resources, and the clock switching is unstable to the entire SDH system. The problem, in turn, achieves the effect of the SDH system smoothly switching the clock. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram showing clock adjustment for an SDH system according to the related art; FIG. 2 is a flow chart showing a clock adjustment method according to an embodiment of the present invention; FIG. A block diagram of a line card of an embodiment of the invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict.

The SDH system uses multiple clock cards to provide clocks to all line cards that carry services. Both clock cards and line cards can use embedded systems (ie, boards). 2 is a flowchart of a clock adjustment method according to an embodiment of the present invention, including: Step S10, the line card detects that a clock selection from a clock card changes; and in step S20, the line card uses a low priority task. Handle clock switching to switch the SDH system to the changed clock. The clock adjustment method sets the clock switching to the priority of the clock, so that the other tasks of the system can be preferentially executed, so that the clock switching does not preempt the CPU resources, and the problem that the clock switching will bring instability to the entire SDH system is achieved. The SDH system smoothly switches the clock effect. For example, the system clock of the two clock cards is divided to generate the system frame header, and the system frame header selection is provided to all the line cards in real time, and the clock module of the line card is provided with a clock selection. The clock card detects the clock switching in real time. If a clock switch occurs or a clock selection request command is received, a clock switch command is sent to the line card; otherwise, it is not sent. After all the line cards of the SDH system detect the clock switching command, they use low priority tasks to handle clock switching. In this way, for each line card, the execution time switching has different delays instead of simultaneous execution, thereby avoiding the impact on the large-scale SDH system. Preferably, step S10 comprises: the line card detecting the clock selection from the clock card using a high priority task. The preferred method sets the detection task to a high priority, so that the clock selection can be obtained as quickly as possible, so that the clock switching is ready as soon as possible. The detection itself does not consume too much resources, so the preferred method does not affect the stability of the system. Preferably, in the above method, before step S10, the method further includes: the line card creates a high priority task for detecting the clock selection at the time of power-on initialization, and sets a task of performing high priority periodically. This setting method is simple and easy to perform, and the execution efficiency is high. Preferably, in the foregoing method, before step S10, the method further comprises: creating, by the line card, a low priority task for processing clock switching during power-on initialization. This setting method is simple and easy to perform, and the execution efficiency is high. For example, during power-on initialization, the line card creates a priority clock adjustment task and receives a clock switch command through a high-priority task for clock selection. The high priority receive task timing detects the clock selection command from the clock module. If the clock selection has not changed, go directly to the next cycle detection cycle. If the clock selection has changed, set the system frame header, and select the clock after the current switch, and then hand it to the clock adjustment task of the processing priority to process and process The process requires a delay to ensure that the low-priority clock adjustment task does not take up CPU time for a long time during the clock adjustment process. Preferably, in the foregoing method, after the step S20 is gathered, the method further includes: the line card generating a reproduction frame header from the switched clock, and selecting the line card from the plurality of system frame headers from the plurality of clock cards. System frame header; monitors the offset between the resulting regenerated frame header and the system frame header. Preferably, in the foregoing method, after monitoring the offset between the obtained regenerated frame header and the system frame header, the method further includes: monitoring the offset exceeding the threshold; adjusting the phase of the clock of the SDH system, Reduce the offset. This preferred method can implement clock synchronization of the SDH system. For example, the line card can monitor the offset between the current playback frame header and the system frame header after the clock is switched. If the threshold is exceeded, the phase of the output clock will be adjusted to reduce the offset between the two headers, otherwise no adjustment is required and exit. Preferably, in the method of any of the above, the priority of the task for processing the priority of the clock switching is the lowest priority. Obviously, setting the clock switch to the lowest priority has the least impact on the SDH system, making the system more stable. The following preferred embodiment combines the technical solutions of the foregoing embodiments, and corresponds to the Linecard-N, which may be a service processing module. Here, a cross-board is taken as an example, and a system frame header selection module and a clock adjustment module are provided on the cross-board. For the cross-connect board, the specific implementation steps are as follows: Step 1: During the power-on process, create the clock adjustment process with the highest priority and 20MS timing. The initialization report is sent to the clock board to request the current clock selection signal, and the clock selection of the configuration cross board is initialized by the received clock board command. Step 2: Receive the clock switch command sent by the clock board in real time. If the current clock selection of the cross board does not change, it will not be processed. If the clock selection changes, first set the clock system frame header selection, then set the clock selection, and then notify The lowest priority clock adjustment task is clocked. The clock adjustment method can use the threshold control method: After the test finds that the offset is less than 60ns (nanoseconds) or more than 80ns, the error will occur, then you can set a high threshold of 75ns and a threshold of 65ns. If more than 75 ns or less than 65 ns is detected, the phase of the clock needs to be adjusted. Each adjustment is positive or negative, and the method of continuous loop adjustment is used until the offset of the frame header is found to be 65 ns. Between the 75ns threshold, the loop is exited, indicating that the entire clock adjustment is complete. 3 is a block diagram showing a line card according to an embodiment of the present invention, including: a detecting module 10 for detecting a change in clock selection from a clock card; and a switching module 20 for processing with a low priority task Clock switching to switch the SDH system to the changed clock. The line card sets the clock switch to a low priority, which ensures that the other tasks of the system are executed preferentially, so that the clock switching does not preempt the CPU resources, and the problem that the clock switching will bring instability to the entire SDH system is achieved. The SDH system smoothly switches the clock effect. Preferably, the detection module detects the clock selection from the clock card using a high priority task. In this way, the clock selection can be obtained as quickly as possible, so that the clock switching is ready as soon as possible. Preferably, in the above line card, the method further includes: a system frame header regeneration module, configured to generate a reproduction frame header from the switched clock; and a system frame header selection module, configured to use multiple systems from the plurality of clock cards The system header of the line card is selected in the frame header; the detecting module is configured to monitor the offset between the obtained regenerated frame header and the system frame header; and the adjustment module is configured to detect that the offset exceeds the threshold, Adjust the phase of the SDH system's clock to reduce the offset. The preferred line card can implement clock synchronization of the SDH system. As can be seen from the above description, the foregoing embodiments of the present invention can ensure that clock switching does not affect services, and that clock adjustment can be performed in the background after clock switching, thereby improving system operation efficiency, which can be said to ensure service transmission. The reliability of the system increases the efficiency of the system. Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device and, in some cases, may be different from the order herein. The steps shown or described are performed, or they are separately fabricated into individual integrated circuit modules, or a plurality of modules or steps are fabricated as a single integrated circuit module. Thus, the invention is not limited to any particular hardware and software. Combine. The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the scope of the present invention are intended to be included within the scope of the present invention.

Claims

Claim

A clock adjustment method for a synchronous digital series SDH system, comprising: the line card detecting that a clock selection from a clock card changes;

The line card processes clock switching using a prioritized task to switch the SDH system to the changed clock.

2. The method according to claim 1, wherein the line card detects that a change in clock selection from the clock card comprises:

The line card uses a high priority task to detect clock selections from the clock card.

The method according to claim 2, wherein before the line card detects that the clock selection from the clock card changes, the method further includes:

The line card creates the high priority task for detecting clock selection at power up initialization and sets the high priority task to be performed periodically.

The method according to claim 1, wherein before the line card detects that the clock selection from the clock card changes, the method further includes:

The line card creates the task for handling the priority of clock switching at power-on initialization.

The method according to claim 1, wherein the line card uses a low priority task to process a clock switch to switch the SDH system to the changed clock, and further includes:

The line card generates a reproduction frame header from the switched clock, and selects a system frame header of the line card from a plurality of system frame headers from the plurality of the clock cards;

An offset between the resulting regenerated frame header and the system frame header is monitored.

The method according to claim 5, wherein, after monitoring the obtained offset between the regenerated frame header and the system frame header, the method further includes:

Monitoring that the offset exceeds a threshold;

The phase of the clock of the SDH system is adjusted to reduce the offset.

The method according to any one of claims 1-6, wherein the priority of the low priority task for processing clock switching is the lowest priority.

8. A line card for synchronizing a digital series SDH system, comprising:

a detecting module, configured to detect a clock selection change from the clock card;

And a switching module, configured to process a clock switch using a low priority task to switch the SDH system to the changed clock.

9. The line card of claim 8, wherein the detection module is configured to detect a clock selection from the clock card using a high priority task.

10. The line card of claim 8, further comprising:

a system frame header regeneration module, configured to generate a reproduction frame header from the switched clock; a system frame header selection module, configured to select a system for obtaining the line card from a plurality of system frame headers from the plurality of clock cards Frame header

a detecting module, configured to monitor an offset between the obtained regenerated frame header and the system frame header;

And an adjustment module, configured to adjust a phase of a clock of the SDH system to reduce the offset when the offset exceeds a threshold.