WO2011106071A2 - Source follower input buffer - Google Patents

Source follower input buffer Download PDF

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Publication number
WO2011106071A2
WO2011106071A2 PCT/US2010/061823 US2010061823W WO2011106071A2 WO 2011106071 A2 WO2011106071 A2 WO 2011106071A2 US 2010061823 W US2010061823 W US 2010061823W WO 2011106071 A2 WO2011106071 A2 WO 2011106071A2
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WO
WIPO (PCT)
Prior art keywords
coupled
nmos transistor
capacitor
source
circuit
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Ceased
Application number
PCT/US2010/061823
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French (fr)
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WO2011106071A3 (en
Inventor
Nitin Agarwal
Visvesvaraya A. Pentakota
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Texas Instruments Japan Ltd
Texas Instruments Inc
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Texas Instruments Japan Ltd
Texas Instruments Inc
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Priority to CN201080064612.7A priority Critical patent/CN102771052B/en
Priority to JP2012554996A priority patent/JP5911434B2/en
Publication of WO2011106071A2 publication Critical patent/WO2011106071A2/en
Publication of WO2011106071A3 publication Critical patent/WO2011106071A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element

Definitions

  • This relates generally to buffers and, more particularly, to source follower buffers with a reduced input capacitance load.
  • circuit 100 generally designates conventional input circuitry for an analog-to-digital converter (ADC).
  • ADC analog-to-digital converter
  • Circuit 100 is generally described in co-pending Patent Application Serial No. 12/199,804, which is hereby incorporated by reference for all purposes.
  • circuit 100 generally comprises a transmission medium (represented by inductor LI), buffer 102 and sample-and-hold (S/H) circuit 104.
  • Buffer 102 generally comprises NMOS transistor Ql (which is coupled to inductor LI), cascoded NMOS transistors Q2 and Q3 (which receive bias voltages NCAS and NBIAS at their respective gates), and capacitor CI.
  • S/H circuit 102 is generally represented (for the sake of simplicity of explanation) as resistor RS, sampling switch SS, and sampling capacitor CS.
  • capacitor CI (which is generally the same size as capacitor CS) provides a signal current for the load (by way of the transistor Q2), while the source follower (transistor Ql) is able to generally define the voltage for the switching load (S/H circuit 104). It is desired to keep the capacitor CI small as it loads the "off-chip" driver. This will mean that transistor Ql will also provide some portion of signal current.
  • An example embodiment of the invention accordingly, provides an apparatus.
  • the apparatus comprises a biasing circuit having: a first capacitor having a first capacitance that receives a first portion of an input signal; and a pair of cascoded transistors, wherein the first capacitor is coupled to a node between the cascaded transistors, and wherein a first cascoded transistor of the pair of cascoded receives a first bias voltage, and wherein a second cascoded transistor of the pair of cascoded transistors receives a second bias voltage; a switched capacitor circuit having a second capacitance; and a source follower buffer that is coupled to the biasing circuit and the switched capacitor circuit, wherein the source follower receives the second bias voltage and receives a second portion of the input signal, and wherein the source follower includes a second capacitor having a third capacitance, and wherein the ratio of first capacitance to the combined second and third capacitances is at least one
  • the source follower buffer further comprises a plurality of source follower buffers that are each coupled to the biasing circuit and that each receive the second portion of the input signal.
  • the first cascoded transistor further comprises a first NMOS transistor that receives the first bias voltage at its gate, and wherein the second cascoded transistor is a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and to the drain of the first NMOS transistor at its gate, and wherein the first capacitor is coupled to the drain of the second NMOS transistor.
  • the biasing circuit further comprises a current source that is coupled to the drain of the first NMOS transistor.
  • the source follower buffer further comprises: a third NMOS transistor that receives the second portion of the input signal at its gate and that is coupled to the second capacitor at its source; and a fourth NMOS transistor that is coupled to the gate of the second NMOS transistor at its gate and that is coupled to the source of the third NMOS transistor at is drain.
  • the body of the third NMOS transistor that receives the second portion of the input signal at its gate and that is coupled to the second capacitor at its source
  • a fourth NMOS transistor that is coupled to the gate of the second NMOS transistor at its gate and that is coupled to the source of the third NMOS transistor at is drain.
  • NMOS transistor is coupled to the second capacitor.
  • the ratio is 10: 1.
  • the switch capacitor circuit is a sample-and-hold (S/H) circuit.
  • an apparatus comprising a biasing circuit having: a first capacitor having a first capacitance that receives a first portion of an input signal; and a pair of cascoded transistors, wherein the first capacitor is coupled to a node between the cascaded transistors, and wherein a first cascoded transistor of the pair of cascoded receives a first bias voltage, and wherein a second cascoded transistor of the pair of cascoded transistors receives a second bias voltage; a source follower buffer that is coupled to the biasing circuit so as to receive the second bias voltage and that receives a second portion of the input signal, wherein the source follower includes a second capacitor having a second capacitance; an S/H circuit that is coupled to the source follower buffer having a third capacitance, wherein the ratio of the first capacitance to the combined second and third capacitances is at least one; an analog-to-digital converter (ADC) pipeline that is coupled to the
  • the source follower buffer further comprises a plurality of source follower buffers that are each coupled to the biasing circuit and that each receive the second portion of the input signal
  • the S/H circuit further comprises a plurality of S/H circuit that are each coupled to at least one of the source follower buffers
  • the ADC pipeline further comprises a plurality of ADC pipelines that are each coupled to at least one of the S/H circuits.
  • the apparatus further comprises a multiplexer that is coupled to each ADC pipeline.
  • an apparatus comprising a biasing circuit having: a current source; a first NMOS transistor that is coupled to the current source at its drain and that receives a bias voltage at its gate; a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and that is coupled to the drain of the first NMOS transistor at its gate; and a first capacitor having a first capacitance that receives a first portion of an input signal and that is coupled to the drain of the second NMOS transistor; a plurality of source follower buffers, wherein each source follower buffer includes: a third NMOS transistor that receives a second portion of the input signal at its gate; a fourth NMOS transistor that is coupled to the source of the third NMOS transistor at its drain and that is coupled to gate of the second NMOS transistor at its gate; and a second capacitor having a second capacitance that is coupled to the source of the third NMOS capacitor; a plurality
  • NMOS transistor is coupled to the second capacitor.
  • FIG. 1 is a circuit diagram of conventional input circuitry for an ADC
  • FIG. 2 is a block diagram of an interleaved ADC in accordance with an example embodiment of the invention.
  • FIG. 3 is a circuit diagram of a portion of the ADC of FIG. 2.
  • FIG. 2 illustrates an interleaved analog-to-digital converter (ADC) 200 in accordance with an example embodiment of the invention.
  • ADC analog-to-digital converter
  • an analog input signal AIN is provided to buffers 202-1 to 202-n (which are each coupled to biasing circuit 212).
  • the output from each buffer 202-1 to 202-n is coupled to a corresponding s ample- and-hold (S/H) circuit 204-1 to 204-n, so that the input signal AIN can be sampled and provided to the corresponding ADC pipeline 206-1 to 206-n for conversion.
  • S/H ample- and-hold
  • Clocking circuit 210 which is coupled to the S/H circuits 204-1 to 204-n and ADC pipelines 206-1 to 206-n, provides timings signals to sample the input signal AIN and convert it to a digital signal.
  • the interleaved digital output signals from ADC pipelines 206- 1 to 206-n are then multiplexed by multiplexer (or mux) 208 to generate digital output signal DOUT.
  • FIG. 3 provides a more detailed view of the bias circuit 212, buffers 202-1 and
  • the biasing circuit 212 generally comprises capacitor CIN, NMOS transistors Q8 and Q9, and current source 302.
  • Buffer 202-1 generally comprises NMOS transistors Q4 and Q5 and capacitor CB1
  • buffer 202-2 generally comprises NMOS transistors Q6 and Q7 and capacitor CB2.
  • portions (INP and INM) of the input signal AIN are provided to the biasing circuit 212 and buffers 202-1 and 202-2 so that the input signal AIN can be sampled by the S/H circuits 204-1 and 204-2.
  • Current source 302 provides a current to the drain of NMOS transistor (which receives a bias voltage NCAS at its gate) and provides a bias voltage NBIASP to the gate of NMOS transistor Q9.
  • Portion INM is provided to the node between cascoded NMOS transistors Q8 and Q9 through capacitor CIN. This enables a signal current to flow from ground through transistor Q9 and capacitor CIN.
  • This signal current is mirrored by each of NMOS transistors Q5 and Q7 so that it can be provided to capacitors CB 1 and CB2. Additionally, portion INP is provided to the gates of NMOS transistors Q4 and Q6 (which each operate as source followers) and do not generally provide the signal current. Thus, this input circuitry is able to supply voltages and currents to S/H circuit 204-1 and 204-2 with improved linearity.
  • capacitors CIN, CB1, CB2, CS1, and CS2 are also generally scaled.
  • the combined capacitances each of capacitors CB 1 and CS1 and capacitors and CB2 and CS2 are at least the same as or smaller than the capacitance of capacitor CIN (which operates as a compensation capacitor).
  • the ratio of the combined capacitance of capacitors CB1 and CS1 and the capacitance of capacitor CIN can be 1: 10.
  • capacitor CIN is coupled to a very low impedance node (which has a small non-linear voltage) so as to generally eliminated a source of non-linearity over other conventional circuits.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Amplifiers (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

An input source follower buffer and biasing circuitry for an analog-to-digital converter (ADC) provides improved linearity. Portions INP, INM of an input signal are input to a biasing circuit 212 and buffers 202-1, 202-2 for sampling by sample-and-hold (S/H) circuits 204-1, 204- 2. Current source 302 provides a current to the drain of NMOS transistor Q8 whose gate receives a bias voltage NCAS and provides a bias voltage NBIASP to the gate of NMOS transistor Q9. Portion INM is provided through capacitor CIN to a node between cascaded transistors Q8, Q9. This enables a signal current to flow from ground through second transistor (Q9) and capacitor CIN. The signal current is mirrored by each NMOS transistor Q5, Q7 and provided to capacitors CBl, CB2. Portion INP is provided to the gates of NMOS transistors Q4, Q6 (which each operate as source followers) and do not generally provide the signal current. The input circuitry is able to supply voltages and currents to S/H circuit 204-1, 204-2 with improved linearity.

Description

SOURCE FOLLOWER INPUT BUFFER
[0001] This relates generally to buffers and, more particularly, to source follower buffers with a reduced input capacitance load.
BACKGROUND
[0002] Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates conventional input circuitry for an analog-to-digital converter (ADC). Circuit 100 is generally described in co-pending Patent Application Serial No. 12/199,804, which is hereby incorporated by reference for all purposes. As shown, circuit 100 generally comprises a transmission medium (represented by inductor LI), buffer 102 and sample-and-hold (S/H) circuit 104. Buffer 102 generally comprises NMOS transistor Ql (which is coupled to inductor LI), cascoded NMOS transistors Q2 and Q3 (which receive bias voltages NCAS and NBIAS at their respective gates), and capacitor CI. S/H circuit 102 is generally represented (for the sake of simplicity of explanation) as resistor RS, sampling switch SS, and sampling capacitor CS.
[0003] With many conventional buffers, the "off-chip" driver that drives transistor Ql
(which is generally a source follower) can drive (moderate) continuous time loads but not switching loads (which are present with the use of S/H circuit 104). In this configuration, capacitor CI (which is generally the same size as capacitor CS) provides a signal current for the load (by way of the transistor Q2), while the source follower (transistor Ql) is able to generally define the voltage for the switching load (S/H circuit 104). It is desired to keep the capacitor CI small as it loads the "off-chip" driver. This will mean that transistor Ql will also provide some portion of signal current. This configuration, with this additional constraint of small capacitor CI, can not only be problematic with respect to its inability to drive switching load but can also significantly and adversely impact the spurious free dynamic range (SFDR) of an interleaved ADC when used in an interleaved ADC, which uses many buffers to drive multiple S/H circuits. Therefore, there is a need for a circuit with improved performance. [0004] Some other conventional circuits are described in: U.S. Patent No. 4,634,993;
U.S. Patent No. 5,764,175; U.S. Patent No. 5,872,469; U.S. Patent No. 6,255,865; U.S. Patent No. 7,385,427; U.S. Pre-Grant Publ. No. 20090206885; and PCT Publ. No. WO07/093475.
SUMMARY
[0005] An example embodiment of the invention, accordingly, provides an apparatus.
The apparatus comprises a biasing circuit having: a first capacitor having a first capacitance that receives a first portion of an input signal; and a pair of cascoded transistors, wherein the first capacitor is coupled to a node between the cascaded transistors, and wherein a first cascoded transistor of the pair of cascoded receives a first bias voltage, and wherein a second cascoded transistor of the pair of cascoded transistors receives a second bias voltage; a switched capacitor circuit having a second capacitance; and a source follower buffer that is coupled to the biasing circuit and the switched capacitor circuit, wherein the source follower receives the second bias voltage and receives a second portion of the input signal, and wherein the source follower includes a second capacitor having a third capacitance, and wherein the ratio of first capacitance to the combined second and third capacitances is at least one
[0006] In accordance with an example embodiment of the invention, the source follower buffer further comprises a plurality of source follower buffers that are each coupled to the biasing circuit and that each receive the second portion of the input signal.
[0007] In accordance with an example embodiment of the invention, the first cascoded transistor further comprises a first NMOS transistor that receives the first bias voltage at its gate, and wherein the second cascoded transistor is a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and to the drain of the first NMOS transistor at its gate, and wherein the first capacitor is coupled to the drain of the second NMOS transistor.
[0008] In accordance with an example embodiment of the invention, the biasing circuit further comprises a current source that is coupled to the drain of the first NMOS transistor.
[0009] In accordance with an example embodiment of the invention, the source follower buffer further comprises: a third NMOS transistor that receives the second portion of the input signal at its gate and that is coupled to the second capacitor at its source; and a fourth NMOS transistor that is coupled to the gate of the second NMOS transistor at its gate and that is coupled to the source of the third NMOS transistor at is drain. [0010] In accordance with an example embodiment of the invention, the body of the third
NMOS transistor is coupled to the second capacitor.
[0011] In accordance with an example embodiment of the invention, the ratio is 10: 1.
[0012] In accordance with an example embodiment of the invention, the switch capacitor circuit is a sample-and-hold (S/H) circuit.
[0013] In accordance with an example embodiment of the invention, an apparatus is provided. The apparatus comprises a biasing circuit having: a first capacitor having a first capacitance that receives a first portion of an input signal; and a pair of cascoded transistors, wherein the first capacitor is coupled to a node between the cascaded transistors, and wherein a first cascoded transistor of the pair of cascoded receives a first bias voltage, and wherein a second cascoded transistor of the pair of cascoded transistors receives a second bias voltage; a source follower buffer that is coupled to the biasing circuit so as to receive the second bias voltage and that receives a second portion of the input signal, wherein the source follower includes a second capacitor having a second capacitance; an S/H circuit that is coupled to the source follower buffer having a third capacitance, wherein the ratio of the first capacitance to the combined second and third capacitances is at least one; an analog-to-digital converter (ADC) pipeline that is coupled to the S/H circuit; and clocking circuitry that is coupled to the S/H circuit and the ADC pipeline.
[0014] In accordance with an example embodiment of the invention, the source follower buffer further comprises a plurality of source follower buffers that are each coupled to the biasing circuit and that each receive the second portion of the input signal, and wherein the S/H circuit further comprises a plurality of S/H circuit that are each coupled to at least one of the source follower buffers, and wherein the ADC pipeline further comprises a plurality of ADC pipelines that are each coupled to at least one of the S/H circuits.
[0015] In accordance with an example embodiment of the invention, the apparatus further comprises a multiplexer that is coupled to each ADC pipeline.
[0016] In accordance with an example embodiment of the invention, an apparatus is provided. The apparatus comprises a biasing circuit having: a current source; a first NMOS transistor that is coupled to the current source at its drain and that receives a bias voltage at its gate; a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and that is coupled to the drain of the first NMOS transistor at its gate; and a first capacitor having a first capacitance that receives a first portion of an input signal and that is coupled to the drain of the second NMOS transistor; a plurality of source follower buffers, wherein each source follower buffer includes: a third NMOS transistor that receives a second portion of the input signal at its gate; a fourth NMOS transistor that is coupled to the source of the third NMOS transistor at its drain and that is coupled to gate of the second NMOS transistor at its gate; and a second capacitor having a second capacitance that is coupled to the source of the third NMOS capacitor; a plurality of S/H circuits, wherein each S/H circuit is coupled to at least one of the source follower buffers at the source of its third NMOS transistor, and wherein each S/H circuit has a third capacitance, and wherein the ratios of the first capacitance to the combined second and third capacitances for each S/H circuits and its corresponding follower buffer is at least one; a plurality of ADC pipelines, wherein each ADC pipeline is coupled to at least one of the S/H circuits; a multiplexer that is coupled to each ADC pipeline; and clocking circuitry that is coupled to each S/H circuit and each ADC pipeline.
[0017] In accordance with an example embodiment of the invention, the body of the third
NMOS transistor is coupled to the second capacitor.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Example embodiments are described with reference to accompanying drawings, wherein:
[0019] FIG. 1 is a circuit diagram of conventional input circuitry for an ADC;
[0020] FIG. 2 is a block diagram of an interleaved ADC in accordance with an example embodiment of the invention; and
[0021] FIG. 3 is a circuit diagram of a portion of the ADC of FIG. 2.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0022] FIG. 2 illustrates an interleaved analog-to-digital converter (ADC) 200 in accordance with an example embodiment of the invention. In operation, an analog input signal AIN is provided to buffers 202-1 to 202-n (which are each coupled to biasing circuit 212). The output from each buffer 202-1 to 202-n is coupled to a corresponding s ample- and-hold (S/H) circuit 204-1 to 204-n, so that the input signal AIN can be sampled and provided to the corresponding ADC pipeline 206-1 to 206-n for conversion. Clocking circuit 210, which is coupled to the S/H circuits 204-1 to 204-n and ADC pipelines 206-1 to 206-n, provides timings signals to sample the input signal AIN and convert it to a digital signal. The interleaved digital output signals from ADC pipelines 206- 1 to 206-n are then multiplexed by multiplexer (or mux) 208 to generate digital output signal DOUT.
[0023] FIG. 3 provides a more detailed view of the bias circuit 212, buffers 202-1 and
202-2, and S/H circuits 204-1 and 204-2. For the sake of simplicity, input circuitry for two ADC pipelines is shown. Additionally, for the sake of simplicity, S/H circuits 204-1 and 204-2 are represented by resistors Rl and R2, sampling switches SSI and SS2, and sampling capacitors CS1 and CS2. The biasing circuit 212 generally comprises capacitor CIN, NMOS transistors Q8 and Q9, and current source 302. Buffer 202-1 generally comprises NMOS transistors Q4 and Q5 and capacitor CB1, while buffer 202-2 generally comprises NMOS transistors Q6 and Q7 and capacitor CB2.
[0024] In operation, portions (INP and INM) of the input signal AIN are provided to the biasing circuit 212 and buffers 202-1 and 202-2 so that the input signal AIN can be sampled by the S/H circuits 204-1 and 204-2. Current source 302 provides a current to the drain of NMOS transistor (which receives a bias voltage NCAS at its gate) and provides a bias voltage NBIASP to the gate of NMOS transistor Q9. Portion INM is provided to the node between cascoded NMOS transistors Q8 and Q9 through capacitor CIN. This enables a signal current to flow from ground through transistor Q9 and capacitor CIN. This signal current is mirrored by each of NMOS transistors Q5 and Q7 so that it can be provided to capacitors CB 1 and CB2. Additionally, portion INP is provided to the gates of NMOS transistors Q4 and Q6 (which each operate as source followers) and do not generally provide the signal current. Thus, this input circuitry is able to supply voltages and currents to S/H circuit 204-1 and 204-2 with improved linearity.
[0025] The capacitance of capacitors CIN, CB1, CB2, CS1, and CS2 are also generally scaled. Typically, the combined capacitances each of capacitors CB 1 and CS1 and capacitors and CB2 and CS2 are at least the same as or smaller than the capacitance of capacitor CIN (which operates as a compensation capacitor). For example, the ratio of the combined capacitance of capacitors CB1 and CS1 and the capacitance of capacitor CIN can be 1: 10. It should also be noted that capacitor CIN is coupled to a very low impedance node (which has a small non-linear voltage) so as to generally eliminated a source of non-linearity over other conventional circuits. Additionally, signal current through an input is reduced, which also helps reduce electromagnetic interference that can become a limiting factor at high speeds. [0026] Embodiments having different combinations of one or more of the features or steps described in the context of example embodiments having all or just some of such features or steps are intended to be covered hereby. Those skilled in the art will appreciate that many other embodiments and variations are also possible within the scope of the claimed invention.

Claims

CLAIMS What is claimed is:
1. An apparatus comprising:
a biasing circuit having:
a first capacitor having a first capacitance that receives a first portion of an input signal; and
a pair of cascoded transistors, wherein the first capacitor is coupled to a node between the cascaded transistors, and wherein a first cascoded transistor of the pair of cascoded receives a first bias voltage, and wherein a second cascoded transistor of the pair of cascoded transistors receives a second bias voltage;
a switched capacitor circuit having a second capacitance; and
a source follower buffer that is coupled to the biasing circuit and the switched capacitor circuit, wherein the source follower receives the second bias voltage and receives a second portion of the input signal, and wherein the source follower includes a second capacitor having a third capacitance, and wherein the ratio of first capacitance to the combined second and third capacitances is at least one.
2. The apparatus of Claim 1, wherein the source follower buffer further comprises a plurality of source follower buffers that are each coupled to the biasing circuit and that each receive the second portion of the input signal.
3. The apparatus of Claim 1, wherein the first cascoded transistor further comprises a first NMOS transistor that receives the first bias voltage at its gate, and wherein the second cascoded transistor is a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and to the drain of the first NMOS transistor at its gate, and wherein the first capacitor is coupled to the drain of the second NMOS transistor.
1
4. The apparatus of Claim 3, wherein the biasing circuit further comprises a current source that is coupled to the drain of the first NMOS transistor.
5. The apparatus of Claim 4, wherein the source follower buffer further comprises: a third NMOS transistor that receives the second portion of the input signal at its gate and that is coupled to the second capacitor at its source; and
a fourth NMOS transistor that is coupled to the gate of the second NMOS transistor at its gate and that is coupled to the source of the third NMOS transistor at is drain.
6. The apparatus of Claim 5, wherein the body of the third NMOS transistor is coupled to the second capacitor.
7. The apparatus of Claim 6, wherein the ratio is 10: 1.
8. The apparatus of Claim 1, wherein the switch capacitor circuit is a sample-and- hold (S/H) circuit.
9. An apparatus comprising:
a biasing circuit having:
a first capacitor having a first capacitance that receives a first portion of an input signal; and
a pair of cascoded transistors, wherein the first capacitor is coupled to a node between the cascaded transistors, and wherein a first cascoded transistor of the pair of cascoded receives a first bias voltage, and wherein a second cascoded transistor of the pair of cascoded transistors receives a second bias voltage;
a source follower buffer that is coupled to the biasing circuit so as to receive the second bias voltage and that receives a second portion of the input signal, wherein the source follower includes a second capacitor having a second capacitance;
2 an S/H circuit that is coupled to the source follower buffer having a third capacitance, wherein the ratio of the first capacitance to the combined second and third capacitances is at least one;
an analog-to-digital converter (ADC) pipeline that is coupled to the S/H circuit; and clocking circuitry that is coupled to the S/H circuit and the ADC pipeline.
10. The apparatus of Claim 9, wherein the source follower buffer further comprises a plurality of source follower buffers that are each coupled to the biasing circuit and that each receive the second portion of the input signal, and wherein the S/H circuit further comprises a plurality of S/H circuit that are each coupled to at least one of the source follower buffers, and wherein the ADC pipeline further comprises a plurality of ADC pipelines that are each coupled to at least one of the S/H circuits.
11. The apparatus of Claim 10, wherein the apparatus further comprises a multiplexer that is coupled to each ADC pipeline.
12. The apparatus of Claim 9, wherein the first cascoded transistor further comprises a first NMOS transistor that receives the first bias voltage at its gate, and wherein the second cascoded transistor is a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and to the drain of the first NMOS transistor at its gate, and wherein the first capacitor is coupled to the drain of the second NMOS transistor.
13. The apparatus of Claim 12, wherein the biasing circuit further comprises a current source that is coupled to the drain of the first NMOS transistor.
14. The apparatus of Claim 13, wherein the source follower buffer further comprises: a third NMOS transistor that receives the second portion of the input signal at its gate and that is coupled to the second capacitor at its source; and
3 a fourth NMOS transistor that is coupled to the gate of the second NMOS transistor at its gate and that is coupled to the source of the third NMOS transistor at is drain.
15. An apparatus comprising:
a biasing circuit having:
a current source;
a first NMOS transistor that is coupled to the current source at its drain and that receives a bias voltage at its gate;
a second NMOS transistor that is coupled to the source of the first NMOS transistor at its drain and that is coupled to the drain of the first NMOS transistor at its gate; and a first capacitor having a first capacitance that receives a first portion of an input signal and that is coupled to the drain of the second NMOS transistor;
a plurality of source follower buffers, wherein each source follower buffer includes:
a third NMOS transistor that receives a second portion of the input signal at its gate;
a fourth NMOS transistor that is coupled to the source of the third NMOS transistor at its drain and that is coupled to gate of the second NMOS transistor at its gate; and a second capacitor having a second capacitance that is coupled to the source of the third NMOS capacitor;
a plurality of S/H circuits, wherein each S/H circuit is coupled to at least one of the source follower buffers at the source of its third NMOS transistor, and wherein each S/H circuit has a third capacitance, and wherein the ratios of the first capacitance to the combined second and third capacitances for each S/H circuits and its corresponding follower buffer is at least one; a plurality of ADC pipelines, wherein each ADC pipeline is coupled to at least one of the S/H circuits;
a multiplexer that is coupled to each ADC pipeline; and
clocking circuitry that is coupled to each S/H circuit and each ADC pipeline.
4
PCT/US2010/061823 2010-02-24 2010-12-22 Source follower input buffer Ceased WO2011106071A2 (en)

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CN201080064612.7A CN102771052B (en) 2010-02-24 2010-12-22 Source follower input buffer
JP2012554996A JP5911434B2 (en) 2010-02-24 2010-12-22 Source follower input buffer

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IN482/CHE/2010 2010-02-24
IN482CH2010 2010-02-24
US12/763,945 US8581634B2 (en) 2010-02-24 2010-04-20 Source follower input buffer
US12/763,945 2010-04-20

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JP5836493B2 (en) * 2012-09-07 2015-12-24 株式会社日立製作所 Interleaved A / D converter

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