WO2011105031A1 - Coding device and coding method - Google Patents

Coding device and coding method Download PDF

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Publication number
WO2011105031A1
WO2011105031A1 PCT/JP2011/000878 JP2011000878W WO2011105031A1 WO 2011105031 A1 WO2011105031 A1 WO 2011105031A1 JP 2011000878 W JP2011000878 W JP 2011000878W WO 2011105031 A1 WO2011105031 A1 WO 2011105031A1
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bit sequence
bits
encoding
data
bit
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PCT/JP2011/000878
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French (fr)
Japanese (ja)
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橋本和作
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パナソニック株式会社
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6525—3GPP LTE including E-UTRA

Definitions

  • the present invention relates to an encoding device and an encoding method.
  • the information signal When an information signal is transmitted from a transmitter to a receiver via a propagation path, the information signal may be transmitted to the receiving side as incorrect information due to the influence of distortion or noise of the propagation path.
  • the transmitter performs an encoding process
  • the receiver performs a decoding process.
  • the convolutional code is known as a code that can be processed relatively easily and can be effectively corrected.
  • 3GPP Third Generation Partnership Project
  • LTE Long Term Evolution
  • UCI uplink control information
  • the tail biting convolutional coding method has been adopted (see, for example, Non-Patent Document 1).
  • FIG. 1 is a diagram illustrating a configuration example of a tail biting convolutional encoder (hereinafter simply referred to as an encoder) disclosed in Non-Patent Document 1.
  • K indicates a sequence length of an input bit sequence (input bit stream c k ) in which an error check bit (for example, CRC (Cyclic Redundancy Check) bit) is added to the information bit sequence. That is, a sequence configured as an initial value of a plurality of registers (six in FIG. 1) included in the encoder and the last sequence of the input bit sequence ((K ⁇ 1) sequences) are the same sequence. . That is, the initial state and the end state of the encoder are the same state.
  • CRC Cyclic Redundancy Check
  • the input bit sequence ck is a data sequence in which 8 CRC bits are added to the information bit sequence. Therefore, in the input bit sequence ck , c (K-8) to c (K-1) (that is, 8 bits from the tail) correspond to CRC bits.
  • Non-Patent Document 1 6 bits (last 6 bits) from the end of the input bit sequence ck used for initialization of a shift register included in the encoder are controlled. It is a CRC bit for control information (UCI), not information (UCI). Therefore, the shift register is not initialized and tail biting convolutional coding cannot be performed unless the CRC calculation is performed on the control information (UCI) in the transmitter. Therefore, in Non-Patent Document 1, CRC calculation processing and tail biting convolutional encoding processing are not parallel processing (pipeline processing), and there is a problem that encoding efficiency (encoding throughput) cannot be improved. is there.
  • An object of the present invention is to provide an encoding device and an encoding method capable of improving encoding throughput in an encoding device that performs tail biting convolutional encoding.
  • the encoding apparatus of the present invention performs error detection encoding of an information bit sequence, calculates error detection bits for the information bit sequence, adds the error detection bits to the information bit sequence, and transmits A multiplexing unit that generates a bit sequence; and an encoding unit that encodes the transmission bit sequence using a tail biting convolutional coding scheme with a constraint length ⁇ , and the multiplexing unit includes the transmission bit sequence.
  • the error detection bit is arranged at the bit position before the (v ⁇ 1) bit from the end of the error.
  • the encoding method of the present invention includes a calculation step of performing error detection encoding of an information bit sequence to calculate an error detection bit for the information bit sequence, and adding the error detection bit to the information bit sequence for transmission.
  • the error detection bit is arranged at the bit position before the (v ⁇ 1) bit from the end of the error.
  • encoding throughput can be improved in an encoding apparatus that performs tail biting convolutional encoding.
  • the figure which shows the example of 1 structure of the conventional tail biting convolutional encoder The block diagram which shows the structure of the encoding apparatus which concerns on one embodiment of this invention
  • the figure which shows the structural example of the transmission bit series which concerns on one embodiment of this invention The figure which shows the encoding process in the encoding apparatus which concerns on one embodiment of this invention
  • the figure which shows the encoding process in the encoding apparatus which concerns on a prior art The figure which shows the structural example of the other transmission bit series of this invention
  • FIG. 2 is a block diagram showing the encoding apparatus according to the present embodiment.
  • the read address control unit 101 firstly uses a convolutional encoding unit 106 (described later) from an information bit sequence (for example, control information (UCI)) stored in the transmission data buffer 102.
  • the transmission data buffer 102 is instructed to read out bits (initial values) required for initialization of the shift register included in the encoder.
  • the read address control unit 101 reads ( ⁇ 1) bits of information bits corresponding to the number of shift registers from the tail of the information bit sequence.
  • the transmission data buffer 102 is instructed to read the sequence.
  • the read address control unit 101 sequentially reads information bit sequences other than the information bit sequence of ( ⁇ 1) bits from the tail of the information bit sequences stored in the transmission data buffer 102 from the top.
  • the transmission data buffer 102 is instructed.
  • the transmission data buffer 102 stores an information bit sequence (for example, control information (UCI)). Further, the transmission data buffer 102 outputs the stored information bit sequence to the register 103, the CRC calculation unit 104, or the selection / multiplexing unit 105 in accordance with an instruction from the read address control unit 101. Specifically, when the transmission data buffer 102 is instructed to read an information bit sequence for ( ⁇ 1) bits from the tail end of the information bit sequence, ( ⁇ 1) from the tail end of the information bit sequence. The information bit sequence for bits is output to the register 103 and the selection / multiplexing unit 105.
  • an information bit sequence for example, control information (UCI)
  • UCI control information
  • the transmission data buffer 102 when the transmission data buffer 102 is instructed to read out the information bit sequences in order from the head, the transmission data buffer 102 starts the information bit sequences other than the information bit sequence of ( ⁇ 1) bits from the tail of the information bit sequences. Are sequentially output to the CRC calculation unit 104 and the selection / multiplexing unit 105.
  • the register 103 stores (buffering) the ( ⁇ 1) bits (that is, the initial value of the shift register included in the encoder) input from the transmission data buffer 102 from the end of the information bit sequence. Further, the register 103 outputs the stored information bit sequence of ( ⁇ 1) bits to the CRC calculation unit 104 and the selection / multiplexing unit 105.
  • the CRC calculation unit 104 performs error detection coding on the information bit sequence to calculate CRC bits for the information bit sequence. Specifically, the CRC calculation unit 104 calculates CRC bits using the information bit sequence input from the transmission data buffer 102 and the information bit sequence input from the register 103. Then, the CRC calculation unit 104 outputs the obtained CRC bits to the selection / multiplexing unit 105.
  • the selection / multiplexing unit 105 outputs the information bit sequence input from the transmission data buffer 102, the information bit sequence input from the register 103, and the CRC bits input from the CRC calculation unit 104 to the convolutional coding unit 106. Select the bit sequence to be used.
  • the selection / multiplexing unit 105 multiplexes the information bit sequence input from the transmission data buffer 102, the information bit sequence input from the register 103, and the CRC bit input from the CRC calculation unit 104, thereby obtaining a CRC. Bits are added to the information bit sequence to generate a transmission bit sequence (the above-described input bit sequence (input bit stream)).
  • the convolutional encoding unit 106 receives an information bit sequence of ( ⁇ 1) bits from the tail of the information bit sequence input from the transmission data buffer 102, and a shift register (( ⁇ 1) The shift register is initialized by setting it to the initial value. Then, the convolutional coding unit 106 uses a tail biting convolutional coding method with a constraint length ⁇ , and transmits a transmission bit sequence (information bit sequence with CRC bits added thereto) input from the selection / multiplexing unit 105. The input bit sequence c k ) is encoded. Note that the convolutional coding unit 106 performs tailbiting convolutional coding in order from the first bit of the transmission bit sequence. The convolutional encoding unit 106 outputs the bit sequence after tailbiting convolutional encoding as encoded data.
  • the encoding rate R of the encoder is 1/3.
  • the transmission data buffer 102 stores the information bit series (data) shown at the top of FIG.
  • the read address control unit 101 reads the information bit sequence (hereinafter referred to as data 2) for ( ⁇ 1) bits from the tail of the information bit sequence (data) shown in FIG. Instruct.
  • the read data 2 (( ⁇ 1) bits) is input to the convolutional encoding unit 106 via the selection / multiplexing unit 105, and the initial values of ( ⁇ 1) shift registers included in the encoder.
  • the read address control unit 101 instructs the transmission data buffer 102 to sequentially read information bit sequences other than data 2 (hereinafter referred to as data 1) from the top of the information bit sequences shown in FIG. That is, as shown in FIG. 3, the information bit sequence (data) stored in the transmission data buffer 102 is divided into data 1 and data 2.
  • the CRC calculation unit 104 performs error detection coding on data 1 and data 2 (that is, an information bit sequence) shown in FIG. 3, and calculates L CRC bits.
  • the selection / multiplexing unit 105 adds a CRC bit to the information bit sequence (data 1 and data 2) to generate a K-bit transmission bit sequence. At this time, the selection / multiplexing unit 105 arranges CRC bits at bit positions before ( ⁇ 1) bits from the tail of the K-bit transmission bit sequence. Here, as shown in FIG. 3, the selection / multiplexing unit 105 further arranges the tail end (last bit) of the CRC bits at a bit position preceding the tail end of the K-bit transmission bit sequence by ⁇ bits. As described above, the CRC bits are inserted into the information bit sequence (data). On the other hand, the selection / multiplexing unit 105 does not use CRC bits but information bit sequences (FIG.
  • the transmission data buffer 102 stores the information bit series (data) shown at the top of FIG.
  • the read address control unit 101 reads the transmission data so as to read the information bit sequence (data 2) for ( ⁇ 1) bits from the tail of the information bit sequence (data shown in FIG. 3). Instructs the buffer 102. Data 2 (( ⁇ 1) bits) read from the transmission data buffer 102 is transferred to the convolutional encoding unit 106 via the selection / multiplexing unit 105, and ( ⁇ 1) pieces of data included in the encoder. Set to the initial value of the shift register. In this way, the convolutional encoding unit 106 initializes the shift register with the data 2 that is a part of the information bit sequence. As a result, the convolutional coding unit 106 is in a state in which tailbiting convolutional coding can be performed.
  • the register 103 stores (buffers) the data 2 input from the transmission data buffer 102.
  • the read address control unit 101 starts the information bit sequence (that is, data 1) other than the data 2 that has already been read from the information bit sequence (data shown in FIG. 3) from the top.
  • the transmission data buffer 102 is instructed to read sequentially.
  • Data 1 read from the transmission data buffer 102 is transferred to the CRC calculation unit 104 and the selection / multiplexing unit 105.
  • the convolutional coding unit 106 is in a state where tailbiting convolutional coding can be performed.
  • data 1 is the head portion of a transmission bit sequence (that is, a coding target bit sequence) composed of data 1, CRC bits, and data 2. Therefore, the convolutional encoding unit 106 performs tailbiting convolutional encoding on each bit of the data 1 sequentially input from the selection / multiplexing unit 105, as shown in FIG. Thereby, encoded data d0, d1, and d2 corresponding to data 1 are generated.
  • the CRC calculation unit 104 reads the data 2 stored in the register 103 when the transfer of the data 1 from the transmission data buffer 102 is completed. Then, CRC calculation section 104 performs error detection coding on data 1 and data 2, that is, the entire information bit sequence, and generates CRC bits (L bits). Note that the CRC calculation unit 104 may read out only the data 1 and advance the CRC calculation before reading out the data 2. In this case, the CRC calculation unit 104 reads the data 2 from the register 103 when the CRC calculation of the data 1 portion is completed, and continues the CRC calculation process. In this way, the CRC calculation unit 104 can start the CRC calculation in parallel with the process of storing the data 2 in the register 103, so that the CRC calculation can be further speeded up.
  • the generated CRC bits are transferred to the convolutional encoding unit 106 via the selection / multiplexing unit 105.
  • the data 2 stored in the register 103 is not transferred to the convolutional coding unit 106.
  • the convolutional coding unit 106 performs tailbiting convolutional coding on each bit of the CRC bits sequentially input from the selection / multiplexing unit 105, as shown in FIG. Thereby, encoded data d0, d1, and d2 corresponding to the CRC bits are generated.
  • the register 103 transfers the stored data 2 to the convolutional coding unit 106 via the selection / multiplexing unit 105. Then, the convolutional coding unit 106 performs tailbiting convolutional coding on each bit of the data 2 sequentially input from the selection / multiplexing unit 105, as shown in FIG. Thereby, encoded data d0, d1, and d2 corresponding to data 2 are generated.
  • the encoding apparatus 100 arranges CRC bits at bit positions before ( ⁇ 1) bits from the tail of the transmission bit sequence. To do. That is, coding apparatus 100 arranges CRC bits at bit positions shifted in the head direction by ( ⁇ 1) bits from the tail of the transmission bit sequence.
  • the bit sequence for ( ⁇ 1) bits from the end of the transmission bit sequence that is, the bit sequence set as the initial value of the shift register included in the encoder is not a CRC bit but an information bit sequence. .
  • the encoding apparatus 100 can initialize the shift register included in the encoder regardless of whether the CRC calculation process is completed. That is, the encoding apparatus 100 can start tail biting convolutional encoding without waiting for CRC calculation processing.
  • data 1, CRC bits, and data 2 constituting a transmission bit sequence (tail bit convolutional encoding target bits) data 1 arranged ahead of the CRC bits Is tail biting convolutionally encoded before completion of the CRC calculation process. That is, as illustrated in FIG. 4, the encoding apparatus 100 can perform a CRC calculation process and a tail biting convolutional encoding process (a process for data 1) in parallel.
  • the encoding apparatus 100 compared with the case where the CRC calculation process and the tail biting convolutional encoding process are performed serially (that is, when the tail biting convolutional encoding process is performed after the CRC calculation process is completed). Since it is possible to reduce the time required to obtain encoded data (encoding result) for all information bit sequences, it is possible to improve the encoding throughput.
  • the encoding apparatus 100 includes a bit position that is ⁇ bits before the end of the transmission bit sequence (that is, the bit position immediately before the bit set to the initial value of the shift register included in the encoder). ), The CRC bits are inserted into the information bit sequence so that the tail end (last bit) of the CRC bits is arranged at (). Thereby, in the K bit transmission bit sequence shown in FIG. 3, bits (data 1) other than the bit (data 2) used for the initial value of the shift register included in the encoder are arranged ahead of the CRC bits. The Therefore, in FIG.
  • the number of bits that are tail-biting convolutionally encoded without waiting for the completion of the CRC bit calculation process is maximized. Can be ensured, and the encoding throughput can be maximized.
  • the information bit sequence temporarily stored in the register 103 (information bit sequence arranged behind the CRC bit in the transmission bit sequence) is necessary for initialization of the shift register included in the encoder. Since only the number of bits (( ⁇ 1) bits) is required, the amount of data of the information bit sequence to be stored in the register 103 can be minimized.
  • the encoding apparatus 100 can further improve the encoding throughput as the data amount of the information bit sequence is larger.
  • the encoding apparatus 100 transfers the information bit sequence (data 2 shown in FIG. 3) set to the initial value of the shift register to the convolutional encoding unit 106 when the shift register included in the encoder is initialized. At the same time, it is temporarily stored in the register 103. Then, the encoding apparatus 100 reads the data 2 stored in the register 103 during the CRC calculation process and the convolutional encoding for the data 2. In other words, in the encoding device 100, the number of times data 2 is read from the transmission data buffer 102 (the number of memory accesses) is one. Also, the encoding apparatus 100 reads an information bit sequence other than the data 2 (data 1 shown in FIG.
  • the number of times data 1 is read from the transmission data buffer 102 (the number of memory accesses) is also one.
  • Non-Patent Document 1 CRC calculation processing and tail biting convolutional coding processing cannot be processed in parallel. Therefore, in the transmitter (encoding device), for example, when the data (information bit sequence) shown in the uppermost part of FIG. 3 is encoded as in the present embodiment, as shown in FIG.
  • the control information (data shown in FIG. 5) is read from the buffer (memory or the like) at each of the timing of performing the tail biting convolutional coding after the CRC calculation. That is, the transmitter (encoding device) needs to read the control information (information bit sequence) from the buffer (memory or the like) a plurality of times, and the number of accesses to the buffer (memory) increases, resulting in an increase in power consumption. End up.
  • the number of times of reading the information bit series (data 1 and data 2 shown in FIG. 3) from the transmission data buffer 102 is sufficient. Therefore, since the number of accesses to the transmission data buffer 102 (memory) can be kept low, an increase in power consumption due to memory access can be prevented.
  • a process of reading data 2 from register 103 is added in order to perform CRC calculation.
  • the encoding apparatus 100 improves the processing speed, and , Can reduce power consumption.
  • the data 2 is the shortest when the tail (last bit) of the CRC bits is arranged at a bit position preceding the last bit of the transmission bit sequence by ⁇ bits. Therefore, also from this point of view, it can be understood that encoding apparatus 100 according to the present embodiment can perform encoding most efficiently when such a bit arrangement is adopted.
  • the encoding device can prevent an increase in power consumption by keeping the number of times of reading information bit sequences from the buffer low.
  • data that is an information bit sequence is divided into data 1, data 3, and data 2 (( ⁇ 1) bits) from the head, and CRC bits are divided between data 1 and data 3. It may be inserted in between. That is, in FIG. 6, the CRC bit is arranged at a bit position before ( ⁇ 1) bits from the end of the transmission bit sequence. When the number of bits of data 3 shown in FIG. 6 is zero, it becomes the same as the transmission bit sequence shown in FIG. Even when the transmission bit sequence shown in FIG. 6 is configured, in the encoding apparatus, the CRC calculation processing and the tail biting convolutional encoding processing (processing for data 1 shown in FIG. 6) are performed in parallel as in the above embodiment. And the encoding throughput can be improved.
  • a bit sequence (information bits set as an initial value of a shift register included in an encoder) arranged behind CRC bits in a transmission bit sequence
  • the register 103 for temporarily storing (including the series) has been described. As described above, this is provided in order to reduce the number of times of reading (memory access number) related to data 2 to the transmission data buffer 102.
  • the register 103 is deleted when there is no influence on the entire system when the number of reads related to the data 2 to the transmission data buffer 102 does not affect the entire system, or when the increase in power consumption due to memory access is negligible. It may be the configuration.
  • the CRC bits for the transmission bit sequence are calculated, but the present invention is not limited to this. That is, even when error detection encoding is performed using another code that cannot be generated without processing the entire information bit sequence, the same problem as described above may occur. Therefore, the invention according to the present embodiment is not limited to CRC, and may be applied to other known error detection coding such as checksum.
  • the encoding apparatus and encoding method of the present invention are useful for improving encoding throughput in error correction encoding using tail biting convolutional codes.

Abstract

Disclosed is a coding device that performs tail-biting convolutional coding, and that can increase coding throughput. In this device, a CRC calculation unit (104) performs error detection coding and calculates a CRC bit with respect to a data bit sequence; a selection/multiplexing unit (105) attaches the CRC bit to the data bit sequence, generating a transmission bit sequence; and a convolutional coding unit (106) encodes the transmission bit sequence using a tail-biting convolutional coding method with a constraint length ν. Here, the selection/multiplexing unit (105) disposes the CRC bit at a bit position before the (ν - 1)-th bit from the end of the transmission bit sequence.

Description

符号化装置及び符号化方法Encoding apparatus and encoding method
　本発明は、符号化装置及び符号化方法に関する。 The present invention relates to an encoding device and an encoding method.
　情報信号が伝搬路を介して送信機から受信機へ伝送されるとき、情報信号は、伝搬路の歪み、雑音等の影響により、受信側に誤った情報として伝わることがある。このような誤りを低減するために、送信機では符号化処理が行われ、受信機では復号処理が行われる。特に、畳み込み符号は、比較的簡易に処理可能な、且つ、効果的に誤り訂正可能な符号として知られている。 When an information signal is transmitted from a transmitter to a receiver via a propagation path, the information signal may be transmitted to the receiving side as incorrect information due to the influence of distortion or noise of the propagation path. In order to reduce such an error, the transmitter performs an encoding process, and the receiver performs a decoding process. In particular, the convolutional code is known as a code that can be processed relatively easily and can be effectively corrected.
　第３世代移動通信システムの標準化グループである３ＧＰＰ（Third Generation Partnership Project）における長期的高度化システム（ＬＴＥ：Long Term Evolution）では、上りリンクの制御情報（ＵＣＩ：Uplink Control Information）の符号化方式として、テイルバイティング畳み込み符号化（tail biting convolutional coding）方式が採用された（例えば、非特許文献１参照）。 In 3GPP (Third Generation Partnership Project), which is a standardization group for 3rd generation mobile communication systems, the long term advanced system (LTE: Long Term Evolution) is used as an encoding method for uplink control information (UCI). The tail biting convolutional coding method has been adopted (see, for example, Non-Patent Document 1).
　以下、テイルバイティング畳み込み符号化について概略説明する。図１は、非特許文献１に開示されたテイルバイティング畳み込み符号化器（以下、単に符号化器という）の一構成例を示す図である。 Hereinafter, the tail biting convolutional coding will be outlined. FIG. 1 is a diagram illustrating a configuration example of a tail biting convolutional encoder (hereinafter simply referred to as an encoder) disclosed in Non-Patent Document 1.
　図１に示す符号化器の符号化率Ｒは１／３であり、拘束長νは７である。また、図１に示す符号化器が備える６個のシフトレジスタ（図１に示す‘Ｄ’）の初期値として、入力ビットストリームｃｋ（ｋ＝０～Ｋ－１）の最後尾から６ビット（ラスト６ビット）の値が設定される。つまり、図１に示す符号化器が備えるシフトレジスタＳｉ（ｉ＝０～５）は、次式（１）に従って初期化される。
　Ｓｉ＝ｃ（Ｋ－１－ｉ）　　　…（１） The coding rate R of the encoder shown in FIG. 1 is 1/3, and the constraint length ν is 7. Further, as initial values of the six shift registers ('D' shown in FIG. 1) included in the encoder shown in FIG. 1, 6 bits from the tail of the input bit stream c k (k = 0 to K−1) are used. The value of (last 6 bits) is set. That is, the shift register S i (i = 0 to 5) included in the encoder shown in FIG. 1 is initialized according to the following equation (1).
S i = c (K-1-i) (1)
　ここで、Ｋは情報ビット系列に誤り検査ビット（例えば、ＣＲＣ（Cyclic Redundancy Check）ビット）が付加された入力ビット系列（入力ビットストリームｃｋ）の系列長を示す。つまり、符号化器が有する複数（図１では６個）のレジスタの初期値として構成される系列と、入力ビット系列（（Ｋ－１）個の系列）の末尾の系列とが同一系列になる。すなわち、符号化器の初期状態と終了状態とは同一状態となる。 Here, K indicates a sequence length of an input bit sequence (input bit stream c k ) in which an error check bit (for example, CRC (Cyclic Redundancy Check) bit) is added to the information bit sequence. That is, a sequence configured as an initial value of a plurality of registers (six in FIG. 1) included in the encoder and the last sequence of the input bit sequence ((K−1) sequences) are the same sequence. . That is, the initial state and the end state of the encoder are the same state.
　なお、非特許文献１によれば、上りリンクの制御情報（ＵＣＩ）の場合、上記入力ビット系列ｃｋは、情報ビット系列に８ビットのＣＲＣビットが付加されたデータ系列となる。そのため、入力ビット系列ｃｋのうち、ｃ（Ｋ－８）～ｃ（Ｋ－１）（つまり、最後尾から８ビット）はＣＲＣビットに相当する。 According to Non-Patent Document 1, in the case of uplink control information (UCI), the input bit sequence ck is a data sequence in which 8 CRC bits are added to the information bit sequence. Therefore, in the input bit sequence ck , c (K-8) to c (K-1) (that is, 8 bits from the tail) correspond to CRC bits.
　また、図１において、シフトレジスタＳｉが初期化された符号化器に入力ビット系列ｃｋが入力された際、符号化器の３系統の出力ビット系列ｄｋ （０）、ｄｋ （１）、ｄｋ （２）が得られる。図１では符号化率Ｒが１／３であるので、１ビットの入力（ｃｋ）に対して、符号化データとして３ビットの出力ビット系列（ｄｋ （０）、ｄｋ （１）、ｄｋ （２））が出力される。 In FIG. 1, when the input bit sequence ck is input to the encoder in which the shift register S i is initialized, the three output bit sequences d k (0) and d k (1 ) , D k (2) . In FIG. 1, since the coding rate R is 1/3, for a 1-bit input (c k ), a 3-bit output bit sequence (d k (0) , d k (1) , d k (2) ) is output.
　上述したように、テイルバイティング畳み込み符号化では、入力ビット系列ｃｋ（被符号化データ）の最後尾から６（＝ν－１）ビットを用いて、符号化器が備えるシフトレジスタを初期化した後、テイルバイティング畳み込み符号化を行うことにより、テイルバイティング畳み込み符号化出力を得ることができる。 As described above, in tail biting convolutional encoding, the shift register included in the encoder is initialized using 6 (= ν−1) bits from the end of the input bit sequence c k (encoded data). Then, tail biting convolutional coding is performed, whereby tailbiting convolutional coding output can be obtained.
　しかしながら、非特許文献１に開示されたテイルバイティング畳み込み符号化では、符号化器が備えるシフトレジスタの初期化に用いる、入力ビット系列ｃｋの最後尾から６ビット（ラスト６ビット）は、制御情報（ＵＣＩ）ではなく、制御情報（ＵＣＩ）に対するＣＲＣビットとなる。そのため、送信機において、制御情報（ＵＣＩ）に対するＣＲＣ計算が行われた後でなければ、シフトレジスタが初期化されず、テイルバイティング畳み込み符号化を行うことができない。よって、非特許文献１では、ＣＲＣ計算処理と、テイルバイティング畳み込み符号化処理とは、並列処理（パイプライン処理）されず、符号化効率（符号化スループット）を向上させることができないという課題がある。 However, in tail biting convolutional coding disclosed in Non-Patent Document 1, 6 bits (last 6 bits) from the end of the input bit sequence ck used for initialization of a shift register included in the encoder are controlled. It is a CRC bit for control information (UCI), not information (UCI). Therefore, the shift register is not initialized and tail biting convolutional coding cannot be performed unless the CRC calculation is performed on the control information (UCI) in the transmitter. Therefore, in Non-Patent Document 1, CRC calculation processing and tail biting convolutional encoding processing are not parallel processing (pipeline processing), and there is a problem that encoding efficiency (encoding throughput) cannot be improved. is there.
　本発明の目的は、テイルバイティング畳み込み符号化を行う符号化装置において、符号化スループットを向上させることができる符号化装置及び符号化方法を提供することである。 An object of the present invention is to provide an encoding device and an encoding method capable of improving encoding throughput in an encoding device that performs tail biting convolutional encoding.
　本発明の符号化装置は、情報ビット系列の誤り検出符号化を行って、前記情報ビット系列に対する誤り検出ビットを計算する計算手段と、前記誤り検出ビットを前記情報ビット系列に付加して、送信ビット系列を生成する多重手段と、拘束長νのテイルバイティング畳み込み符号化方式を用いて、前記送信ビット系列を符号化する符号化手段と、を具備し、前記多重手段は、前記送信ビット系列の最後尾から（前記ν－１）ビットよりも前のビット位置に前記誤り検出ビットを配置する構成を採る。 The encoding apparatus of the present invention performs error detection encoding of an information bit sequence, calculates error detection bits for the information bit sequence, adds the error detection bits to the information bit sequence, and transmits A multiplexing unit that generates a bit sequence; and an encoding unit that encodes the transmission bit sequence using a tail biting convolutional coding scheme with a constraint length ν, and the multiplexing unit includes the transmission bit sequence. The error detection bit is arranged at the bit position before the (v−1) bit from the end of the error.
　本発明の符号化方法は、情報ビット系列の誤り検出符号化を行って、前記情報ビット系列に対する誤り検出ビットを計算する計算ステップと、前記誤り検出ビットを前記情報ビット系列に付加して、送信ビット系列を生成する多重ステップと、拘束長νのテイルバイティング畳み込み符号化方式を用いて、前記送信ビット系列を符号化する符号化ステップと、を具備し、前記多重ステップは、前記送信ビット系列の最後尾から（前記ν－１）ビットよりも前のビット位置に前記誤り検出ビットを配置する構成を採る。 The encoding method of the present invention includes a calculation step of performing error detection encoding of an information bit sequence to calculate an error detection bit for the information bit sequence, and adding the error detection bit to the information bit sequence for transmission. A multiplexing step for generating a bit sequence, and an encoding step for encoding the transmission bit sequence using a tail biting convolutional coding scheme with a constraint length ν, wherein the multiplexing step includes the transmission bit sequence. The error detection bit is arranged at the bit position before the (v−1) bit from the end of the error.
　本発明によれば、テイルバイティング畳み込み符号化を行う符号化装置において、符号化スループットを向上させることができる。 According to the present invention, encoding throughput can be improved in an encoding apparatus that performs tail biting convolutional encoding.
従来のテイルバイティング畳み込み符号化器の一構成例を示す図The figure which shows the example of 1 structure of the conventional tail biting convolutional encoder 本発明の一実施の形態に係る符号化装置の構成を示すブロック図The block diagram which shows the structure of the encoding apparatus which concerns on one embodiment of this invention 本発明の一実施の形態に係る送信ビット系列の構成例を示す図The figure which shows the structural example of the transmission bit series which concerns on one embodiment of this invention 本発明の一実施の形態に係る符号化装置における符号化処理を示す図The figure which shows the encoding process in the encoding apparatus which concerns on one embodiment of this invention 従来技術に係る符号化装置における符号化処理を示す図The figure which shows the encoding process in the encoding apparatus which concerns on a prior art 本発明のその他の送信ビット系列の構成例を示す図The figure which shows the structural example of the other transmission bit series of this invention
　以下、本発明の一実施の形態について図面を参照して詳細に説明する。 Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
　図２は、本実施の形態に係る符号化装置を示すブロック図である。図２に示す符号化装置１００において、読み出しアドレス制御部１０１は、まず、送信データバッファ１０２に格納されている情報ビット系列（例えば、制御情報（ＵＣＩ））から、後述する畳み込み符号化部１０６（符号化器）が備えるシフトレジスタの初期化に要するビット（初期値）を読み出すように、送信データバッファ１０２に指示する。具体的には、テイルバイティング畳み込み符号化の拘束長をνとすると、読み出しアドレス制御部１０１は、情報ビット系列の最後尾から、シフトレジスタ数に対応する（ν－１）ビット分の情報ビット系列を読み出すように、送信データバッファ１０２に指示する。次いで、読み出しアドレス制御部１０１は、送信データバッファ１０２に格納されている情報ビット系列のうち、最後尾から（ν－１）ビット分の情報ビット系列以外の情報ビット系列を先頭から順に読み出すように、送信データバッファ１０２に指示する。 FIG. 2 is a block diagram showing the encoding apparatus according to the present embodiment. In the encoding apparatus 100 shown in FIG. 2, the read address control unit 101 firstly uses a convolutional encoding unit 106 (described later) from an information bit sequence (for example, control information (UCI)) stored in the transmission data buffer 102. The transmission data buffer 102 is instructed to read out bits (initial values) required for initialization of the shift register included in the encoder. Specifically, assuming that the constraint length of tail biting convolutional coding is ν, the read address control unit 101 reads (ν−1) bits of information bits corresponding to the number of shift registers from the tail of the information bit sequence. The transmission data buffer 102 is instructed to read the sequence. Next, the read address control unit 101 sequentially reads information bit sequences other than the information bit sequence of (ν−1) bits from the tail of the information bit sequences stored in the transmission data buffer 102 from the top. The transmission data buffer 102 is instructed.
　送信データバッファ１０２は、情報ビット系列（例えば、制御情報（ＵＣＩ））を格納する。また、送信データバッファ１０２は、読み出しアドレス制御部１０１からの指示に従って、格納している情報ビット系列を、レジスタ１０３、ＣＲＣ計算部１０４又は選択・多重部１０５に出力する。具体的には、送信データバッファ１０２は、情報ビット系列の最後尾から（ν－１）ビット分の情報ビット系列を読み出すように指示された場合、情報ビット系列の最後尾から（ν－１）ビット分の情報ビット系列をレジスタ１０３及び選択・多重部１０５に出力する。また、送信データバッファ１０２は、情報ビット系列を先頭から順に読み出すように指示された場合、情報ビット系列のうち、最後尾から（ν－１）ビット分の情報ビット系列以外の情報ビット系列を先頭から順にＣＲＣ計算部１０４及び選択・多重部１０５に出力する。 The transmission data buffer 102 stores an information bit sequence (for example, control information (UCI)). Further, the transmission data buffer 102 outputs the stored information bit sequence to the register 103, the CRC calculation unit 104, or the selection / multiplexing unit 105 in accordance with an instruction from the read address control unit 101. Specifically, when the transmission data buffer 102 is instructed to read an information bit sequence for (ν−1) bits from the tail end of the information bit sequence, (ν−1) from the tail end of the information bit sequence. The information bit sequence for bits is output to the register 103 and the selection / multiplexing unit 105. Further, when the transmission data buffer 102 is instructed to read out the information bit sequences in order from the head, the transmission data buffer 102 starts the information bit sequences other than the information bit sequence of (ν−1) bits from the tail of the information bit sequences. Are sequentially output to the CRC calculation unit 104 and the selection / multiplexing unit 105.
　レジスタ１０３は、送信データバッファ１０２から入力される、情報ビット系列の最後尾から（ν－１）ビット（つまり、符号化器が備えるシフトレジスタの初期値）を記憶（バッファリング）する。また、レジスタ１０３は、記憶している（ν－１）ビットの情報ビット系列を、ＣＲＣ計算部１０４及び選択・多重部１０５に出力する。 The register 103 stores (buffering) the (ν−1) bits (that is, the initial value of the shift register included in the encoder) input from the transmission data buffer 102 from the end of the information bit sequence. Further, the register 103 outputs the stored information bit sequence of (ν−1) bits to the CRC calculation unit 104 and the selection / multiplexing unit 105.
　ＣＲＣ計算部１０４は、情報ビット系列に対して誤り検出符号化を行って、情報ビット系列に対するＣＲＣビットを計算する。具体的には、ＣＲＣ計算部１０４は、送信データバッファ１０２から入力される情報ビット系列、及び、レジスタ１０３から入力される情報ビット系列を用いて、ＣＲＣビットを計算する。そして、ＣＲＣ計算部１０４は、得られたＣＲＣビットを選択・多重部１０５に出力する。 The CRC calculation unit 104 performs error detection coding on the information bit sequence to calculate CRC bits for the information bit sequence. Specifically, the CRC calculation unit 104 calculates CRC bits using the information bit sequence input from the transmission data buffer 102 and the information bit sequence input from the register 103. Then, the CRC calculation unit 104 outputs the obtained CRC bits to the selection / multiplexing unit 105.
　選択・多重部１０５は、送信データバッファ１０２から入力される情報ビット系列、レジスタ１０３から入力される情報ビット系列、及び、ＣＲＣ計算部１０４から入力されるＣＲＣビットについて、畳み込み符号化部１０６へ出力するビット系列を選択する。また、選択・多重部１０５は、送信データバッファ１０２から入力される情報ビット系列、レジスタ１０３から入力される情報ビット系列、及び、ＣＲＣ計算部１０４から入力されるＣＲＣビットを多重することにより、ＣＲＣビットを情報ビット系列に付加して、送信ビット系列（上述した入力ビット系列（入力ビットストリーム））を生成する。 The selection / multiplexing unit 105 outputs the information bit sequence input from the transmission data buffer 102, the information bit sequence input from the register 103, and the CRC bits input from the CRC calculation unit 104 to the convolutional coding unit 106. Select the bit sequence to be used. The selection / multiplexing unit 105 multiplexes the information bit sequence input from the transmission data buffer 102, the information bit sequence input from the register 103, and the CRC bit input from the CRC calculation unit 104, thereby obtaining a CRC. Bits are added to the information bit sequence to generate a transmission bit sequence (the above-described input bit sequence (input bit stream)).
　畳み込み符号化部１０６は、まず、送信データバッファ１０２から入力される、情報ビット系列の最後尾から（ν－１）ビット分の情報ビット系列を、符号化器が備えるシフトレジスタ（（ν－１）個）の初期値に設定することにより、シフトレジスタを初期化する。そして、畳み込み符号化部１０６は、拘束長νのテイルバイティング畳み込み符号化方式を用いて、選択・多重部１０５から入力される送信ビット系列（ＣＲＣビットが付加された情報ビット系列。つまり、上述した入力ビット系列ｃｋ）を符号化する。なお、畳み込み符号化部１０６は、送信ビット系列の先頭のビットから順にテイルバイティング畳み込み符号化を施す。畳み込み符号化部１０６は、テイルバイティング畳み込み符号化後のビット系列を符号化データとして出力する。 First, the convolutional encoding unit 106 receives an information bit sequence of (ν−1) bits from the tail of the information bit sequence input from the transmission data buffer 102, and a shift register ((ν−1) The shift register is initialized by setting it to the initial value. Then, the convolutional coding unit 106 uses a tail biting convolutional coding method with a constraint length ν, and transmits a transmission bit sequence (information bit sequence with CRC bits added thereto) input from the selection / multiplexing unit 105. The input bit sequence c k ) is encoded. Note that the convolutional coding unit 106 performs tailbiting convolutional coding in order from the first bit of the transmission bit sequence. The convolutional encoding unit 106 outputs the bit sequence after tailbiting convolutional encoding as encoded data.
　次に、畳み込み符号化部１０６（符号化器）に入力される送信ビット系列の構成例について説明する。 Next, a configuration example of a transmission bit sequence input to the convolutional encoding unit 106 (encoder) will be described.
　以下の説明では、符号化器の符号化率Ｒを１／３とする。また、送信データバッファ１０２には、図３最上段に示す情報ビット系列（データ）が格納されている。 In the following description, the encoding rate R of the encoder is 1/3. In addition, the transmission data buffer 102 stores the information bit series (data) shown at the top of FIG.
　読み出しアドレス制御部１０１は、まず、図３に示す情報ビット系列（データ）の最後尾から（ν－１）ビット分の情報ビット系列（以下、データ２という）を読み出すように送信データバッファ１０２に指示する。読み出されたデータ２（（ν－１）ビット）は、選択・多重部１０５を介して畳み込み符号化部１０６に入力され、符号化器が備える（ν－１）個のシフトレジスタの初期値に設定される。 First, the read address control unit 101 reads the information bit sequence (hereinafter referred to as data 2) for (ν−1) bits from the tail of the information bit sequence (data) shown in FIG. Instruct. The read data 2 ((ν−1) bits) is input to the convolutional encoding unit 106 via the selection / multiplexing unit 105, and the initial values of (ν−1) shift registers included in the encoder. Set to
　さらに、読み出しアドレス制御部１０１は、図３に示す情報ビット系列のうち、データ２以外の情報ビット系列（以下、データ１という）を先頭から順に読み出すように送信データバッファ１０２に指示する。すなわち、図３に示すように、送信データバッファ１０２に格納されている情報ビット系列（データ）は、データ１とデータ２とに分割される。 Further, the read address control unit 101 instructs the transmission data buffer 102 to sequentially read information bit sequences other than data 2 (hereinafter referred to as data 1) from the top of the information bit sequences shown in FIG. That is, as shown in FIG. 3, the information bit sequence (data) stored in the transmission data buffer 102 is divided into data 1 and data 2.
　また、ＣＲＣ計算部１０４は、図３に示すデータ１及びデータ２（つまり、情報ビット系列）に対して誤り検出符号化を行い、ＬビットのＣＲＣビットを計算する。 Also, the CRC calculation unit 104 performs error detection coding on data 1 and data 2 (that is, an information bit sequence) shown in FIG. 3, and calculates L CRC bits.
　そして、選択・多重部１０５は、ＣＲＣビットを情報ビット系列（データ１及びデータ２）に付加して、Ｋビットの送信ビット系列を生成する。このとき、選択・多重部１０５は、Ｋビットの送信ビット系列の最後尾から（ν－１）ビットよりも前のビット位置にＣＲＣビットを配置する。ここでは、図３に示すように、選択・多重部１０５は、さらに、Ｋビットの送信ビット系列の最後尾からνビットだけ前のビット位置にＣＲＣビットの最後尾（最終ビット）が配置されるように、ＣＲＣビットを情報ビット系列（データ）に挿入する。一方、選択・多重部１０５は、送信ビット系列の最後尾から（ν－１）ビットだけ前までの（ν－１）ビット分のビット位置には、ＣＲＣビットではなく、情報ビット系列（図３ではデータ２）を配置する。これにより、図３に示すように、データ１、ＣＲＣビット、データ２の順で構成される、Ｋビットの送信ビット系列が生成される。 The selection / multiplexing unit 105 adds a CRC bit to the information bit sequence (data 1 and data 2) to generate a K-bit transmission bit sequence. At this time, the selection / multiplexing unit 105 arranges CRC bits at bit positions before (ν−1) bits from the tail of the K-bit transmission bit sequence. Here, as shown in FIG. 3, the selection / multiplexing unit 105 further arranges the tail end (last bit) of the CRC bits at a bit position preceding the tail end of the K-bit transmission bit sequence by ν bits. As described above, the CRC bits are inserted into the information bit sequence (data). On the other hand, the selection / multiplexing unit 105 does not use CRC bits but information bit sequences (FIG. 3) at bit positions corresponding to (ν−1) bits before the last (ν−1) bits from the end of the transmission bit sequence. Then, data 2) is arranged. As a result, as shown in FIG. 3, a transmission bit sequence of K bits configured in the order of data 1, CRC bits, and data 2 is generated.
　次に、本実施の形態に係る符号化装置１００（図２）における符号化処理の詳細について説明する。以下の説明では、送信データバッファ１０２には、図３最上段に示す情報ビット系列（データ）が格納されている。 Next, details of the encoding process in encoding apparatus 100 (FIG. 2) according to the present embodiment will be described. In the following description, the transmission data buffer 102 stores the information bit series (data) shown at the top of FIG.
　図４に示すように、読み出しアドレス制御部１０１は、情報ビット系列（図３に示すデータ）の最後尾から（ν－１）ビット分の情報ビット系列（データ２）を読み出すように、送信データバッファ１０２に指示する。送信データバッファ１０２から読み出されたデータ２（（ν－１）ビット）は、選択・多重部１０５を介して畳み込み符号化部１０６に転送され、符号化器が備える（ν－１）個のシフトレジスタの初期値に設定される。このように、畳み込み符号化部１０６では、情報ビット系列の一部であるデータ２によってシフトレジスタが初期化される。これにより、畳み込み符号化部１０６では、テイルバイティング畳み込み符号化を実施可能な状態になる。 As shown in FIG. 4, the read address control unit 101 reads the transmission data so as to read the information bit sequence (data 2) for (ν−1) bits from the tail of the information bit sequence (data shown in FIG. 3). Instructs the buffer 102. Data 2 ((ν−1) bits) read from the transmission data buffer 102 is transferred to the convolutional encoding unit 106 via the selection / multiplexing unit 105, and (ν−1) pieces of data included in the encoder. Set to the initial value of the shift register. In this way, the convolutional encoding unit 106 initializes the shift register with the data 2 that is a part of the information bit sequence. As a result, the convolutional coding unit 106 is in a state in which tailbiting convolutional coding can be performed.
　また、レジスタ１０３は、送信データバッファ１０２から入力されるデータ２を記憶（バッファリング）する。 Further, the register 103 stores (buffers) the data 2 input from the transmission data buffer 102.
　次いで、図４に示すように、読み出しアドレス制御部１０１は、情報ビット系列（図３に示すデータ）のうち、既に読み出されたデータ２以外の情報ビット系列（つまり、データ１）を先頭から順に読み出すように、送信データバッファ１０２に指示する。送信データバッファ１０２から読み出されたデータ１は、ＣＲＣ計算部１０４及び選択・多重部１０５に転送される。 Next, as shown in FIG. 4, the read address control unit 101 starts the information bit sequence (that is, data 1) other than the data 2 that has already been read from the information bit sequence (data shown in FIG. 3) from the top. The transmission data buffer 102 is instructed to read sequentially. Data 1 read from the transmission data buffer 102 is transferred to the CRC calculation unit 104 and the selection / multiplexing unit 105.
　ここで、畳み込み符号化部１０６では、テイルバイティング畳み込み符号化を実施可能な状態である。また、図３に示すように、データ１は、データ１とＣＲＣビットとデータ２とから構成される送信ビット系列（つまり、符号化対象ビット系列）の先頭部分である。そこで、畳み込み符号化部１０６は、図４に示すように、選択・多重部１０５から順次入力されるデータ１の各ビットに対して、テイルバイティング畳み込み符号化を行う。これにより、データ１に対応する符号化データｄ０，ｄ１，ｄ２が生成される。 Here, the convolutional coding unit 106 is in a state where tailbiting convolutional coding can be performed. As shown in FIG. 3, data 1 is the head portion of a transmission bit sequence (that is, a coding target bit sequence) composed of data 1, CRC bits, and data 2. Therefore, the convolutional encoding unit 106 performs tailbiting convolutional encoding on each bit of the data 1 sequentially input from the selection / multiplexing unit 105, as shown in FIG. Thereby, encoded data d0, d1, and d2 corresponding to data 1 are generated.
　また、図４に示すように、ＣＲＣ計算部１０４は、送信データバッファ１０２からのデータ１の転送が完了すると、レジスタ１０３に記憶されているデータ２を読み出す。そして、ＣＲＣ計算部１０４は、データ１及びデータ２、つまり、情報ビット系列全体に対して誤り検出符号化を行い、ＣＲＣビット（Ｌビット）を生成する。なお、ＣＲＣ計算部１０４は、データ２を読み出す前に、データ１のみを読み出してＣＲＣ計算を進めておいてもよい。この場合、ＣＲＣ計算部１０４は、データ１部分のＣＲＣ計算が終わった時点でレジスタ１０３からデータ２を読み出してＣＲＣ計算の処理を続行する。このようにすると、ＣＲＣ計算部１０４は、データ２をレジスタ１０３に記憶する処理と並行してＣＲＣ計算を開始することができるので、ＣＲＣ計算の更なる高速化を図ることができる。 As shown in FIG. 4, the CRC calculation unit 104 reads the data 2 stored in the register 103 when the transfer of the data 1 from the transmission data buffer 102 is completed. Then, CRC calculation section 104 performs error detection coding on data 1 and data 2, that is, the entire information bit sequence, and generates CRC bits (L bits). Note that the CRC calculation unit 104 may read out only the data 1 and advance the CRC calculation before reading out the data 2. In this case, the CRC calculation unit 104 reads the data 2 from the register 103 when the CRC calculation of the data 1 portion is completed, and continues the CRC calculation process. In this way, the CRC calculation unit 104 can start the CRC calculation in parallel with the process of storing the data 2 in the register 103, so that the CRC calculation can be further speeded up.
　そして、生成されたＣＲＣビットは、選択・多重部１０５を介して畳み込み符号化部１０６に転送される。なお、このとき、レジスタ１０３に記憶されているデータ２は、畳み込み符号化部１０６に転送されない。そして、畳み込み符号化部１０６は、図４に示すように、選択・多重部１０５から順次入力されるＣＲＣビットの各ビットに対して、テイルバイティング畳み込み符号化を行う。これにより、ＣＲＣビットに対応する符号化データｄ０，ｄ１，ｄ２が生成される。 Then, the generated CRC bits are transferred to the convolutional encoding unit 106 via the selection / multiplexing unit 105. At this time, the data 2 stored in the register 103 is not transferred to the convolutional coding unit 106. Then, the convolutional coding unit 106 performs tailbiting convolutional coding on each bit of the CRC bits sequentially input from the selection / multiplexing unit 105, as shown in FIG. Thereby, encoded data d0, d1, and d2 corresponding to the CRC bits are generated.
　ＣＲＣビットのテイルバイティング畳み込み符号化が完了すると、レジスタ１０３は、記憶しているデータ２を、選択・多重部１０５を介して畳み込み符号化部１０６に転送する。そして、畳み込み符号化部１０６は、図４に示すように、選択・多重部１０５から順次入力されるデータ２の各ビットに対して、テイルバイティング畳み込み符号化を行う。これにより、データ２に対応する符号化データｄ０，ｄ１，ｄ２が生成される。 When the CRC bit tail biting convolutional coding is completed, the register 103 transfers the stored data 2 to the convolutional coding unit 106 via the selection / multiplexing unit 105. Then, the convolutional coding unit 106 performs tailbiting convolutional coding on each bit of the data 2 sequentially input from the selection / multiplexing unit 105, as shown in FIG. Thereby, encoded data d0, d1, and d2 corresponding to data 2 are generated.
　このように、テイルバイティング畳み込み符号化方式の拘束長をνとした場合、符号化装置１００は、送信ビット系列の最後尾から（ν－１）ビットよりも前のビット位置にＣＲＣビットを配置する。すなわち、符号化装置１００は、送信ビット系列の最後尾から（ν－１）ビット分だけ先頭方向にシフトさせたビット位置にＣＲＣビットを配置する。 As described above, when the constraint length of the tail biting convolutional coding scheme is ν, the encoding apparatus 100 arranges CRC bits at bit positions before (ν−1) bits from the tail of the transmission bit sequence. To do. That is, coding apparatus 100 arranges CRC bits at bit positions shifted in the head direction by (ν−1) bits from the tail of the transmission bit sequence.
　よって、送信ビット系列の最後尾から（ν－１）ビット分のビット系列、つまり、符号化器が備えるシフトレジスタの初期値に設定されるビット系列は、ＣＲＣビットではなく、情報ビット系列となる。これにより、符号化装置１００は、ＣＲＣ計算処理が完了したか否かに依らず、符号化器が備えるシフトレジスタを初期化できる。すなわち、符号化装置１００は、ＣＲＣ計算処理を待たずにテイルバイティング畳み込み符号化を開始することができる。具体的には、図４に示すように、送信ビット系列（テイルバイティング畳み込み符号化対象ビット）を構成するデータ１、ＣＲＣビット及びデータ２のうち、ＣＲＣビットよりも前方に配置されるデータ１は、ＣＲＣ計算処理の完了前にテイルバイティング畳み込み符号化される。つまり、図４に示すように、符号化装置１００は、ＣＲＣ計算処理と、テイルバイティング畳み込み符号化処理（データ１に対する処理）とを、並列に処理することが可能となる。 Therefore, the bit sequence for (ν−1) bits from the end of the transmission bit sequence, that is, the bit sequence set as the initial value of the shift register included in the encoder is not a CRC bit but an information bit sequence. . Thereby, the encoding apparatus 100 can initialize the shift register included in the encoder regardless of whether the CRC calculation process is completed. That is, the encoding apparatus 100 can start tail biting convolutional encoding without waiting for CRC calculation processing. Specifically, as shown in FIG. 4, among data 1, CRC bits, and data 2 constituting a transmission bit sequence (tail bit convolutional encoding target bits), data 1 arranged ahead of the CRC bits Is tail biting convolutionally encoded before completion of the CRC calculation process. That is, as illustrated in FIG. 4, the encoding apparatus 100 can perform a CRC calculation process and a tail biting convolutional encoding process (a process for data 1) in parallel.
　よって、符号化装置１００では、ＣＲＣ計算処理及びテイルバイティング畳み込み符号化処理をシリアルに処理を行う場合（つまり、ＣＲＣ計算処理の完了後にテイルバイティング畳み込み符号化処理を行う場合）と比較して、全ての情報ビット系列に対する符号化データ（符号化結果）を得るまでの時間を短縮することができるため、符号化スループットを向上させることができる。 Therefore, in the encoding apparatus 100, compared with the case where the CRC calculation process and the tail biting convolutional encoding process are performed serially (that is, when the tail biting convolutional encoding process is performed after the CRC calculation process is completed). Since it is possible to reduce the time required to obtain encoded data (encoding result) for all information bit sequences, it is possible to improve the encoding throughput.
　特に、図３では、符号化装置１００は、送信ビット系列の最後尾から、νビットだけ前のビット位置（つまり、符号化器が備えるシフトレジスタの初期値に設定されるビットの直前のビット位置）にＣＲＣビットの最後尾（最終ビット）が配置されるように、ＣＲＣビットを情報ビット系列に挿入する。これにより、図３に示すＫビットの送信ビット系列では、符号化器が備えるシフトレジスタの初期値に用いられるビット（データ２）以外のビット（データ１）は、ＣＲＣビットよりも前方に配置される。よって、図３では、ＣＲＣビットの計算処理の完了を待たずにテイルバイティング畳み込み符号化されるビット数（つまり、ＣＲＣ計算処理と並列にテイルバイティング畳み込み符号化処理できるビット数）を最大限確保することができ、符号化スループットを最大にすることができる。また、この場合、レジスタ１０３に一時的に記憶される情報ビット系列（送信ビット系列においてＣＲＣビットよりも後方に配置される情報ビット系列）は、符号化器が備えるシフトレジスタの初期化に必要なビット数（（ν－１）ビット）のみで済むため、レジスタ１０３に記憶すべき情報ビット系列のデータ量を必要最小限に抑えることができる。 In particular, in FIG. 3, the encoding apparatus 100 includes a bit position that is ν bits before the end of the transmission bit sequence (that is, the bit position immediately before the bit set to the initial value of the shift register included in the encoder). ), The CRC bits are inserted into the information bit sequence so that the tail end (last bit) of the CRC bits is arranged at (). Thereby, in the K bit transmission bit sequence shown in FIG. 3, bits (data 1) other than the bit (data 2) used for the initial value of the shift register included in the encoder are arranged ahead of the CRC bits. The Therefore, in FIG. 3, the number of bits that are tail-biting convolutionally encoded without waiting for the completion of the CRC bit calculation process (that is, the number of bits that can be tail-biting convolutionally encoded in parallel with the CRC calculation process) is maximized. Can be ensured, and the encoding throughput can be maximized. In this case, the information bit sequence temporarily stored in the register 103 (information bit sequence arranged behind the CRC bit in the transmission bit sequence) is necessary for initialization of the shift register included in the encoder. Since only the number of bits ((ν−1) bits) is required, the amount of data of the information bit sequence to be stored in the register 103 can be minimized.
　また、情報ビット系列のデータ量が大きいほど、ＣＲＣ計算処理の完了を待たずにテイルバイティング畳み込み符号化を行うことができるビット数（送信ビット系列においてＣＲＣビットよりも前方に配置されるビット数）をより多く確保できる。よって、符号化装置１００では、情報ビット系列のデータ量が大きいほど、符号化スループットをより向上させることが可能となる。 In addition, the larger the data amount of the information bit sequence, the more the number of bits that can be tail-biting convolutionally encoded without waiting for the completion of the CRC calculation process (the number of bits arranged ahead of the CRC bits in the transmission bit sequence) ) Can be secured more. Therefore, the encoding apparatus 100 can further improve the encoding throughput as the data amount of the information bit sequence is larger.
　また、符号化装置１００は、符号化器が備えるシフトレジスタの初期化の際、シフトレジスタの初期値に設定される情報ビット系列（図３に示すデータ２）を畳み込み符号化部１０６に転送するとともに、レジスタ１０３に一時的に記憶する。そして、符号化装置１００は、ＣＲＣ計算処理時、及び、データ２に対する畳み込み符号化時には、レジスタ１０３に記憶されているデータ２を読み出す。すなわち、符号化装置１００では、送信データバッファ１０２からのデータ２の読み出し回数（メモリアクセス回数）は１回となる。また、符号化装置１００は、データ２以外の情報ビット系列（図３に示すデータ１）を送信データバッファ１０２から読み出して、ＣＲＣ計算処理と、データ１に対する畳み込み符号化処理とを並列に行う。すなわち、符号化装置１００では、送信データバッファ１０２からのデータ１の読み出し回数（メモリアクセス回数）も１回となる。 Also, the encoding apparatus 100 transfers the information bit sequence (data 2 shown in FIG. 3) set to the initial value of the shift register to the convolutional encoding unit 106 when the shift register included in the encoder is initialized. At the same time, it is temporarily stored in the register 103. Then, the encoding apparatus 100 reads the data 2 stored in the register 103 during the CRC calculation process and the convolutional encoding for the data 2. In other words, in the encoding device 100, the number of times data 2 is read from the transmission data buffer 102 (the number of memory accesses) is one. Also, the encoding apparatus 100 reads an information bit sequence other than the data 2 (data 1 shown in FIG. 3) from the transmission data buffer 102 and performs a CRC calculation process and a convolutional encoding process on the data 1 in parallel. That is, in the encoding device 100, the number of times data 1 is read from the transmission data buffer 102 (the number of memory accesses) is also one.
　ここで、非特許文献１では、ＣＲＣ計算処理とテイルバイティング畳み込み符号化処理とを並列処理できない。そのため、送信機（符号化装置）では、例えば、本実施の形態と同様に図３最上段に示すデータ（情報ビット系列）を符号化する場合には、図５に示すように、ＣＲＣ計算処理を行うタイミング、及び、ＣＲＣ計算後にテイルバイティング畳み込み符号化を行うタイミングのそれぞれで、制御情報（図５に示すデータ）をバッファ（メモリ等）から読み出す。つまり、送信機（符号化装置）は、制御情報（情報ビット系列）をバッファ（メモリ等）から複数回読み出す必要があり、バッファ（メモリ）に対するアクセス回数が多くなるため、消費電力が増大してしまう。 Here, in Non-Patent Document 1, CRC calculation processing and tail biting convolutional coding processing cannot be processed in parallel. Therefore, in the transmitter (encoding device), for example, when the data (information bit sequence) shown in the uppermost part of FIG. 3 is encoded as in the present embodiment, as shown in FIG. The control information (data shown in FIG. 5) is read from the buffer (memory or the like) at each of the timing of performing the tail biting convolutional coding after the CRC calculation. That is, the transmitter (encoding device) needs to read the control information (information bit sequence) from the buffer (memory or the like) a plurality of times, and the number of accesses to the buffer (memory) increases, resulting in an increase in power consumption. End up.
　これに対して、本実施の形態に係る符号化装置１００では、送信データバッファ１０２からの、情報ビット系列（図３に示すデータ１及びデータ２）の読み出し回数が１回で済む。よって、送信データバッファ１０２（メモリ）へのアクセス回数を低く抑えることができるため、メモリアクセスによる消費電力の増大を防ぐことができる。なお、本実施の形態に係る符号化装置１００では、図４に示すように、ＣＲＣ計算を行うためにレジスタ１０３からデータ２を読み出す処理が追加される。しかし、データ２は明らかに情報ビット系列全体（図３に示すデータ（＝データ１＋データ２））より短い。そのため、情報ビット系列全体（図３に示すデータ）を読み直さなくてはならない従来技術（図５）と比較して、本実施の形態に係る符号化装置１００では、処理速度を向上させ、また、消費電力を抑えることができる。なお、データ２が最も短くなるのは、送信ビット系列の最後尾から、νビットだけ前のビット位置にＣＲＣビットの最後尾（最終ビット）が配置される場合である。したがって、この観点からも、本実施の形態に係る符号化装置１００では、このようなビット配置をとる場合が、最も効率よく符号化を行うことができると分かる。 On the other hand, in the encoding apparatus 100 according to the present embodiment, the number of times of reading the information bit series (data 1 and data 2 shown in FIG. 3) from the transmission data buffer 102 is sufficient. Therefore, since the number of accesses to the transmission data buffer 102 (memory) can be kept low, an increase in power consumption due to memory access can be prevented. In addition, in encoding apparatus 100 according to the present embodiment, as shown in FIG. 4, a process of reading data 2 from register 103 is added in order to perform CRC calculation. However, data 2 is clearly shorter than the entire information bit sequence (data shown in FIG. 3 (= data 1 + data 2)). Therefore, compared with the prior art (FIG. 5) in which the entire information bit sequence (data shown in FIG. 3) must be re-read, the encoding apparatus 100 according to the present embodiment improves the processing speed, and , Can reduce power consumption. Note that the data 2 is the shortest when the tail (last bit) of the CRC bits is arranged at a bit position preceding the last bit of the transmission bit sequence by ν bits. Therefore, also from this point of view, it can be understood that encoding apparatus 100 according to the present embodiment can perform encoding most efficiently when such a bit arrangement is adopted.
　このようにして、本実施の形態によれば、テイルバイティング畳み込み符号化を行う符号化装置において、符号化スループットを向上させることができる。さらに、本実施の形態によれば、符号化装置では、バッファからの情報ビット系列の読み出し回数を低く抑えることで、消費電力の増大を防ぐことができる。 Thus, according to the present embodiment, it is possible to improve the coding throughput in the coding apparatus that performs tail biting convolutional coding. Furthermore, according to the present embodiment, the encoding device can prevent an increase in power consumption by keeping the number of times of reading information bit sequences from the buffer low.
　なお、本実施の形態では、図３に示すように、送信ビット系列の最後尾からνビットだけ前のビット位置にＣＲＣビットの最後尾（最終ビット）が配置される場合について説明した。しかし、本発明に係る符号化装置では、これに限らず、送信ビット系列の最後尾から（ν－１）ビットよりも前のビット位置にＣＲＣビットが配置されればよい。すなわち、送信ビット系列ｃｋ（ｋ＝０～Ｋ－１）において、ｃｋ－（ν－１）～ｃｋ－１以外であれば、いずれのビット位置にＣＲＣビットを配置してもよい。例えば、図６に示すように、情報ビット系列であるデータを、先頭からデータ１、データ３、データ２（（ν－１）ビット）に分割し、ＣＲＣビットを、データ１とデータ３との間に挿入してもよい。つまり、図６では、ＣＲＣビットは、送信ビット系列の最後尾から（ν－１）ビットよりも前のビット位置に配置される。なお、図６に示すデータ３のビット数がゼロの場合には図３に示す送信ビット系列と同一になる。図６に示す送信ビット系列を構成する場合でも、上記実施の形態と同様、符号化装置では、ＣＲＣ計算処理と、テイルバイティング畳み込み符号化処理（図６に示すデータ１に対する処理）とを並列に行うことができ、符号化スループットを向上させることができる。 In the present embodiment, as shown in FIG. 3, a case has been described in which the last bit (last bit) of the CRC bits is arranged at a bit position preceding the last bit of the transmission bit sequence by ν bits. However, the coding apparatus according to the present invention is not limited to this, and the CRC bits may be arranged at bit positions before (ν−1) bits from the end of the transmission bit sequence. That is, in the transmission bit sequence c k (k = 0 to K−1), the CRC bits may be arranged at any bit position other than c k− (ν−1) to c k−1 . For example, as shown in FIG. 6, data that is an information bit sequence is divided into data 1, data 3, and data 2 ((ν−1) bits) from the head, and CRC bits are divided between data 1 and data 3. It may be inserted in between. That is, in FIG. 6, the CRC bit is arranged at a bit position before (ν−1) bits from the end of the transmission bit sequence. When the number of bits of data 3 shown in FIG. 6 is zero, it becomes the same as the transmission bit sequence shown in FIG. Even when the transmission bit sequence shown in FIG. 6 is configured, in the encoding apparatus, the CRC calculation processing and the tail biting convolutional encoding processing (processing for data 1 shown in FIG. 6) are performed in parallel as in the above embodiment. And the encoding throughput can be improved.
　また、本実施の形態に係る符号化装置１００（図２）では、送信ビット系列においてＣＲＣビットよりも後方に配置されるビット系列（符号化器が備えるシフトレジスタの初期値として設定される情報ビット系列を含む）を一時的に記憶するためのレジスタ１０３を備える場合について説明した。これは、上述したように、送信データバッファ１０２へのデータ２に関する読み出し回数（メモリアクセス回数）を削減するために備えている。しかし、送信データバッファ１０２へのデータ２に関する読み出し回数が複数になることがシステム全体に影響を与えない場合、又は、メモリアクセスによる消費電力の増大が無視できるほど小さい場合には、レジスタ１０３を削除した構成であってもよい。 Also, in coding apparatus 100 (FIG. 2) according to the present embodiment, a bit sequence (information bits set as an initial value of a shift register included in an encoder) arranged behind CRC bits in a transmission bit sequence The case where the register 103 for temporarily storing (including the series) is provided has been described. As described above, this is provided in order to reduce the number of times of reading (memory access number) related to data 2 to the transmission data buffer 102. However, the register 103 is deleted when there is no influence on the entire system when the number of reads related to the data 2 to the transmission data buffer 102 does not affect the entire system, or when the increase in power consumption due to memory access is negligible. It may be the configuration.
　また、本実施の形態に係る符号化装置では、送信ビット系列に対するＣＲＣビットを計算していたが、これに限るものではない。すなわち、情報ビット系列全体を処理しなくては生成できない他の符号を用いて誤り検出符号化を行う場合であっても、上述した課題と同様の課題が発生しうる。したがって、本実施の形態に係る発明は、ＣＲＣに限らず、チェックサムなどの公知の他の誤り検出符号化に適用してもよい。 In the encoding apparatus according to the present embodiment, the CRC bits for the transmission bit sequence are calculated, but the present invention is not limited to this. That is, even when error detection encoding is performed using another code that cannot be generated without processing the entire information bit sequence, the same problem as described above may occur. Therefore, the invention according to the present embodiment is not limited to CRC, and may be applied to other known error detection coding such as checksum.
　２０１０年２月２４日出願の特願２０１０－０３８９００の日本出願に含まれる明細書、図面および要約書の開示内容は、すべて本願に援用される。 The disclosure of the specification, drawings and abstract contained in the Japanese application of Japanese Patent Application No. 2010-038900 filed on February 24, 2010 is incorporated herein by reference.
　本発明の符号化装置及び符号化方法は、テイルバイティング畳み込み符号を用いた誤り訂正符号化において、符号化スループットを向上させるものとして有用である。 The encoding apparatus and encoding method of the present invention are useful for improving encoding throughput in error correction encoding using tail biting convolutional codes.
　１００　符号化装置
　１０１　読み出しアドレス制御部
　１０２　送信データバッファ
　１０３　レジスタ
　１０４　ＣＲＣ計算部
　１０５　選択・多重部
　１０６　畳み込み符号化部 DESCRIPTION OF SYMBOLS 100 Coding apparatus 101 Read address control part 102 Transmission data buffer 103 Register 104 CRC calculation part 105 Selection / multiplexing part 106 Convolution coding part

Claims (3)

  1. 　情報ビット系列の誤り検出符号化を行って、前記情報ビット系列に対する誤り検出ビットを計算する計算手段と、
    　前記誤り検出ビットを前記情報ビット系列に付加して、送信ビット系列を生成する多重手段と、
    　拘束長νのテイルバイティング畳み込み符号化方式を用いて、前記送信ビット系列を符号化する符号化手段と、を具備し、
    　前記多重手段は、前記送信ビット系列の最後尾から（前記ν－１）ビットよりも前のビット位置に前記誤り検出ビットを配置する、
    　符号化装置。     Calculating means for performing error detection encoding of the information bit sequence and calculating error detection bits for the information bit sequence;
    A multiplexing means for adding the error detection bits to the information bit sequence to generate a transmission bit sequence;
    Encoding means for encoding the transmission bit sequence using a tail biting convolutional encoding scheme with a constraint length ν,
    The multiplexing means arranges the error detection bit at a bit position before (v−1) bits from the tail of the transmission bit sequence.
    Encoding device.
  2. 　前記多重手段は、前記送信ビット系列の最後尾から（前記ν－１）ビットよりも前のビット位置に前記誤り検出ビットが配置され、かつ、前記送信ビット系列の最後尾から前記νビットだけ前のビット位置に前記誤り検出ビットの最後尾が配置されるように、前記誤り検出ビットを前記情報ビット列に挿入する、
    　請求項１記載の符号化装置。     The multiplexing means is arranged such that the error detection bit is arranged at a bit position before (v−1) bits from the tail of the transmission bit sequence, and ν bits before the tail of the transmission bit sequence. Inserting the error detection bit into the information bit string so that the tail of the error detection bit is arranged at the bit position of
    The encoding device according to claim 1.
  3. 　情報ビット系列の誤り検出符号化を行って、前記情報ビット系列に対する誤り検出ビットを計算する計算ステップと、
    　前記誤り検出ビットを前記情報ビット系列に付加して、送信ビット系列を生成する多重ステップと、
    　拘束長νのテイルバイティング畳み込み符号化方式を用いて、前記送信ビット系列を符号化する符号化ステップと、を具備し、
    　前記多重ステップは、前記送信ビット系列の最後尾から（前記ν－１）ビットよりも前のビット位置に前記誤り検出ビットを配置する、
    　符号化方法。     A calculation step of performing error detection encoding of the information bit sequence to calculate an error detection bit for the information bit sequence;
    A multiplexing step of adding the error detection bits to the information bit sequence to generate a transmission bit sequence;
    An encoding step for encoding the transmission bit sequence using a tail length convolutional encoding scheme with a constraint length ν,
    The multiplexing step arranges the error detection bit at a bit position before (v−1) bits from the tail of the transmission bit sequence.
    Encoding method.
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