WO2011100351A1 - Semiconductor die package structure - Google Patents

Semiconductor die package structure Download PDF

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Publication number
WO2011100351A1
WO2011100351A1 PCT/US2011/024226 US2011024226W WO2011100351A1 WO 2011100351 A1 WO2011100351 A1 WO 2011100351A1 US 2011024226 W US2011024226 W US 2011024226W WO 2011100351 A1 WO2011100351 A1 WO 2011100351A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor die
flip chip
package
spacer
die
Prior art date
Application number
PCT/US2011/024226
Other languages
French (fr)
Inventor
Piyush Gupta
Shantanu Kalchuri
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to JP2012552159A priority Critical patent/JP2013519238A/en
Priority to EP11704010A priority patent/EP2534686A1/en
Priority to KR1020127023654A priority patent/KR20120125370A/en
Priority to BR112012020055A priority patent/BR112012020055A2/en
Priority to CN201180009172XA priority patent/CN102763217A/en
Publication of WO2011100351A1 publication Critical patent/WO2011100351A1/en

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Definitions

  • the present disclosure generally relates to packaged semiconductor dies. More specifically, the present disclosure relates to improved semiconductor die packages wherein a first die is placed upon a second die and a spacer.
  • chip packages include multiple semiconductor dies. Some chip packages include a Radio Frequency (RF) die of a small form factor and a larger digital die.
  • RF Radio Frequency
  • FIGURE 1 One prior art chip package is shown in FIGURE 1.
  • the chip package 100 includes an RF die 101 and a digital die 102.
  • the larger digital die 102 is structured as a flip chip Ball Grid Array (BGA), and the RF die 101 uses wire bond structures.
  • BGA Ball Grid Array
  • the chip package 100 uses the capillary underfill 103, which increases the production cost and results in a larger overall package, since the capillary underfill 103 extends outwardly somewhat from the length and width dimensions of the larger digital die 102.
  • wire bonds with the stacked RF die 101 tends to degrade RF performance because the inductance of the wire is very high and causes nonlinearities in the RF die 101.
  • Various embodiments of the present disclosure include a system in a package that has a flip chip semiconductor die on a package substrate, a spacer on the package substrate, and a wire bond semiconductor die supported by the spacer and the flip chip semiconductor die.
  • a chip package includes a flip chip semiconductor die on a package substrate, means for dissipating heat on the package substrate, and a wire bond semiconductor die supported by the heat dissipation means and the flip chip semiconductor die.
  • a method for assembling a system in a package includes disposing a flip chip semiconductor die on a package substrate, disposing a flip chip spacer on the package substrate, and disposing a wire bond semiconductor die onto the spacer and the flip chip semiconductor die.
  • a system in a package comprises a flip chip semiconductor die on a package substrate, means for providing mechanical support disposed upon the package substrate, and a wire bond semiconductor die disposed upon the mechanical supporting means and the flip chip semiconductor die.
  • FIGURE 1 is an illustration of a prior art chip package.
  • FIGURE 2 is a block diagram showing an exemplary wireless communication system in which an embodiment of the disclosure may be advantageously employed.
  • FIGURES 3A and 3B are top view and side view block diagrams, respectively of an exemplary chip package, adapted according to one embodiment of the disclosure.
  • FIGURE 4 is an illustration of an exemplary chip package, adapted according to one embodiment of the disclosure.
  • FIGURE 5 is an illustration of an exemplary process, adapted according to one embodiment of the disclosure, for making a chip package.
  • FIGURE 2 shows an exemplary wireless communication system
  • FIGURE 1 shows three remote units 220, 230, and 240 and two base stations 250 and 260. It will be recognized that wireless communication systems may have many more remote units and base stations.
  • Remote units 220, 230, and 240 include improved semiconductor die packages 225A, 225B, and 225C, respectively, which are embodiments as discussed further below.
  • FIGURE 2 shows forward link signals 280 from the base stations 250 and 260 and the remote units 220, 230, and 240 and reverse link signals 290 from the remote units 220, 230, and 240 to base stations 250 and 260.
  • remote unit 220 is shown as a mobile telephone
  • remote unit 230 is shown as a portable computer
  • remote unit 240 is shown as a computer in a wireless local loop system.
  • the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, media players, such as music players, video players, and entertainment units, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
  • PCS personal communication systems
  • FIGURE 2 illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units.
  • the disclosure may be suitably employed in any device which includes a semiconductor die package.
  • FIGURES 3A and 3B are top view and side view block diagrams, respectively, of the exemplary chip package 300, adapted according to one embodiment of the disclosure.
  • FIGURE 3A shows a top-down view of the chip package 300.
  • FIGURE 3B shows a side view of the chip package 300.
  • the chip package 300 includes an RF die 301, implemented as a flip-chip BGA, a digital die 302 with wire bonds 304, and a spacer 303 disposed upon a package substrate 305.
  • the digital die 302 is disposed upon, and supported by, the spacer 303 and the RF chip 301. Since the RF die 301 is implemented as a flip chip BGA, it does not suffer the decreased RF performance of the embodiment shown in FIGURE 1.
  • the chip package 300 can forego use of a capillary underfill in favor the Mold-Only Underfill (MUF) 306 because the mold-only underfill 306 encases and adequately supports both chips 301 and 302.
  • the mold-only underfill process is limited for use with small dies and high pitch dies.
  • the smaller die (301) is a flip chip die with a larger pitch so that it is readily adapted for use with a mold-only underfill process.
  • the larger digital die 102 is a flip chip die with a small pitch, making a mold-only underfill process less desirable than the capillary underfill 103.
  • underfill adheres a die to its contact on a package to protect against the effects of thermal expansion and mechanical shock.
  • the mold-only underfill 306 is underfill that encapsulates the entire package, rather than a single die.
  • the embodiment shown in FIGURES 3A and 3B takes advantage of the mold-only underfill 306 as an underfill for the RF die 301, thereby eliminating steps taken by the prior art of FIGURE 1 to apply capillary underfill. It should be noted, though, that various embodiments do not exclude the use of capillary underfill.
  • the RF die 301 is placed somewhat off-center of the package 300 so that the signals therefrom can be routed easily to the edge of the package 300. However, were the spacer 303 to be eliminated from the package 300, the amount of overhang of the digital die 302 would be excessive. Thus, in one aspect, the spacer 303 provides mechanical support for the digital die 302 while allowing the RF die 301 to be placed off-center. Furthermore, in the embodiment of FIGURES 3A and 3B, the mold- only underfill 306 is made of epoxy with particulates, such as silica particles. The spacer 303, in this embodiment, is made of silicon which conducts heat more effectively than the epoxy compound of the mold-only underfill 306.
  • the spacer 303 by virtue of its material, provides a path for heat from the digital die 302 to be transferred to the substrate 305 thereby providing heat dissipation.
  • the spacer 303 includes thermally conductive materials, such as copper, in through vias to further increase the heat transfer capabilities of the spacer 303.
  • FIGURE 4 is an illustration of an exemplary chip package 400, adapted according to one embodiment of the disclosure.
  • Passive devices include, for example, inductors, capacitors, and resistors.
  • the chip package 400 includes a spacer 403, implemented as a flip chip BGA, with passive devices integrated thereon (not shown).
  • the passive devices are in electrical communication with other components in the chip package 400 by virtue of the flip chip contacts of the spacer 403, and the spacer 403 provides mechanical support and heat transfer as described above with respect to FIGURES 3 A and 3B.
  • Implementing passive devices upon a spacer, such as the spacer 403, may in some embodiments save space by moving otherwise externally-placed passive devices within the footprint of the spacer.
  • chip packages may include two or more of each.
  • some embodiments may include two or more structures that each include a wire bond die disposed on top of a spacer and a flip chip die.
  • other embodiments may include structures that each include a wire bond die disposed upon one or more spacers and one or more flip chip dies.
  • suitable materials now known or later developed for substrates, dies, spacers and underfills may be incorporated into various embodiments of the disclosure.
  • FIGURE 5 is an illustration of the exemplary process 500, adapted according to one embodiment of the disclosure, for making a chip package.
  • Process 500 may be performed, for example, by one or more machines and computer- controlled processes in a fabrication facility.
  • a flip chip semiconductor die is disposed on a package substrate.
  • the flip chip semiconductor die includes an RF die.
  • the block 501 can include any of a variety of suitable techniques for disposing the semiconductor die, including but not limited to, aligning solder bumps on the semiconductor die with contacts on the package substrate and flowing the solder material after alignment.
  • a spacer is disposed upon the package substrate.
  • the spacer may be disposed upon the package substrate in a manner similar to techniques used to dispose the die on the package substrate in block 501.
  • the spacer is a dummy spacer, it may be disposed upon the package substrate by, for example, use of epoxy die attach material.
  • a wire bond semiconductor die is disposed onto the spacer and the flip chip semiconductor die by, e.g., use of epoxy die attach material.
  • types of digital dies include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), general purpose processors, and the like.
  • DSPs Digital Signal Processors
  • ASICs Application Specific Integrated Circuits
  • the block 503 in some embodiments also includes making the wire bond connections between the contacts of the wire bond semiconductor die and the package substrate.
  • mold-only underfill is applied to the package so that the mold underfill surrounds the flip chip semiconductor die, the spacer and the wire bond die, as is shown in FIGURES 3A, 3B, and 4.
  • the package itself is completed, it is ready to be installed in one or more devices, such as a cell phone, a navigation device, a media player, a personal digital assistant (PDA), a computer, or the like.
  • devices such as a cell phone, a navigation device, a media player, a personal digital assistant (PDA), a computer, or the like.
  • the process 500 is shown as a series of discrete processes, but embodiments are not necessarily limited to the process shown in FIGURE 5. Some embodiments may add, omit, rearrange, or modify one or more blocks in process 500. For instance, blocks 501 and 502 may be transposed or performed at the same time. Furthermore, in some embodiments, capillary underfill may be applied to the flip chip semiconductor die, whereas it may be omitted in favor of the mold-only underfill in other embodiments. Moreover, various embodiments may include integrating passive devices upon the spacer by, for example, thin film processing.
  • Various embodiments include advantages over prior art chip packages. For instance, some embodiments increase RF performance by implementing an RF chip as a flip chip BGA, rather than as a wire bond structure, without increasing the size of the package as a whole. In fact, some embodiments utilize a smaller package than that shown in FIGURE 1 by utilizing vertical stacking and eliminating capillary underfill. Additionally, some embodiments take advantage of the heat conducting properties of silicon (or other) material in spacers by using spacers for heat dissipation of a wire bond die.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A system in a package comprising a flip chip semiconductor die on a package substrate, a spacer on the package substrate, and a wire bond semiconductor die supported by the spacer and the flip chip semiconductor die.

Description

SEMICONDUCTOR DIE PACKAGE STRUCTURE
TECHNICAL FIELD
[0001] The present disclosure generally relates to packaged semiconductor dies. More specifically, the present disclosure relates to improved semiconductor die packages wherein a first die is placed upon a second die and a spacer.
BACKGROUND
[0002] Conventionally, chip packages include multiple semiconductor dies. Some chip packages include a Radio Frequency (RF) die of a small form factor and a larger digital die. One prior art chip package is shown in FIGURE 1. The chip package 100 includes an RF die 101 and a digital die 102. In FIGURE 1, the larger digital die 102 is structured as a flip chip Ball Grid Array (BGA), and the RF die 101 uses wire bond structures. The chip package 100 uses the capillary underfill 103, which increases the production cost and results in a larger overall package, since the capillary underfill 103 extends outwardly somewhat from the length and width dimensions of the larger digital die 102. Furthermore, using wire bonds with the stacked RF die 101 tends to degrade RF performance because the inductance of the wire is very high and causes nonlinearities in the RF die 101. Another approach, not shown herein, implements both of the dies 101 and 102 with wire bond structures. Such approach also suffers from decreased RF performance.
[0003] Yet another approach, also not shown herein, places both dies
101 and 102 side-by-side in the package. However, the side-by-side approach comes at a cost of increased package size, even more so than for the embodiment shown in FIGURE 1.
BRIEF SUMMARY
[0004] Various embodiments of the present disclosure include a system in a package that has a flip chip semiconductor die on a package substrate, a spacer on the package substrate, and a wire bond semiconductor die supported by the spacer and the flip chip semiconductor die.
[0005] According to another embodiment, a chip package includes a flip chip semiconductor die on a package substrate, means for dissipating heat on the package substrate, and a wire bond semiconductor die supported by the heat dissipation means and the flip chip semiconductor die.
[0006] According to another embodiment of the disclosure, a method for assembling a system in a package includes disposing a flip chip semiconductor die on a package substrate, disposing a flip chip spacer on the package substrate, and disposing a wire bond semiconductor die onto the spacer and the flip chip semiconductor die.
[0007] According to yet another embodiment of the disclosure, a system in a package comprises a flip chip semiconductor die on a package substrate, means for providing mechanical support disposed upon the package substrate, and a wire bond semiconductor die disposed upon the mechanical supporting means and the flip chip semiconductor die.
[0008] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the technology of the disclosure as set forth in the appended claims. The novel features which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings.
[0010] FIGURE 1 is an illustration of a prior art chip package. [0011] FIGURE 2 is a block diagram showing an exemplary wireless communication system in which an embodiment of the disclosure may be advantageously employed.
[0012] FIGURES 3A and 3B are top view and side view block diagrams, respectively of an exemplary chip package, adapted according to one embodiment of the disclosure.
[0013] FIGURE 4 is an illustration of an exemplary chip package, adapted according to one embodiment of the disclosure.
[0014] FIGURE 5 is an illustration of an exemplary process, adapted according to one embodiment of the disclosure, for making a chip package.
DETAILED DESCRIPTION
[0015] FIGURE 2 shows an exemplary wireless communication system
200 in which an embodiment of the disclosure may be advantageously employed. For purposes of illustration, FIGURE 1 shows three remote units 220, 230, and 240 and two base stations 250 and 260. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units 220, 230, and 240 include improved semiconductor die packages 225A, 225B, and 225C, respectively, which are embodiments as discussed further below. FIGURE 2 shows forward link signals 280 from the base stations 250 and 260 and the remote units 220, 230, and 240 and reverse link signals 290 from the remote units 220, 230, and 240 to base stations 250 and 260.
[0016] In FIGURE 2, remote unit 220 is shown as a mobile telephone, remote unit 230 is shown as a portable computer, and remote unit 240 is shown as a computer in a wireless local loop system. For example, the remote units may be mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, GPS enabled devices, navigation devices, set top boxes, media players, such as music players, video players, and entertainment units, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof. Although FIGURE 2 illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. The disclosure may be suitably employed in any device which includes a semiconductor die package. [0017] FIGURES 3A and 3B are top view and side view block diagrams, respectively, of the exemplary chip package 300, adapted according to one embodiment of the disclosure. FIGURE 3A shows a top-down view of the chip package 300. FIGURE 3B shows a side view of the chip package 300.
[0018] The chip package 300 includes an RF die 301, implemented as a flip-chip BGA, a digital die 302 with wire bonds 304, and a spacer 303 disposed upon a package substrate 305. In the chip package 300, the digital die 302 is disposed upon, and supported by, the spacer 303 and the RF chip 301. Since the RF die 301 is implemented as a flip chip BGA, it does not suffer the decreased RF performance of the embodiment shown in FIGURE 1.
[0019] Furthermore the chip package 300, in some embodiments, can forego use of a capillary underfill in favor the Mold-Only Underfill (MUF) 306 because the mold-only underfill 306 encases and adequately supports both chips 301 and 302. Typically, the mold-only underfill process is limited for use with small dies and high pitch dies. In FIGURE 3, the smaller die (301) is a flip chip die with a larger pitch so that it is readily adapted for use with a mold-only underfill process. By contrast, in FIGURE 1, the larger digital die 102 is a flip chip die with a small pitch, making a mold-only underfill process less desirable than the capillary underfill 103. As is known in the art, underfill adheres a die to its contact on a package to protect against the effects of thermal expansion and mechanical shock. The mold-only underfill 306 is underfill that encapsulates the entire package, rather than a single die. The embodiment shown in FIGURES 3A and 3B takes advantage of the mold-only underfill 306 as an underfill for the RF die 301, thereby eliminating steps taken by the prior art of FIGURE 1 to apply capillary underfill. It should be noted, though, that various embodiments do not exclude the use of capillary underfill.
[0020] The RF die 301 is placed somewhat off-center of the package 300 so that the signals therefrom can be routed easily to the edge of the package 300. However, were the spacer 303 to be eliminated from the package 300, the amount of overhang of the digital die 302 would be excessive. Thus, in one aspect, the spacer 303 provides mechanical support for the digital die 302 while allowing the RF die 301 to be placed off-center. Furthermore, in the embodiment of FIGURES 3A and 3B, the mold- only underfill 306 is made of epoxy with particulates, such as silica particles. The spacer 303, in this embodiment, is made of silicon which conducts heat more effectively than the epoxy compound of the mold-only underfill 306. Thus, the spacer 303, by virtue of its material, provides a path for heat from the digital die 302 to be transferred to the substrate 305 thereby providing heat dissipation. In another embodiment, the spacer 303 includes thermally conductive materials, such as copper, in through vias to further increase the heat transfer capabilities of the spacer 303.
[0021] FIGURE 4 is an illustration of an exemplary chip package 400, adapted according to one embodiment of the disclosure. In many embodiments it is possible to use a thin-film deposition process to implement passive devices on one or more spacers. Passive devices include, for example, inductors, capacitors, and resistors. The chip package 400 includes a spacer 403, implemented as a flip chip BGA, with passive devices integrated thereon (not shown). The passive devices are in electrical communication with other components in the chip package 400 by virtue of the flip chip contacts of the spacer 403, and the spacer 403 provides mechanical support and heat transfer as described above with respect to FIGURES 3 A and 3B. Implementing passive devices upon a spacer, such as the spacer 403, may in some embodiments save space by moving otherwise externally-placed passive devices within the footprint of the spacer.
[0022] The embodiments shown above include one wire bond die, one spacer, and one smaller flip chip die, but embodiments are not so limited. For instance, chip packages may include two or more of each. Thus, some embodiments may include two or more structures that each include a wire bond die disposed on top of a spacer and a flip chip die. Moreover, other embodiments may include structures that each include a wire bond die disposed upon one or more spacers and one or more flip chip dies. Furthermore, while specific materials have been mentioned above, it is noted that other suitable materials now known or later developed for substrates, dies, spacers and underfills may be incorporated into various embodiments of the disclosure.
[0023] FIGURE 5 is an illustration of the exemplary process 500, adapted according to one embodiment of the disclosure, for making a chip package. Process 500 may be performed, for example, by one or more machines and computer- controlled processes in a fabrication facility.
[0024] In the block 501, a flip chip semiconductor die is disposed on a package substrate. In some embodiments the flip chip semiconductor die includes an RF die. The block 501 can include any of a variety of suitable techniques for disposing the semiconductor die, including but not limited to, aligning solder bumps on the semiconductor die with contacts on the package substrate and flowing the solder material after alignment.
[0025] In the block 502, a spacer is disposed upon the package substrate.
In embodiments wherein the spacer has passive devices integrated thereon, the spacer may be disposed upon the package substrate in a manner similar to techniques used to dispose the die on the package substrate in block 501. In embodiments wherein the spacer is a dummy spacer, it may be disposed upon the package substrate by, for example, use of epoxy die attach material.
[0026] In the block 503, a wire bond semiconductor die is disposed onto the spacer and the flip chip semiconductor die by, e.g., use of epoxy die attach material. Examples of types of digital dies include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), general purpose processors, and the like. The block 503 in some embodiments also includes making the wire bond connections between the contacts of the wire bond semiconductor die and the package substrate.
[0027] In the block 504, mold-only underfill is applied to the package so that the mold underfill surrounds the flip chip semiconductor die, the spacer and the wire bond die, as is shown in FIGURES 3A, 3B, and 4. Once the package itself is completed, it is ready to be installed in one or more devices, such as a cell phone, a navigation device, a media player, a personal digital assistant (PDA), a computer, or the like.
[0028] The process 500 is shown as a series of discrete processes, but embodiments are not necessarily limited to the process shown in FIGURE 5. Some embodiments may add, omit, rearrange, or modify one or more blocks in process 500. For instance, blocks 501 and 502 may be transposed or performed at the same time. Furthermore, in some embodiments, capillary underfill may be applied to the flip chip semiconductor die, whereas it may be omitted in favor of the mold-only underfill in other embodiments. Moreover, various embodiments may include integrating passive devices upon the spacer by, for example, thin film processing.
[0029] Various embodiments include advantages over prior art chip packages. For instance, some embodiments increase RF performance by implementing an RF chip as a flip chip BGA, rather than as a wire bond structure, without increasing the size of the package as a whole. In fact, some embodiments utilize a smaller package than that shown in FIGURE 1 by utilizing vertical stacking and eliminating capillary underfill. Additionally, some embodiments take advantage of the heat conducting properties of silicon (or other) material in spacers by using spacers for heat dissipation of a wire bond die.
[0030] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the technology of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

CLAIMS What is claimed is:
1. A system in a package comprising:
a flip chip semiconductor die on a package substrate;
a spacer on the package substrate; and
a wire bond semiconductor die supported by the spacer and the flip chip semiconductor die.
2. The system of claim 1 further comprising a mold underfill surrounding the flip chip semiconductor die, the spacer and the wire bond semiconductor die.
3. The system of claim 2 in which the mold underfill comprises an epoxy material.
4. The system of claim 1 further comprising a capillary underfill surrounding at least a portion of the flip chip semiconductor die.
5. The system of claim 1 in which the spacer comprises an integrated passive device.
6. The system of claim 1 in which the system in a package is disposed in an item selected from a group consisting of:
a handheld device; and
a personal computer.
7. The system of claim 1 in which the flip chip semiconductor die comprises a Radio Frequency (RF) die.
8. The system of claim 1 in which the wire bond semiconductor die comprises a digital die.
9. The system of claim 1 in which the spacer and wire bond semiconductor die are thermally coupled.
10. The system of claim 9 in which the spacer comprises a material that has a greater thermal conductivity than a mold underfill that is disposed on the package substrate.
11. A method for assembling a system in a package, comprising:
disposing a flip chip semiconductor die on a package substrate;
disposing a spacer on the package substrate; and
disposing a wire bond semiconductor die onto the spacer and the flip chip semiconductor die.
12. The method of claim 11 further comprising:
applying mold underfill to the package so that the mold underfill surrounds the flip chip semiconductor die, the spacer and the wire bond semiconductor die.
13. The method of claim 11 further comprising:
integrating at least one passive devices on the spacer.
14. The method of claim 11 further comprising installing the system in a package in a device selected from a group consisting of:
a media player;
a navigation device;
a communication device;
a personal digital assistant (PDA); and
a computer.
15. A system in a package, comprising:
a flip chip semiconductor die on a package substrate;
means for dissipating heat on the package substrate; and
a wire bond semiconductor die supported by the heat dissipation means and the flip chip semiconductor die.
16. The system of claim 15 further comprising a mold underfill surrounding the flip chip semiconductor die, the heat dissipation means and the wire bond semiconductor die.
17. The system of claim 15 comprising no capillary underfill surrounding the flip chip semiconductor die.
18. A system in a package, comprising:
a flip chip semiconductor die on a package substrate;
means, disposed upon the package substrate, for providing mechanical support; and
a wire bond semiconductor die disposed upon the mechanical supporting means and the flip chip semiconductor die.
19. The system of claim 18 in which the mechanical supporting means comprises an integrated passive device and a ball grid array.
20. The system of claim 18 in which the flip chip semiconductor die comprises a Radio Frequency (RF) die.
PCT/US2011/024226 2010-02-10 2011-02-09 Semiconductor die package structure WO2011100351A1 (en)

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KR1020127023654A KR20120125370A (en) 2010-02-10 2011-02-09 Semiconductor die package structure
BR112012020055A BR112012020055A2 (en) 2010-02-10 2011-02-09 semiconductor wafer package structure.
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130286595A1 (en) * 2012-04-27 2013-10-31 Qualcomm Incorporated Thermal management floorplan for a multi-tier stacked ic package
US9418974B2 (en) 2014-04-29 2016-08-16 Micron Technology, Inc. Stacked semiconductor die assemblies with support members and associated systems and methods
JP2016529716A (en) * 2014-07-07 2016-09-23 インテル アイピー コーポレーション Package-on-package multilayer microelectronic structure
US9978732B2 (en) * 2014-09-30 2018-05-22 Skyworks Solutions, Inc. Network with integrated passive device and conductive trace in packaging substrate and related modules and devices
CN107369678A (en) * 2016-05-13 2017-11-21 北京中电网信息技术有限公司 A kind of system-in-a-package method and its encapsulation unit
US10037970B2 (en) 2016-09-08 2018-07-31 Nxp Usa, Inc. Multiple interconnections between die
US20190287881A1 (en) * 2018-03-19 2019-09-19 Stmicroelectronics S.R.L. Semiconductor package with die stacked on surface mounted devices
KR102540050B1 (en) 2018-07-05 2023-06-05 삼성전자주식회사 Semiconductor package
US11081468B2 (en) * 2019-08-28 2021-08-03 Micron Technology, Inc. Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030045029A1 (en) * 2000-05-11 2003-03-06 Yoshiaki Emoto Semiconductor device and method for manufacturing the same
US20040145040A1 (en) * 2003-01-29 2004-07-29 Toshiyuki Fukuda Semiconductor device and manufacturing method for the same
US20050156323A1 (en) * 2004-01-08 2005-07-21 Matsushita Electric Industrial Co., Ltd. Semiconductor apparatus
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
EP1724833A2 (en) * 2005-05-20 2006-11-22 NEC Electronics Corporation SIP (system-in-package) type package containing analog semiconductor chip and digital semiconductor chip stacked in order, and method for manufacturing the same
US20080017976A1 (en) * 2003-09-30 2008-01-24 Intel Corporation Capillary underfill and mold encapsulation method and apparatus
US20090166887A1 (en) * 2007-12-27 2009-07-02 Suresh Upadhyayula Semiconductor package including flip chip controller at bottom of die stack

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7479407B2 (en) * 2002-11-22 2009-01-20 Freescale Semiconductor, Inc. Digital and RF system and method therefor
JP2005303056A (en) * 2004-04-13 2005-10-27 Toshiba Corp Semiconductor integrated circuit device
US7116002B2 (en) * 2004-05-10 2006-10-03 Taiwan Semiconductor Manufacturing Company, Ltd. Overhang support for a stacked semiconductor device, and method of forming thereof
KR100665217B1 (en) * 2005-07-05 2007-01-09 삼성전기주식회사 A semiconductor multi-chip package
KR100764682B1 (en) * 2006-02-14 2007-10-08 인티그런트 테크놀로지즈(주) Ic chip and package
JP4331179B2 (en) * 2006-03-20 2009-09-16 パナソニック株式会社 Semiconductor device
US7592702B2 (en) * 2006-07-31 2009-09-22 Intel Corporation Via heat sink material
TWI319618B (en) * 2006-12-18 2010-01-11 Advanced Semiconductor Eng Three dimensional package and method of making the same
US7851906B2 (en) * 2007-03-26 2010-12-14 Endicott Interconnect Technologies, Inc. Flexible circuit electronic package with standoffs
US7691747B2 (en) * 2007-11-29 2010-04-06 STATS ChipPAC, Ltd Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8405197B2 (en) * 2009-03-25 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system with stacked configuration and method of manufacture thereof
US9093391B2 (en) * 2009-09-17 2015-07-28 Stats Chippac Ltd. Integrated circuit packaging system with fan-in package and method of manufacture thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030045029A1 (en) * 2000-05-11 2003-03-06 Yoshiaki Emoto Semiconductor device and method for manufacturing the same
US20040145040A1 (en) * 2003-01-29 2004-07-29 Toshiyuki Fukuda Semiconductor device and manufacturing method for the same
US20080017976A1 (en) * 2003-09-30 2008-01-24 Intel Corporation Capillary underfill and mold encapsulation method and apparatus
US6930378B1 (en) * 2003-11-10 2005-08-16 Amkor Technology, Inc. Stacked semiconductor die assembly having at least one support
US20050156323A1 (en) * 2004-01-08 2005-07-21 Matsushita Electric Industrial Co., Ltd. Semiconductor apparatus
EP1724833A2 (en) * 2005-05-20 2006-11-22 NEC Electronics Corporation SIP (system-in-package) type package containing analog semiconductor chip and digital semiconductor chip stacked in order, and method for manufacturing the same
US20090166887A1 (en) * 2007-12-27 2009-07-02 Suresh Upadhyayula Semiconductor package including flip chip controller at bottom of die stack

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2534686A1 *

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JP2013519238A (en) 2013-05-23
TW201140769A (en) 2011-11-16
KR20120125370A (en) 2012-11-14
BR112012020055A2 (en) 2016-05-10
US20110193243A1 (en) 2011-08-11
CN102763217A (en) 2012-10-31
EP2534686A1 (en) 2012-12-19

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