WO2011099113A1 - Differential amplifier circuit - Google Patents

Differential amplifier circuit Download PDF

Info

Publication number
WO2011099113A1
WO2011099113A1 PCT/JP2010/051849 JP2010051849W WO2011099113A1 WO 2011099113 A1 WO2011099113 A1 WO 2011099113A1 JP 2010051849 W JP2010051849 W JP 2010051849W WO 2011099113 A1 WO2011099113 A1 WO 2011099113A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistors
input stage
input
pair
emitter
Prior art date
Application number
PCT/JP2010/051849
Other languages
French (fr)
Japanese (ja)
Inventor
俊也 土生
Original Assignee
株式会社島津製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社島津製作所 filed Critical 株式会社島津製作所
Priority to PCT/JP2010/051849 priority Critical patent/WO2011099113A1/en
Publication of WO2011099113A1 publication Critical patent/WO2011099113A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45352—Indexing scheme relating to differential amplifiers the AAC comprising a combination of a plurality of transistors, e.g. Darlington coupled transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45371—Indexing scheme relating to differential amplifiers the AAC comprising parallel coupled multiple transistors at their source and gate and drain or at their base and emitter and collector, e.g. in a cascode dif amp, only those forming the composite common source transistor or the composite common emitter transistor respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45466—Indexing scheme relating to differential amplifiers the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45468—Indexing scheme relating to differential amplifiers the CSC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45496—Indexing scheme relating to differential amplifiers the CSC comprising one or more extra resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45498—Indexing scheme relating to differential amplifiers the CSC comprising only resistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45702—Indexing scheme relating to differential amplifiers the LC comprising two resistors

Definitions

  • the present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit that amplifies a signal in a microwave band.
  • FIG. 3 is a configuration diagram of a conventionally known differential amplifier circuit using transistors (see, for example, Patent Document 1).
  • the two transistors 10 and 12 in the input stage having the same characteristics are arranged symmetrically, and the voltage V ref + V dif given to the first input terminal 11 is input to the base terminal of the first input stage transistor 10.
  • the voltage V ref applied to the second input terminal 13 is input to the base terminal of the second input stage transistor 12.
  • the emitter terminals of the transistors 10 and 12 are connected to the suction end of a common constant current source 21 via resistors 19 and 20 having a resistance value R E , respectively.
  • the collector terminals of the transistors 10 and 12 are respectively connected to the positive power supply line of the voltage V CC via the resistors 14 and 15 having a resistance value R C.
  • a load resistor 16 having a resistance value R L is connected between the collector terminals of the transistors 10 and 12.
  • the emitter currents of the input stage transistors 10 and 12 are equal to each other at I 0 .
  • the emitter current of the first input stage transistor 10 increases to I 0 + I dif , and conversely, the emitter current of the second input stage transistor 12 is I 0.
  • I def (V dif / 2R E ) ⁇ ⁇ ( ⁇ V be1 ⁇ V be2 ) / 2R E ⁇ (2) It becomes.
  • R out R c // (R L / 2) It is. That is, it is ideal that the input and output of the differential amplifier circuit are proportional to each other.
  • the transistor generally has a linearity error due to nonlinearity, the second term on the right side of the equation (2) is It will not be zero. Therefore, the input and output of the differential amplifier circuit are not completely proportional.
  • the present invention has been made in view of the above problems, and has as its main object to improve the frequency characteristics of a differential amplifier circuit.
  • first and second input signals are input to the base terminals of a pair of input stage transistors, and the collector terminals of the input stage transistors are respectively connected via resistors.
  • a differential amplifier circuit connected to a positive power supply and extracting a signal corresponding to a difference between the first and second input signals from between a collector terminal of a pair of input stage transistors;
  • the emitter terminals of the pair of input transistors are connected to the collector terminals of a pair of compensation transistors, and the emitter terminals of the pair of compensation transistors are connected to a common constant current source through resistors, respectively.
  • Each of the base terminals of the compensation transistor is connected to the collector terminal of the other compensation transistor.
  • the input stage transistor and the compensating transistor having the collector terminal connected to the emitter terminal thereof have the same characteristics. Since the influence of the base-emitter voltage change of the pair of input stage transistors is canceled by the base-emitter voltage change due to the current flowing through each of the pair of compensation transistors, the relationship between the input differential voltage and the output voltage, In other words, the gain is determined simply by the value of the resistance serving as a load. Thereby, the relationship between the input and the output can be made proportional without the input stage transistor being connected in parallel with a plurality of transistors.
  • the compensation transistor is arranged on the emitter side (low voltage side) of the input stage transistor, but the compensation transistor is arranged on the collector side (high voltage side) of the input stage transistor. It can also be modified to arrange. However, in that case, a common bias voltage is applied to each base terminal of the pair of compensation transistors.
  • the first and second input signals are inputted to the base terminals of the pair of input stage transistors, and the emitter terminals of the input stage transistors have resistances respectively.
  • a differential amplifier circuit that is connected to a common constant current source through which a signal corresponding to the difference between the first and second input signals is extracted from between the collector terminals of the pair of input stage transistors,
  • the collector terminals of the pair of input stage transistors are connected to the emitter terminals of the pair of compensation transistors through resistors, respectively, and a common bias voltage is applied to the base terminals of the pair of compensation transistors. Both collector terminals are connected to a positive power source.
  • the pair of input stage transistors and the pair of compensation transistors all have the same characteristics.
  • the relationship between the input differential voltage and the output voltage can be made proportional without the input stage transistor being connected in parallel with a plurality of transistors. Therefore, the demerit of connecting the input stage transistor in parallel with a plurality of transistors, that is, stray inductance or stray capacitance due to the wiring pattern for connecting the plurality of transistors in parallel on the circuit board, or between the plurality of parallel transistors There is no restriction on the frequency band due to the difference in signal propagation delay time, and the frequency characteristics can be improved. Further, the linearity error of input / output is reduced, and the gain of the amplifier circuit is determined only by the resistance value of the resistor, so that the gain accuracy and stability are improved.
  • the block diagram of the differential amplifier circuit by one Example (1st Example) of 1st invention The block diagram of the differential amplifier circuit by one Example (2nd Example) of 2nd invention.
  • the block diagram of the conventional differential amplifier circuit The block diagram of the conventional differential amplifier circuit.
  • FIG. 1 is a block diagram of a differential amplifier circuit according to the first embodiment.
  • the same components as those of the conventional differential amplifier circuit shown in FIGS. 3 and 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the base terminals of the pair of compensation transistors 17 and 18 are connected to the collector terminal of the other compensation transistor, respectively.
  • the compensating transistors 17 and 18 have the same characteristics as the input stage transistors 10 and 12.
  • the emitter current of the first input stage transistor 10 and the emitter current of the first compensating transistor 17 are equal. Since the transistors 10 and 17 have the same characteristics, if the emitter currents are equal, the base-emitter voltage changes are equal, and both are ⁇ V be1 . Similarly, since the emitter current of the second input stage transistor 12 and the emitter current of the second compensation transistor 18 are equal, the base-emitter voltage changes of the transistors 12 and 18 are also equal, both of which are ⁇ V be2 .
  • the emitter potential of the first compensation transistor 17 is V ref ⁇ V be2 ⁇ V be1
  • the emitter potential of the second compensation transistor 18 is V ref + V dif ⁇ V be2 ⁇ V be1 .
  • R out R c // ( RL / 2). That is, the voltage change ⁇ V out of the differential output is proportional to the voltage change V def of the input, and the linearity error unlike the conventional differential amplifier circuit described above does not occur.
  • FIG. 2 is a block diagram of a differential amplifier circuit according to the second embodiment.
  • compensation transistors 30 and 31 having the same characteristics as the input stage transistors 10 and 12 are respectively disposed between the resistors 14 and 15 and the positive power supply line.
  • a common bias voltage V BB is applied to the base terminals of the first compensation transistor 30 and the second compensation transistor 31.
  • the resistors 14 and 15 themselves serve as load resistors, and the output voltage ⁇ V out is taken out between the collector terminals of the input stage transistors 10 and 12.
  • V def (V def ⁇ 2 ⁇ V BE ) / 2R E (8) It becomes.
  • the gain G of the circuit of FIG. 1 is obtained as 2.0 using the above equation (6). This also almost coincides with the results in Table 1.
  • the circuit of FIG. 1 differs from the circuit of FIG. 3 in that the transistor characteristic value (emitter equivalent resistance) does not contribute to the gain, and the gain is determined simply by the resistance value of the resistance element. As a result, gain accuracy and stability can be improved.

Abstract

Between each emitter terminal of one pair of input stage transistors (10 and 12) and resistors (19 and 20), compensating transistors (17 and 18) are inserted, respectively, and each base terminal of the transistors (17 and 18) is mutually connected to the collector terminal of the other transistor (17 or 18). The effects of changes in the base-to-emitter voltage of the input stage transistors (10 and 12) are cancelled by changes in the base-to-emitter voltage of the compensating transistors (17 and 18), and therefore, the proportionality of the relationship of the differential voltage Vdif of the input to the output voltage ΔVout does not depend on equivalent resistance of the emitters of the transistors, but only on the values of the resistors (14 to 16). As a result, the need as in the prior art to connect a plurality of transistors in parallel at the input stage does not exist, and therefore, it is possible to improve frequency characteristics, resulting in increases in precision of gain and degree of reliability.

Description

差動増幅回路Differential amplifier circuit
　本発明は差動増幅回路に関し、特に、マイクロ波帯域の信号を増幅する差動増幅回路に関する。 The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit that amplifies a signal in a microwave band.
　差動増幅回路は様々な回路に広く使用されている。図３は従来知られている一般的な、トランジスタを用いた差動増幅回路の構成図である（例えば特許文献１参照）。 The differential amplifier circuit is widely used in various circuits. FIG. 3 is a configuration diagram of a conventionally known differential amplifier circuit using transistors (see, for example, Patent Document 1).
　図３において、同一特性である入力段の２個のトランジスタ１０、１２は対称に配置され、第１入力端子１１に与えられた電圧Ｖref＋Ｖdifが第１入力段トランジスタ１０のベース端子に入力され、第２入力端子１３に与えられた電圧Ｖrefが第２入力段トランジスタ１２のベース端子に入力される。各トランジスタ１０、１２のエミッタ端子はそれぞれ、抵抗値がＲEである抵抗１９、２０を介して共通の定電流源２１の吸い込み端に接続される。一方、各トランジスタ１０、１２のコレクタ端子はそれぞれ、抵抗値がＲCである抵抗１４、１５を介して電圧ＶCCの正電源線に接続される。そして、これらトランジスタ１０、１２のコレクタ端子間には抵抗値がＲLである負荷抵抗１６が接続されている。 In FIG. 3, the two transistors 10 and 12 in the input stage having the same characteristics are arranged symmetrically, and the voltage V ref + V dif given to the first input terminal 11 is input to the base terminal of the first input stage transistor 10. The voltage V ref applied to the second input terminal 13 is input to the base terminal of the second input stage transistor 12. The emitter terminals of the transistors 10 and 12 are connected to the suction end of a common constant current source 21 via resistors 19 and 20 having a resistance value R E , respectively. On the other hand, the collector terminals of the transistors 10 and 12 are respectively connected to the positive power supply line of the voltage V CC via the resistors 14 and 15 having a resistance value R C. A load resistor 16 having a resistance value R L is connected between the collector terminals of the transistors 10 and 12.
　定電流源２１に流れる電流が２Ｉ0一定であるとすると、差電圧Ｖdifが０である場合、つまり第１入力端子１１に与えられる電圧が第２入力端子１３に与えられる電圧と同じＶrefである場合には、入力段トランジスタ１０、１２のエミッタ電流はＩ0で等しくなる。第１入力端子１１に与えられる電圧がＶref＋Ｖdifになると、第１入力段トランジスタ１０のエミッタ電流はＩ0＋Ｉdifに増加し、逆に、第２入力段トランジスタ１２のエミッタ電流はＩ0－Ｉdifに減少する。第１入力段トランジスタ１０のエミッタ電流がＩdifだけ増加したときの該トランジスタ１０のベース－エミッタ間電圧変化をΔＶbe1とし、第２入力段トランジスタ１２のエミッタ電流がＩdifだけ減少したときの該トランジスタ１２のベース－エミッタ間電圧変化をΔＶbe2とすると、次の(1)式が成り立つ。
　　Ｖref＋Ｖdif－ΔＶbe1－ＲE（Ｉ0＋Ｉdif）＝Ｖref－ΔＶbe2＋ＲE（Ｉ0－Ｉdif）　　…(1) Assuming that the current flowing through the constant current source 21 is constant at 2I 0 , when the difference voltage V dif is 0, that is, the voltage applied to the first input terminal 11 is the same as the voltage applied to the second input terminal 13 V ref In this case, the emitter currents of the input stage transistors 10 and 12 are equal to each other at I 0 . When the voltage applied to the first input terminal 11 becomes V ref + V dif , the emitter current of the first input stage transistor 10 increases to I 0 + I dif , and conversely, the emitter current of the second input stage transistor 12 is I 0. -I dif The base-emitter voltage change of the transistor 10 when the emitter current of the first input stage transistor 10 increases by I dif is ΔV be1, and the emitter current of the second input stage transistor 12 decreases by I dif When the voltage change between the base and emitter of the transistor 12 is ΔV be2 , the following equation (1) is established.
V ref + V dif −ΔV be1 −R E (I 0 + I dif ) = V ref −ΔV be2 + R E (I 0 −I dif ) (1)
　(1)式を整理すると、
　　Ｉdef＝（Ｖdif／２ＲE）－｛（ΔＶbe1－ΔＶbe2）／２ＲE　｝　　　…(2)
となる。一方、負荷抵抗１６の両端間に得られる出力電圧ΔＶoutは、
　　ΔＶout＝２ＲoutＩdif　　　…(3)
　　　　但し、Ｒout＝Ｒc //（ＲL／２）
である。即ち、差動増幅回路の入力と出力とは比例するのが理想的であるが、一般にトランジスタは非線形性に起因する直線性誤差を有しているため、(2)式の右辺第２項は０にはならない。そのため、上記差動増幅回路の入力と出力とは完全には比例しないことになる。 (1)
I def = (V dif / 2R E ) − {(ΔV be1 −ΔV be2 ) / 2R E } (2)
It becomes. On the other hand, the output voltage ΔV out obtained across the load resistor 16 is
ΔV out = 2R out I dif (3)
However, R out = R c // (R L / 2)
It is. That is, it is ideal that the input and output of the differential amplifier circuit are proportional to each other. However, since the transistor generally has a linearity error due to nonlinearity, the second term on the right side of the equation (2) is It will not be zero. Therefore, the input and output of the differential amplifier circuit are not completely proportional.
　そこで、従来、図４に示すように、入力段のトランジスタ１０、１２を、トランジスタを複数並列接続した構成１０’、１２’に置き換えることにより、トランジスタ１個当たりの電流変化量を小さくし、直線性誤差を低減することが行われている。 Therefore, conventionally, as shown in FIG. 4, by replacing the transistors 10 and 12 in the input stage with a configuration 10 ′ and 12 ′ in which a plurality of transistors are connected in parallel, the amount of current change per transistor is reduced, and a straight line Reducing the sex error has been done.
　しかしながら、回路基板上でトランジスタを複数並列接続すると、これらトランジスタを相互に接続する配線パターンが長くなり、浮遊インダクタンスや浮遊容量が増大して発振が生じ易くなる。そうした発振を防止するためにはベース抵抗などを挿入する必要があり、これが周波数特性を低下させる一因となる。また、複数並列接続されたトランジスタの間の信号伝播遅延時間に差が生じ、差動出力の立ち上がりが鈍って周波数特性をさらに低下させることになる。特にマイクロ波用増幅回路のように広帯域が要求される場合には、上記のような周波数特性の低下は非常に問題となる。 However, when a plurality of transistors are connected in parallel on the circuit board, the wiring pattern for connecting these transistors to each other becomes longer, stray inductance and stray capacitance increase, and oscillation tends to occur. In order to prevent such oscillation, it is necessary to insert a base resistor or the like, which causes a decrease in frequency characteristics. Further, a difference occurs in the signal propagation delay time between a plurality of transistors connected in parallel, and the rise of the differential output becomes dull and the frequency characteristics are further deteriorated. In particular, when a wide band is required as in a microwave amplifier circuit, the above-described deterioration in frequency characteristics becomes a serious problem.
実開平６－８１１２７号公報（図２）Japanese Utility Model Publication No. 6-81127 (FIG. 2)
　本発明は上記課題に鑑みてなされたものであり、差動増幅回路の周波数特性を向上させることを主な目的としている。 The present invention has been made in view of the above problems, and has as its main object to improve the frequency characteristics of a differential amplifier circuit.
　上記課題を解決するために成された第１発明は、一対の入力段トランジスタの各ベース端子に第１及び第２の入力信号が入力され、該入力段トランジスタのコレクタ端子はそれぞれ抵抗を介して正電源に接続され、第１及び第２の入力信号の差分に応じた信号を一対の入力段トランジスタのコレクタ端子の間から取り出す差動増幅回路であって、
　前記一対の入力段トランジスタのエミッタ端子にそれぞれ一対の補償用トランジスタのコレクタ端子が接続され、前記一対の補償用トランジスタの各エミッタ端子はそれぞれ抵抗を介して共通の定電流源に接続され、前記一対の補償用トランジスタの各ベース端子は他方の補償用トランジスタのコレクタ端子に互いに接続されてなることを特徴としている。 According to a first aspect of the present invention for solving the above-described problems, first and second input signals are input to the base terminals of a pair of input stage transistors, and the collector terminals of the input stage transistors are respectively connected via resistors. A differential amplifier circuit connected to a positive power supply and extracting a signal corresponding to a difference between the first and second input signals from between a collector terminal of a pair of input stage transistors;
The emitter terminals of the pair of input transistors are connected to the collector terminals of a pair of compensation transistors, and the emitter terminals of the pair of compensation transistors are connected to a common constant current source through resistors, respectively. Each of the base terminals of the compensation transistor is connected to the collector terminal of the other compensation transistor.
　第１発明に係る差動増幅回路では、入力段トランジスタとそのエミッタ端子にコレクタ端子が接続された補償用トランジスタとは同一特性のものが用いられる。この一対の補償用トランジスタにそれぞれ流れる電流によるベース－エミッタ間電圧変化により、一対の入力段トランジスタのベース－エミッタ間電圧変化の影響がキャンセルされるため、入力の差電圧と出力電圧との関係、つまりゲインは単純に負荷となる抵抗の値だけで決まるようになる。それにより、入力段トランジスタを複数トランジスタの並列接続にすることなく、入力と出力との関係を比例関係にすることができる。 In the differential amplifier circuit according to the first aspect of the invention, the input stage transistor and the compensating transistor having the collector terminal connected to the emitter terminal thereof have the same characteristics. Since the influence of the base-emitter voltage change of the pair of input stage transistors is canceled by the base-emitter voltage change due to the current flowing through each of the pair of compensation transistors, the relationship between the input differential voltage and the output voltage, In other words, the gain is determined simply by the value of the resistance serving as a load. Thereby, the relationship between the input and the output can be made proportional without the input stage transistor being connected in parallel with a plurality of transistors.
　上記第１発明に係る差動増幅回路では、補償用トランジスタを入力段トランジスタのエミッタ側（低電圧側）に配置していたが、補償用トランジスタを入力段トランジスタのコレクタ側（高電圧側）に配置するように変形することもできる。但し、その場合には、一対の補償用トランジスタの各ベース端子に共通のバイアス電圧を印加する。 In the differential amplifier circuit according to the first aspect of the invention, the compensation transistor is arranged on the emitter side (low voltage side) of the input stage transistor, but the compensation transistor is arranged on the collector side (high voltage side) of the input stage transistor. It can also be modified to arrange. However, in that case, a common bias voltage is applied to each base terminal of the pair of compensation transistors.
　即ち、上記課題を解決するために成された第２発明は、一対の入力段トランジスタの各ベース端子に第１及び第２の入力信号が入力され、該入力段トランジスタのエミッタ端子はそれぞれ抵抗を介して共通の定電流源に接続され、第１及び第２の入力信号の差分に応じた信号を一対の入力段トランジスタのコレクタ端子の間から取り出す差動増幅回路であって、
　前記一対の入力段トランジスタのコレクタ端子はそれぞれ抵抗を介して一対の補償用トランジスタのエミッタ端子に接続され、前記一対の補償用トランジスタの各ベース端子には共通のバイアス電圧が印加されるとともに、各コレクタ端子はともに正電源に接続されてなることを特徴としている。 That is, in the second invention made to solve the above problems, the first and second input signals are inputted to the base terminals of the pair of input stage transistors, and the emitter terminals of the input stage transistors have resistances respectively. A differential amplifier circuit that is connected to a common constant current source through which a signal corresponding to the difference between the first and second input signals is extracted from between the collector terminals of the pair of input stage transistors,
The collector terminals of the pair of input stage transistors are connected to the emitter terminals of the pair of compensation transistors through resistors, respectively, and a common bias voltage is applied to the base terminals of the pair of compensation transistors. Both collector terminals are connected to a positive power source.
　この第２発明に係る差動増幅回路では、一対の入力段トランジスタ及び一対の補償用トランジスタは全て同一特性のものが用いられる。 In the differential amplifier circuit according to the second aspect of the invention, the pair of input stage transistors and the pair of compensation transistors all have the same characteristics.
　第１及び第２発明に係る差動増幅回路によれば、入力段トランジスタを複数トランジスタの並列接続にすることなく、入力の差電圧と出力電圧との関係を比例関係にすることができる。したがって、入力段トランジスタを複数のトランジスタの並列接続にすることによるデメリット、即ち、回路基板上で複数トランジスタを並列接続するための配線パターンによる浮遊インダクタンスや浮遊容量、或いは、複数並列されたトランジスタの間の信号伝播遅延時間の差、などに起因する周波数帯域の制約がなくなり、周波数特性を向上させることができる。また、入出力の直線性誤差が小さくなり、且つ、増幅回路のゲインが抵抗器の抵抗値によってのみ決まるので、ゲインの精度や安定度が向上する。 According to the differential amplifier circuits according to the first and second inventions, the relationship between the input differential voltage and the output voltage can be made proportional without the input stage transistor being connected in parallel with a plurality of transistors. Therefore, the demerit of connecting the input stage transistor in parallel with a plurality of transistors, that is, stray inductance or stray capacitance due to the wiring pattern for connecting the plurality of transistors in parallel on the circuit board, or between the plurality of parallel transistors There is no restriction on the frequency band due to the difference in signal propagation delay time, and the frequency characteristics can be improved. Further, the linearity error of input / output is reduced, and the gain of the amplifier circuit is determined only by the resistance value of the resistor, so that the gain accuracy and stability are improved.
第１発明の一実施例（第１実施例）による差動増幅回路の構成図。The block diagram of the differential amplifier circuit by one Example (1st Example) of 1st invention. 第２発明の一実施例（第２実施例）による差動増幅回路の構成図。The block diagram of the differential amplifier circuit by one Example (2nd Example) of 2nd invention. 従来の差動増幅回路の構成図。The block diagram of the conventional differential amplifier circuit. 従来の差動増幅回路の構成図。The block diagram of the conventional differential amplifier circuit.
　　［第１実施例］
　第１発明に係る差動増幅回路の一実施例（第１実施例）について、添付図面を参照しつつ説明する。図１はこの第１実施例による差動増幅回路の構成図である。図３及び図４に示した従来の差動増幅回路と同じ構成要素には同じ符号を付して詳細な説明を省く。 [First embodiment]
An embodiment (first embodiment) of a differential amplifier circuit according to the first invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram of a differential amplifier circuit according to the first embodiment. The same components as those of the conventional differential amplifier circuit shown in FIGS. 3 and 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
　この第１実施例の差動増幅回路では、図３に示した従来構成における第１入力段トランジスタ１０のエミッタ端子と抵抗値がＲEである抵抗１９との間に第１補償用トランジスタ１７が挿入され、同様に第２入力段トランジスタ１２のエミッタ端子と抵抗値がＲEである抵抗２０との間に第２補償用トランジスタ１８が挿入されている。それら一対の補償用トランジスタ１７、１８のベース端子は、他方の補償用トランジスタのコレクタ端子にそれぞれ接続されている。補償用トランジスタ１７、１８は入力段トランジスタ１０、１２と同一特性のものが用いられる。 In the differential amplifier circuit of the first embodiment, the first compensation transistor 17 between the resistor 19 an emitter terminal and a resistance value of R E of the first input stage transistor 10 in the conventional structure shown in FIG. 3 it is inserted, likewise the emitter terminal and the resistance value of the second input stage transistor 12 has a second compensation transistor 18 is inserted between the resistor 20 is R E. The base terminals of the pair of compensation transistors 17 and 18 are connected to the collector terminal of the other compensation transistor, respectively. The compensating transistors 17 and 18 have the same characteristics as the input stage transistors 10 and 12.
　図１に示すように、第１入力段トランジスタ１０のベース端子にＶref＋Ｖdif、第２入力段トランジスタ１２のベース端子にＶrefが入力されたとき、負荷抵抗１６の両端には、入力の差電圧Ｖdifに応じた出力電圧ΔＶoutが発生するが、この差動増幅回路ではトランジスタ１０、１２の非線形性の影響が補償用トランジスタ１７、１８により補償され、出力電圧ΔＶoutは差電圧Ｖdifに比例したものとなる。この原理を次に説明する。 As shown in FIG. 1, when V ref + V dif is input to the base terminal of the first input stage transistor 10 and V ref is input to the base terminal of the second input stage transistor 12, both ends of the load resistor 16 have input inputs. An output voltage ΔV out corresponding to the difference voltage V dif is generated. In this differential amplifier circuit, the influence of the nonlinearity of the transistors 10 and 12 is compensated by the compensating transistors 17 and 18, and the output voltage ΔV out is the difference voltage V It is proportional to dif . This principle will be described next.
　いま、補償用トランジスタ１７、１８のベース電流は十分に小さいのでこれを無視すると、第１入力段トランジスタ１０のエミッタ電流と第１補償用トランジスタ１７のエミッタ電流とは等しい。それらトランジスタ１０、１７は同一特性であるので、エミッタ電流が等しければベース－エミッタ電圧変化も等しくなり、いずれもΔＶbe1である。同様に、第２入力段トランジスタ１２のエミッタ電流と第２補償用トランジスタ１８のエミッタ電流とは等しくなるので、それらトランジスタ１２、１８のベース－エミッタ電圧変化も等しくなり、いずれもΔＶbe2である。第１補償用トランジスタ１７のエミッタ電位は、Ｖref－ΔＶbe2－ΔＶbe1、第２補償用トランジスタ１８のエミッタ電位は、Ｖref＋Ｖdif－ΔＶbe2－ΔＶbe1、である。 Now, since the base currents of the compensating transistors 17 and 18 are sufficiently small and ignored, the emitter current of the first input stage transistor 10 and the emitter current of the first compensating transistor 17 are equal. Since the transistors 10 and 17 have the same characteristics, if the emitter currents are equal, the base-emitter voltage changes are equal, and both are ΔV be1 . Similarly, since the emitter current of the second input stage transistor 12 and the emitter current of the second compensation transistor 18 are equal, the base-emitter voltage changes of the transistors 12 and 18 are also equal, both of which are ΔV be2 . The emitter potential of the first compensation transistor 17 is V ref −ΔV be2 −ΔV be1 , and the emitter potential of the second compensation transistor 18 is V ref + V dif −ΔV be2 −ΔV be1 .
　定電流源２１に流れる一定電流が２Ｉ0であるとすると、図示するように、第１補償用トランジスタ１７のエミッタ電流はＩ0＋Ｉdef、第２補償用トランジスタ１８のエミッタ電流はＩ0－Ｉdef、となる。したがって、次の(4)式が成り立つ。
　　Ｖref－ΔＶbe2－ΔＶbe1－ＲE（Ｉ0＋Ｉdef）＝Ｖref＋Ｖdif－ΔＶbe2－ΔＶbe1－ＲE（Ｉ0－Ｉdef）　　…(4)
　(4)式を整理すると、
　　Ｉdef＝Ｖdef／２ＲE　　　 …(5)
となる。この回路でも(3)式が成り立つから、これに(5)式を代入し、
　　ΔＶout＝２ＲoutＩdif＝（Ｒout／ＲE）Ｖdef
と求まる。このとき、増幅回路のゲインＧは、
　　Ｇ＝ΔＶout／Ｖdef＝Ｒout／ＲE　　　　　　…(6)
である。但し、Ｒout＝Ｒc//（ＲL／２）である。
即ち、差動出力の電圧変化ΔＶoutは入力の電圧変化Ｖdefに比例し、上述した従来の差動増幅回路のような直線性誤差は生じないことになる。 Assuming that the constant current flowing through the constant current source 21 is 2I 0 , the emitter current of the first compensation transistor 17 is I 0 + I def and the emitter current of the second compensation transistor 18 is I 0 −I, as shown in the figure. def . Therefore, the following equation (4) holds.
V ref −ΔV be2 −ΔV be1 −R E (I 0 + I def ) = V ref + V dif −ΔV be2 −ΔV be1 −R E (I 0 −I def ) (4)
(4)
I def = V def / 2R E (5)
It becomes. In this circuit, equation (3) holds, so substitute equation (5)
ΔV out = 2R out I dif = (R out / R E ) V def
It is obtained. At this time, the gain G of the amplifier circuit is
G = ΔV out / V def = R out / R E (6)
It is. However, R out = R c // ( RL / 2).
That is, the voltage change ΔV out of the differential output is proportional to the voltage change V def of the input, and the linearity error unlike the conventional differential amplifier circuit described above does not occur.
　　［第２実施例］
　次に、第２発明に係る差動増幅回路の一実施例（第２実施例）について、添付図面を参照しつつ説明する。図２はこの第２実施例による差動増幅回路の構成図である。 [Second Embodiment]
Next, an embodiment (second embodiment) of a differential amplifier circuit according to the second invention will be described with reference to the accompanying drawings. FIG. 2 is a block diagram of a differential amplifier circuit according to the second embodiment.
　この第２実施例の差動増幅回路では、入力段トランジスタ１０、１２と同一特性である補償用トランジスタ３０、３１をそれぞれ抵抗１４、１５と正電源線との間に配置している。第１補償用トランジスタ３０と第２補償用トランジスタ３１のベース端子には共通のバイアス電圧ＶBBが印加されている。なお、この回路では、抵抗１４、１５自体が負荷抵抗として、入力段トランジスタ１０、１２のコレクタ端子間から出力電圧ΔＶoutが取り出される。 In the differential amplifier circuit of the second embodiment, compensation transistors 30 and 31 having the same characteristics as the input stage transistors 10 and 12 are respectively disposed between the resistors 14 and 15 and the positive power supply line. A common bias voltage V BB is applied to the base terminals of the first compensation transistor 30 and the second compensation transistor 31. In this circuit, the resistors 14 and 15 themselves serve as load resistors, and the output voltage ΔV out is taken out between the collector terminals of the input stage transistors 10 and 12.
　この第２実施例の差動増幅回路において第１実施例と同様に、出力電圧ΔＶoutが差電圧Ｖdifに比例したものとなる原理を説明する。 In the differential amplifier circuit of the second embodiment, the principle that the output voltage ΔV out is proportional to the differential voltage V dif will be described as in the first embodiment.
　トランジスタ１０、１２、３０、３１のベース電流は十分に小さいのでこれを無視すると、第１補償用トランジスタ３０のエミッタ電流と第１入力段トランジスタ１０のエミッタ電流とは等しい（Ｉ0＋Ｉdef）。したがって、それらトランジスタ１０、３０のベース－エミッタ電圧ＶBEの変化量ΔＶBEも等しくなる。同様に、第２補償用トランジスタ３１のエミッタ電流と第２入力段トランジスタ１２のエミッタ電流も等しい（Ｉ0－Ｉdef）。したがって、それらトランジスタ１２、３１のベース－エミッタ電圧ＶBEの変化量ΔＶBE（但しマイナス）も等しくなる。したがって、次の(7)式が成り立つ。
　　Ｖref－ＶBE＋ΔＶBE－ＲE（Ｉ0ーＩdef）＝Ｖref＋Ｖdif－ＶBE－ΔＶBE－ＲE（Ｉ0＋Ｉdef）　　…(7) Since the base currents of the transistors 10, 12, 30, and 31 are sufficiently small and neglected, the emitter current of the first compensation transistor 30 and the emitter current of the first input stage transistor 10 are equal (I 0 + I def ). Therefore, the variation ΔV BE of the base-emitter voltage V BE of the transistors 10 and 30 is also equal. Similarly, the emitter current of the second compensating transistor 31 and the emitter current of the second input stage transistor 12 are equal (I 0 -I def ). Accordingly, the variation ΔV BE (however, minus) of the base-emitter voltage V BE of these transistors 12 and 31 becomes equal. Therefore, the following equation (7) holds.
V ref −V BE + ΔV BE −R E (I 0 −I def ) = V ref + V dif −V BE −ΔV BE −R E (I 0 + I def ) (7)
　(7)式を整理すると、
　　Ｉdef＝(Ｖdefー２ΔＶBE）／２ＲE　　　 …(8)
となる。第１入力段トランジスタ１０のコレクタ端子の電位Ｖtc1は、
　　Ｖtc1＝ＶBB－ＶBEーΔＶBEーＲC（Ｉ0＋Ｉdef）
であり、第２入力段トランジスタ１２のコレクタ端子の電位Ｖtc2は、
　　Ｖtc2＝ＶBB－ＶBE＋ΔＶBEーＲC（Ｉ0－Ｉdef）
である。したがって、出力電圧ΔＶoutは、
　　ΔＶout＝Ｖtc2－Ｖtc1＝２ΔＶBE＋２ＲCＩdef　　 …(9)
 ここで、ＲC＝ＲEとし、(9)式に(8)式を代入すると、
　　ΔＶout＝Ｖdif
となり、ゲインＧ＝１として差電圧を出力電圧として取り出すことができる。 (7)
I def = (V def −2ΔV BE ) / 2R E (8)
It becomes. The potential V tc1 of the collector terminal of the first input stage transistor 10 is
V tc1 = V BB −V BE −ΔV BE −R C (I 0 + I def )
The potential V tc2 of the collector terminal of the second input stage transistor 12 is
V tc2 = V BB −V BE + ΔV BE −R C (I 0 −I def )
It is. Therefore, the output voltage ΔV out is
ΔV out = V tc2 −V tc1 = 2ΔV BE + 2R C I def (9)
Here, if R C = R E and substituting equation (8) into equation (9),
ΔV out = V dif
Thus, the difference voltage can be extracted as the output voltage with the gain G = 1.
　図１に示した第１実施例による差動増幅回路と図３に示した従来の差動増幅回路の特性の相違を、回路シミュレータを用いて評価した結果を説明する。具体的には、シミュレーションソフトウエアとしてPSpice（米国Cadence Design Systems社製）を使用した。図１の回路の各パラメータは、ＶCC＝1.4[V]、Ｖref＝0、Ｖdif＝125[mV]、ＲC＝25[Ω]、ＲE＝12.5[Ω]、２Ｉ0＝15[mA]、トランジスタ１０、１２、１７、１８には東芝製高周波トランジスタMT3S102TXのデバイスモデルを用いた。図３の回路の各パラメータも同様である。図１及び図３の回路のゲインと直線性誤差を計算した結果を次の表１に示す。 The result of evaluating the difference in characteristics between the differential amplifier circuit according to the first embodiment shown in FIG. 1 and the conventional differential amplifier circuit shown in FIG. 3 using a circuit simulator will be described. Specifically, PSpice (made by Cadence Design Systems, USA) was used as simulation software. The parameters of the circuit of FIG. 1 are as follows: V CC = 1.4 [V], V ref = 0, V dif = 125 [mV], R C = 25 [Ω], R E = 12.5 [Ω], 2I 0 = 15 [mA] The device model of Toshiba high frequency transistor MT3S102TX was used for transistors 10, 12, 17, and 18. The same applies to each parameter of the circuit of FIG. The results of calculating the gain and linearity error of the circuits of FIGS. 1 and 3 are shown in Table 1 below.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
　図３の回路のゲインＧは、トランジスタ１０、１２のエミッタ等価抵抗をｒeとすると、
　　Ｇ＝ΔＶout／Ｖdif＝Ｒout／（ＲE＋ｒe）
となり、PSpiceに用いたデバイスモデルのトランジスタのｒe＝4.3[Ω]より、ゲインＧは1.49と計算できる。これは表１の結果にほぼ一致している。一方、図１の回路のゲインＧは、上記の(6)式を用い、2.0と求まる。これも、表１の結果にほぼ一致している。
　以上のように、図１の回路は図３の回路と異なり、トランジスタの特性値（エミッタ等価抵抗）のゲインへの寄与がなくなり、ゲインが単純に抵抗素子の抵抗値だけで決まる。これにより、ゲインの精度、安定度の向上が図れる。 Gain G of the circuit of Figure 3, when the emitter equivalent resistance of the transistors 10, 12 and r e,
G = ΔV out / V dif = R out / (R E + r e )
Thus, the gain G can be calculated to be 1.49 from r e = 4.3 [Ω] of the transistor of the device model used for PSpice. This almost coincides with the results in Table 1. On the other hand, the gain G of the circuit of FIG. 1 is obtained as 2.0 using the above equation (6). This also almost coincides with the results in Table 1.
As described above, the circuit of FIG. 1 differs from the circuit of FIG. 3 in that the transistor characteristic value (emitter equivalent resistance) does not contribute to the gain, and the gain is determined simply by the resistance value of the resistance element. As a result, gain accuracy and stability can be improved.
　なお、上記実施例は本発明の一例であり、本発明の趣旨の範囲で適宜変形、修正、追加などを行っても本願請求の範囲に包含されることは当然である。 It should be noted that the above embodiment is an example of the present invention, and it is a matter of course that modifications, corrections, additions, and the like are appropriately included in the scope of the present application within the scope of the present invention.
１０、１２…入力段トランジスタ
１１、１３…入力端子
１４、１５、１９、２０…抵抗
１６…負荷抵抗
１７、１８、３０、３１…補償用トランジスタ
２１…定電流源 DESCRIPTION OF SYMBOLS 10, 12 ... Input stage transistor 11, 13 ... Input terminal 14, 15, 19, 20 ... Resistor 16 ... Load resistance 17, 18, 30, 31 ... Compensation transistor 21 ... Constant current source

Claims (2)

  1. 　一対の入力段トランジスタの各ベース端子に第１及び第２の入力信号が入力され、該入力段トランジスタのコレクタ端子はそれぞれ抵抗を介して正電源に接続され、第１及び第２の入力信号の差分に比例した信号を一対の入力段トランジスタのコレクタ端子の間から取り出す差動増幅回路であって、
    　前記一対の入力段トランジスタのエミッタ端子にそれぞれ一対の補償用トランジスタのコレクタ端子が接続され、前記一対の補償用トランジスタの各エミッタ端子はそれぞれ抵抗を介して共通の定電流源に接続され、前記一対の補償用トランジスタの各ベース端子は他方の補償用トランジスタのコレクタ端子に互いに接続されてなることを特徴とする差動増幅回路。     The first and second input signals are input to the base terminals of the pair of input stage transistors, and the collector terminals of the input stage transistors are connected to a positive power source through resistors, respectively, and the first and second input signals A differential amplifier circuit that extracts a signal proportional to the difference from between the collector terminals of a pair of input stage transistors,
    The emitter terminals of the pair of input transistors are connected to the collector terminals of a pair of compensation transistors, and the emitter terminals of the pair of compensation transistors are connected to a common constant current source through resistors, respectively. Each of the base terminals of the compensation transistor is connected to the collector terminal of the other compensation transistor.
  2. 　一対の入力段トランジスタの各ベース端子に第１及び第２の入力信号が入力され、該入力段トランジスタのエミッタ端子はそれぞれ抵抗を介して共通の定電流源に接続され、第１及び第２の入力信号の差分に比例した信号を一対の入力段トランジスタのコレクタ端子の間から取り出す差動増幅回路であって、
    　前記一対の入力段トランジスタのコレクタ端子はそれぞれ抵抗を介して一対の補償用トランジスタのエミッタ端子に接続され、
    　前記一対の補償用トランジスタの各ベース端子には共通のバイアス電圧が印加されるとともに、各コレクタ端子はともに正電源に接続されてなることを特徴とする差動増幅回路。     The first and second input signals are input to the base terminals of the pair of input stage transistors, and the emitter terminals of the input stage transistors are connected to a common constant current source through resistors, respectively. A differential amplifier circuit that extracts a signal proportional to a difference between input signals from between collector terminals of a pair of input stage transistors,
    The collector terminals of the pair of input stage transistors are respectively connected to the emitter terminals of the pair of compensation transistors via resistors,
    A differential amplifier circuit, wherein a common bias voltage is applied to each base terminal of the pair of compensating transistors, and each collector terminal is connected to a positive power source.
PCT/JP2010/051849 2010-02-09 2010-02-09 Differential amplifier circuit WO2011099113A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2010/051849 WO2011099113A1 (en) 2010-02-09 2010-02-09 Differential amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2010/051849 WO2011099113A1 (en) 2010-02-09 2010-02-09 Differential amplifier circuit

Publications (1)

Publication Number Publication Date
WO2011099113A1 true WO2011099113A1 (en) 2011-08-18

Family

ID=44367424

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/051849 WO2011099113A1 (en) 2010-02-09 2010-02-09 Differential amplifier circuit

Country Status (1)

Country Link
WO (1) WO2011099113A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1051248A (en) * 1996-07-31 1998-02-20 Mitsumi Electric Co Ltd Differential amplifier circuit
JPH1098338A (en) * 1996-09-20 1998-04-14 Mitsumi Electric Co Ltd Mutual conductance circuit
JP2000510656A (en) * 1995-12-27 2000-08-15 マキシム インテグレイテッド プロダクツ，インコーポレイテッド Differential amplifier with improved low voltage linearity
JP2002524900A (en) * 1998-08-27 2002-08-06 マキシム・インテグレイテッド・プロダクツ・インコーポレイテッド Differential amplifier with gain linearity by transconductance compensation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000510656A (en) * 1995-12-27 2000-08-15 マキシム インテグレイテッド プロダクツ，インコーポレイテッド Differential amplifier with improved low voltage linearity
JPH1051248A (en) * 1996-07-31 1998-02-20 Mitsumi Electric Co Ltd Differential amplifier circuit
JPH1098338A (en) * 1996-09-20 1998-04-14 Mitsumi Electric Co Ltd Mutual conductance circuit
JP2002524900A (en) * 1998-08-27 2002-08-06 マキシム・インテグレイテッド・プロダクツ・インコーポレイテッド Differential amplifier with gain linearity by transconductance compensation

Similar Documents

Publication Publication Date Title
KR20120064617A (en) Voltage regulator
US9331648B2 (en) Amplifier circuit with improved slew rate
US7859339B2 (en) Differential amplification circuit
US7253677B1 (en) Bias circuit for compensating fluctuation of supply voltage
US4425551A (en) Differential amplifier stage having bias compensating means
JP4511150B2 (en) Constant voltage generator
US10992271B2 (en) Amplifier with input bias current cancellation
CN108693912B (en) Bandgap reference circuit with inverted bandgap pairs
WO2011099113A1 (en) Differential amplifier circuit
JP2010220195A (en) Current conveyor based instrumentation amplifier
TW202303165A (en) Current sensing circuit
US9727074B1 (en) Bandgap reference circuit and method therefor
EP3220156B1 (en) Sensor device
JP5788739B2 (en) Voltage variable gain amplifier circuit
JPS58117730A (en) Output stage for integrated ecl circuit
US9985589B2 (en) System and method for improving total harmonic distortion of an amplifier
JP5003176B2 (en) Differential amplifier circuit
JPH03190308A (en) Transformer conductance amplifier
CN114690832B (en) Current generating circuit, logarithmic amplifier and logarithmic slope stability improving method thereof
KR101360648B1 (en) Instrumentation amplifier using second generation current-conveyer
KR101008487B1 (en) Temperature-Compensated Reference Current Supplying Circuit
JP6820175B2 (en) Differential amplifier and voltage follower circuit
US7863985B1 (en) High frequency amplifier linearization technique
JP2011170443A (en) Reference voltage generation circuit and semiconductor device
JP4586708B2 (en) Differential amplifier

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10845716

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10845716

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP