WO2011081300A3 - 저 전력 트레이스 캐쉬 및 명령어 세트 예측기를 구비한 프로세서 시스템 - Google Patents

저 전력 트레이스 캐쉬 및 명령어 세트 예측기를 구비한 프로세서 시스템 Download PDF

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Publication number
WO2011081300A3
WO2011081300A3 PCT/KR2010/008233 KR2010008233W WO2011081300A3 WO 2011081300 A3 WO2011081300 A3 WO 2011081300A3 KR 2010008233 W KR2010008233 W KR 2010008233W WO 2011081300 A3 WO2011081300 A3 WO 2011081300A3
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WO
WIPO (PCT)
Prior art keywords
command set
processor system
low
power trace
trace cache
Prior art date
Application number
PCT/KR2010/008233
Other languages
English (en)
French (fr)
Other versions
WO2011081300A2 (ko
Inventor
김철홍
심성훈
최홍준
Original Assignee
전남대학교산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 전남대학교산학협력단 filed Critical 전남대학교산학협력단
Publication of WO2011081300A2 publication Critical patent/WO2011081300A2/ko
Publication of WO2011081300A3 publication Critical patent/WO2011081300A3/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Power Sources (AREA)

Abstract

본 발명은 프로세서 시스템에 관한 것으로, 보다 구체적으로는 분기예측기(Branch predictor)를 포함하는 프로세서 시스템에 있어서, 분기가 일어나지 않을 것으로 예측되는 명령어들을 하나의 세트로 하여 복수 개의 명령어 세트를 저장하는 저전력 트레이스 캐쉬 및 다음에 실행될 명령어 세트를 예측하여 하나의 명령어 세트가 인출되는 동안 프로세서 코어에서 분기예측기 및 주 명령어 캐쉬로의 접근을 차단하는 명령어 세트 예측기를 구비하여 상기 분기예측기의 동작에 의해 소비되는 전력을 절감할 수 있는 프로세서 시스템에 관한 것이다.
PCT/KR2010/008233 2009-12-28 2010-11-22 저 전력 트레이스 캐쉬 및 명령어 세트 예측기를 구비한 프로세서 시스템 WO2011081300A2 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020090132139A KR101086457B1 (ko) 2009-12-28 2009-12-28 저 전력 트레이스 캐쉬 및 명령어 세트 예측기를 구비한 프로세서 시스템
KR10-2009-0132139 2009-12-28

Publications (2)

Publication Number Publication Date
WO2011081300A2 WO2011081300A2 (ko) 2011-07-07
WO2011081300A3 true WO2011081300A3 (ko) 2011-09-15

Family

ID=44226937

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/008233 WO2011081300A2 (ko) 2009-12-28 2010-11-22 저 전력 트레이스 캐쉬 및 명령어 세트 예측기를 구비한 프로세서 시스템

Country Status (2)

Country Link
KR (1) KR101086457B1 (ko)
WO (1) WO2011081300A2 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITMI20110387A1 (it) * 2011-03-11 2012-09-12 Antonio Sambusseti Emisfera per l'ampliamento vescicale in pazienti con bassa compliance
KR101294629B1 (ko) * 2011-08-31 2013-08-08 전남대학교산학협력단 3차원 멀티코어 프로세서의 분기예측기 배치방법 및 3차원 멀티코어 프로세서
US9262163B2 (en) 2012-12-29 2016-02-16 Intel Corporation Real time instruction trace processors, methods, and systems

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6247097B1 (en) * 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US20050125632A1 (en) * 2003-12-03 2005-06-09 Advanced Micro Devices, Inc. Transitioning from instruction cache to trace cache on label boundaries
US6988190B1 (en) * 1999-11-15 2006-01-17 Samsung Electronics, Co., Ltd. Method of an address trace cache storing loop control information to conserve trace cache area

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6247097B1 (en) * 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US6988190B1 (en) * 1999-11-15 2006-01-17 Samsung Electronics, Co., Ltd. Method of an address trace cache storing loop control information to conserve trace cache area
US20050125632A1 (en) * 2003-12-03 2005-06-09 Advanced Micro Devices, Inc. Transitioning from instruction cache to trace cache on label boundaries

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KIM, C.H. ET AL.: "Energy-Effective Instruction Fetch Unit for Embedded Processors", CCNC 2008 IEEE, 10 January 2008 (2008-01-10), pages 734 - 735, XP031211977 *

Also Published As

Publication number Publication date
KR20110075638A (ko) 2011-07-06
KR101086457B1 (ko) 2011-11-25
WO2011081300A2 (ko) 2011-07-07

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