WO2011074329A1 - Method for manufacturing piezoelectric device - Google Patents

Method for manufacturing piezoelectric device Download PDF

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Publication number
WO2011074329A1
WO2011074329A1 PCT/JP2010/068890 JP2010068890W WO2011074329A1 WO 2011074329 A1 WO2011074329 A1 WO 2011074329A1 JP 2010068890 W JP2010068890 W JP 2010068890W WO 2011074329 A1 WO2011074329 A1 WO 2011074329A1
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piezoelectric
single crystal
thin film
substrate
manufacturing
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PCT/JP2010/068890
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French (fr)
Japanese (ja)
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米田年麿
神藤始
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株式会社村田製作所
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
    • G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
    • G01C19/5607—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using vibrating tuning forks
    • G01C19/5628—Manufacturing; Trimming; Mounting; Housings
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C19/00—Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
    • G01C19/56—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
    • G01C19/5719—Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces using planar vibrating masses driven in a translation vibration along an axis
    • G01C19/5769—Manufacturing; Mounting; Housings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies

Definitions

  • the present invention relates to a method of manufacturing a piezoelectric device using a piezoelectric single crystal thin film, particularly a piezoelectric device having the thin film on an SOI substrate.
  • FIG. 1 is a diagram schematically illustrating a manufacturing process of the piezoelectric vibration gyro device disclosed in Patent Document 1.
  • a piezoelectric single crystal substrate 1 and an SOI substrate 2 are prepared.
  • the SOI substrate 2 is a substrate in which an oxide film 30 and a silicon layer 40 are stacked in this order on a silicon substrate 50 having a predetermined thickness.
  • FIG. 1B the surface of the SOI substrate 2 on the silicon layer 40 side and the back surface of the piezoelectric single crystal substrate 1 are bonded.
  • FIG. 1 is a diagram schematically illustrating a manufacturing process of the piezoelectric vibration gyro device disclosed in Patent Document 1.
  • the piezoelectric single crystal substrate 1 is polished from the back side by mechanical polishing and CMP (CHEMICAL Mechanical Polishing) until a piezoelectric thin film 15 having a desired thickness is obtained. Then, when the upper electrode 60 is formed on the surface of the piezoelectric thin film 15 and the hole 81 and the void layer 80 are formed by etching, the cross section becomes the state shown in FIG.
  • CMP CHEMICAL Mechanical Polishing
  • the resonance frequency is determined by the shape and length of the piezoelectric thin film and the material of the piezoelectric thin film.
  • the resonance frequency decreases when the thickness of the vibrating body made of the piezoelectric thin film and the support is reduced, and the resonance frequency increases when the length of the vibrating body is shortened. Therefore, if the length of the vibrating body is shortened in order to reduce the outer shape of the piezoelectric device, the resonance frequency increases as described above. Therefore, in order to reduce the resonance frequency that has been increased by shortening the length of the vibrating body, it is necessary to reduce the thickness of the vibrating body. That is, how much the piezoelectric device can be reduced depends on how thin the vibrating body can be. In addition, the thinner the vibrating body is, the more gyro sensor can be created that is more sensitive to external force.
  • the thickness of the support can be reduced to about several ⁇ m by using the SOI substrate.
  • the piezoelectric thin film is usually obtained by mechanical polishing and CMP. In this polishing, only the piezoelectric thin film 15 having a thickness of up to 10 ⁇ m could be formed.
  • precise polishing it is possible to produce a piezoelectric thin film 15 having a thickness of several ⁇ m.
  • the processing time required for the precise polishing is significantly increased and the manufacturing cost is increased. there were.
  • the thickness of the piezoelectric thin film 15 that can be created in consideration of the manufacturing cost is up to 10 ⁇ m, it is possible to reduce the outer shape of the piezoelectric vibration gyro device and improve the sensitivity to external force. I could't do any more.
  • the polishing step since the piezoelectric single crystal substrate 1 is polished by mechanical polishing and CMP to create the piezoelectric thin film 15, the polished single crystal piezoelectric material disappears. That is, in the manufacturing method of Patent Document 1 described above, a large amount of single crystal piezoelectric material is consumed in the polishing process only for the production of the piezoelectric thin film 15, which contributes to high manufacturing costs.
  • an object of the present invention is to provide a method for manufacturing a piezoelectric device capable of manufacturing an ultrathin film type piezoelectric device having an ultrathin piezoelectric single crystal thin film on an SOI substrate at a low cost.
  • the present invention relates to a method for manufacturing a piezoelectric device including a support and a piezoelectric single crystal thin film bonded to the surface of the support.
  • This method for manufacturing a piezoelectric device includes at least an ion implantation process, a bonding process, and a peeling process.
  • ions are implanted into the piezoelectric single crystal substrate to form an ion implantation layer in which the concentration of the element implanted in the piezoelectric single crystal substrate reaches a peak.
  • the bonding step the surface on the ion implantation layer side of the piezoelectric single crystal substrate and the surface on the semiconductor thin film layer side of the SOI substrate as a support are bonded.
  • the piezoelectric single crystal substrate is heated to perform peeling using the ion implantation layer as a peeling surface, and a piezoelectric single crystal thin film is formed on the surface of the SOI substrate on the semiconductor thin film layer side.
  • the ion implantation depth is determined by the ion implantation energy, and the ion implantation layer can be formed at a desired depth by changing the ion implantation energy.
  • the peeling step the piezoelectric single crystal thin film is formed on the SOI substrate by performing peeling using the ion implantation layer as a peeling surface. That is, since the thickness of the piezoelectric single crystal thin film is determined by the ion implantation energy, the thickness of the piezoelectric single crystal thin film can be freely adjusted.
  • an extremely thin piezoelectric single crystal thin film having a desired thickness can be formed on the SOI substrate by an ion implantation process, a bonding process, and a peeling process.
  • the SOI substrate is a substrate in which an oxide film and a semiconductor thin film layer are stacked in this order on a silicon substrate having a predetermined thickness.
  • An ultrathin thin film refers to a thin film having a thickness of 10 ⁇ m or less.
  • the piezoelectric single crystal substrate from which the piezoelectric single crystal thin film has been peeled can be reused in the ion implantation step. That is, since a plurality of piezoelectric single crystal thin films can be formed from one piezoelectric single crystal substrate, single crystal piezoelectric material can be saved.
  • an ultrathin film type piezoelectric device having an ultrathin piezoelectric single crystal thin film on an SOI substrate can be manufactured at low cost. Therefore, since the length of the vibrating body can be shortened by the thickness of the piezoelectric single crystal thin film, the external shape of the piezoelectric device can be reduced. Further, the sensitivity to external force can be improved by reducing the thickness of the piezoelectric single crystal thin film.
  • the method for manufacturing a piezoelectric device includes a film forming step of forming at least an electrode film on the surface of the piezoelectric single crystal substrate on the ion implantation layer side between the ion implantation step and the bonding step.
  • a piezoelectric device having a structure in which an electrode film is formed on the surface of the piezoelectric single crystal thin film on the semiconductor thin film layer side can be formed.
  • the thickness of the piezoelectric single crystal thin film formed on the SOI substrate is extremely thin, the piezoelectric single crystal thin film is easily affected by stress due to the difference in linear expansion coefficient between the piezoelectric single crystal thin film and the SOI substrate. Therefore, in this manufacturing method, a dielectric film is formed on the surface of the piezoelectric single crystal substrate on the side of the ion implantation layer, and a dielectric film that buffers the difference in linear expansion coefficient is provided between the piezoelectric single crystal thin film and the SOI substrate. It may be formed.
  • the method for manufacturing a piezoelectric device according to the present invention includes an etching step of forming a void layer by etching the oxide film layer of the SOI substrate after the peeling step.
  • a piezoelectric device having a structure in which a gap layer is formed between a silicon substrate and a semiconductor thin film layer can be formed.
  • the material of the piezoelectric single crystal thin film is lithium niobate or lithium tantalate.
  • Lithium niobate is an easily available material with excellent piezoelectricity.
  • a piezoelectric single crystal thin film made of lithium niobate on the surface of the SOI substrate on the semiconductor thin film layer side, a highly sensitive piezoelectric sensor with high conversion efficiency between electric energy and mechanical energy can be obtained.
  • lithium tantalate is a material that is easily available and has moderate piezoelectricity.
  • a piezoelectric single crystal thin film made of lithium tantalate on the surface of the SOI substrate on the semiconductor thin film layer side, a piezoelectric sensor with high sensitivity and good temperature characteristics can be obtained.
  • the etching process is performed in a multi-state in which a plurality of piezoelectric devices can be simultaneously formed.
  • an ultra-thin film type piezoelectric device having an ultra-thin piezoelectric single crystal thin film on an SOI substrate can be manufactured at low cost.
  • FIG. 1 is a diagram schematically illustrating a manufacturing process of the piezoelectric vibration gyro device disclosed in Patent Document 1.
  • FIG. 2 is a flowchart showing the method for manufacturing the piezoelectric device according to the first embodiment.
  • FIG. 3 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG.
  • FIG. 4 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG.
  • FIG. 5 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG.
  • FIG. 6 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG.
  • FIG. 7 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG. FIG.
  • FIG. 8 is a flowchart showing a method for manufacturing a piezoelectric device according to the second embodiment.
  • FIG. 9 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG.
  • FIG. 10 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG.
  • a method for manufacturing a piezoelectric device according to the first embodiment of the present invention will be described with reference to the drawings.
  • an extremely thin film piezoelectric device for a gyro using a piezoelectric thin film will be described as an example of the piezoelectric device.
  • FIG. 2 is a flowchart showing a method for manufacturing the piezoelectric device according to the first embodiment.
  • 3 to 7 are views schematically showing the manufacturing process of the piezoelectric device according to the first embodiment.
  • a piezoelectric single crystal substrate 1 and an SOI (Silicon On Insulator) substrate 2 are prepared.
  • the piezoelectric single crystal substrate 1 uses an LN (LiNbO 3 ) substrate having a predetermined thickness.
  • LN is a material that is easily available and excellent in piezoelectricity.
  • the piezoelectric single crystal substrate 1 and the SOI substrate 2 are prepared by mirror-polishing the respective bonding surfaces by CMP or the like.
  • the piezoelectric single crystal substrate 1 is an LT (LiTaO 3 ) substrate that is easily available and has appropriate piezoelectricity, an LBO (Li 2 B 4 O 7 ) substrate, a langasite (La 3 Ga 5 SiO 14 ) substrate, A KN (KNbO 3 ) substrate, a KLN (K 3 Li 2 Nb 5 O 15 ) substrate, or the like may be used.
  • the SOI substrate 2 is a substrate in which an oxide film 30 and a silicon layer 40 are laminated in this order on a silicon substrate 50 having a predetermined thickness.
  • the SOI substrate 2 a multi-state substrate in which a plurality of single ultrathin piezoelectric devices are arranged is used.
  • the silicon substrate 50 is a substrate made of Si.
  • the oxide film 30 is an oxide film of Si.
  • the oxide film 30 is made of a material that can select an etching gas or an etchant that can change the etching rate with respect to the silicon layer 40 or the like, and is made of a material that is more easily etched than the silicon layer 40.
  • the silicon layer 40 is a layer made of Si, and has a thickness of several ⁇ m to several hundred ⁇ m.
  • helium ions are implanted from the back surface 12 side of the piezoelectric single crystal substrate 1 to form an ion implantation layer 100 on the piezoelectric single crystal substrate 1 (FIG. 2: S101).
  • a ion implantation layer 100 is formed on the piezoelectric single crystal substrate 1 (FIG. 2: S101).
  • LN substrate is used as the piezoelectric single crystal substrate 1
  • He + ion implantation is performed from the back surface 12 to a depth of about 0.6 ⁇ m, for example, by accelerating energy of 180 KeV and a dose of 2.0 ⁇ 10 16 atoms / cm 2.
  • the He + ion layer (helium distribution portion) is formed at the position of, and the ion implantation layer 100 is formed.
  • the ion implantation layer 100 can be formed at a desired depth.
  • the ion implantation layer 100 is a portion where the concentration of the ion element implanted in the piezoelectric single crystal substrate 1 reaches a peak.
  • ion implantation is performed under conditions according to each substrate.
  • activated bonding is preferably used for this bonding.
  • This activated bonding is a bonding method in which Ar is irradiated with an Ar ion beam or the like in a vacuum at room temperature and the bonding surface is activated and does not require heating.
  • the composite of the piezoelectric single crystal substrate 1 and the SOI substrate 2 is heated (for example, at 500 ° C.) to perform separation using the ion implantation layer 100 as a separation surface (FIG. 2: S103).
  • FIG. 5B the composite piezoelectric substrate 3 in which the piezoelectric single crystal thin film 10 is formed on the surface of the silicon layer 40 of the SOI substrate 2 is obtained.
  • a piezoelectric single crystal thin film 10 having a thickness of 0.6 ⁇ m is formed on the SOI substrate 2.
  • FIG. 5C a piezoelectric single crystal substrate 1 'from which the piezoelectric single crystal thin film 10 has been peeled is obtained.
  • the heating temperature can be lowered by heating in a reduced pressure atmosphere.
  • the surface of the piezoelectric single crystal thin film 10 thus peeled and the back surface of the piezoelectric single crystal substrate 1 ′ are polished and flattened by CMP or the like (FIG. 2: S104).
  • an ultrathin piezoelectric single crystal thin film 10 having a thickness of 0.6 ⁇ m is formed on the SOI substrate 2. Since the piezoelectric single crystal thin film 10 is a single crystal piezoelectric thin film, it is superior in piezoelectricity to a polycrystalline piezoelectric thin film formed by sputtering, vapor deposition, CVD, or the like.
  • the piezoelectric single crystal substrate 1 ′ from which the piezoelectric single crystal thin film 10 has been peeled can be reused in S ⁇ b> 101. That is, a plurality of piezoelectric single crystal thin films 10 can be formed from one piezoelectric single crystal substrate 1.
  • an upper electrode 60 having a predetermined thickness is formed on the surface of the piezoelectric single crystal thin film 10 using Al (aluminum) or the like (FIG. 2: S105).
  • Al aluminum
  • S105 silicon dioxide
  • the upper electrode 60 not only Al but also W, Mo, Ta, Hf, Cu, Pt, Ti, or the like may be used alone or in combination depending on device specifications.
  • a resist film is formed on the surface of the piezoelectric single crystal thin film 10 on which the upper electrode 60 is formed (FIG. 2: S106). Then, using a photolithography technique, an etching window for forming the hole 81 penetrating the piezoelectric single crystal thin film 10 and the silicon layer 40 is formed in the resist film.
  • holes 81 are formed in the piezoelectric single crystal thin film 10 and the silicon layer 40 as shown in FIG. 6B (FIG. 2: S107).
  • the oxide film 30 is removed by flowing an etching gas or an etching solution through the hole 81 (FIG. 2: S108).
  • the space in which the oxide film 30 was formed becomes a void layer 80 as shown in FIG.
  • the etching gas or etching liquid used in S108 is an etching gas or etching liquid corresponding to the oxide film 30, and is different in type from S107.
  • a finished surface electrode pattern is formed (FIG. 2: S109). More specifically, bump pads 61 that are electrically connected to the upper electrode 60 are formed, and bumps (not shown) are formed on all the bump pads 61.
  • packaging using a mold is performed through a dividing process in which a plurality of ultrathin film piezoelectric devices formed in a multi-state on the SOI substrate 2 are divided into individual ultrathin film piezoelectric devices. In this way, an ultrathin film type piezoelectric device is formed. Therefore, a plurality of ultra-thin film type piezoelectric devices can be manufactured collectively.
  • the ion implantation depth is determined by the ion implantation energy, and the ion implantation layer 100 can be formed at a desired depth by changing the ion implantation energy.
  • the piezoelectric single crystal thin film 10 is formed on the SOI substrate 2 by performing peeling using the ion implantation layer 100 as a peeling surface. That is, since the thickness of the piezoelectric single crystal thin film 10 is determined by ion implantation energy, the thickness of the piezoelectric single crystal thin film 10 can be freely adjusted.
  • the ultrathin piezoelectric single crystal thin film 10 having a desired thickness (10 ⁇ m or less) can be formed on the SOI substrate 2 by an ion implantation process, a bonding process, and a peeling process. Further, the piezoelectric single crystal substrate 1 ′ from which the piezoelectric single crystal thin film 10 has been peeled can be reused in S ⁇ b> 101. That is, since a plurality of piezoelectric single crystal thin films 10 can be formed from one piezoelectric single crystal substrate 1, single crystal piezoelectric material can be saved.
  • an ultrathin film type piezoelectric device having the ultrathin piezoelectric single crystal thin film 10 on the SOI substrate 2 can be manufactured at low cost. Accordingly, the length of the vibrating body including the piezoelectric thin film 10 and the support can be shortened by reducing the thickness of the piezoelectric single crystal thin film 10, so that the outer shape of the piezoelectric device can be reduced. Moreover, the sensitivity with respect to external force can be improved by reducing the thickness of the vibrating body.
  • the piezoelectric single crystal thin film 10 made of LN on the surface of the SOI substrate 2 on the silicon layer 40 side, a highly sensitive piezoelectric sensor with high conversion efficiency between electric energy and mechanical energy can be obtained.
  • the piezoelectric single crystal thin film 10 made of LT is formed on the surface of the SOI substrate 2 on the silicon layer 40 side, a piezoelectric sensor with high sensitivity and good temperature characteristics can be obtained.
  • the manufacturing cost of the ultra-thin film type piezoelectric device can be greatly reduced.
  • FIG. 8 is a flowchart showing a method for manufacturing a piezoelectric device according to the second embodiment.
  • 9 to 10 are views schematically showing the manufacturing process of the piezoelectric device according to the second embodiment.
  • the piezoelectric device manufacturing method of this embodiment differs from the piezoelectric device manufacturing method shown in the first embodiment in that a lower electrode is formed.
  • S202 corresponds to the process.
  • S201 and S203 to S210 in FIG. 8 are the same as S101 and S102 to S109 shown in the first embodiment, respectively. Therefore, regarding S203 to S210 in FIG. 8, only the points that differ depending on S202 in FIG. 8 will be described in detail.
  • a lower portion having a predetermined thickness is formed on the back surface 12 of the piezoelectric single crystal substrate 1 using Al (aluminum) or the like.
  • the electrode 20 is formed (FIG. 8: S202).
  • the lower electrode 20 not only Al but also W, Mo, Ta, Hf, Cu, Pt, Ti, or the like may be used alone or in combination depending on the device specifications.
  • FIG. 9B the surface of the silicon layer 40 on the silicon substrate 50 and the back surface of the lower electrode 20 of the piezoelectric single crystal substrate 1 are joined (FIG. 8: S203).
  • the joining method is the same as that in the first embodiment.
  • the composite of the piezoelectric single crystal substrate 1 and the SOI substrate 2 is heated (in this embodiment, at 500 ° C.), and peeling is performed using the ion implantation layer 100 as a peeling surface (FIG. 8: S204).
  • the composite piezoelectric substrate 4 in which the lower electrode 20 and the piezoelectric single crystal thin film 10 are formed in this order on the surface of the silicon layer 40 on the silicon substrate 50 is obtained. Therefore, the lower electrode 20 is formed between the silicon layer 40 and the piezoelectric single crystal thin film 10. Also in the manufacturing method of this embodiment, as shown in FIG.
  • a piezoelectric single crystal substrate 1 'from which the piezoelectric single crystal thin film 10 has been peeled is obtained. Therefore, the piezoelectric single crystal substrate 1 ′ from which the piezoelectric single crystal thin film 10 has been peeled can be reused in S201.
  • an ultrathin piezoelectric single crystal thin film 10 having a desired thickness can be formed on the SOI substrate 2 by ion implantation, bonding, and peeling.
  • the piezoelectric single crystal substrate 1 ′ from which the piezoelectric single crystal thin film 10 has been peeled can be reused in S ⁇ b> 201. Therefore, according to the piezoelectric device manufacturing method of this embodiment, the same effects as the piezoelectric device manufacturing method of the first embodiment can be obtained.
  • the piezoelectric single crystal thin film 10 formed on the SOI substrate 2 is extremely thin, the piezoelectric single crystal thin film 10 is affected by the stress due to the difference in linear expansion coefficient between the piezoelectric single crystal thin film 10 and the SOI substrate 2. Easy to receive. Therefore, in implementation, a dielectric film is formed on the back surface 12 of the piezoelectric single crystal substrate 1 in addition to the lower electrode 20 in S202, and the difference in linear expansion coefficient between the piezoelectric single crystal thin film 10 and the SOI substrate 2 is buffered. A dielectric film may be formed between the piezoelectric single crystal thin film 10 and the SOI substrate 2.
  • the gyro piezoelectric device has been described as an example. However, the manufacturing method of the present invention is also applied to F-BARs, plate wave devices, RF switches, vibration power generation elements, and the like. Can be applied.

Abstract

Provided is a method for manufacturing a piezoelectric device, with which an extremely thin-film piezoelectric device that has an extremely thin piezoelectric monocrystal thin film on an SOI substrate can be manufactured at low cost. Ion injection depth is determined by ion injection energy, and an ion-injected layer (100) can be formed at a desired depth by varying the ion injection energy. In a peeling process, a piezoelectric monocrystal thin film (10) is formed on an SOI substrate (2) by peeling off the ion-injected layer (100) as a peeled-off surface. In other words, since the thickness of the piezoelectric monocrystal thin film (10) is determined by the ion injection energy, the thickness of the piezoelectric monocrystal thin film (10) can be freely adjusted. Consequently, according to this manufacturing method, an extremely thin piezoelectric monocrystal thin film (10) having the desired thickness can be formed on the SOI substrate (2) by means of ion injection, bonding, and peeling. In addition, monocrystal piezoelectric material can be conserved because a piezoelectric monocrystal substrate (1') from which the piezoelectric monocrystal thin film (10) has been peeled can be reused in the ion injection process.

Description

圧電デバイスの製造方法Method for manufacturing piezoelectric device
　この発明は、圧電単結晶の薄膜を用いた圧電デバイス、特にＳＯＩ基板上に当該薄膜を有する圧電デバイスの製造方法に関するものである。 The present invention relates to a method of manufacturing a piezoelectric device using a piezoelectric single crystal thin film, particularly a piezoelectric device having the thin film on an SOI substrate.
　現在、圧電単結晶の薄膜をＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板上に形成した圧電デバイスが多く開発されている。この種の圧電デバイスの製造方法としては、例えば特許文献１に開示されている。以下、特許文献１に示されている圧電振動ジャイロ装置の製造方法について図１を基に説明する。 Currently, many piezoelectric devices in which a piezoelectric single crystal thin film is formed on an SOI (Silicon On Insulator) substrate have been developed. A method for manufacturing this type of piezoelectric device is disclosed in, for example, Patent Document 1. Hereinafter, a method of manufacturing the piezoelectric vibration gyro device disclosed in Patent Document 1 will be described with reference to FIG.
　図１は、特許文献１に示されている圧電振動ジャイロ装置の製造工程を模式的に示す図である。まず、圧電単結晶基板１とＳＯＩ基板２とを用意する。ＳＯＩ基板２は、図１（Ａ）に示すように、所定厚みのシリコン基板５０に酸化膜３０とシリコン層４０とをこの順に積層した基板である。
　次に、図１（Ｂ）に示すように、ＳＯＩ基板２のシリコン層４０側の表面と圧電単結晶基板１の裏面とを接合する。
　次に、図１（Ｃ）に示すように、所望の厚みの圧電薄膜１５が得られるまで圧電単結晶基板１を裏面側から機械的研磨およびＣＭＰ（ＣＨＥＭＩＣＡＬ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）で研磨する。
　そして、上部電極６０を圧電薄膜１５の表面に形成し、エッチングにより孔部８１及び空隙層８０を形成すると、断面が図１（Ｄ）に示す状態となる。 FIG. 1 is a diagram schematically illustrating a manufacturing process of the piezoelectric vibration gyro device disclosed in Patent Document 1. In FIG. First, a piezoelectric single crystal substrate 1 and an SOI substrate 2 are prepared. As shown in FIG. 1A, the SOI substrate 2 is a substrate in which an oxide film 30 and a silicon layer 40 are stacked in this order on a silicon substrate 50 having a predetermined thickness.
Next, as shown in FIG. 1B, the surface of the SOI substrate 2 on the silicon layer 40 side and the back surface of the piezoelectric single crystal substrate 1 are bonded.
Next, as shown in FIG. 1C, the piezoelectric single crystal substrate 1 is polished from the back side by mechanical polishing and CMP (CHEMICAL Mechanical Polishing) until a piezoelectric thin film 15 having a desired thickness is obtained.
Then, when the upper electrode 60 is formed on the surface of the piezoelectric thin film 15 and the hole 81 and the void layer 80 are formed by etching, the cross section becomes the state shown in FIG.
　以上のような製造工程を経て、圧電単結晶薄膜１５をＳＯＩ基板２上に形成した圧電デバイスが得られる。 Through the above manufacturing process, a piezoelectric device in which the piezoelectric single crystal thin film 15 is formed on the SOI substrate 2 is obtained.
特開２００６－３００６２号公報JP 2006-30062 JP
　圧電デバイスにおいて、その共振周波数は、圧電薄膜の長さや厚み等の形状や圧電薄膜の材質で決まる。一般にユニモルフ型屈曲振動子では、圧電薄膜及び支持体からなる振動体の厚みを薄くすれば共振周波数が下がり、振動体の長さを短くすれば共振周波数が上がる。そのため、圧電デバイスの外形形状の小型化を図るために振動体の長さを短くすると、前述のように共振周波数が上がってしまう。よって、振動体の長さを短くすることにより高くなった共振周波数を下げるためには、振動体の厚みを薄くする必要がある。即ち、圧電デバイスをどれだけ小型化できるかは、振動体の厚みをどれだけ薄くできるかにかかっている。また、振動体の厚みが薄ければ薄い程、外力に対する感度に優れたジャイロセンサを作成できる。 In a piezoelectric device, the resonance frequency is determined by the shape and length of the piezoelectric thin film and the material of the piezoelectric thin film. In general, in a unimorph type flexural vibrator, the resonance frequency decreases when the thickness of the vibrating body made of the piezoelectric thin film and the support is reduced, and the resonance frequency increases when the length of the vibrating body is shortened. Therefore, if the length of the vibrating body is shortened in order to reduce the outer shape of the piezoelectric device, the resonance frequency increases as described above. Therefore, in order to reduce the resonance frequency that has been increased by shortening the length of the vibrating body, it is necessary to reduce the thickness of the vibrating body. That is, how much the piezoelectric device can be reduced depends on how thin the vibrating body can be. In addition, the thinner the vibrating body is, the more gyro sensor can be created that is more sensitive to external force.
　しかしながら、上記特許文献１に示されている圧電振動ジャイロ装置の製造方法において、ＳＯＩ基板を用いることで支持体の厚みは数μｍ程度まで薄くできるが、圧電薄膜については機械的研磨およびＣＭＰによる通常の研磨では、１０μｍまでの厚みの圧電薄膜１５しか作成できなかった。精密な研磨を行った場合、数μｍの厚みの圧電薄膜１５を作成することは可能であるが、その精密な研磨に要する加工時間が大幅に長くなり、製造コストが増大してしまうという問題があった。よって、上記特許文献１の製造方法では、製造コストを考慮して作成できる圧電薄膜１５の厚みが１０μｍまでであったため、同圧電振動ジャイロ装置の外形形状の小型化や外力に対する感度の向上を、これ以上図ることができなかった。 However, in the manufacturing method of the piezoelectric vibration gyro device disclosed in Patent Document 1, the thickness of the support can be reduced to about several μm by using the SOI substrate. However, the piezoelectric thin film is usually obtained by mechanical polishing and CMP. In this polishing, only the piezoelectric thin film 15 having a thickness of up to 10 μm could be formed. When precise polishing is performed, it is possible to produce a piezoelectric thin film 15 having a thickness of several μm. However, there is a problem that the processing time required for the precise polishing is significantly increased and the manufacturing cost is increased. there were. Therefore, in the manufacturing method of Patent Document 1, since the thickness of the piezoelectric thin film 15 that can be created in consideration of the manufacturing cost is up to 10 μm, it is possible to reduce the outer shape of the piezoelectric vibration gyro device and improve the sensitivity to external force. I couldn't do any more.
　また、上記研磨工程では圧電薄膜１５の作成のために機械的研磨およびＣＭＰにより圧電単結晶基板１を研磨しているため、研磨された単結晶の圧電材料は消失してしまう。即ち、上記特許文献１の製造方法では、圧電薄膜１５の作成のためだけに大量の単結晶の圧電材料が研磨工程において消費されていたため、製造コスト高の一因となっていた。 Further, in the polishing step, since the piezoelectric single crystal substrate 1 is polished by mechanical polishing and CMP to create the piezoelectric thin film 15, the polished single crystal piezoelectric material disappears. That is, in the manufacturing method of Patent Document 1 described above, a large amount of single crystal piezoelectric material is consumed in the polishing process only for the production of the piezoelectric thin film 15, which contributes to high manufacturing costs.
　したがって、本発明の目的は、極薄の圧電単結晶薄膜をＳＯＩ基板上に有する極薄膜型圧電デバイスを低コストで製造できる圧電デバイスの製造方法を提供することにある。 Therefore, an object of the present invention is to provide a method for manufacturing a piezoelectric device capable of manufacturing an ultrathin film type piezoelectric device having an ultrathin piezoelectric single crystal thin film on an SOI substrate at a low cost.
　この発明は、支持体と、支持体の表面に接合する圧電単結晶薄膜とを備える圧電デバイスの製造方法に関するものである。この圧電デバイスの製造方法では、少なくとも、イオン注入工程、接合工程、および剥離工程を有する。
　イオン注入工程は、圧電単結晶基板にイオンを注入することで、圧電単結晶基板の中で注入された元素の濃度がピークになるイオン注入層を形成する。接合工程は、圧電単結晶基板のイオン注入層側の面と支持体であるＳＯＩ基板の半導体薄膜層側の面とを接合する。剥離工程は、圧電単結晶基板を加熱してイオン注入層を剥離面とした剥離を行い、圧電単結晶薄膜をＳＯＩ基板の半導体薄膜層側の面に形成する。 The present invention relates to a method for manufacturing a piezoelectric device including a support and a piezoelectric single crystal thin film bonded to the surface of the support. This method for manufacturing a piezoelectric device includes at least an ion implantation process, a bonding process, and a peeling process.
In the ion implantation process, ions are implanted into the piezoelectric single crystal substrate to form an ion implantation layer in which the concentration of the element implanted in the piezoelectric single crystal substrate reaches a peak. In the bonding step, the surface on the ion implantation layer side of the piezoelectric single crystal substrate and the surface on the semiconductor thin film layer side of the SOI substrate as a support are bonded. In the peeling step, the piezoelectric single crystal substrate is heated to perform peeling using the ion implantation layer as a peeling surface, and a piezoelectric single crystal thin film is formed on the surface of the SOI substrate on the semiconductor thin film layer side.
　この製造方法のイオン注入工程において、イオン注入深さは、イオン注入エネルギーで決まり、イオン注入エネルギーを変えることで所望の深さにイオン注入層を形成できる。そして、剥離工程において、イオン注入層を剥離面とした剥離を行うことで、圧電単結晶薄膜がＳＯＩ基板上に形成される。即ち、圧電単結晶薄膜の厚みはイオン注入エネルギーで決まるため、圧電単結晶薄膜の厚みを自由に調整できる。従って、この製造方法によれば、イオン注入工程、接合工程、および剥離工程により、所望の厚みの極薄の圧電単結晶薄膜をＳＯＩ基板上に形成することができる。ここで、ＳＯＩ基板は、所定厚みからなるシリコン基板に酸化膜と半導体薄膜層とをこの順に積層した基板である。極薄の薄膜とは、厚み１０μｍ以下の薄膜をいう。
　また、上記剥離工程において、圧電単結晶薄膜を剥離した圧電単結晶基板はイオン注入工程で再利用することができる。即ち、１枚の圧電単結晶基板から複数の圧電単結晶薄膜を形成することができるため、単結晶の圧電材料を節約することができる。 In the ion implantation step of this manufacturing method, the ion implantation depth is determined by the ion implantation energy, and the ion implantation layer can be formed at a desired depth by changing the ion implantation energy. Then, in the peeling step, the piezoelectric single crystal thin film is formed on the SOI substrate by performing peeling using the ion implantation layer as a peeling surface. That is, since the thickness of the piezoelectric single crystal thin film is determined by the ion implantation energy, the thickness of the piezoelectric single crystal thin film can be freely adjusted. Therefore, according to this manufacturing method, an extremely thin piezoelectric single crystal thin film having a desired thickness can be formed on the SOI substrate by an ion implantation process, a bonding process, and a peeling process. Here, the SOI substrate is a substrate in which an oxide film and a semiconductor thin film layer are stacked in this order on a silicon substrate having a predetermined thickness. An ultrathin thin film refers to a thin film having a thickness of 10 μm or less.
In the peeling step, the piezoelectric single crystal substrate from which the piezoelectric single crystal thin film has been peeled can be reused in the ion implantation step. That is, since a plurality of piezoelectric single crystal thin films can be formed from one piezoelectric single crystal substrate, single crystal piezoelectric material can be saved.
　よって、この実施形態の圧電デバイスの製造方法によれば、極薄の圧電単結晶薄膜をＳＯＩ基板上に有する極薄膜型圧電デバイスを低コストで製造できる。従って、圧電単結晶薄膜の厚みを薄くした分、振動体の長さを短くすることができるため、圧電デバイスの外形形状の小型化を図ることができる。また、圧電単結晶薄膜の厚みを薄くしたことにより、外力に対する感度を向上させることができる。 Therefore, according to the method for manufacturing a piezoelectric device of this embodiment, an ultrathin film type piezoelectric device having an ultrathin piezoelectric single crystal thin film on an SOI substrate can be manufactured at low cost. Therefore, since the length of the vibrating body can be shortened by the thickness of the piezoelectric single crystal thin film, the external shape of the piezoelectric device can be reduced. Further, the sensitivity to external force can be improved by reducing the thickness of the piezoelectric single crystal thin film.
　また、この発明の圧電デバイスの製造方法では、イオン注入工程と接合工程との間に、圧電単結晶基板のイオン注入層側の面に、少なくとも電極膜を形成する膜形成工程を有する。 In addition, the method for manufacturing a piezoelectric device according to the present invention includes a film forming step of forming at least an electrode film on the surface of the piezoelectric single crystal substrate on the ion implantation layer side between the ion implantation step and the bonding step.
　この製造方法では、剥離工程を終えると、圧電単結晶薄膜の半導体薄膜層側の面に電極膜が形成された構造の圧電デバイスを形成できる。
　また、ＳＯＩ基板上に形成される圧電単結晶薄膜の厚みが極めて薄いため、圧電単結晶薄膜は、圧電単結晶薄膜とＳＯＩ基板との線膨張係数の差による応力の影響を受けやすい。そこで、この製造方法では、誘電体膜を圧電単結晶基板のイオン注入層側の面に形成し、当該線膨張係数の差を緩衝する誘電体膜を圧電単結晶薄膜とＳＯＩ基板との間に形成しても構わない。 In this manufacturing method, when the peeling step is finished, a piezoelectric device having a structure in which an electrode film is formed on the surface of the piezoelectric single crystal thin film on the semiconductor thin film layer side can be formed.
In addition, since the thickness of the piezoelectric single crystal thin film formed on the SOI substrate is extremely thin, the piezoelectric single crystal thin film is easily affected by stress due to the difference in linear expansion coefficient between the piezoelectric single crystal thin film and the SOI substrate. Therefore, in this manufacturing method, a dielectric film is formed on the surface of the piezoelectric single crystal substrate on the side of the ion implantation layer, and a dielectric film that buffers the difference in linear expansion coefficient is provided between the piezoelectric single crystal thin film and the SOI substrate. It may be formed.
　また、この発明の圧電デバイスの製造方法では、剥離工程の後に、ＳＯＩ基板の酸化膜層をエッチングすることで、空隙層を形成するエッチング工程を有する。 In addition, the method for manufacturing a piezoelectric device according to the present invention includes an etching step of forming a void layer by etching the oxide film layer of the SOI substrate after the peeling step.
　この製造方法では、シリコン基板と半導体薄膜層との間に空隙層が形成された構造の圧電デバイスを形成できる。 In this manufacturing method, a piezoelectric device having a structure in which a gap layer is formed between a silicon substrate and a semiconductor thin film layer can be formed.
　また、この発明の圧電デバイスの製造方法において、圧電単結晶の薄膜の材質は、ニオブ酸リチウム又はタンタル酸リチウムである。 In the piezoelectric device manufacturing method of the present invention, the material of the piezoelectric single crystal thin film is lithium niobate or lithium tantalate.
　ニオブ酸リチウムは、入手が容易で、圧電性に優れた材料である。ニオブ酸リチウム製の圧電単結晶薄膜をＳＯＩ基板の半導体薄膜層側の面に形成することで、電気エネルギーと機械エネルギーとの変換効率の高い、高感度な圧電センサが得られる。
　一方、タンタル酸リチウムは、入手が容易で、適度な圧電性を有する材料である。タンタル酸リチウム製の圧電単結晶薄膜をＳＯＩ基板の半導体薄膜層側の面に形成することで、高感度で温度特性の良好な圧電センサが得られる。 Lithium niobate is an easily available material with excellent piezoelectricity. By forming a piezoelectric single crystal thin film made of lithium niobate on the surface of the SOI substrate on the semiconductor thin film layer side, a highly sensitive piezoelectric sensor with high conversion efficiency between electric energy and mechanical energy can be obtained.
On the other hand, lithium tantalate is a material that is easily available and has moderate piezoelectricity. By forming a piezoelectric single crystal thin film made of lithium tantalate on the surface of the SOI substrate on the semiconductor thin film layer side, a piezoelectric sensor with high sensitivity and good temperature characteristics can be obtained.
　また、この発明の圧電デバイスの製造方法では、上記エッチング工程までを、複数の圧電デバイスが同時形成可能なマルチ状態で行い、
　複数の圧電デバイスを個別の圧電デバイスに分割する分割工程を有する。 In the piezoelectric device manufacturing method of the present invention, the etching process is performed in a multi-state in which a plurality of piezoelectric devices can be simultaneously formed.
A dividing step of dividing the plurality of piezoelectric devices into individual piezoelectric devices;
　この製造方法では、エッチング工程までの全工程がマルチ状態で行われる。そして、この製造方法における分割工程が、そのエッチング工程の後に行われる。この分割工程により、１つの圧電デバイスが完成する。
　以上より、複数の圧電デバイスを一括製造できる。従って、圧電デバイスの製造コストを大幅に削減できる。 In this manufacturing method, all processes up to the etching process are performed in a multi-state. And the division | segmentation process in this manufacturing method is performed after the etching process. By this dividing step, one piezoelectric device is completed.
As described above, a plurality of piezoelectric devices can be manufactured at once. Therefore, the manufacturing cost of the piezoelectric device can be greatly reduced.
　この発明によれば、極薄の圧電単結晶薄膜をＳＯＩ基板上に有する極薄膜型圧電デバイスを低コストで製造できる。 According to the present invention, an ultra-thin film type piezoelectric device having an ultra-thin piezoelectric single crystal thin film on an SOI substrate can be manufactured at low cost.
図１は、特許文献１に示されている圧電振動ジャイロ装置の製造工程を模式的に示す図である。FIG. 1 is a diagram schematically illustrating a manufacturing process of the piezoelectric vibration gyro device disclosed in Patent Document 1. In FIG. 図２は、第１の実施形態に係る圧電デバイスの製造方法を示すフローチャートである。FIG. 2 is a flowchart showing the method for manufacturing the piezoelectric device according to the first embodiment. 図３は、図２に示す圧電デバイスの製造工程を模式的に示す図である。FIG. 3 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG. 図４は、図２に示す圧電デバイスの製造工程を模式的に示す図である。FIG. 4 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG. 図５は、図２に示す圧電デバイスの製造工程を模式的に示す図である。FIG. 5 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG. 図６は、図２に示す圧電デバイスの製造工程を模式的に示す図である。FIG. 6 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG. 図７は、図２に示す圧電デバイスの製造工程を模式的に示す図である。FIG. 7 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG. 図８は、第２の実施形態に係る圧電デバイスの製造方法を示すフローチャートである。FIG. 8 is a flowchart showing a method for manufacturing a piezoelectric device according to the second embodiment. 図９は、図８に示す圧電デバイスの製造工程を模式的に示す図である。FIG. 9 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG. 図１０は、図８に示す圧電デバイスの製造工程を模式的に示す図である。FIG. 10 is a diagram schematically showing a manufacturing process of the piezoelectric device shown in FIG.
　本発明の第１の実施形態に係る圧電デバイスの製造方法について、図を参照して説明する。なお、以下の説明では、圧電デバイスとして、圧電薄膜を用いたジャイロ用の極薄膜型圧電デバイスを例に説明する。 A method for manufacturing a piezoelectric device according to the first embodiment of the present invention will be described with reference to the drawings. In the following description, an extremely thin film piezoelectric device for a gyro using a piezoelectric thin film will be described as an example of the piezoelectric device.
　図２は、第１の実施形態に係る圧電デバイスの製造方法を示すフローチャートである。図３～図７は、第１の実施形態に係る圧電デバイスの製造工程を模式的に示す図である。 FIG. 2 is a flowchart showing a method for manufacturing the piezoelectric device according to the first embodiment. 3 to 7 are views schematically showing the manufacturing process of the piezoelectric device according to the first embodiment.
　まず、図３（Ａ）（Ｂ）に示すように、圧電単結晶基板１と、ＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板２とを用意する。圧電単結晶基板１は、所定厚みのＬＮ（ＬｉＮｂＯ３）基板を利用する。ＬＮは、入手が容易で、圧電性に優れた材料である。なお、圧電単結晶基板１とＳＯＩ基板２は、それぞれの接合面がＣＭＰ等により鏡面研磨したものを用意する。 First, as shown in FIGS. 3A and 3B, a piezoelectric single crystal substrate 1 and an SOI (Silicon On Insulator) substrate 2 are prepared. The piezoelectric single crystal substrate 1 uses an LN (LiNbO 3 ) substrate having a predetermined thickness. LN is a material that is easily available and excellent in piezoelectricity. Note that the piezoelectric single crystal substrate 1 and the SOI substrate 2 are prepared by mirror-polishing the respective bonding surfaces by CMP or the like.
　上記圧電単結晶基板１は、入手が容易で適度な圧電性を有するＬＴ（ＬｉＴａＯ３）基板の他、ＬＢＯ（Ｌｉ２Ｂ４Ｏ７）基板やランガサイト（Ｌａ３Ｇａ５ＳｉＯ１４）基板、ＫＮ（ＫＮｂＯ３）基板、ＫＬＮ（Ｋ３Ｌｉ２Ｎｂ５Ｏ１５）基板等を用いても構わない。 The piezoelectric single crystal substrate 1 is an LT (LiTaO 3 ) substrate that is easily available and has appropriate piezoelectricity, an LBO (Li 2 B 4 O 7 ) substrate, a langasite (La 3 Ga 5 SiO 14 ) substrate, A KN (KNbO 3 ) substrate, a KLN (K 3 Li 2 Nb 5 O 15 ) substrate, or the like may be used.
　上記ＳＯＩ基板２は、図３（Ｂ）に示すように、所定厚みからなるシリコン基板５０に酸化膜３０とシリコン層４０とをこの順に積層した基板である。ここで、ＳＯＩ基板２としては、極薄膜型圧電デバイス単体が複数配列されるマルチ状態の基板を用いる。シリコン基板５０は、Ｓｉからなる基板である。酸化膜３０は、Ｓｉの酸化膜である。酸化膜３０は、シリコン層４０等に対してエッチングレートを異ならせられるようなエッチングガスもしくはエッチング液が選択可能な材料からなり、シリコン層４０よりもエッチングされやすい材料からなる。シリコン層４０は、Ｓｉからなる層であり、その厚みは、数μｍ～数１００μｍである。 As shown in FIG. 3B, the SOI substrate 2 is a substrate in which an oxide film 30 and a silicon layer 40 are laminated in this order on a silicon substrate 50 having a predetermined thickness. Here, as the SOI substrate 2, a multi-state substrate in which a plurality of single ultrathin piezoelectric devices are arranged is used. The silicon substrate 50 is a substrate made of Si. The oxide film 30 is an oxide film of Si. The oxide film 30 is made of a material that can select an etching gas or an etchant that can change the etching rate with respect to the silicon layer 40 or the like, and is made of a material that is more easily etched than the silicon layer 40. The silicon layer 40 is a layer made of Si, and has a thickness of several μm to several hundred μm.
　次に、図４に示すように、圧電単結晶基板１の裏面１２側からヘリウムイオンを注入することで、圧電単結晶基板１にイオン注入層１００を形成する（図２：Ｓ１０１）。例えば圧電単結晶基板１にＬＮ基板を用いれば、加速エネルギー１８０ＫｅＶで２．０×１０１６ａｔｏｍ／ｃｍ２のドーズ量によりＨｅ＋イオン注入を行うことにより、裏面１２から例えば深さ約０，６μｍの位置にＨｅ＋イオン層（ヘリウム分布部分）が形成されて、イオン注入層１００が形成される。このイオン注入深さは、イオン注入エネルギーで決まるため、所望の深さにイオン注入層１００を形成できる。このイオン注入層１００は、圧電単結晶基板１の中で注入されたイオン元素の濃度がピークになる部分である。
　なお、圧電単結晶基板１にＬＮ基板以外の素材を用いた場合、それぞれの基板に応じた条件でイオン注入を行う。 Next, as shown in FIG. 4, helium ions are implanted from the back surface 12 side of the piezoelectric single crystal substrate 1 to form an ion implantation layer 100 on the piezoelectric single crystal substrate 1 (FIG. 2: S101). For example, when an LN substrate is used as the piezoelectric single crystal substrate 1, He + ion implantation is performed from the back surface 12 to a depth of about 0.6 μm, for example, by accelerating energy of 180 KeV and a dose of 2.0 × 10 16 atoms / cm 2. The He + ion layer (helium distribution portion) is formed at the position of, and the ion implantation layer 100 is formed. Since the ion implantation depth is determined by the ion implantation energy, the ion implantation layer 100 can be formed at a desired depth. The ion implantation layer 100 is a portion where the concentration of the ion element implanted in the piezoelectric single crystal substrate 1 reaches a peak.
When a material other than the LN substrate is used for the piezoelectric single crystal substrate 1, ion implantation is performed under conditions according to each substrate.
　次に、図５（Ａ）に示すように、ＳＯＩ基板２のシリコン層４０の表面と圧電単結晶基板１の裏面１２とを接合する（図２：Ｓ１０２）。
　なお、この接合には、活性化接合を用いると良い。この活性化接合とは、常温において、真空中でＡｒイオンビーム等を照射して接合面を活性化させた状態で接合するものであり、加熱を必要としない接合方法である。この方法を用いることにより、親水化接合のような接合後に水素を脱気するための加熱処理を必要とせず、加熱による圧電デバイスの特性の劣化や、圧電単結晶基板１とＳＯＩ基板２との線膨張係数の差による応力の発生を防止できる。 Next, as shown in FIG. 5A, the surface of the silicon layer 40 of the SOI substrate 2 and the back surface 12 of the piezoelectric single crystal substrate 1 are joined (FIG. 2: S102).
Note that activated bonding is preferably used for this bonding. This activated bonding is a bonding method in which Ar is irradiated with an Ar ion beam or the like in a vacuum at room temperature and the bonding surface is activated and does not require heating. By using this method, heat treatment for degassing hydrogen after bonding such as hydrophilic bonding is not required, deterioration of the characteristics of the piezoelectric device due to heating, and the relationship between the piezoelectric single crystal substrate 1 and the SOI substrate 2 Generation of stress due to the difference in linear expansion coefficient can be prevented.
　次に、圧電単結晶基板１とＳＯＩ基板２との複合体を（例えば５００℃で）加熱し、イオン注入層１００を剥離面とした剥離を行う（図２：Ｓ１０３）。これにより、図５（Ｂ）に示すように、ＳＯＩ基板２のシリコン層４０の表面に圧電単結晶薄膜１０が形成された複合圧電基板３が得られる。この実施形態においては、０．６μｍの厚みの圧電単結晶薄膜１０がＳＯＩ基板２上に形成される。また、図５（Ｃ）に示すように、圧電単結晶薄膜１０を剥離した圧電単結晶基板１´が得られる。
　なお、上記Ｓ１０３の際、減圧雰囲気下で加熱すれば、加熱温度を低くすることができる。 Next, the composite of the piezoelectric single crystal substrate 1 and the SOI substrate 2 is heated (for example, at 500 ° C.) to perform separation using the ion implantation layer 100 as a separation surface (FIG. 2: S103). As a result, as shown in FIG. 5B, the composite piezoelectric substrate 3 in which the piezoelectric single crystal thin film 10 is formed on the surface of the silicon layer 40 of the SOI substrate 2 is obtained. In this embodiment, a piezoelectric single crystal thin film 10 having a thickness of 0.6 μm is formed on the SOI substrate 2. Further, as shown in FIG. 5C, a piezoelectric single crystal substrate 1 'from which the piezoelectric single crystal thin film 10 has been peeled is obtained.
In addition, in the case of S103, the heating temperature can be lowered by heating in a reduced pressure atmosphere.
　そして、このように剥離形成した圧電単結晶薄膜１０の表面と圧電単結晶基板１´の裏面とをＣＭＰ処理等により研磨して平坦化する（図２：Ｓ１０４）。この結果、厚み０．６μｍの極薄の圧電単結晶薄膜１０がＳＯＩ基板２上に形成される。この圧電単結晶薄膜１０は、単結晶の圧電薄膜であるため、スパッタ、蒸着、ＣＶＤ法等で成膜される多結晶の圧電薄膜より圧電性に優れている。また、圧電単結晶薄膜１０を剥離した圧電単結晶基板１´はＳ１０１で再利用することができる。即ち、１枚の圧電単結晶基板１から複数の圧電単結晶薄膜１０を形成することができる。 Then, the surface of the piezoelectric single crystal thin film 10 thus peeled and the back surface of the piezoelectric single crystal substrate 1 ′ are polished and flattened by CMP or the like (FIG. 2: S104). As a result, an ultrathin piezoelectric single crystal thin film 10 having a thickness of 0.6 μm is formed on the SOI substrate 2. Since the piezoelectric single crystal thin film 10 is a single crystal piezoelectric thin film, it is superior in piezoelectricity to a polycrystalline piezoelectric thin film formed by sputtering, vapor deposition, CVD, or the like. Further, the piezoelectric single crystal substrate 1 ′ from which the piezoelectric single crystal thin film 10 has been peeled can be reused in S <b> 101. That is, a plurality of piezoelectric single crystal thin films 10 can be formed from one piezoelectric single crystal substrate 1.
　次に、図６（Ａ）に示すように、圧電単結晶薄膜１０の表面上に、Ａｌ（アルミニウム）等を用いて、所定厚みの上部電極６０を形成する（図２：Ｓ１０５）。
　なお、この上部電極６０には、Ａｌのみでなく、デバイスの仕様に応じて、Ｗ、Ｍｏ、Ｔａ、Ｈｆ、Ｃｕ、Ｐｔ、Ｔｉ等を単体もしくは組み合わせて用いてもよい。 Next, as shown in FIG. 6A, an upper electrode 60 having a predetermined thickness is formed on the surface of the piezoelectric single crystal thin film 10 using Al (aluminum) or the like (FIG. 2: S105).
For the upper electrode 60, not only Al but also W, Mo, Ta, Hf, Cu, Pt, Ti, or the like may be used alone or in combination depending on device specifications.
　次に、上部電極６０が形成された圧電単結晶薄膜１０の表面に、レジスト膜を形成する（図２：Ｓ１０６）。そして、フォトリソグラフィ技術を用いて、圧電単結晶薄膜１０およびシリコン層４０を貫通する孔部８１を形成するためのエッチング窓をレジスト膜に形成する。 Next, a resist film is formed on the surface of the piezoelectric single crystal thin film 10 on which the upper electrode 60 is formed (FIG. 2: S106). Then, using a photolithography technique, an etching window for forming the hole 81 penetrating the piezoelectric single crystal thin film 10 and the silicon layer 40 is formed in the resist film.
　次に、このエッチング窓を介してエッチングガスもしくはエッチング液を流入させることで、図６（Ｂ）に示すように、圧電単結晶薄膜１０及びシリコン層４０に孔部８１を形成する（図２：Ｓ１０７）。 Next, by passing an etching gas or an etchant through the etching window, holes 81 are formed in the piezoelectric single crystal thin film 10 and the silicon layer 40 as shown in FIG. 6B (FIG. 2: S107).
　そして、エッチングガスもしくはエッチング液を孔部８１を介して流入させることで、酸化膜３０を除去する（図２：Ｓ１０８）。この結果、酸化膜３０が形成されていた空間は、図７（Ａ）に示すような空隙層８０となる。
　なお、Ｓ１０８で使用するエッチングガスもしくはエッチング液は、酸化膜３０に応じたエッチングガスもしくはエッチング液であり、上記Ｓ１０７と種類の異なるものである。 Then, the oxide film 30 is removed by flowing an etching gas or an etching solution through the hole 81 (FIG. 2: S108). As a result, the space in which the oxide film 30 was formed becomes a void layer 80 as shown in FIG.
Note that the etching gas or etching liquid used in S108 is an etching gas or etching liquid corresponding to the oxide film 30, and is different in type from S107.
　次に、図７（Ｂ）に示すように、仕上げ表面電極パターンを形成する（図２：Ｓ１０９）。詳述すると、上部電極６０に導通するバンプパッド６１が形成され、全バンプパッド６１上に不図示のバンプを形成する。 Next, as shown in FIG. 7B, a finished surface electrode pattern is formed (FIG. 2: S109). More specifically, bump pads 61 that are electrically connected to the upper electrode 60 are formed, and bumps (not shown) are formed on all the bump pads 61.
　最後に、ＳＯＩ基板２上にマルチ状態で形成された複数の極薄膜型圧電デバイスから個別の極薄膜型圧電デバイスに分割する分割工程を経て、モールド金型を用いたパッケージングを行う。このようにして極薄膜型圧電デバイスを形成する。そのため、複数の極薄膜型圧電デバイスを一括製造できる。 Finally, packaging using a mold is performed through a dividing process in which a plurality of ultrathin film piezoelectric devices formed in a multi-state on the SOI substrate 2 are divided into individual ultrathin film piezoelectric devices. In this way, an ultrathin film type piezoelectric device is formed. Therefore, a plurality of ultra-thin film type piezoelectric devices can be manufactured collectively.
　以上に示す製造方法において、イオン注入深さは、イオン注入エネルギーで決まり、イオン注入エネルギーを変えることで所望の深さにイオン注入層１００を形成できる。そして、剥離工程において、イオン注入層１００を剥離面とした剥離を行うことで、圧電単結晶薄膜１０がＳＯＩ基板２上に形成される。即ち、圧電単結晶薄膜１０の厚みはイオン注入エネルギーで決まるため、圧電単結晶薄膜１０の厚みを自由に調整できる。従って、この製造方法によれば、イオン注入工程、接合工程、および剥離工程により、所望の厚み（１０μｍ以下）の極薄の圧電単結晶薄膜１０をＳＯＩ基板２上に形成することができる。
　また、圧電単結晶薄膜１０を剥離した圧電単結晶基板１´はＳ１０１で再利用することができる。即ち、１枚の圧電単結晶基板１から複数の圧電単結晶薄膜１０を形成することができるため、単結晶の圧電材料を節約することができる。 In the manufacturing method described above, the ion implantation depth is determined by the ion implantation energy, and the ion implantation layer 100 can be formed at a desired depth by changing the ion implantation energy. Then, in the peeling step, the piezoelectric single crystal thin film 10 is formed on the SOI substrate 2 by performing peeling using the ion implantation layer 100 as a peeling surface. That is, since the thickness of the piezoelectric single crystal thin film 10 is determined by ion implantation energy, the thickness of the piezoelectric single crystal thin film 10 can be freely adjusted. Therefore, according to this manufacturing method, the ultrathin piezoelectric single crystal thin film 10 having a desired thickness (10 μm or less) can be formed on the SOI substrate 2 by an ion implantation process, a bonding process, and a peeling process.
Further, the piezoelectric single crystal substrate 1 ′ from which the piezoelectric single crystal thin film 10 has been peeled can be reused in S <b> 101. That is, since a plurality of piezoelectric single crystal thin films 10 can be formed from one piezoelectric single crystal substrate 1, single crystal piezoelectric material can be saved.
　よって、この実施形態の圧電デバイスの製造方法によれば、極薄の圧電単結晶薄膜１０をＳＯＩ基板２上に有する極薄膜型圧電デバイスを低コストで製造できる。従って、圧電単結晶薄膜１０の厚みを薄くした分、圧電薄膜１０及び支持体からなる振動体の長さを短くすることができるため、圧電デバイスの外形形状の小型化を図ることができる。また、同振動体の厚みを薄くしたことにより、外力に対する感度を向上させることができる。 Therefore, according to the method for manufacturing a piezoelectric device of this embodiment, an ultrathin film type piezoelectric device having the ultrathin piezoelectric single crystal thin film 10 on the SOI substrate 2 can be manufactured at low cost. Accordingly, the length of the vibrating body including the piezoelectric thin film 10 and the support can be shortened by reducing the thickness of the piezoelectric single crystal thin film 10, so that the outer shape of the piezoelectric device can be reduced. Moreover, the sensitivity with respect to external force can be improved by reducing the thickness of the vibrating body.
　また、ＬＮ製の圧電単結晶薄膜１０をＳＯＩ基板２のシリコン層４０側の面に形成することで、電気エネルギーと機械エネルギーとの変換効率の高い、高感度な圧電センサが得られる。一方、ＬＴ製の圧電単結晶薄膜１０をＳＯＩ基板２のシリコン層４０側の面に形成した場合、高感度で温度特性の良好な圧電センサが得られる。 Further, by forming the piezoelectric single crystal thin film 10 made of LN on the surface of the SOI substrate 2 on the silicon layer 40 side, a highly sensitive piezoelectric sensor with high conversion efficiency between electric energy and mechanical energy can be obtained. On the other hand, when the piezoelectric single crystal thin film 10 made of LT is formed on the surface of the SOI substrate 2 on the silicon layer 40 side, a piezoelectric sensor with high sensitivity and good temperature characteristics can be obtained.
　また、複数の極薄膜型圧電デバイスを一括製造できるため、極薄膜型圧電デバイスの製造コストを大幅に削減できる。 Also, since a plurality of ultra-thin film type piezoelectric devices can be manufactured at once, the manufacturing cost of the ultra-thin film type piezoelectric device can be greatly reduced.
　次に、第２の実施形態に係る圧電デバイスの製造方法について、図を参照して説明する。
　図８は、第２の実施形態に係る圧電デバイスの製造方法を示すフローチャートである。図９～図１０は、第２の実施形態に係る圧電デバイスの製造工程を模式的に示す図である。 Next, a method for manufacturing a piezoelectric device according to the second embodiment will be described with reference to the drawings.
FIG. 8 is a flowchart showing a method for manufacturing a piezoelectric device according to the second embodiment. 9 to 10 are views schematically showing the manufacturing process of the piezoelectric device according to the second embodiment.
　この実施形態の圧電デバイスの製造方法は、第１の実施形態に示した圧電デバイスの製造方法に対して、下部電極を形成する点で相違するものである。図８では、Ｓ２０２が当該工程に対応する。
　なお、図８のＳ２０１、Ｓ２０３～Ｓ２１０は、それぞれ第１の実施形態に示したＳ１０１、Ｓ１０２～Ｓ１０９と同じである。そのため、図８のＳ２０３～Ｓ２１０に関しては、図８のＳ２０２によって異なってくる点のみを詳述する。 The piezoelectric device manufacturing method of this embodiment differs from the piezoelectric device manufacturing method shown in the first embodiment in that a lower electrode is formed. In FIG. 8, S202 corresponds to the process.
Note that S201 and S203 to S210 in FIG. 8 are the same as S101 and S102 to S109 shown in the first embodiment, respectively. Therefore, regarding S203 to S210 in FIG. 8, only the points that differ depending on S202 in FIG. 8 will be described in detail.
　図９（Ａ）に示すように、Ｓ２０１において圧電単結晶基板１にイオン注入層１００を形成した後、圧電単結晶基板１の裏面１２上に、Ａｌ（アルミニウム）等を用いて所定厚みの下部電極２０を形成する（図８：Ｓ２０２）。
　なお、下部電極２０には、Ａｌのみでなく、デバイスの仕様に応じて、Ｗ、Ｍｏ、Ｔａ、Ｈｆ、Ｃｕ、Ｐｔ、Ｔｉ等を単体もしくは組み合わせて用いてもよい。 As shown in FIG. 9A, after the ion implantation layer 100 is formed on the piezoelectric single crystal substrate 1 in S201, a lower portion having a predetermined thickness is formed on the back surface 12 of the piezoelectric single crystal substrate 1 using Al (aluminum) or the like. The electrode 20 is formed (FIG. 8: S202).
For the lower electrode 20, not only Al but also W, Mo, Ta, Hf, Cu, Pt, Ti, or the like may be used alone or in combination depending on the device specifications.
　次に、図９（Ｂ）に示すように、シリコン基板５０上のシリコン層４０の表面と圧電単結晶基板１の下部電極２０の裏面とを接合する（図８：Ｓ２０３）。
　なお、接合方法は、第１の実施形態と同じである。 Next, as shown in FIG. 9B, the surface of the silicon layer 40 on the silicon substrate 50 and the back surface of the lower electrode 20 of the piezoelectric single crystal substrate 1 are joined (FIG. 8: S203).
The joining method is the same as that in the first embodiment.
　次に、圧電単結晶基板１とＳＯＩ基板２との複合体を（この実施形態では５００℃で）加熱し、イオン注入層１００を剥離面とした剥離を行う（図８：Ｓ２０４）。これにより、図９（Ｃ）に示すように、シリコン基板５０上のシリコン層４０の表面に、下部電極２０と圧電単結晶薄膜１０とがこの順に形成された複合圧電基板４が得られる。そのため、下部電極２０がシリコン層４０と圧電単結晶薄膜１０との間に形成される。また、この実施形態の製造方法においても、図５（Ｃ）に示すように、圧電単結晶薄膜１０を剥離した圧電単結晶基板１´が得られる。よって、圧電単結晶薄膜１０を剥離した圧電単結晶基板１´をＳ２０１で再利用することができる。 Next, the composite of the piezoelectric single crystal substrate 1 and the SOI substrate 2 is heated (in this embodiment, at 500 ° C.), and peeling is performed using the ion implantation layer 100 as a peeling surface (FIG. 8: S204). As a result, as shown in FIG. 9C, the composite piezoelectric substrate 4 in which the lower electrode 20 and the piezoelectric single crystal thin film 10 are formed in this order on the surface of the silicon layer 40 on the silicon substrate 50 is obtained. Therefore, the lower electrode 20 is formed between the silicon layer 40 and the piezoelectric single crystal thin film 10. Also in the manufacturing method of this embodiment, as shown in FIG. 5C, a piezoelectric single crystal substrate 1 'from which the piezoelectric single crystal thin film 10 has been peeled is obtained. Therefore, the piezoelectric single crystal substrate 1 ′ from which the piezoelectric single crystal thin film 10 has been peeled can be reused in S201.
　以後、Ｓ２０９までの工程を経ると、断面が図１０に示す状態となる。そして、Ｓ２１０において仕上げ表面電極パターンを形成した後、第１の実施形態で述べた分割工程とパッケージング工程に進み、極薄膜型圧電デバイスを形成する。 Thereafter, when the process up to S209 is performed, the cross section becomes the state shown in FIG. Then, after forming the finished surface electrode pattern in S210, the process proceeds to the dividing step and the packaging step described in the first embodiment to form an ultrathin film type piezoelectric device.
　以上に示す製造方法においても、イオン注入、接合、剥離により、所望の厚みで極薄の圧電単結晶薄膜１０をＳＯＩ基板２上に形成することができる。また、圧電単結晶薄膜１０を剥離した圧電単結晶基板１´はＳ２０１で再利用することができる。そのため、この実施形態の圧電デバイスの製造方法によれば、第１の実施形態の圧電デバイスの製造方法と同様の効果を奏する。 Also in the manufacturing method described above, an ultrathin piezoelectric single crystal thin film 10 having a desired thickness can be formed on the SOI substrate 2 by ion implantation, bonding, and peeling. In addition, the piezoelectric single crystal substrate 1 ′ from which the piezoelectric single crystal thin film 10 has been peeled can be reused in S <b> 201. Therefore, according to the piezoelectric device manufacturing method of this embodiment, the same effects as the piezoelectric device manufacturing method of the first embodiment can be obtained.
　なお、ＳＯＩ基板２上に形成される圧電単結晶薄膜１０の厚みが極めて薄いため、圧電単結晶薄膜１０は、圧電単結晶薄膜１０とＳＯＩ基板２との線膨張係数の差による応力の影響を受けやすい。そこで、実施の際は、Ｓ２０２において下部電極２０に加えて誘電体膜を圧電単結晶基板１の裏面１２上に形成し、圧電単結晶薄膜１０とＳＯＩ基板２との線膨張係数の差を緩衝する誘電体膜を圧電単結晶薄膜１０とＳＯＩ基板２との間に形成しても構わない。
　また、上述の各実施形態では、ジャイロ用の圧電デバイスを例に説明したが、他に、Ｆ－ＢＡＲ、板波デバイス、ＲＦスイッチ、振動発電素子等に対しても、本発明の製造方法を適用することができる。 In addition, since the thickness of the piezoelectric single crystal thin film 10 formed on the SOI substrate 2 is extremely thin, the piezoelectric single crystal thin film 10 is affected by the stress due to the difference in linear expansion coefficient between the piezoelectric single crystal thin film 10 and the SOI substrate 2. Easy to receive. Therefore, in implementation, a dielectric film is formed on the back surface 12 of the piezoelectric single crystal substrate 1 in addition to the lower electrode 20 in S202, and the difference in linear expansion coefficient between the piezoelectric single crystal thin film 10 and the SOI substrate 2 is buffered. A dielectric film may be formed between the piezoelectric single crystal thin film 10 and the SOI substrate 2.
In each of the above-described embodiments, the gyro piezoelectric device has been described as an example. However, the manufacturing method of the present invention is also applied to F-BARs, plate wave devices, RF switches, vibration power generation elements, and the like. Can be applied.
　また、上述の実施形態の説明は、すべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は、上述の実施形態ではなく、特許請求の範囲によって示される。さらに、本発明の範囲には、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 Further, the description of the above-described embodiment is an example in all respects, and should be considered not restrictive. The scope of the present invention is shown not by the above embodiments but by the claims. Furthermore, the scope of the present invention is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.
　１…圧電単結晶基板
　２…ＳＯＩ基板
　３…複合圧電基板
　４…複合圧電基板
　１０…圧電薄膜
　１００…イオン注入層
　２０…下部電極
　３０…酸化膜
　４０…シリコン層
　５０…支持基板
　６０…上部電極
　６１…バンプパッド
　８０…空隙層
　８１…孔部 DESCRIPTION OF SYMBOLS 1 ... Piezoelectric single crystal substrate 2 ... SOI substrate 3 ... Composite piezoelectric substrate 4 ... Composite piezoelectric substrate 10 ... Piezoelectric thin film 100 ... Ion implantation layer 20 ... Lower electrode 30 ... Oxide film 40 ... Silicon layer 50 ... Support substrate 60 ... Upper electrode 61 ... Bump pad 80 ... Void layer 81 ... Hole

Claims (5)

  1. 　支持体と、前記支持体の表面に接合する圧電単結晶薄膜とを備える圧電デバイスの製造方法であって、
    　圧電単結晶基板にイオンを注入することで、イオン注入層を形成するイオン注入工程と、
    　前記圧電単結晶基板の前記イオン注入層側の面と前記支持体であるＳＯＩ基板の半導体薄膜層側の面とを接合する接合工程と、
    　前記圧電単結晶基板を加熱して前記イオン注入層を剥離面とした剥離を行い、単結晶の前記圧電薄膜を前記ＳＯＩ基板の前記半導体薄膜層側の面に形成する剥離工程と、
    　を有する圧電デバイスの製造方法。     A method of manufacturing a piezoelectric device comprising a support and a piezoelectric single crystal thin film bonded to the surface of the support,
    An ion implantation step of forming an ion implantation layer by implanting ions into the piezoelectric single crystal substrate;
    A bonding step of bonding the surface on the ion implantation layer side of the piezoelectric single crystal substrate and the surface on the semiconductor thin film layer side of the SOI substrate as the support;
    A peeling step of heating the piezoelectric single crystal substrate to perform peeling using the ion implantation layer as a peeling surface, and forming the piezoelectric thin film of single crystal on the semiconductor thin film layer side of the SOI substrate;
    A method of manufacturing a piezoelectric device having
  2. 　前記イオン注入工程と前記接合工程との間に、前記圧電単結晶基板の前記イオン注入層側の面に、電極膜および誘電体膜の少なくとも一方の膜を形成する膜形成工程を有する、請求項１に記載の圧電デバイスの製造方法。 The film forming step of forming at least one of an electrode film and a dielectric film on a surface of the piezoelectric single crystal substrate on the ion implantation layer side between the ion implantation step and the bonding step. A method for manufacturing the piezoelectric device according to claim 1.
  3. 　前記剥離工程の後に、前記ＳＯＩ基板の酸化膜層をエッチングすることで、空隙層を形成するエッチング工程を有する、請求項１または請求項２に記載の圧電デバイスの製造方法。 3. The method for manufacturing a piezoelectric device according to claim 1, further comprising an etching step of forming a void layer by etching the oxide film layer of the SOI substrate after the peeling step.
  4. 　前記圧電単結晶の薄膜の材質は、ニオブ酸リチウム又はタンタル酸リチウムである、請求項１から請求項３のいずれかに記載の圧電デバイスの製造方法。 The method for manufacturing a piezoelectric device according to any one of claims 1 to 3, wherein a material of the thin film of the piezoelectric single crystal is lithium niobate or lithium tantalate.
  5. 　前記エッチング工程までを、複数の圧電デバイスが同時形成可能なマルチ状態で行い、
    　前記複数の圧電デバイスを個別の圧電デバイスに分割する分割工程を有する、請求項３または請求項４に記載の圧電デバイスの製造方法。     Up to the etching step is performed in a multi-state in which a plurality of piezoelectric devices can be formed simultaneously,
    The method for manufacturing a piezoelectric device according to claim 3, further comprising a dividing step of dividing the plurality of piezoelectric devices into individual piezoelectric devices.
PCT/JP2010/068890 2009-12-18 2010-10-26 Method for manufacturing piezoelectric device WO2011074329A1 (en)

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CN108475722A (en) * 2015-12-22 2018-08-31 索泰克公司 For temperature-compensating surface acoustic wave device or the substrate of bulk acoustic wave device
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