WO2011071273A2

WO2011071273A2 - Sram based address generator for each layer and address generator including the same

Info

Publication number: WO2011071273A2
Application number: PCT/KR2010/008595
Authority: WO
Inventors: Sang-Hyeon Baeg; Zahid Ullah
Original assignee: Iucf-Hyu (Industry-University Cooperation Foundation Hanyang University)
Priority date: 2009-12-08
Filing date: 2010-12-02
Publication date: 2011-06-16
Also published as: KR101074495B1; WO2011071273A3; KR20110064633A

Abstract

An SRAM based address generator is provided, which can perform a TCAM function that returns an address of data when the data is input. The address generator includes n bit position tables receiving n input sub-words each of which is composed of w bits and outputting bit position data of addresses indicated by (w-b) bits of the respective sub-words, last index data, and bit values indicated by b bits of the sub-words among the bit position data; a first AND operation unit receiving and performing an AND operation of the n bit values and outputting n enable signals; n address generators receiving the bit position data, the last index data, and the enable signals and outputting address data; n address position tables receiving the address data and outputting address position data of the addresses indicated by the address data; and a second AND operation unit receiving and performing an AND operation of the n address position data and outputting first matching addresses.

Description

SRAM BASED ADDRESS GENERATOR FOR EACH LAYER AND ADDRESS GENERATOR INCLUDING THE SAME

The present invention relates to an address generator. More particularly, the present invention relates to an SRAM based address generator which can output an address of data when the data is input.

An address generator (AG) 5, as illustrated in FIG. 1, is a device that output an address of data when the corresponding data is input. As a representative, a CAM (Content Addressable Memory) may be exemplified. Unlike a RAM (Random Access Memory), the CAM is a memory that receives data and returns an address of the input data.

On the other hand, a TCAM (Ternary Content Addressable Memory) is a memory that can store “X (don’t care)” in addition to “0” and “1” as data values. Although the TCAM has a high search speed and thus wins popularity, its use is limited due to the cost that is caused by the power consumption or the like as an amount of stored data increases.

Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and a subject to be achieved by the present invention is to provide an address generator for each layer which can perform an address return function of a TCAM at low cost.

Another subject to be achieved by the present invention is to provide an address generator which can perform an address return function of a TCAM.

Additional advantages, subjects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.

In one aspect of the present invention, there is provided an address generator for each layer, which includes n bit position tables receiving n input sub-words each of which is composed of w bits, and outputting bit position data of addresses indicated by (w-b) bits of the respective sub-words, last index data, and bit values indicated by b bits of the sub-words among the bit position data; a first AND operation unit receiving and performing an AND operation of the n bit values and outputting n enable signals; n address generators receiving the bit position data, the last index data, and the enable signals, and outputting address data; n address position tables receiving the address data and outputting address position data of the addresses indicated by the address data; and a second AND operation unit receiving and performing an AND operation of the n address position data, and outputting first matching addresses.

In another aspect of the present invention, there is provided an address generator, which includes m address generators for respective layers; and a second encoder receiving m first matching addresses or second matching addresses from the m address generators for the respective layers, and outputting third matching addresses.

According to the present invention as constructed above, in the case of using the address generators according to an embodiment of the present invention, the TCAM address return function can be performed at low cost by returning the addresses of the input words using the bit position tables and the address position tables stored in an SRAM instead of forming the TCAM.

The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a conceptual diagram of an address generator;

FIG. 2 is a diagram explaining a hybrid partition;

FIG. 3 is a configuration diagram explaining an address generator for each layer according to an embodiment of the present invention;

FIG. 4 is a diagram explaining a bit position table;

FIG. 5 is a diagram explaining an address position table;

FIG. 6 is a configuration diagram explaining an address generator according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating an example of a TCAM;

FIG. 8 is a diagram illustrating the performing of hybrid partitions with respect to the TCAM of FIG. 7;

FIGS. 9 to 12 are diagrams illustrating bit position tables and address position tables that can perform the TCAM function; and

FIG. 13 is a diagram explaining the operation of an address generator according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The aspects and features of the present invention and methods for achieving the aspects and features will be apparent by referring to the embodiments to be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed hereinafter, but can be implemented in diverse forms. The matters defined in the description, such as the detailed construction and elements, are nothing but specific details provided to assist those of ordinary skill in the art in a comprehensive understanding of the invention, and the present invention is only defined within the scope of the appended claims.

In the entire description of the present invention, the same drawing reference numerals are used for the same elements across various figures. The term “and/or” includes respective items as described and all combinations of one or more of the items.

In the following description of the present invention, the terms used are for explaining embodiments of the present invention, but do not limit the scope of the present invention. In the description, a singular expression may include plural expressions unless specially described. The term “comprises” and/or “comprising” used in the description means that one or more other components, steps, operation and/or existence or addition of elements are not excluded in addition to the described components, steps, operation and/or elements.

Although the terms “first, second, and so forth” are used to describe diverse elements, components and/or sections, such elements, components and/or sections are not limited by the terms. The terms are used only to discriminate an element, component, or section from other elements, components, or sections. Accordingly, in the following description, a first element, first component, or first section may be different from or may be identical to a second element, second component, or second section.

Unless specially defined, all terms (including technical and scientific terms) used in the description could be used as meanings commonly understood by those ordinary skilled in the art to which the present invention belongs. In addition, terms that are generally used but are not defined in the dictionary are not interpreted ideally or excessively unless they have been clearly and specially defined.

Hereinafter, with reference to FIGS. 2 to 5, an address generator for each layer according to an embodiment of the present invention will be described.

FIG. 2 is a diagram explaining a hybrid partition. FIG. 3 is a configuration diagram explaining an address generator for each layer according to an embodiment of the present invention. FIG. 4 is a diagram explaining a bit position table, and FIG. 5 is a diagram explaining an address position table.

First, referring to FIG. 2 which conceptually illustrates a hybrid-partitioned TCAM (Ternary Content Addressable Memory), a TCAM is divided into n vertical partitions and m horizontal partitions, and respective partitions HP11, HP12, …, and HP1n, which belong to horizontal partitions, may constitute one layer. For example, the partitions HP11, HP12, …, and HP1n, which belong to the first horizontal partitions, may constitute a first layer (layer 1), and the partitions HP21, HP22, …, and HP2n, which belong to the second horizontal partitions, may constitute a second layer (layer 2). In the same manner, the partitions HPm1, HPm2, …, and HPmn, which belong to the m-th horizontal partitions, may constitute an m-th layer (layer m).

The address generator for each layer according to an embodiment of the present invention receives an input word W, and if the input word exists on the layer, it returns the address, while if the input word does not exist on the layer, it does not return the address. Specifically, the address generator that belongs to the first layer (layer 1) receives the input word W, and if the input word W exists on the first layer (layer 1), it returns the address, while if the input word W does not exist on the first layer, it does not return the address. The address generator that belongs to the second layer (layer 2) receives the input word W, and if the input word W exists on the second layer (layer 2), it returns the address, while if the input word W does not exist on the second layer, it does not return the address. Accordingly, if m layers exist as illustrated in FIG. 2, m address generators for each layer exist.

Referring to FIG. 3, the address generator 100 for each layer according to an embodiment of the present invention includes n bit position tables (BPT) 10, a first AND operation unit 20, n address position table address generators (APTAG) 30, n address position tables (APT) 40, a second AND operation unit 50, and a first encoder 60.

The bit position table 10 receives input sub-words each of which is composed of w bits, and outputs bit position data of addresses indicated by (w-b) bits of the sub-words, last index data composed of (w+1) bits, and bit values indicated by b bits of the sub-words among the bit position data. Specifically, if the input word composed of w bits is divided into n input sub-words each of which is composed of w bits, the bit position table 10 receives an input sub-word composed of w bits, and outputs bit position data of addresses indicated by (w-b) bits of the sub-word, last index data composed of (w+1) bits, and bit values indicated by b bits of the sub-word among the bit position data.

Here, n may be equal to the number of vertical partitions as illustrated in FIG. 2. That is, if two vertical partitions exist, the address generator for each layer according to an embodiment of the present invention includes two bit position tables 10, and each bit position table 10 receives the input sub-word composed of w bits (here, W=2w), and outputs the bit position data of the address indicated by (w-b) bits of the sub-word, the last index data composed of (w+1) bits, and the bit value indicated by b bits of the sub-word among the bit position data.

Next, referring to FIG. 4, the bit position table includes 2^(w-b) bit position table addresses composed of (w-b) bits, and each address includes the bit position data composed of 2^b bits, and the last index data composed of (w+1) bits.

Here, if the input sub-word exists, each bit of the bit position data may be “1”, while if the input sub-word does not exist, each bit of the bit position data may be “0”. In addition, the last index data may be a value that is obtained by subtracting “1” from the number of bits whose bit value is “1” among the bit position data of the address that precedes the indicated address.

On the other hand, “b” is a bit position index (BPI), and may be the number of lower bits of the input sub-word composed of w bits. That is, for example, if the input sub-word is “1000”, “w” becomes w=4, and at this time, if two lower bits (b=2) is the bit position index, the two upper bits “10” may mean the bit position table address of the bit position table 10 and the two lower bits “00” may be used to indicate the bit value having the index of “00” among the bit position data of the address “10” of the bit position table. This will be described in more detail when the operation of the address generator according to an embodiment of the present invention is described later.

Referring again to FIG. 3, the first AND operation unit 20 receives n bit values (“1” as illustrated in FIG. 3) from the n bit position tables 10, performs an AND operation thereof, and outputs an enable signal (Enable signal in FIG. 3) for enabling the n address generators 30. Here, since the bit values of the respective bit position data is “1” when the input sub-word exists in the respective bit position table 10, the first AND operation unit 20 may not output the enable signal in the case where even one bit value is “0”. This is because there is no reason for further performing the search if the corresponding input word does not exist in all of the horizontal partitions.

The address generator 30 is a unit that generates addresses of the address position table 40, and if it is enabled by an enable signal received from the first AND operation unit 20, it receives the bit position data and the last index data from the bit position table 10, and outputs address data of the address position table 40 which is obtained by adding the number of bits whose value is “1” among the bit position data and the last index data. Here, the address generator for each layer according to an embodiment of the present invention includes n address generators 30, which is equal to the number of bit position tables 10 as described above.

The address position table 40 receives the address data (APTA in FIG. 3), and outputs second address position data (K-bit row in FIG. 3) composed of K bits. Specifically, the address position table 40 receives the address data (APTA in FIG. 3) from the address generator 30, and outputs the address position data composed of K bits, which is in the address indicated by the address data. On the other hand, the address generator for each layer according to an embodiment of the present invention includes n address position tables 40, which is equal to the number of bit position tables 10 as described above.

Next, referring to FIG. 5, the address position table includes 2^w addresses at maximum, and each address includes the address position data composed of K bits. Here, the address position data may be “1” if the input sub-word exists, and may be “0” if the input sub-word does not exist.

On the other hand, the bit position tables 10 and the address position tables 40 of the address generator for each layer according to an embodiment of the present invention may be stored in a memory. Specifically, the bit position tables 10 and the address position tables 40 of the address generator for each layer according to an embodiment of the present invention may be stored in an SRAM. By returning the address values with respect to the input word using the n bit position tables 10 and address position tables 40 stored in the SRAM, the cost can be reduced in comparison to a case in which the TCAM is actually formed to return the address values. That is, by returning the addresses of the input words using the bit position tables 10 and address position tables 40 stored in the SRAM rather than forming the TCAM, the TCAM address return function can be performed at low cost.

Referring again to FIG. 3, the second AND operation unit 50 receives n address position data (K-bit row in FIG. 3) composed of k bits, performs an AND operation thereof, and outputs a first matching address (Matching Location in FIG. 3). Specifically, the second AND operation unit 50 receives n address position data composed of k bits from the n address position tables 40, performs the AND operation thereof, and then outputs an index value of bits of which the resultant value is “1”. One or more index value may be output, and in this case, the second AND operation unit 50 outputs all the indexes to the first matching address.

The first encoder 60 receives the first matching address (Matching Location in FIG. 3), and outputs a second matching address (Potential Matching Address (PMA) in FIG. 3). Specifically, the first encoder 60 receives the first matching address from the second AND operation unit 50, and outputs the smallest index value among them as the second matching address. Here, since the first encoder exists for each layer, it may be a local priority encoder (LPE).

Next, referring to FIG. 6, an address generator according to an embodiment of the present invention will be described.

FIG. 6 is a configuration diagram explaining an address generator according to an embodiment of the present invention.

Referring to FIG. 6, the address generator 200 includes m address generators 100 for each layer and a second encoder 110.

The number of address generators 100 for each layer may be m that is as many as the number of horizontal partitions. If the input word composed of W bits is divided into n input sub-words composed of w bits, the address generator 100 for each layer receives the respective input sub-words, and outputs a second matching address PMA for each layer.

The second encoder 110 receives the m second matching addresses PMA from the m address generators 100 for each layer, and outputs a third matching address MA. Specifically, the second encoder 110 receives the m second matching addresses PMA from the address generators 100 for each layer, and outputs the smallest index value among them as the third matching address. Here, since only one second encoder exists, it may be a global priority encoder (GPE).

In the case of using the address generator according to an embodiment of the present invention, rather than forming the TCAM and returning the address of the input word by searching the whole TCAM, only the plurality or tables stored in the SRAM is used, and thus the TCAM address return function can be performed at lower cost.

Next, with reference to FIGS. 7 to 13, the operation of the address generator according to an embodiment of the present invention will be described.

FIG. 7 is a diagram illustrating an example of a TCAM, and FIG. 8 is a diagram illustrating the performing of hybrid partitions with respect to the TCAM of FIG. 7. FIGS. 9 to 12 are diagrams illustrating bit position tables and address position tables that can perform the TCAM function. FIG. 13 is a diagram explaining the operation of an address generator according to an embodiment of the present invention.

First, if it is assumed that the TCAM as illustrated in FIG. 7 exists, the TCAM can return the address value in which the input word exists with respect to the input word. For example, the TCAM as illustrated in FIG. 7 can return the corresponding address value of “1” with respect to the input word of “00010010”.

Now, referring to FIGS. 8 to 13, the operation of the address generator according to an embodiment of the present invention, which can perform the same function at low cost using the bit position tables and the address position tables stored in the SRAM, will be described.

First, the TCAM of FIG. 7 may be hybrid-partitioned as illustrated in FIG. 8. In this case, m=4, n=2, and k=4. That is, four layers are provided, and each layer includes four rows, and each layer has the address generator for each layer. In this case, since the address generator for each layer is vertically partitioned into two, it can include two bit position tables (10 in FIG. 3), a first AND operation unit (20 in FIG. 3), two address generators (30 in FIG. 3), two address position tables (40 in FIG. 3), a second AND operation unit (50 in FIG. 3), and a first encoder (60 in FIG. 3). The bit position table and the address position table for each layer are illustrated in FIGS. 9 to 12.

Now, referring to FIG. 13, if it is assumed that “00010010” is provided as the input word (W in FIG. 6) as described above, it can be provided to the address generators for each layer of the first to fourth layers (Layer 1 to Layer 4 in FIG. 6) as an input value as illustrated in FIG. 6.

First, referring to FIG. 13, the operation of the address generator of the first layer (Layer 1) will be described. The input word “00010010” is divided into two sub-words “0001” and “0010”, and the divided sub-words are provided to the first bit position table BPT1 and the second bit position table BPT2, respectively. Here, if it is assumed that the bit position index b is 2, two upper bits “00” of “0001” means the bit position table address BPTA of the first bit position table BPT1, and two lower bits “01” means the bit position index BPI. Also, two upper bits “00” of “0010” means the bit position table address BPTA of the second bit position table BPT2, and two lower bits “10” means the bit position index BPI.

Now, referring to FIGS. 9 and 13, it can be recognized that if the BPTA of the BPT1 is “00” and the BPI is “01”, the bit value of the bit position data is “1”. Accordingly, it can be recognized that “0001” exists in the first vertical partition of the first layer (Layer 1). Also, it can be recognized that if the BPTA of the BPT2 is “00” and the BPI is “01”, the bit value of the bit position data is “1”. Accordingly, it can be recognized that “0001” exists in the second vertical partition of the first layer (Layer 1). Accordingly, since the bit values of the bit position data output from the BPT1 and BPT2 are “1” in all, the first AND operation unit (20 in FIG. 3) provides the enable output signal (Enable Signal in FIG. 3) to the first and second address generators (30 in FIG. 3).

The first address generator, as illustrated in FIG. 13, receives “1100” from the BPT1 as the bit position data (2^b), and “-1” as the last index data, and thus can output (-1+2=1) to the address data APTA. Also, the second address generator, as illustrated in FIG. 13, receives “0010” from the BPT2 as the bit position data (2^b), and “-1” as the last index data, and thus can output (-1+1=0) to the address data APTA.

The address position table APT1 receives “1” as the address data, and thus can output “0100” that is four-bit (k=4) data stored in the corresponding address as the address position data (K-bit row in FIG. 3). Also, the address position table APT2 receives “0” as the address data, and thus can output “0100” that is four-bit data stored in the corresponding address as the second address position data (K-bit row in FIG. 3).

The second AND operation unit (50 in FIG. 3) performs an AND operation with respect to such two address position data, and the result of AND operation is “0100”. Accordingly, the second AND operation unit can output “1” as the first matching address (Matching Location in FIG. 3). The first encoder receives this value, and outputs “1”, which is the smallest value among them, to the second matching address.

In the embodiment of the invention, one first matching address is provided. However, if the result of the AND operation performed by the second AND operation unit (50 in FIG. 3) is “1110”, the first matching address may be “0”, “1”, and “2”.

By performing the above-described process with respect to the second layer (Layer 2) to the fourth layer (Layer 4) as illustrated in FIGS. 10 to 12, the input word “00010010” does not exist in the second to fourth layers, and thus the second matching address is not output.

Last, since there is not the second matching address output from the second to fourth layers, the second encoder (110 in FIG. 6) can output “1”, which is the smallest second matching address output from the first layer, as the third matching address. It can be recognized that this value is equal to “1” that is the returned address value through providing of the input word “00010010” to the TCAM as illustrated in FIG. 7.

Although preferred embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

The present invention can be applied to electronic industry using memories, but the application of the present invention is not limited thereto.

Claims

An address generator for each layer comprising:

n bit position tables receiving n input sub-words each of which is composed of w bits, and outputting bit position data of addresses indicated by (w-b) bits of the respective sub-words, last index data, and bit values indicated by b bits of the sub-words among the bit position data;

a first AND operation unit receiving and performing an AND operation of the n bit values and outputting n enable signals;

n address generators receiving the bit position data, the last index data, and the enable signals, and outputting address data;

n address position tables receiving the address data and outputting address position data of the addresses indicated by the address data; and

a second AND operation unit receiving and performing an AND operation of the n address position data, and outputting first matching addresses.
The address generator of claim 1, wherein the bit position tables and the address position tables are stored in a memory.
The address generator of claim 2, wherein the memory includes an SRAM.
The address generator of claim 1, wherein the bit position table includes 2^(w-b) addresses composed of (w-b) bits, and

the address includes the bit position data composed of 2^b bits and the last index data composed of (w+1) bits.
The address generator of claim 1, wherein a bit value that each bit of the bit position data can possess is either “0” or “1”, and

the address generator outputs the address data by adding the number of bits of which the bit value is “1” among the bit position data and the last index data.
The address generator of claim 1, wherein the address position table includes 2^w addresses composed of w bits, and

each address includes the address position data composed of k bits.
The address generator of claim 1, further comprising a first encoder receiving the first matching address and outputting a second matching address.
The address generator of claim 1, wherein the first encoder outputs the first matching address that is the smallest address among the first matching addresses as the second matching address.
An address generator comprising:

m address generators for respective layers recited in any one of claims 1 to 8; and

a second encoder receiving the m first or second matching addresses from the m address generators for the respective layers, and outputting third matching addresses.
The address generator of claim 9, wherein the second encoder outputs the first or second matching address that is the smallest address among the m first or second matching addresses as the third matching address.