WO2011058870A1

WO2011058870A1 - Group-iii nitride crystal substrate, group-iii nitride crystal substrate with epitaxial layer, semiconductor device and method of manufacturing thereof

Info

Publication number: WO2011058870A1
Application number: PCT/JP2010/068840
Authority: WO
Inventors: 恵二石橋; 祐介善積
Original assignee: 住友電気工業株式会社
Priority date: 2009-11-13
Filing date: 2010-10-25
Publication date: 2011-05-19
Also published as: JP2011108720A

Abstract

Disclosed is a group-III nitride crystal substrate, wherein interstices between specified parallel crystal lattice planes that are obtained from x-ray diffraction measurement that changes the depth of x-ray penetration from the primary plane (1s) of the crystal substrate while satisfying the x-ray diffraction conditions of an arbitrary specified parallel crystal lattice plane of a group-III nitride crystal substrate (1) are such that uniform distortion of the surface layer of the crystal substrate, as denoted by the value of |d₁ - d₂|/d₂ that is derived from the interstice d₁ at x-ray penetration depth of 0.3μm and the interstice d₂ at x-ray penetration depth of 5μm is 1.9x10^-3 or less, and the lattice bearing of the primary plane (1s) inclines between 10 and 81 degrees inclusive from the plane (1c) of either the (0001) plane or the (000-1) plane of the crystal substrate in the <11-20> direction. Thus is provided a group-III nitride crystal substrate, a group-III nitride crystal substrate with epitaxial layer, and a semiconductor device and a method of manufacturing same, which are suitable for manufacturing light emitting devices wherein blueshift in emitted light is alleviated.

Description

Group III nitride crystal substrate, group III nitride crystal substrate with epi layer, and semiconductor device and method for manufacturing the same

The present invention relates to a group III nitride crystal substrate, a group III nitride crystal substrate with an epi layer, and a semiconductor device and a method for manufacturing the same, and particularly, preferably used as a substrate for epitaxial crystal growth of a semiconductor layer in manufacturing a semiconductor device. Group III nitride crystal substrate.

As is well known, various semiconductor devices using nitride semiconductor crystals (for example, group III nitride semiconductor crystals) have been produced in recent years. As typical examples of such semiconductor devices, nitride semiconductor light emitting devices (for example, Group III nitride semiconductor light-emitting devices) have been manufactured.

In the manufacture of a nitride semiconductor device, generally, a plurality of nitride semiconductor layers (for example, group III nitride semiconductor layers) are epitaxially grown on a substrate. The crystal quality of the epitaxially grown nitride semiconductor layer is affected by the state of the surface layer of the substrate used for the epitaxial growth, and affects the performance of the semiconductor device including the nitride semiconductor layer. Therefore, when a nitride semiconductor crystal is used as such a substrate, it is desirable that at least the main surface of the substrate serving as the base for epitaxial growth does not contain distortion and is smooth.

That is, the main surface of the nitride semiconductor substrate used for epitaxial growth is generally subjected to smoothing processing and distortion removal processing. In this case, the gallium nitride semiconductor is relatively hard among the compound semiconductors, and the surface smoothing process is not easy, and the distortion removing process after the smoothing process is not easy.

In US Pat. No. 6,596,079 (Patent Document 1), when a substrate is produced from an (AlGaIn) N bulk crystal grown by vapor phase epitaxy on an (AlGaIn) N seed crystal, the surface of the substrate polished mechanically is used. A method of forming a substrate surface having an RMS (root mean square) surface roughness of 1 nm or less by removing surface damage by performing CMP (Chemical Mechanical Polishing), etching or the like on the substrate is disclosed. US Pat. No. 6,488,767 (Patent Document 2) discloses an Al _x Ga _y In _z N (0 <y ≦ 1, x + y + z = 1) substrate having an RMS surface roughness of 0.15 nm by CMP treatment. The CMP treating agent includes Al ₂ O ₃ abrasive grains, SiO ₂ abrasive grains, a pH adjuster, and an oxidizing agent.

Conventionally, as described above, a GaN substrate having a substrate surface finished by removing a work-affected layer during mechanical polishing is obtained by mechanically polishing a GaN crystal and then performing CMP treatment or dry etching. However, the CMP process has a low processing speed and has a problem in cost and productivity. In dry etching, there is a problem of surface roughness.

That is, the finishing method by CMP of the Si substrate and the polishing agent in that method are not suitable for a hard nitride semiconductor substrate, and slow the removal rate of the surface layer. In particular, GaN is chemically stable and difficult to perform wet etching, so that CMP processing is not easy. Further, although the surface of the nitride semiconductor can be removed by dry etching, there is no effect of flattening the surface in the horizontal direction, so that surface smoothing cannot be obtained.

Further, as described above, in order to epitaxially grow a good crystalline compound semiconductor layer on the main surface of the substrate, it is necessary to use a substrate surface having a surface layer with a good crystal quality with less processing damage and less distortion. is necessary. However, the crystal quality of the surface layer required on the main surface of the substrate is not clear.

Therefore, in Japanese Patent Application Laid-Open No. 2007-005526 (Patent Document 3), a nitride crystal substrate and a semiconductor device using the substrate are subjected to CMP under predetermined conditions after mechanically polishing a GaN crystal or an AlN crystal, Nitride in which at least one of uniform strain, non-uniform strain and plane orientation deviation of crystal surface layer evaluated by X-ray diffraction measurement changing X-ray penetration depth from the surface of the crystal is within a predetermined range It has been proposed that a crystal substrate is suitable for the manufacture of semiconductor devices.

US Pat. No. 6,596,079 US Pat. No. 6,488,767 JP 2007-005526 A

Here, the substrates exemplified in the above-mentioned US Pat. No. 6,596,079 (Patent Document 1), US Pat. No. 6,488,767 (Patent Document 2) and JP-A-2007-005526 (Patent Document 3) are as follows: These are hexagonal wurtzite group III nitride crystals, and their main surface is the (0001) plane. For this reason, in a light-emitting device that is a semiconductor device in which at least one semiconductor layer epitaxially grown on the main surface of the crystal substrate is formed, the main surface of the semiconductor layer is also the (0001) plane, and the (0001) plane is Since it is a polar surface whose polarity changes in the normal direction of the surface, the blue confinement of emission due to the increase in current injection amount increases due to the quantum confined Stark effect caused by piezo polarization due to such polarity, and the emission intensity decreases.

On the other hand, in order to manufacture a light emitting device in which emission blue shift is suppressed, the polarity of the main surface of the substrate used for manufacturing the light emitting device is reduced, that is, the main surface of the substrate is a surface other than the (0001) plane. It is necessary to.

However, regarding the substrate suitable for manufacturing a light emitting device in which the blue shift of light emission is suppressed, the plane orientation of the main surface, the surface roughness of the main surface, the crystallinity of the surface layer, etc. are completely unknown.

Accordingly, the present invention provides a group III nitride crystal substrate, a group III nitride crystal substrate with an epi layer, a semiconductor device, and a method for manufacturing the same suitable for manufacturing a light emitting device in which blue shift of light emission is suppressed. Objective.

The group III nitride crystal substrate according to an aspect of the present invention changes the X-ray penetration depth from the main surface of the crystal substrate while satisfying the X-ray diffraction conditions of any specific parallel crystal lattice plane of the group III nitride crystal substrate. Obtained from an interplanar spacing d ₁ at an X-ray penetration depth of 0.3 μm and an interplanar spacing d ₂ at an X-ray penetration depth of 5 μm. The uniform distortion of the surface layer of the crystal substrate represented by the value of d ₁ −d ₂ | / d ₂ is 1.9 × 10 ⁻³ or less, and the plane orientation of the main surface is the (0001) plane of the crystal substrate and It is inclined from 10 ° to 81 ° in any of the (000-1) planes in the <11-20> direction.

The group III nitride crystal substrate according to another aspect of the present invention has an X-ray penetration depth from the main surface of the crystal substrate while satisfying the X-ray diffraction conditions of any specific parallel crystal lattice plane of the group III nitride crystal substrate. In the diffraction intensity profile of the specific parallel crystal lattice plane obtained from the changing X-ray diffraction measurement, the half-value width v ₁ of the diffraction intensity peak at an X-ray penetration depth of 0.3 μm and the diffraction intensity peak at an X-ray penetration depth of 5 μm The non-uniform distortion of the surface layer of the crystal substrate represented by the value of | v ₁ −v ₂ | obtained from the half-value width v _{2 of the} crystal substrate is 130 arcsec or less, and the plane orientation of the main surface is (0001) of the crystal substrate It is inclined at 10 ° or more and 81 ° or less in the <11-20> direction from either the plane or the (000-1) plane.

The group III nitride crystal substrate according to still another aspect of the present invention changes the X-ray penetration depth from the main surface of the crystal substrate with respect to the X-ray diffraction of any specific parallel crystal lattice plane of the group III nitride crystal substrate. Obtained from the half-value width w ₁ of the diffraction intensity peak at an X-ray penetration depth of 0.3 μm and the half-value width w ₂ of the diffraction intensity peak at an X-ray penetration depth of 5 μm in the rocking curve measured in the above | w ₁ The plane orientation deviation of the specific parallel crystal lattice plane of the surface layer of the crystal substrate represented by the value of −w ₂ | is 350 arcsec or less, and the plane orientation of the main surface is (0001) plane and (000-1) of the crystal substrate. ) Tilted in the <11-20> direction from 10 ° to 81 ° from any one of the surfaces.

The main surface of the group III nitride crystal substrate can have a surface roughness Ra of 5 nm or less. Further, the main surface can have a surface roughness Ry of 50 nm or less. Further, the plane orientation of the main surface is {11-22} plane, {22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {11-2-2} plane, { The tilt angle is 0 ° or more and less than 0.1 ° with respect to any one of the 22-4-3} plane, the {11-2-1} plane, and the {22-4-1} plane. can do. Further, the plane orientation of the main surface is {11-22} plane, {22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {11-2-2} plane, { It can be inclined from 0.1 ° to 4 ° from any one of the 22-4-3}, {11-2-1}, and {22-4-1} surfaces. Further, the concentration of oxygen present on the main surface can be 2 atomic% or more and 16 atomic% or less. Further, the dislocation density on the main surface can be set to 1 × 10 ⁷ cm ⁻² or less. Further, the group III nitride crystal substrate can have a diameter of 40 mm or more and 150 mm or less.

The group III nitride crystal substrate with an epi layer according to still another aspect of the present invention includes at least one semiconductor layer formed by epitaxial growth on the main surface of the group III nitride crystal substrate.

A semiconductor device according to still another aspect of the present invention includes the above-described group III nitride crystal substrate with an epi layer. About said semiconductor device, the semiconductor layer contained in a group III nitride crystal substrate with an epi layer can contain the light emitting layer which emits light whose peak wavelength is 430 nm or more and 550 nm or less.

According to still another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein an X-ray penetration depth from a main surface of a crystal substrate is set while satisfying an X-ray diffraction condition of an arbitrary specific parallel crystal lattice plane of a group III nitride crystal substrate. In the plane spacing of the specific parallel crystal lattice plane obtained from the changing X-ray diffraction measurement, the plane spacing d ₁ at the X-ray penetration depth of 0.3 μm and the plane spacing d ₂ at the X-ray penetration depth of 5 μm are obtained. The uniform strain of the surface layer of the crystal substrate represented by the value of | d ₁ −d ₂ | / d ₂ is 1.9 × 10 ⁻³ or less, and the plane orientation of the main surface is the (0001) plane of the crystal substrate and A step of preparing a crystal substrate inclined from 10 ° to 81 ° in any of the (000-1) planes in the <11-20> direction, and at least one semiconductor layer on the main surface of the crystal substrate Epi-layered I by epitaxial growth of layers Forming a group II nitride crystal substrate.

According to still another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein an X-ray penetration depth from a main surface of a crystal substrate is set while satisfying an X-ray diffraction condition of an arbitrary specific parallel crystal lattice plane of a group III nitride crystal substrate. In the diffraction intensity profile of the specific parallel crystal lattice plane obtained from the changing X-ray diffraction measurement, the half-value width v ₁ of the diffraction intensity peak at an X-ray penetration depth of 0.3 μm and the diffraction intensity peak at an X-ray penetration depth of 5 μm The non-uniform distortion of the surface layer of the crystal substrate expressed by the value of | v ₁ −v ₂ | obtained from the half-value width v _{2 of the} crystal substrate is 130 arcsec or less, and the plane orientation of the main surface is the (0001) plane of the crystal substrate And a step of preparing a crystal substrate inclined from 10 ° to 81 ° in the <11-20> direction from any one of the (000-1) planes, and at least one layer on the main surface of the crystal substrate semiconductor The and forming a group III nitride crystal substrate with an epitaxial layer by epitaxial growth, a.

According to still another aspect of the present invention, there is provided a method for manufacturing a semiconductor device by changing an X-ray penetration depth from a main surface of a crystal substrate with respect to X-ray diffraction of an arbitrary specific parallel crystal lattice plane of a group III nitride crystal substrate. In the measured rocking curve, obtained from the half width w ₁ of the diffraction intensity peak at an X-ray penetration depth of 0.3 μm and the half width w ₂ of the diffraction intensity peak at an X-ray penetration depth of 5 μm | w ₁ − The plane orientation deviation of the specific parallel crystal lattice plane of the surface layer of the crystal substrate represented by the value of w ₂ | is 350 arcsec or less, and the plane orientation of the main surface is the (0001) plane and (000-1) plane of the crystal substrate And a step of preparing a crystal substrate inclined at 10 ° or more and 81 ° or less in the <11-20> direction from any of the above surfaces, and epitaxially growing at least one semiconductor layer on the main surface of the crystal substrate And forming a group III nitride crystal substrate with an epitaxial layer by a.

In the step of forming a group III nitride crystal substrate with an epi layer in the method for manufacturing a semiconductor device, the semiconductor layer includes a light emitting layer, and the light emitting layer emits light having a peak wavelength of 430 nm or more and 550 nm or less. can do.

ADVANTAGE OF THE INVENTION According to this invention, the group III nitride crystal substrate suitable for manufacture of the light-emitting device with which the blue shift of light was suppressed and emitted light intensity increased, the group III nitride crystal substrate with an epi layer, a semiconductor device, and its manufacturing method Can be provided.

It is a schematic sectional drawing which shows the state of the crystal | crystallization of the depth direction from the main surface of a group III nitride crystal substrate. It is the schematic which shows the measurement axis and measurement angle in the X-ray diffraction method used for this invention. It is the schematic which shows an example of the uniform distortion of the crystal lattice of a group III nitride crystal substrate. FIG. 3B is a schematic diagram showing the spacing between specific parallel crystal lattice planes in the diffraction intensity profile of the X-ray diffraction method related to the uniform strain of the crystal lattice of the group III nitride crystal substrate of FIG. 3A. It is the schematic which shows an example of the nonuniform distortion of the crystal lattice of a group III nitride crystal substrate. It is the schematic which shows the half value width of the diffraction intensity peak in the diffraction intensity profile of the X-ray diffraction regarding the nonuniform distortion of the crystal lattice of the group III nitride crystal substrate of FIG. 4A. It is the schematic which shows an example of the plane orientation shift | offset | difference of the specific parallel crystal lattice plane of a group III nitride crystal substrate. It is the schematic which shows the half value width of the diffraction intensity peak in the rocking curve of X-ray diffraction regarding the plane orientation shift | offset | difference of the specific parallel crystal lattice plane of the group III nitride crystal substrate of FIG. 5A. It is the schematic which shows an example of the group III nitride crystal substrate concerning this invention. FIG. 6 is a schematic diagram showing an example of the inclination of the main surface in the <11-20> direction from the (0001) plane of the main surface in the group III nitride crystal substrate according to the present invention. FIG. 6 is a schematic view showing another example of the inclination in the <11-20> direction from the (0001) plane of the main surface in the group III nitride crystal substrate according to the present invention. FIG. 6 is a schematic view showing still another example of the inclination in the <11-20> direction from the (0001) plane of the main surface in the group III nitride crystal substrate according to the present invention. FIG. 6 is a schematic view showing still another example of the inclination in the <11-20> direction from the (0001) plane of the main surface in the group III nitride crystal substrate according to the present invention. FIG. 5 is a schematic diagram showing an example of the inclination of the main surface in the <11-20> direction from the (000-1) plane of the main surface in the group III nitride crystal substrate according to the present invention. FIG. 6 is a schematic view showing another example of the inclination of the main surface in the <11-20> direction from the (000-1) plane of the main surface in the group III nitride crystal substrate according to the present invention. FIG. 5 is a schematic diagram showing still another example of the inclination of the main surface in the <11-20> direction from the (000-1) plane of the main surface in the group III nitride crystal substrate according to the present invention. FIG. 5 is a schematic diagram showing still another example of the inclination of the main surface in the <11-20> direction from the (000-1) plane of the main surface in the group III nitride crystal substrate according to the present invention. It is a schematic sectional drawing which shows an example of the group III nitride crystal substrate with an epi layer concerning this invention. It is a schematic sectional drawing which shows an example of the semiconductor device concerning this invention.

[Group III nitride crystal substrate]
In crystal geometry, a display (mirror display) such as (hkl) or (hkil) is used to indicate the plane orientation of the crystal plane. The plane orientation of the crystal plane in a hexagonal crystal such as a group III nitride crystal forming the group III nitride crystal substrate is represented by (hkil). Here, h, k, i and l are integers called Miller indices and have a relationship of i = − (h + k). The plane having the plane orientation (hkil) is referred to as the (hkil) plane. In the present specification, the individual plane orientation is represented by (hkil), and the generic plane orientation including (hkil) and the plane orientation equivalent to the crystal geometry is represented by {hkil}. Further, each direction is represented by [hkil], and [hkil] and a direction including a crystal geometrically equivalent direction is represented by <hkil>. Negative indices are generally expressed by adding “-” (bar) on the number representing the index in the crystal geometry, but in this specification, before the number representing the index. Represented with a negative sign (-).

Here, the group III nitride crystal has polarity in the <0001> direction because the group III element atomic plane and the nitrogen atomic plane are alternately arranged in the <0001> direction. In the present application, the crystal axes are set so that the group III element atomic plane is the (0001) plane and the nitrogen atomic plane is the (000-1) plane.

In the present invention, by using the X-ray diffraction method, the crystallinity in the surface layer of the group III nitride crystal substrate can be directly evaluated without destroying the crystal. Here, the evaluation of crystallinity means evaluating the degree of crystal distortion, and specifically, evaluating the degree of crystal lattice distortion and crystal plane misalignment. That means. The crystal lattice distortion includes a uniform strain in which the crystal lattice is uniformly distorted and a non-uniform strain in which the crystal lattice is distorted non-uniformly. The crystal orientation deviation of the crystal lattice plane refers to the magnitude of variation in which the plane orientation of the lattice plane of each crystal lattice is deviated from the average orientation of the plane orientation of the crystal plane of the entire crystal lattice.

As shown in FIG. 1, a group III nitride crystal substrate 1 is formed by cutting a group III nitride crystal from a main surface 1s of the crystal substrate by processing such as cutting, grinding or polishing from a group III nitride crystal body. At least one of a uniform distortion, a non-uniform distortion and a plane orientation deviation of the crystal lattice occurs (FIG. 1 shows a case where a uniform distortion, a non-uniform distortion and a plane orientation deviation of the crystal lattice occur in the surface layer 1p. ). In addition, the surface adjacent layer 1q adjacent to the surface layer 1p may have at least one of a uniform distortion of the crystal lattice, a non-uniform distortion of the crystal lattice, and a plane orientation shift of the crystal lattice (FIG. 1 shows the surface adjacent layer 1q). This shows the case where the crystal lattice is misaligned.) Further, the inner layer 1r inside the surface adjacent layer 1q is considered to have the original crystal structure of the crystal. The state and thickness of the surface layer 1p and the surface adjacent layer 1q vary depending on the grinding or polishing method and degree in the surface processing.

Here, the crystallinity of the surface layer can be directly and reliably evaluated by evaluating the uniform strain, nonuniform strain and / or plane orientation deviation of the crystal lattice in the depth direction from the main surface of the crystal substrate. it can.

In the present invention, the X-ray diffraction measurement for evaluating the crystallinity of the surface layer of the group III nitride crystal substrate is performed while satisfying the X-ray diffraction conditions of any specific parallel crystal lattice plane of the group III nitride crystal substrate. The X-ray penetration depth from the main surface is changed.

Here, referring to FIG. 1 and FIG. 2, the diffraction condition of an arbitrary specific parallel crystal lattice plane 1d refers to a condition in which X-rays are diffracted by the arbitrarily specified parallel crystal lattice plane, and the Bragg angle Is X, the wavelength of X-ray is λ, and the interplanar spacing of the specific parallel crystal lattice plane 1d is d, X-rays are diffracted by the parallel crystal lattice plane satisfying Bragg's conditional expression (2dsinθ = nλ, where n is an integer). Is done.

Also, the X-ray penetration depth refers to the distance in the vertical depth direction from the main surface 1s of the crystal substrate when the intensity of the incident X-ray is 1 / e (e is the base of natural logarithm). Referring to FIG. 2, this X-ray penetration depth T corresponds to the X-ray absorption coefficient μ of group III nitride crystal substrate 1, the tilt angle χ of main surface 1s of the crystal substrate, and the main surface 1s of crystal substrate. The X-ray incident angle ω and the Bragg angle θ are expressed as in Expression (1). The χ axis 21 is in the plane formed by the incident X-ray 11 and the outgoing X-ray 12, and the ω axis 22 (2θ axis) is perpendicular to the plane formed by the incident X-ray 11 and the outgoing X-ray 12. The φ axis 23 is perpendicular to the main surface 1s of the crystal substrate. The rotation angle φ indicates the rotation angle within the main surface 1s of the crystal substrate.

Therefore, by adjusting at least one of the tilt angle χ, the X-ray incident angle ω, and the rotation angle φ so as to satisfy the diffraction condition for the specific parallel crystal lattice plane, the X-ray penetration depth T can be continuously set. Can be changed.

In order to continuously change the X-ray penetration depth T so as to satisfy the diffraction condition on the specific parallel crystal lattice plane 1d, the specific parallel crystal lattice plane 1d and the main surface 1s of the crystal substrate are not parallel. It is necessary. If the specific parallel crystal lattice plane and the main surface of the crystal substrate are parallel, the Bragg angle θ, which is an angle between the specific parallel crystal lattice plane 1d and the incident X-ray 11, and the main surface 1s of the crystal substrate and the incident X-ray 11 The X-ray incident angle ω, which is the angle formed by the above, becomes the same, and the X-ray penetration depth cannot be changed in the specific parallel crystal lattice plane 1d. As described above, the specific parallel crystal lattice plane is not particularly limited except that it is not parallel to the main surface of the crystal substrate, but from the viewpoint of easy evaluation by X-ray diffraction at a desired penetration depth ( 10-10) plane, (10-11) plane, (10-13) plane, (10-15) plane, (11-20) plane, (22-41) plane, (11-21) plane, (11 −22), (11-24), (10-1-1), (10-1-3), (10-1-5), (22-4-1), (11 The (2-1) plane, (11-2-2) plane, (11-2-4) plane, etc. are preferably used.

Here, the X-ray penetration depth is changed to irradiate an arbitrary specific parallel crystal lattice plane of the crystal substrate with X-rays, and the uniform distortion of the crystal lattice is determined from the change in the interplanar spacing in the diffraction intensity profile for the specific parallel crystal lattice plane. The crystal lattice non-uniform distortion is evaluated from the change in the half-value width of the diffraction intensity peak in the diffraction intensity profile, and the plane orientation deviation of the crystal lattice is evaluated from the change in the half-value width of the diffraction intensity peak in the rocking curve.

Referring to FIG. 6, group III nitride crystal substrate 1 according to the present invention has a main surface 1s whose plane orientation is either the (0001) plane or the (000-1) plane of the crystal substrate. It is inclined at an inclination angle α of 10 ° or more and 81 ° or less in the <11-20> direction from 1c. The inclination angle α from the surface 1c of either the (0001) plane or the (000-1) plane to the <11-20> direction is 10 ° or more when the plane orientation of the main surface of the group III nitride crystal substrate is In the light emitting device that is a semiconductor device including at least one semiconductor layer epitaxially grown on the main surface of the crystal substrate, the piezoelectric polarization of the light emitting layer in the semiconductor layer is suppressed, and the quantum confined Stark effect is reduced. Since recombination of holes and electrons is facilitated and the light emission transition probability is increased, the blue shift of the light emitting device is reduced and the integrated intensity of light emission is increased. The tilt angle α in the <11-20> direction from the surface 1c of any one of the (0001) plane and the (000-1) plane is 81 ° or less when the plane orientation of the main surface of the group III nitride crystal substrate is In a light-emitting device that is a semiconductor device including at least one semiconductor layer epitaxially grown on the main surface of the crystal substrate, the dislocation density of the light-emitting layer in the semiconductor layer is reduced, so that the integrated intensity of light emission can be increased. it can. From this point of view, the inclination angle α of the plane orientation of the main surface in the <11-20> direction from any one of the (0001) plane and the (000-1) plane of the group III nitride crystal substrate is 16 °. It is preferably 81 ° or less, more preferably 39 ° or more and 80 ° or less, and further preferably 63 ° or more and 79 ° or less. Here, the inclination angle α of the main surface in the <11-20> direction from either the (0001) plane or the (000-1) plane can be measured by an X-ray diffraction method or the like.

(Embodiment 1)
With reference to FIGS. 1, 2, 3A and B, and FIG. 6, a group III nitride crystal substrate 1 according to an embodiment of the present invention is an arbitrary parallel crystal lattice of group III nitride crystal substrate 1. While satisfying the X-ray diffraction conditions of the surface 1d (referring to the specific parallel crystal lattice plane 1d formed by the specific parallel

crystal lattice planes

31d, 32d, and 33d of each crystal lattice, the same applies hereinafter), The interplanar spacing d ₁ at the X-ray penetration depth of 0.3 μm and the X-ray of 5 μm in the plane spacing of the specific parallel crystal lattice plane 1d obtained from the X-ray diffraction measurement changing the X-ray penetration depth from the main surface 1s. The uniform strain of the surface layer 1p of the crystal substrate expressed by the value of | d ₁ −d ₂ | / d ₂ obtained from the interplanar spacing d ₂ at the penetration depth is 1.9 × 10 ⁻³ or less, The plane orientation of the surface 1s is such that the (0001) plane of the crystal substrate and It is inclined in the <11-20> direction 10 ° or more 81 ° or less from any surface 1c of (000-1) plane.

The group III nitride crystal substrate 1 of the present embodiment has a uniform distortion of the surface layer 1p of 1.9 × 10 ⁻³ or less and any one of the (0001) plane and the (000-1) plane The inclination angle α of the surface orientation of the main surface 1s from the surface 1c to the <10-10> direction is 10 ° or more and 81 ° or less, so that at least one semiconductor layer is epitaxially grown on the main surface 1s of the crystal substrate. The blue shift of a light-emitting device that is a semiconductor device including a layer can be reduced and the integrated intensity of light emission can be increased. From this viewpoint, the uniform strain of the surface layer 1p is preferably 1.3 × 10 ⁻³ or less, more preferably 1.1 × 10 ⁻³ or less, further preferably 0.9 × 10 ⁻³ or less, 0.6 × 10 ⁻³ or less is particularly preferable. Here, the uniform strain of the surface layer 1p is preferably as small as possible, and in this application as well, it is reduced to about 0.4 × 10 ⁻³ by adjusting the processing conditions of the main surface of the crystal substrate, as will be described later. ing. Further, the inclination angle α of the surface orientation of the main surface 1s is preferably 16 ° or more and 81 ° or less, more preferably 39 ° or more and 80 ° or less, and further preferably 63 ° or more and 79 ° or less.

Here, referring to FIG. 1, the X-ray penetration depth of 0.3 μm corresponds to the distance from main surface 1s of group III nitride crystal substrate 1 to surface layer 1p, and the X-ray penetration depth of 5 μm is III. This corresponds to the distance from main surface 1s of group nitride crystal substrate 1 to the inside of inner layer 1r. At this time, referring to FIG. 3A, the interplanar spacing d ₂ at the X-ray penetration depth of 5 μm is considered to be the spacing of the specific parallel crystal lattice plane 1d of the group III nitride crystal, but the X-ray penetration depth is 0. The interplanar spacing d ₁ at 3 μm depends on the surface processing of the group III nitride crystal substrate 1 (for example, the tensile stress 30 in the direction parallel to the specific parallel crystal lattice plane 1d). Reflecting the uniform distortion, it takes a value different from the surface spacing d ₂ at the X-ray penetration depth of 5 μm.

In the above case, with reference to FIG. 3B, in the diffraction intensity profile for the specific parallel crystal lattice plane 1d shown in FIG. 3A of the group III nitride crystal substrate, the interplanar spacings d ₁ and X at an X-ray penetration depth of 0.3 μm A surface interval d ₂ at a line penetration depth of 5 μm appears. Accordingly, there is a ratio of the difference between d ₁ and d ₂ for d ₂ | d ₁ -d ₂ | by / d ₂ values, it is possible to represent a uniform strain of the surface layer.

(Embodiment 2)
Referring to FIGS. 1, 2, 4A and B, and FIG. 6, group III nitride crystal substrate 1 according to another embodiment of the present invention is an arbitrary parallel crystal of group III nitride crystal substrate 1. The crystal substrate while satisfying the X-ray diffraction conditions of the lattice plane 1d (referred to as specific parallel crystal lattice planes 1d formed by the specific parallel

crystal lattice planes

41d, 42d, and 43d of each crystal lattice; the same applies hereinafter). In the diffraction intensity profile of the specific parallel crystal lattice plane 1d obtained from the X-ray diffraction measurement changing the X-ray penetration depth from the main surface 1s, the half-value width v of the diffraction intensity peak at the X-ray penetration depth of 0.3 μm _The nonuniform strain of the surface layer 1p of the crystal substrate expressed by the value of | v ₁ −v ₂ | obtained from ₁ and the half-value width v ₂ of the diffraction intensity peak at an X-ray penetration depth of 5 μm is 130 arcsec or less. , The plane orientation of the surface 1s is inclined at from either side 1c of (0001) plane and the (000-1) plane of the crystal substrate <11-20> 81 ° 10 ° or more in a direction less.

The group III nitride crystal substrate 1 of the present embodiment has a nonuniform strain of the surface layer 1p of 130 arcsec or less, and <11 from any one of the (0001) plane and (000-1) plane 1c. A semiconductor device including at least one semiconductor layer epitaxially grown on the main surface 1s of the crystal substrate when the inclination angle α of the plane orientation of the main surface 1s in the −20> direction is 10 ° or more and 81 ° or less As a result, the blue shift of the light emitting device can be reduced and the integrated intensity of light emission can be increased. From this viewpoint, the nonuniform strain of the surface layer 1p is preferably 90 arcsec or less, more preferably 75 arcsec or less, and further preferably 30 arcsec or less. Here, the non-uniform distortion of the surface layer 1p is preferably as small as possible, and in this application as well, it is reduced to 0 arcsec by adjusting the processing conditions of the main surface of the crystal substrate, as will be described later. Further, the inclination angle α of the surface orientation of the main surface 1s is preferably 16 ° or more and 81 ° or less, more preferably 39 ° or more and 80 ° or less, and further preferably 63 ° or more and 79 ° or less.

Here, referring to FIG. 1, the X-ray penetration depth of 0.3 μm corresponds to the distance from main surface 1s of group III nitride crystal substrate 1 to surface layer 1p, and the X-ray penetration depth of 5 μm is III. This corresponds to the distance from main surface 1s of group nitride crystal substrate 1 to the inside of inner layer 1r. At this time, referring to FIG. 4A, the half-value width v ₂ of the diffraction intensity peak at an X-ray penetration depth of 5 μm is considered to be the original half-value width of the group III nitride crystal. The half-value width v ₁ of the diffraction intensity peak at 3 μm is a non-uniform distortion of the crystal lattice of the surface layer 1p due to the influence of the surface processing of the group III nitride crystal substrate 1 (for example, the distance between the crystal lattice planes is d ₃ , D ₄ to d ₅ , and d ₆ are different from each other, taking a value different from the half-value width v ₂ of the diffraction intensity peak at the X-ray penetration depth of 5 μm.

In the above case, referring to FIG. 4B, the half value of the diffraction intensity peak at the X-ray penetration depth of 0.3 μm in the diffraction intensity profile for the specific parallel crystal lattice plane 1d shown in FIG. 4A of the group III nitride crystal substrate. A width v ₁ and a half-value width v ₂ of a diffraction intensity peak at an X-ray penetration depth of 5 μm appear. Therefore, the uneven strain of the surface layer 1p can be expressed by the value of | v ₁ −v ₂ | which is the difference between v ₁ and v ₂ .

(Embodiment 3)
Referring to FIGS. 1, 2, 5 A and B and FIG. 6, group III nitride crystal substrate 1 which is another embodiment of the present invention is an arbitrary parallel crystal of group III nitride crystal substrate 1. The main surface of the crystal substrate with respect to the X-ray diffraction of the lattice plane 1d (referring to the specific parallel crystal lattice plane 1d formed by the specific parallel

crystal lattice planes

51d, 52d, 53d of each crystal lattice; the same applies hereinafter). In the rocking curve measured by changing the X-ray penetration depth from _{1 s} , the half-value width w ₁ of the diffraction intensity peak at an X-ray penetration depth of 0.3 μm and the diffraction intensity peak at an X-ray penetration depth of 5 μm The plane orientation deviation of the specific parallel crystal lattice plane 1d of the surface layer 1p of the crystal substrate represented by the value of | w ₁ −w ₂ | obtained from the half width w ₂ is 350 arcsec or less, and the plane orientation of the main surface 1s Is a crystalline group The (0001) plane and inclined at a (000-1) from any surface 1c of surface <11-20> direction 10 ° or more 81 ° or less.

In the group III nitride crystal substrate 1 of the present embodiment, the surface orientation deviation of the specific parallel crystal lattice plane of the surface layer 1p is 350 arcsec or less, and one of the (0001) plane and the (000-1) plane The inclination angle α of the surface orientation of the main surface 1s from the surface 1c to the <11-20> direction is not less than 10 ° and not more than 81 °, whereby at least one layer epitaxially grown on the main surface 1s of the crystal substrate is formed. The blue shift of a light emitting device that is a semiconductor device including a semiconductor layer can be reduced and the integrated intensity of light emission can be increased. From this viewpoint, the plane orientation deviation of the specific parallel crystal lattice plane of the surface layer 1p is preferably 190 arcsec or less, more preferably 120 arcsec or less, and further preferably 50 arcsec or less. Here, the smaller the plane orientation deviation of the specific parallel crystal lattice plane of the surface layer 1p, the better. In this application as well, it is reduced to 0 arcsec by adjusting the processing conditions of the main surface of the crystal substrate as described later. ing. Further, the inclination angle α of the surface orientation of the main surface 1s is preferably 16 ° or more and 81 ° or less, more preferably 39 ° or more and 80 ° or less, and further preferably 63 ° or more and 79 ° or less.

Here, referring to FIG. 1, the X-ray penetration depth of 0.3 μm corresponds to the distance from main surface 1s of group III nitride crystal substrate 1 to surface layer 1p, and the X-ray penetration depth of 5 μm is III. This corresponds to the distance from main surface 1s of group nitride crystal substrate 1 to the inside of inner layer 1r. At this time, referring to FIG. 5A, the half-value width w ₂ of the diffraction intensity peak at the X-ray penetration depth of 5 μm is considered to be the original half-value width of the group III nitride crystal. The half-value width w ₁ of the diffraction intensity peak at 3 μm is the deviation of the plane orientation of the specific parallel crystal lattice plane of the crystal lattice of the surface layer 1p due to the influence of the surface processing of the group III nitride crystal substrate 1 (for example, the specific crystal lattice Reflecting the parallel

crystal lattice planes

51d, 52d, and 53d having different plane orientations), it takes a value different from the half width w ₂ at the X-ray penetration depth of 5 μm.

In the above case, referring to FIG. 5B, the half-value width of the diffraction intensity peak at the X-ray penetration depth of 0.3 μm in the rocking curve for the specific parallel crystal lattice plane 1d shown in FIG. 5A of the group III nitride crystal substrate w ₁ and the half width w ₂ of the diffraction intensity peak at the X-ray penetration depth of 5 μm appear. Therefore, the plane orientation deviation of the specific parallel crystal lattice plane of the crystal surface layer can be expressed by the value of | w ₁ −w ₂ | which is the difference between w ₁ and w ₂ .

In group III nitride crystal substrate 1 of the first to third embodiments described above, it is preferable that main surface 1s has a surface roughness Ra of 5 nm or less. Here, the surface roughness Ra means the arithmetic average roughness Ra specified in JIS B 0601-1994. Specifically, the surface roughness Ra is 10 μm square as a reference area in the direction of the average surface from the roughness curved surface ( 10 μm × 10 μm = 100 μm ² , the same applies hereinafter), and the absolute value (that is, distance) of deviation from the average surface of the extracted portion to the measurement curved surface is summed and averaged over the reference area. Such surface roughness Ra can be measured by an AFM (atomic force microscope), an optical interference type roughness meter, or the like. By setting the surface roughness Ra of the main surface of the group III nitride crystal substrate to 5 nm or less, a semiconductor layer having a low dislocation density and good crystallinity can be epitaxially grown on the main surface of the group III nitride crystal substrate. Thus, a semiconductor device having good characteristics such as a light emitting device having a high integrated intensity of light emission can be obtained. From this viewpoint, the surface roughness Ra of the main surface of the group III nitride crystal substrate is more preferably 3 nm or less, and further preferably 1 nm or less.

On the other hand, from the viewpoint of enhancing the productivity of the group III nitride crystal substrate and the semiconductor device, the surface roughness Ra of the main surface of the group III nitride crystal substrate is preferably 1 nm or more. Therefore, from the viewpoint of achieving both high quality and high productivity of the group III nitride crystal substrate and the semiconductor device, the surface roughness Ra of the main surface of the group III nitride crystal substrate is preferably 1 nm to 3 nm.

Further, in the group III nitride crystal substrate 1 of the first to third embodiments, the main surface 1s preferably has a surface roughness Ry of 50 nm or less. Here, the surface roughness Ry means the maximum height Ry defined in JIS B 0601-1994. Specifically, the surface roughness Ry is extracted from the roughness curved surface by a 10 μm square as a reference area in the direction of the average surface. This is the sum of the height from the average surface of the extracted portion to the highest peak and the depth to the lowest valley bottom. Such surface roughness Ry can be measured by an AFM (atomic force microscope), an optical interference roughness meter, or the like. By setting the surface roughness Ry of the main surface of the group III nitride crystal substrate to 50 nm or less, a semiconductor layer having a low dislocation density and good crystallinity can be epitaxially grown on the main surface of the group III nitride crystal substrate. Thus, a semiconductor device having good characteristics such as a light emitting device having a high integrated intensity of light emission can be obtained. From such a viewpoint, the surface roughness Ry of the main surface of the group III nitride crystal substrate is more preferably 30 nm or less, and further preferably 10 nm or less. Moreover, 10 nm or more and 30 nm or less are preferable from a viewpoint of making high quality and high productivity compatible.

7 to 14, in the group III nitride crystal substrate 1 of the first to third embodiments, the plane orientation of the main surface 1s is {11-22} plane of the crystal substrate, { 22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {22-4-3} plane, {11-2-1} plane, and {22- It is preferable that the inclination angle β from any one of the 4-1} planes is inclined at 0 ° or more and 4 ° or less.

Here, the plane orientation of the main surface 1s is {11-22} plane, {22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {22- 4-3} plane, {11-2-1} plane, and {22-4-1} plane, the inclination angle β from any plane orientation is substantially parallel with 0 ° or more and less than 0.1 °. The concentration of In (indium) in the well layer in the light emitting layer included in the at least one semiconductor layer epitaxially grown on the main surface 1s can be increased, so that the desired composition can be obtained without lowering the growth temperature. Growth can be achieved and the crystallinity of the well layer can be improved. In a light-emitting device that is a semiconductor device, good emission characteristics can be obtained by reducing the half-value width of an emission peak appearing in an emission spectrum by improving the crystallinity of a well layer.

Also, the plane orientation of the main surface 1s is {11-22} plane, {22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {11-2-2} plane, { Even if the inclination angle β from any one of the 22-4-3}, {11-2-1}, and {22-4-1} planes is 0.1 ° or more and 4 ° or less, The plane orientation of the main surface 1s is {11-22} plane, {22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {22- 4-3}, {11-2-1} plane, and {22-4-1} plane, when the inclination angle β from the plane orientation is substantially parallel to 0 ° or more and less than 0.1 ° As a result, a semiconductor device having good light emission characteristics almost the same as those described above can be obtained. Also, the plane orientation of the main surface 1s is {11-22} plane, {22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {11-2-2} plane, { When the inclination angle β from any one of the 22-4-3} plane, {11-2-1} plane and {22-4-1} plane is 0.1 ° or more and 4 ° or less, growth occurs. Since the morphology of the semiconductor layer (including the light emitting layer) to be improved is improved, the obtained light emitting device (semiconductor device) has good light emitting characteristics.

Referring to FIG. 1, in group III nitride crystal substrate 1 of the first to third embodiments, the concentration of oxygen present on main surface 1s is 2 atomic% or more and 16 atomic% or less. preferable. Here, the oxygen existing on the main surface 1s means oxygen taken in by the main surface 1s being oxidized, oxygen attached to the main surface 1s, and the like. When the concentration of oxygen present on main surface 1s of group III nitride crystal substrate 1 is lower than 2 atomic%, the gap between the crystal substrate in the formed semiconductor device and the semiconductor layer formed by epitaxial growth on the crystal substrate. The interface resistance increases, and the integrated intensity of light emission decreases. When the concentration of oxygen present on the main surface 1s of the crystal substrate is higher than 16 atomic%, the crystallinity of the semiconductor layer epitaxially grown on the main surface of the crystal substrate is lowered, so that the integrated intensity of light emission is lowered. From this viewpoint, the concentration of oxygen present on the main surface 1s is more preferably 3 atomic percent or more and 10 atomic percent or less. Here, the concentration of oxygen present on the main surface is measured by AES (Auger atomic spectroscopy), XPS (X-ray photoelectron spectroscopy), or the like.

That is, from the viewpoint of being able to measure by the above AES and XPS, oxygen present on the main surface 1s in the present invention is taken into the main surface 1s by oxygen adhering to the main surface 1s and oxidation of the crystal substrate. Oxygen which is taken into the region from the main surface to a depth of up to about 10 nm, usually up to about 5 nm.

Referring to FIG. 1, it is preferable that dislocation density on main surface 1s is 1 × 10 ⁷ cm ⁻² or less for group III nitride crystal substrates 1 of the above-described first to third embodiments. When the dislocation density at the main surface of the crystal substrate is higher than 1 × 10 ⁷ cm ⁻² , the crystallinity of the semiconductor layer epitaxially grown on the main surface of the crystal substrate is lowered, so that the integrated intensity of light emission is lowered. From this viewpoint, the dislocation density on the main surface 1s is more preferably 1 × 10 ⁶ cm ⁻² or less, and further preferably 1 × 10 ⁵ cm ⁻² or less. From the viewpoint of increasing cost and efficiency in the production of semiconductor devices, the dislocation density on the main surface 1s is preferably 1 × 10 ² cm ⁻² or more.

From the viewpoint of increasing cost and efficiency in production of semiconductor devices, the diameter of the group III nitride crystal substrate is preferably 40 mm or more, and more preferably 50 mm or more. When the diameter of the substrate is large, the number of devices that can be manufactured from one substrate increases. In order to manufacture a large-diameter substrate, the diameter of the base substrate can be increased, a thick crystal can be grown, cut out at a desired angle, and processed. Further, a plurality of substrates of group III nitride crystals having a small diameter are arranged so that their side surfaces are adjacent to each other, and a group III nitride crystal is grown on the main surface of each of the plurality of substrates. In this case, the group III nitride crystals are bonded to each other and grown as a single crystal, and the obtained group III nitride crystal can be processed into a large-diameter group III nitride crystal substrate.

Also, from the viewpoint of improving shape accuracy such as reducing warpage and thickness distribution, the diameter of the group III nitride crystal substrate is preferably 150 mm or less, and more preferably 100 mm or less.

The impurity (dopant) added to the group III nitride crystal substrate is not particularly limited, but the following are preferably used from the viewpoint of producing a conductive substrate and an insulating substrate. The specific resistance is 5 × 10 ⁻⁵ Ω · cm or more and 0.5 Ω · cm or less (preferably 5 × 10 ⁻⁴ Ω · cm or more and 0.05 Ω · cm or less), and the carrier concentration is 1 × 10 ¹⁶ cm ⁻³ or more and 1 In an n-type conductive substrate within the range of × 10 ²⁰ cm ⁻³ or less (preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less), the crystallinity is maintained and the desired range is maintained. From the viewpoint of obtaining conductivity, the impurity added to the substrate is preferably O or Si. Insulating substrates having a specific resistance in the range of 1 × 10 ⁴ Ω · cm to 1 × 10 ¹¹ Ω · cm (preferably 1 × 10 ⁶ Ω · cm to 1 × 10 ¹⁰ Ω · cm) From the viewpoint of obtaining desired insulation within such a range while maintaining the above, the impurities added to the substrate are preferably C and Fe. Here, the specific resistance of the substrate can be measured by a four-probe method, a two-probe method, or the like. The carrier concentration of the substrate can be measured by a Hall measurement method, a CV measurement method, or the like.

[Method for Producing Group III Nitride Crystal Substrate]
The manufacturing method of the group III nitride crystal substrate of the above-described first to third embodiments is not particularly limited. For example, a step of growing a group III nitride crystal, a group III nitride crystal, By cutting out from a plurality of planes parallel to a plane having an inclination angle α in the <11-20> direction of 10 ° or more and 81 ° or less from either the (0001) plane or the (000-1) plane of the crystal , 0001) and (000-1) planes to form a group III nitride crystal substrate having a main surface with an inclination angle α in the <11-20> direction of 10 ° to 81 ° And processing the main surface of the group III nitride crystal substrate.

(Process for producing Group III nitride crystal)
The production method of the group III nitride crystal is not particularly limited, and includes a vapor phase growth method such as an HVPE (hydride vapor phase growth) method and a sublimation method, a liquid phase growth method such as a flux method and an ammonothermal method. Preferably used. For example, an HVPE method, a flux, an ammonothermal method, or the like is preferably used for manufacturing a GaN crystal, and an HVPE method, a sublimation method, or the like is preferably used for manufacturing an AlN crystal. The HVPE method or the like is preferably used for the production of the AlGaN crystal body and the InGaN crystal body.

In the production of the above group III nitride crystal, there is no particular limitation on the base substrate, but a group III nitride crystal with high crystallinity and small crystal lattice mismatch with the group III nitride crystal is grown. From the point of view, a GaAs substrate, a sapphire substrate, a SiC substrate, or the like is preferably used.

(Group III nitride crystal substrate formation process)
The group III nitride crystal produced as described above has an inclination angle α of 10 to the <11-20> direction from either the (0001) plane or the (000-1) plane of the crystal. There is no particular limitation on the method of cutting with a plurality of surfaces parallel to the surface of not less than ° and not more than 81 °, and various cutting methods such as a wire saw, inner peripheral blade, outer peripheral blade, laser processing, electric discharge processing, and water jet can be used. it can.

(Main surface processing step of group III nitride crystal substrate)
The main surface processing method for flattening the main surface of the group III nitride crystal substrate formed as described above and reducing the work-affected layer is not particularly limited, but both the surface roughness and the work-affected layer are reduced. From the viewpoint of reduction, it is preferable to perform chemical mechanical polishing (CMP) after mechanical processing of either grinding or mechanical polishing. Note that it is not necessary to completely remove the work-affected layer of the group III nitride crystal substrate, and the main surface can be modified by annealing before the semiconductor layer is epitaxially grown. Annealing before the growth of the semiconductor layer rearranges the crystals in the surface layer of the crystal substrate, thereby enabling the epitaxial growth of the semiconductor layer with good crystallinity.

Main surface of group III nitride crystal substrate whose plane orientation is inclined from 10 ° to 81 ° in the <11-20> direction from either the (0001) plane or the (000-1) plane A CMP suitable for efficiently reducing both the surface roughness and the work-affected layer will be described below.

In the slurry used for CMP, the relationship between the pH value X and the oxidation-reduction potential value Y (mV) has the following formulas (2) and (3):
Y ≧ −50X + 1300 (2)
Y ≦ −50X + 1800 (3)
Is preferably satisfied. When Y <−50X + 1300, the polishing rate becomes low, and the mechanical load during CMP increases, so that the surface quality of the group III nitride crystal substrate decreases. If Y> −50X + 1800, the corrosive action on the polishing pad and the polishing apparatus increases, and stable polishing becomes difficult.

Further, from the viewpoint of further improving the polishing rate and improving the surface quality of the group III nitride crystal substrate, the following formula (4)
Y ≧ −50X + 1400 (4)
It is preferable to satisfy this relationship.

In general, acids such as hydrochloric acid, sulfuric acid, and nitric acid, and alkalis such as KOH and NaOH are added to the CMP slurry, but these acids and / or alkali alone oxidize the surface of chemically stable gallium nitride. The effect to do is small. Therefore, it is preferable to further increase the redox potential by adding an oxidizing agent so as to satisfy the relationship of the above formulas (2) and (3) or the above formulas (3) and (4).

The oxidizing agent added to the CMP slurry is not particularly limited, but from the viewpoint of increasing the polishing rate, chlorinated isocyanuric acid such as hypochlorous acid and trichloroisocyanuric acid, and chlorinated isocyanuric acid such as sodium dichloroisocyanurate. Salt, permanganate such as potassium permanganate, dichromate such as potassium dichromate, bromate such as potassium bromate, thiosulfate such as sodium thiosulfate, nitric acid, sulfuric acid, hydrochloric acid, hydrogen peroxide water Ozone and the like are preferably used. In addition, these oxidizing agents may be used independently or may use 2 or more together.

The pH of the CMP slurry is preferably 6 or less or 8 or more. The polishing rate can be increased by bringing an acidic slurry having a pH of 6 or less or a basic slurry having a pH of 8 or more into contact with the group III nitride crystal and etching away the work-affected layer of the group III nitride crystal. . From this viewpoint, the pH of the slurry is more preferably 4 or less or 10 or more.

Here, there are no particular limitations on the acid and base used to adjust the pH of the slurry, for example, inorganic acids such as hydrochloric acid, nitric acid, sulfuric acid, phosphoric acid, formic acid, acetic acid, oxalic acid, citric acid, malic acid, tartaric acid In addition to organic acids such as succinic acid, phthalic acid, and fumaric acid, bases such as KOH, NaOH, NH ₄ OH, and amines, salts such as sulfates, carbonates, and phosphates can be used. Moreover, pH can also be adjusted by addition of the said oxidizing agent.

The CMP slurry preferably contains abrasive grains. The polishing rate can be further increased by the abrasive grains. The abrasive grains included in the slurry are not particularly limited, and low-hardness abrasive grains having a hardness lower than the hardness of the group III nitride crystal substrate can be used. By using low-hardness abrasive grains, the surface roughness of the main surface of the crystal substrate and the work-affected layer can be reduced.

Here, the low-hardness abrasive grains are not particularly limited as long as they are abrasive grains having a hardness lower than the hardness of the group III nitride crystal as the object to be polished, but SiO ₂ , CeO ₂ , TiO ₂ , MgO, MnO ₂ Fe ₂ O ₃ , Fe ₃ O ₄ , NiO, ZnO, CoO, Co ₃ O ₄ , CuO, Cu ₂ O, GeO ₂ , CaO, Ga ₂ O ₃ , In ₂ O ₃ Abrasive grains containing two materials are preferred.

The abrasive grains are not limited to oxides containing a single metal element, but are oxides containing two or more metal elements (for example, those having a structure such as ferrite, perovskite, spinel or ilmenite). Also good. Also, nitrides such as AlN, GaN and InN, carbonates such as CaCO ₃ and BaCO ₃ , metals such as Fe, Cu, Ti and Ni, and carbon (specifically, carbon black, carbon nanotube, C60, etc.) It can also be used.

Further, from the viewpoint of reducing the surface roughness Ra, Ry in a short time without generating scratches on the main surface of the group III nitride crystal substrate, the abrasive grains should be secondary particles bonded with primary particles. preferable. The ratio (D ₂ / D ₁ ratio) of the average particle diameter D ₂ of the secondary particles to the average particle diameter D ₁ of the primary particles is preferably 1.6 or more, and the average particle diameter D _{2 of the} secondary particles is It is preferably 200 nm or more, and the shape of the secondary particles is preferably at least one of a saddle shape, a block shape, and a chain shape, and the primary particles are chemically formed of fumed silica or colloidal silica. SiO ₂ abrasive grains that are bonded secondary particles are preferred. The primary particle diameter can be evaluated from the adsorption specific surface area by the gas adsorption method, and the secondary particles can be evaluated by the dynamic light scattering method.

Further, from the viewpoint of reducing the uniform strain, non-uniform strain and / or plane orientation deviation of the surface layer of the group III nitride crystal substrate, the pH value X and the oxidation-reduction potential value Y (mV) in the slurry used for CMP. -50X + 1300 ≦ Y ≦ −50X + 1800, and the contact coefficient C (unit: 10 ⁻⁶ m) in CMP is 1.0 × 10 ⁻⁶ m or more and 2.0 × 10 ⁻⁶ m or less. preferable. The contact coefficient C is more preferably 1.2 × 10 ⁻⁶ m or more and 1.8 × 10 ⁻⁶ m or less. Here, the contact coefficient C is expressed by the following formula using the viscosity of the slurry as η (unit: mPa · s), the peripheral speed V (unit: m / s) in CMP, and the pressure P (unit: kPa) in CMP. 5)
C = η × V / P (5)
It is expressed as When the contact coefficient C of the slurry is smaller than 1.0 × 10 ⁻⁶ m, the load on the group III nitride crystal substrate is increased in CMP, so that the surface layer of the group III nitride crystal substrate is uniformly strained and non-uniform. Distortion and / or plane orientation deviation increases. When the contact coefficient C of the slurry is larger than 2.0 × 10 ⁻⁶ m, the polishing rate decreases, so that the surface roughness of the main surface of the group III nitride crystal substrate, the uniform strain of the surface layer, the nonuniform strain and / Or misorientation increases. The viscosity of the slurry can be adjusted by adding a high-viscosity organic compound such as ethylene glycol or an inorganic compound such as boehmite, and can be measured using a B-type viscometer, Ostwald-type viscometer, or the like.

Further, a group III nitride crystal was further grown on the main surface 1s of the group III nitride crystal substrate 1 of one or more of the first to third embodiments obtained as described above, and was grown. A group III nitride crystal substrate is produced by cutting a group III nitride crystal in a plane parallel to the main surface 1s of the crystal substrate, and the main surface of the group III nitride crystal substrate is surface-treated in the same manner as described above. As a result, the Group III nitride crystal substrates of Embodiments 1 to 3 can be further manufactured. The group III nitride crystal substrate used as the base substrate for the further growth (repeated growth) of the group III nitride crystal is not necessarily a single crystal substrate, and a plurality of small size crystal substrates may be used. . It can be joined to form a single crystal during repeated growth. A large-diameter group III nitride crystal substrate can be obtained by bonding during repeated growth. Further, a crystal substrate cut out from a group III nitride crystal bonded by repeated growth can be used as a base substrate and can be repeatedly grown again. Thus, the production cost can be reduced by repeatedly using the group III nitride crystal for growth.

Here, the method for further growing the group III nitride crystal on the main surface 1s of the group III nitride crystal substrate 1 of the first to third embodiments is not particularly limited, and includes an HVPE method, a sublimation method, and the like. A liquid phase growth method such as a vapor phase growth method, a flux method, or an ammonothermal method is preferably used. For example, an HVPE method, a flux method, an ammonothermal method, or the like is preferably used for manufacturing a GaN crystal, and an HVPE method, a sublimation method, or the like is preferably used for manufacturing an AlN crystal. The HVPE method or the like is preferably used for the production of the AlGaN crystal and the InGaN crystal.

[Group III nitride crystal substrate with epi layer]
(Embodiment 4)
Referring to FIG. 15, one embodiment of a group III nitride crystal substrate with an epi layer according to the present invention is formed by epitaxial growth on main surface 1s of group III nitride crystal substrate 1 of embodiments 1 to 3. And at least one semiconductor layer 2.

In the group III nitride crystal substrate 3 with an epi layer of the present embodiment, the semiconductor layer 2 is epitaxially grown on the main surface 1s of the group III nitride crystal substrate 1, and therefore the plane orientation of the main surface 2s of the semiconductor layer 2 Is the same as the plane orientation of the main surface 1 s of the group III nitride crystal substrate 1. The plane orientation of the main surface 1s of the group III nitride crystal substrate 1 of Embodiments 1 to 3 is 10 ° or more in the <11-20> direction from either the (0001) plane or the (000-1) plane. Since it is inclined at a predetermined inclination angle α of 81 ° or less, the plane orientation of the main surface 2s of the semiconductor layer 2 is the <11-20> direction from either the (0001) plane or the (000-1) plane. Are inclined at a predetermined inclination angle α of 10 ° to 81 °. In this way, the crystallinity is high and the plane orientation of the main surface 2s is a predetermined inclination of 10 ° or more and 81 ° or less in the <11-20> direction from either the (0001) plane or the (000-1) plane. The epitaxial layer-attached group III nitride crystal substrate 3 including the semiconductor layer 2 having the angle α is obtained.

Although there is no restriction | limiting in particular in the formation method of the semiconductor layer 2, From a viewpoint of growing a highly crystalline semiconductor layer epitaxially, vapor phase growth, such as MOCVD (metal organic chemical vapor deposition) method, MBE (molecular beam epitaxy) method, etc. The method is preferably used.

[Semiconductor devices]
(Embodiment 5)
Referring to FIG. 16, one embodiment of a semiconductor device according to the present invention includes a group III nitride crystal substrate 3 with an epi layer according to a fourth embodiment.

In the group III nitride crystal substrate 3 with an epi layer of the fourth embodiment included in the semiconductor device of the present embodiment, the plane orientation of the main surface 1s is from either the (0001) plane or the (000-1) plane. It is formed by epitaxial growth on main surface 1s of group III nitride crystal substrate 1 of Embodiments 1 to 3 inclined at a predetermined inclination angle α of 10 ° to 81 ° in the 11-20> direction. One or more semiconductor layers 2 are included. The semiconductor layer 2 has high crystallinity, and the main surface has a plane orientation of 10 ° or more and 81 ° or less in the <11-20> direction from either the (0001) plane or the (000-1) plane. Therefore, the piezoelectric polarization is suppressed and the quantum confined Stark effect is also suppressed, so that the characteristics of the semiconductor device of this embodiment are enhanced. For example, in the light-emitting device in which the light-emitting layer 210 is included in the semiconductor layer 2, the piezoelectric polarization is suppressed and the quantum confined Stark effect is suppressed, so that the blue shift of light emission is suppressed and the light emission intensity is improved. Therefore, the light emitting layer 210 that emits light having a peak wavelength of 430 nm or more and 550 nm or less with high efficiency can be formed in the semiconductor layer 2. In particular, the emission intensity of light in the green region having a wavelength of 500 nm to 550 nm is significantly improved.

Referring to FIG. 16, the semiconductor device of the present embodiment includes group-III nitride crystal substrate 3 with an epi layer of the fourth embodiment. Epi-layer III-nitride crystal substrate 3 has a plane orientation of main surface 1s of 10 ° or more and 81 ° or less in the <11-20> direction from either the (0001) plane or the (000-1) plane. The group III nitride crystal substrate 1 of Embodiments 1 to 3 is inclined at an inclination angle α. In addition, the epitaxial layer group III nitride crystal substrate 3 is an n-type layer having a thickness of 1000 nm which is sequentially formed as at least one semiconductor layer 2 on one main surface 1s of the group III nitride crystal substrate 1. GaN layer 202, n-type In _x1 Al _y1 Ga _1-x1-y1 N (0 <x1, 0 <y1, x1 + y1 <1) cladding layer 204 having a thickness of 1200 nm, n-type GaN guide layer 206 having a thickness of 200 nm, thickness 65 nm thick undoped In _x2 Ga _{1 -x2} N (0 <x2 <1) guide layer 208, 15 nm thick GaN barrier layer and 3 nm thick In _x3 Ga _{1 -x3} N (0 <x3 <1) well A light emitting layer 210 having a three-period MQW (multiple quantum well) structure composed of layers, an undoped In _x4 Ga _1-x4 N (0 <x4 <1) guide layer 222 having a thickness of 65 nm, and a p having a thickness of 20 nm -type Al _{_x5} Ga _{_1-x5} N ( <X5 <1) blocking layer 224, a thickness of 200 nm p-type GaN layer 226, a thickness of 400 nm p-type _{_{_{In x6 Al y6 Ga 1-x6}}} -y6 N (0 <x6,0 <y6, x6 + y6 <1) cladding And a p-type GaN contact layer 230 having a thickness of 50 nm. A 300 nm thick SiO ₂ insulating layer 300 is partially formed on the p-type GaN contact layer 230, and the p-side electrode 400 is formed on the exposed p-type GaN contact layer 230 and a part of the SiO ₂ insulating layer 300. Is formed. An n-side electrode 500 is formed on the other main surface of group III nitride crystal substrate 1.

[Method for Manufacturing Semiconductor Device]
Referring to FIG. 16, as an embodiment of the method for manufacturing a semiconductor device according to the present invention, a step of preparing a group III nitride crystal substrate of Embodiments 1 to 3, and at least on the main surface 1s of the crystal Forming a group III nitride crystal substrate with an epi layer by growing one semiconductor layer 2. With this manufacturing method, a semiconductor device having high characteristics in which the quantum confined Stark effect due to piezoelectric polarization of the semiconductor layer is suppressed can be obtained. For example, the inclusion of the light emitting layer 210 in the semiconductor layer 2 suppresses the quantum confined Stark effect due to piezoelectric polarization of the light emitting layer 210, thereby suppressing the blue shift of light emission and light emission (for example, the peak wavelength is 430 nm or more and 550 nm). A light emitting device having a high integrated intensity of the following light emission (especially, light emission in a green region having a peak wavelength of 500 nm to 550 nm) is obtained.

Referring to FIG. 16, in the manufacturing method of semiconductor device 4 of this embodiment, specifically, group III nitride crystal substrate 1 of Embodiments 1 to 3 is first prepared. Preparation of group III nitride crystal substrate 1 is as described in [Group III nitride crystal substrate] and [Method of manufacturing group III nitride crystal substrate], and will not be repeated.

Next, at least one semiconductor layer 2 is grown on the main surface 1s of the prepared group III nitride crystal substrate 1 to form a group III nitride crystal substrate 3 with an epi layer. The growth method of the semiconductor layer 2 is not particularly limited, but from the viewpoint of epitaxially growing a semiconductor layer with high crystallinity, vapor phase growth such as MOCVD (metal organic chemical vapor deposition) method, MBE (molecular beam epitaxy) method, etc. The method is preferably used.

For example, as at least one semiconductor layer 2 on one main surface 1s of group III nitride crystal substrate 1, n-type GaN layer 202 having a thickness of 1000 nm and n-type In _{x1 having} a thickness of 1200 nm are formed by, for example, MOCVD. Al _y1 Ga _1-x1-y1 N clad layer 204, n-type GaN guide layer 206 with a thickness of 200 nm, undoped In _x2 Ga _1-x2 N guide layer 208 with a thickness of 65 nm, GaN barrier layer with a thickness of 15 nm and a thickness A light emitting layer 210 having a three-period MQW (multiple quantum well) structure composed of a 3 nm thick In _x3 Ga _1-x3 N well layer, a 65 nm thick undoped In _x4 Ga _1-x4 N guide layer 222, and a thickness is 20nm of p-type Al _{_x5} Ga _{_1-x5} N blocking layer 224, a thickness of 200 nm p-type GaN layer 226, a thickness of 400 nm p-type _{_{_{in x6 Al y6 Ga 1-x6}}} -y6 N cladding layer 2 8, and sequentially growing a p-type GaN contact layer 230 having a thickness of 50nm.

Next, a 300 nm thick SiO ₂ insulating layer 300 is formed on the p-type GaN contact layer 230 by vapor deposition. Next, a stripe window having a width of 10 μm is formed by photolithography and wet etching. A laser stripe is provided parallel to the direction in which the <0001> direction axis is projected onto the main surface of the semiconductor layer. Next, a Ni / Au electrode is formed as a p-side electrode 400 on the stripe window and a part of the SiO ₂ insulating layer 300 by vapor deposition. A Ti / Al / Ti / Au electrode is formed as the n-side electrode 500 on the other main surface of the group III nitride crystal substrate by vapor deposition.

Example I
1. Production of Group III Nitride Crystal Using a GaAs crystal substrate having a diameter of 50 mm as a base substrate, a GaN crystal (group III nitride crystal) having a thickness of 50 mm was grown by the HVPE method. That is, by heating a boat containing metal Ga to 800 ° C. in an atmospheric pressure HVPE reactor and introducing a mixed gas of HCl gas and carrier gas (H ₂ gas) into the boat, Reaction with HCl gas produced GaCl gas. At the same time, by introducing a mixed gas of NH ₃ gas and carrier gas (H ₂ gas) into the HVPE reactor, GaCl gas and NH ₃ gas are reacted to form GaAs installed in the HVPE reactor. A GaN crystal was grown on a crystal substrate (underlying substrate). Here, the growth temperature of the GaN crystal was 1050 ° C., the HCl gas partial pressure in the HVPE reactor was 2 kPa, and the NH ₃ gas partial pressure was 30 kPa.

2. Production of Group III Nitride Crystal Substrate The GaN crystal (Group III nitride crystal) obtained above is tilted between 0 ° and 90 ° in the [11-20] direction with respect to the (0001) plane. By slicing along a plane parallel to the plane having α, a GaN crystal substrate (group III nitride crystal substrate) having a main surface with the plane orientation shown in Table 1 was produced.

3. Surface processing of group III nitride crystal substrate The main surface of the GaN crystal substrate (group III nitride crystal substrate) obtained above is lapped (mechanically polished), and then subjected to CMP (chemical mechanical polishing) to produce a semiconductor. A GaN crystal substrate for devices was obtained. Here, for lapping, three types of diamond abrasive grains having an abrasive grain size of 2 μm, 3 μm, and 9 μm are prepared, and the grain size of the diamond abrasive grains is gradually reduced using a copper surface plate or a tin surface plate. I went. Wrapping pressure ^{100gf / cm 2 ~ 500gf / cm} 2 (9.8kPa ~ 49.0kPa), the rotational speed of the GaN crystal substrate and the surface plate was 30 rpm (rotation / min) ~ 60rpm. Further, CMP includes colloidal silica (primary particle diameter is 70 nm, secondary particle diameter is 190 nm) in which primary particles are chemically bonded as abrasive grains to form secondary particles, nitric acid as a pH regulator, Using a slurry containing trichloroisocyanuric acid as an oxidizing agent and adjusting the pH and redox potential (ORP) to the values shown in Table 1, the contact coefficient C was adjusted to the values shown in Table 1.

Measure the diffracted X-rays from the (10-13) plane (specific parallel crystal lattice plane in this measurement) with the X-ray penetration depth changed from 0.3 μm to 5 μm for the surface-processed GaN crystal substrate. To obtain the (10-13) plane spacing in the diffraction intensity profile, the half-value width of the diffraction intensity peak, and the half-value width of the diffraction intensity peak in the rocking curve, and the uniform strain of the surface layer of the GaN crystal substrate from these values Then, non-uniform distortion and plane orientation deviation of the crystal lattice plane were evaluated. For X-ray diffraction measurement, a parallel optical system, CuK _α1 X-ray wavelength was used. The X-ray penetration depth was controlled by changing at least one of the X-ray incident angle ω with respect to the crystal surface, the tilt angle χ of the crystal surface, and the rotation angle φ within the crystal surface. From the viewpoint of facilitating the evaluation by X-ray diffraction at the X-ray penetration depth, in Examples I-3 and I-4, the (11-22) plane is used as the specific parallel crystal lattice plane. 5, I-13 and I-14 use the (10-11) plane as the specific parallel crystal lattice plane, and Example I-6 uses the (11-21) plane as the specific parallel crystal lattice plane. 7 uses the (22-41) plane as the specific parallel crystal lattice plane, and in Examples I-10, I-11, I-12, and I-18 uses the (10-15) plane as the specific parallel crystal lattice plane. In Example I-15, the (10-1-3) plane was used as the specific parallel crystal lattice plane, and in Example I-16, the (10-1-5) plane was used as the specific parallel crystal lattice plane.

The specific resistance of another GaN crystal substrate obtained by the same manufacturing method and surface processing method as in this example was 1 × 10 ⁻² Ω · cm as measured by the four-probe method, and its carrier The concentration was 2 × 10 ¹⁸ cm ^{−3 as} measured by the Hall measurement method.

4). Manufacturing of Semiconductor Device Referring to FIG. 16, at least one semiconductor layer is formed on one main surface 1s of the GaN crystal substrate (Group III nitride crystal substrate 1) for a semiconductor device obtained above by MOCVD. As the layer 2, an n-type GaN layer 202 having a thickness of 1000 nm, an n-type In _x1 Al _y1 Ga _1-x1-y1 N (x1 = 0.03, y1 = 0.14) cladding layer 204 having a thickness of 1200 nm, a thickness 200 nm n-type GaN guide layer 206, 65 nm thick undoped In _x2 Ga _{1 -x2} N (x2 = 0.03) guide layer 208, 15 nm thick GaN barrier layer and 3 nm thick In _x3 Ga ₁₋ A light emitting layer 210 having a three-period MQW (multiple quantum well) structure composed of _x3 N (x3 = 0.2 to 0.3) well layers, 65 nm thick undoped In _x4 Ga _{1 -x4} N (x4 = 0.03 Guide layer 222, a thickness of 20 nm p-type _{_{Al x5 Ga 1-x5 N (}} x5 = 0.11) blocking layer 224, p-type GaN layer 226 having a thickness of 200 nm, a thickness of 400 nm p-type In _x6 Al _y6 Ga _{1 A -x6-y6} N (x6 = 0.03, y6 = 0.14) clad layer 228 and a p-type GaN contact layer 230 having a thickness of 50 nm were grown sequentially.

Next, a 300 nm thick SiO ₂ insulating layer 300 was formed on the p-type GaN contact layer 230 by vapor deposition. Next, a stripe window having a width of 10 μm was formed by photolithography and wet etching. A laser stripe was provided parallel to the direction in which the <0001> direction axis was projected onto the main surface of the semiconductor layer. Next, a Ni / Au electrode was formed as the p-side electrode 400 on the stripe window and a part of the SiO ₂ insulating layer 300 by vapor deposition. Next, the other main surface of the GaN crystal substrate (Group III nitride crystal substrate 1) was mirror-finished by lapping (mechanical polishing). Next, a Ti / Al / Ti / Au electrode was formed as the n-side electrode 500 by vapor deposition on the mirror-finished main surface of the GaN crystal substrate. At this time, the thickness and thickness of each layer of the wafer were measured using a contact film thickness meter or by observing the wafer cross section including the substrate using an optical microscope or SEM (scanning electron microscope).

A laser scriber using a YAG laser having a peak wavelength of 355 nm was used for manufacturing the resonator mirror for the laser stripe. When a break is made using a laser scriber, it is possible to improve the oscillation chip yield compared to the case where diamond scribe is used. The conditions for forming the scribe grooves were a laser beam output of 100 mW and a scanning speed of 5 mm / s. The formed scribe groove was, for example, a groove having a length of 30 μm, a width of 10 μm, and a depth of 40 μm. A scribe groove was formed by directly irradiating the main surface of the semiconductor layer with a laser beam through an insulating film opening portion of the substrate at a pitch of 800 μm. The resonator length was 600 μm. Using a blade, a resonant mirror was prepared by cleaving. A laser bar was produced by breaking on the back side of the substrate by pressing.

Next, a dielectric multilayer film was coated on the end face of the laser bar by vacuum deposition. The dielectric multilayer film was formed by alternately laminating SiO ₂ and TiO ₂ . The film thickness was adjusted in the range of 50 nm to 100 nm, respectively, so that the peak wavelength of the reflectance was in the range of 500 nm to 530 nm. The reflection surface of one end face was set to 10 periods, the design value of reflectivity was designed to about 95%, the reflection surface of the other end face was set to 6 periods, and the design value of reflectivity was about 80%.

The semiconductor device obtained as described above was evaluated by energization at room temperature (25 ° C.) as follows. As a power source, a pulse power source having a pulse width of 500 ns and a duty ratio of 0.1% was used to energize the surface electrode by dropping a needle. The current density was 100 A / cm ² . The LED mode light was observed by placing an optical fiber on the main surface side of the laser bar and measuring the emission spectrum emitted from the main surface. Table 1 shows the integrated intensities of emission peaks in the wavelength range of 500 nm to 550 nm of the emission spectrum of LED mode light. Table 1 summarizes the full width at half maximum of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light. The laser beam was observed by placing an optical fiber on the end face side of the laser bar and measuring the emission spectrum emitted from the end face. The emission peak wavelength of the LED mode light was 500 nm to 550 nm. The oscillation peak wavelength of the laser beam was 500 nm to 530 nm.

As is apparent from Table 1, with respect to the group III nitride crystal substrate, the uniform distortion of the surface layer is 1.9 × 10 ⁻³ or less, the nonuniform distortion of the surface layer is 130 arcsec or less, and / or the specific parallel crystal of the surface layer The plane orientation deviation of the lattice plane is 350 arcsec or less, and the plane orientation of the main surface is tilted from 10 ° to 81 ° in the <11-20> direction from the (0001) plane or the (000-1) plane. In this case, the integrated intensity of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device using such a crystal substrate was increased. Further, the plane orientation of the main surface is {11-22}, {22-43}, {11-21}, {22-41}, {11-2-2}, {22-4-3}, {11 -2-1} and {22-4-1}, the half-value width of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device using such a crystal substrate is Reduced.

For Examples I-2 and I-10, the blue shift was evaluated by measuring the emission wavelength of LED mode light at current densities of 1 A / cm ² and 100 A / cm ² , respectively. The blue shift in Example I-2 was 40 nm, and the blue shift in Example I-10 was 10 nm. For the group III nitride crystal substrate, the uniform distortion of the surface layer is 1.9 × 10 ⁻³ or less, the nonuniform distortion of the surface layer is 130 arcsec or less, and / or the plane orientation deviation of the specific parallel crystal lattice plane of the surface layer is 350 arcsec And when the plane orientation of the main surface is inclined at 10 ° or more and 81 ° or less in the <11-20> direction from the (0001) plane or the (000-1) plane, such a crystal substrate The blue shift of the semiconductor device using the semiconductor was extremely small.

Example II
CMP includes colloidal silica (primary particle size is 15 nm, secondary particle size is 40 nm) in which primary particles are chemically combined as abrasive grains into secondary particles, and citric acid and oxidation are used as pH regulators. Except for adjusting the contact coefficient C to the value shown in Table 2 using a slurry containing trichloroisocyanuric acid as the agent and adjusting the pH and redox potential (ORP) to the values shown in Table 2. Is similar to Example I, which manufactures a GaN crystal substrate (Group III nitride crystal substrate) and a semiconductor device, and the surface layer of the surface processed GaN crystal substrate has uniform strain, nonuniform strain, and crystal lattice plane In addition to evaluating the plane orientation deviation, the integrated intensity and half width of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device were measured. . The results are summarized in Table 2.

As is apparent from Table 2, the group orientation of the group III nitride crystal substrate is tilted from 10 ° to 81 ° in the <11-20> direction from the (0001) plane or the (000-1) plane of the main surface. In this case, the smaller the uniform distortion of the surface layer, the nonuniform distortion and / or the plane orientation deviation of the specific parallel crystal lattice plane, the wavelength of the emission spectrum of the LED mode light of the semiconductor device using such a crystal substrate is 500 nm to 550 nm. The integrated intensity of the emission peak in the range is increased.

Example III
The surface orientation of the main surface of the GaN crystal substrate (group III nitride crystal substrate) is (11-21) (the inclination angle α from the (0001) plane is 73 °), and CMP is used as spherical colloidal silica ( Using a slurry containing sodium carbonate as a pH adjusting agent, sodium dichloroisocyanurate as an oxidizing agent, and adjusting the pH and redox potential (ORP) to the values shown in Table 3 A GaN crystal substrate (group III nitride crystal substrate) and a semiconductor device were manufactured and surface-processed in the same manner as in Example I except that the coefficient C was adjusted to the value shown in Table 3. The uniform strain and non-uniform strain of the surface layer of the formed GaN crystal substrate and the plane orientation deviation of the crystal lattice plane are evaluated, and the wavelength of the emission spectrum of the LED mode light of the semiconductor device is 500 n The integrated intensity and full width at half maximum of the emission peak in the range of m to 550 nm were measured. The results are summarized in Table 3.

As is apparent from Table 3, with respect to the group III nitride crystal substrate, the uniform distortion of the surface layer is 1.9 × 10 ⁻³ or less, the nonuniform distortion of the surface layer is 130 arcsec or less, and / or the specific parallel crystal of the surface layer The plane orientation deviation of the lattice plane is 350 arcsec or less, and the plane orientation of the main surface is tilted from 10 ° to 81 ° in the <11-20> direction from the (0001) plane or the (000-1) plane. In this case, as the surface roughness Ra, Ry of the main surface decreases, the integrated intensity of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device using such a crystal substrate increases.

Example IV
The surface orientation of the main surface of the GaN crystal substrate (group III nitride crystal substrate) is (22-43) (inclination angle α from the (0001) plane is 65 °), and the primary particles are chemically treated with CMP as abrasive grains. Colloidal silica (primary particle size is 35 nm, secondary particle size is 70 nm), which is bonded to each other and contains sulfuric acid as a pH regulator, hydrogen peroxide and trichloroisocyanuric acid as an oxidizing agent. The same as Example I, except that the contact coefficient C was adjusted to the value shown in Table 4 using the slurry adjusted to pH and redox potential (ORP) as shown in Table 4. Then, a GaN crystal substrate (group III nitride crystal substrate) and a semiconductor device are manufactured, and the uniform strain and non-uniform strain of the surface layer of the surface-processed GaN crystal substrate and the misorientation of the crystal lattice plane are evaluated. With The integrated intensity and half-value width of the emission peak in the wavelength range of 500 nm to 550 nm of the emission spectrum of the LED mode light of the semiconductor device were measured. The results are summarized in Table 4.

As is apparent from Table 4, with respect to the group III nitride crystal substrate, the uniform distortion of the surface layer is 1.9 × 10 ⁻³ or less, the nonuniform distortion of the surface layer is 130 arcsec or less, and / or the specific parallel crystal of the surface layer The plane orientation deviation of the lattice plane is 350 arcsec or less, and the plane orientation of the main surface is tilted from 10 ° to 81 ° in the <11-20> direction from the (0001) plane or the (000-1) plane. In the case where the concentration of oxygen present on the main surface is measured by AES (Auger atomic spectroscopy), when it is 2 atomic% or more and 16 atomic% or less, the LED mode light of the semiconductor device using the crystal substrate is measured. The integrated intensity of the emission peak increased.

(Example V)
1. Production of Group III Nitride Crystal and Group III Nitride Crystal Substrate For Examples V-1 and V-2, the surface orientation of the main surface produced in Example I-10 of Example I as the base substrate was (11-22 The GaN crystal body was grown by the flux method using the GaN crystal substrate (Group III nitride crystal substrate). That is, a GaN crystal substrate (underlying substrate), metal Ga as a Ga raw material, and metal Na as a flux were accommodated in a crucible so that Ga: Na was 1: 1 in terms of molar ratio. The crucible was then heated to obtain a 800 ° C. Ga—Na melt in contact with the (11-22) main surface of the GaN crystal substrate. In this Ga—Na melt, 5 MPa of N ₂ gas was dissolved as an N raw material to grow a GaN crystal having a thickness of 2 mm on the (11-22) main surface of the GaN crystal substrate. As the crystal growth progressed, the dislocation density decreased. The dislocation density of the main surface of the GaN crystal substrate was adjusted by the difference in the position of the GaN crystal substrate taken from the GaN crystal (see Table 5).

For Examples V-3 to V-6, the growth by the HVPE method was carried out by using a GaN crystal substrate (Group III) having a main surface of (11-22) as the base substrate manufactured in Example I-10 of Example I. Using a nitride crystal substrate), a GaN crystal having a thickness of 5 mm was grown by HVPE. The growth conditions of the GaN crystal by the HVPE method were the same as in Example I. As the crystal growth progressed, the dislocation density decreased. The dislocation density of the main surface of the GaN crystal substrate was adjusted by the difference in the position of the GaN crystal substrate taken from the GaN crystal (see Table 5).

2. Surface processing of group III nitride crystal substrate Fumed silica (primary particle size is 20 nm, secondary particle size is 150 nm) in which CMP is performed to form secondary particles by chemically bonding primary particles as chain. The contact coefficient C is a value shown in Table 2 using a slurry that contains malic acid as a pH adjuster, potassium permanganate as an oxidizer, and adjusted to pH and redox potential (ORP) values shown in the table. A GaN crystal substrate for a semiconductor device was obtained by surface-treating a GaN crystal substrate (Group III nitride crystal substrate) in the same manner as in Example I except that the adjustment was performed so that The uniform strain and non-uniform strain of the surface layer of the GaN crystal substrate for semiconductor devices (surface-processed GaN crystal substrate) thus obtained were evaluated in the same manner as in Example I.

3. Production of Semiconductor Device Using the GaN crystal substrate for semiconductor device obtained above, a semiconductor device was produced in the same manner as in Example I, and the emission mode wavelength range of the LED mode light of the semiconductor device was in the range of 500 nm to 550 nm. The integrated intensity and half-value width of the emission peak at were measured. The results are summarized in Table 5.

As is apparent from Table 5, with respect to the group III nitride crystal substrate, the uniform distortion of the surface layer is 1.9 × 10 ⁻³ or less, the nonuniform distortion of the surface layer is 130 arcsec or less, and / or the specific parallel crystal of the surface layer The plane orientation deviation of the lattice plane is 350 arcsec or less, and the plane orientation of the main surface is tilted from 10 ° to 81 ° in the <11-20> direction from the (0001) plane or the (000-1) plane. In this case, the lower the dislocation density on the main surface of the group III nitride crystal substrate, for example, the dislocation density is 1 × 10 ⁷ cm ⁻² or less, 1 × 10 ⁶ cm ⁻² or less, and further 1 × 10 ⁵ cm ^−. accordance smaller and ² below, the integrated intensity of the emission peak in the wavelength range of 500 nm ~ 550 nm of the emission spectrum of the LED-mode light of the semiconductor device using such a crystal substrate is increased . Even when a plurality of GaN crystal substrates were used as the base substrate and a single GaN crystal joined from the base substrate was grown by the flux method or the HVPE method, the same result as above was obtained. .

Example VI
CMP includes spherical colloidal silica (particle size: 30 nm) as abrasive grains, hydrochloric acid as a pH adjuster, hydrogen peroxide water and trichloroisocyanuric acid as oxidizing agents, pH, redox potential (ORP) and viscosity. Using the slurry prepared to the values shown in Table 6, except that the CMP peripheral speed, the CMP pressure, and the contact coefficient C were adjusted to the values shown in Table 6, the same as in Example I, A GaN crystal substrate (Group III nitride crystal substrate) was surface processed. The uniform strain and non-uniform strain of the surface layer of the surface-processed GaN crystal substrate and the misorientation of the crystal lattice plane were evaluated in the same manner as in Example I. The results are summarized in Table 6.

As is clear from Table 6, the pH value X and the redox potential value Y (mV) are
−50X + 1300 ≦ Y ≦ −50X + 1800
Using the slurry having the following relationship, CMP is performed so that the contact coefficient C is 1.0 × 10 ⁻⁶ m or more and 2.0 × 10 ⁻⁶ m or less, whereby the plane orientation of the main surface is (0001). Even in a group III nitride crystal substrate inclined at 10 ° or more and 81 ° or less in the <11-20> direction from the plane or the (000-1) plane, the uniform distortion of the surface layer is 1.9 × 10 ^−3. In the following, the nonuniform strain of the surface layer could be 130 arcsec or less and / or the plane orientation deviation of the specific parallel crystal lattice plane ((10-13) plane) of the surface layer could be 350 arcsec or less.

Here, when the oxidation-reduction potential (ORP) is low, the action of oxidizing the main surface of the group III nitride crystal substrate becomes weak, so the mechanical action during CMP becomes strong, and the surface of the group III nitride crystal substrate becomes strong. The uniform strain, non-uniform strain and plane orientation deviation of the layer increased. When the oxidation-reduction potential was high, stable polishing became difficult, and uniform distortion, non-uniform distortion, and plane orientation deviation of the surface layer of the group III nitride crystal substrate increased. When the contact coefficient was small, the load on the group III nitride crystal substrate at the time of CMP became strong, and the uniform strain, nonuniform strain, and plane orientation deviation of the surface layer of the group III nitride crystal substrate increased. When the contact coefficient was large, the CMP rate was greatly reduced, the effect of surface modification was reduced, and the uniform strain, nonuniform strain, and plane orientation deviation of the surface layer of the group III nitride crystal substrate were increased.

(Example VII)
A GaN crystal substrate (Group III nitride crystal substrate) having a main surface orientation of (11-21) prepared in Example II-5 was cut to obtain a plurality of small-piece substrates having a size of 5 mm × 20 mm to 5 mm × 45 mm. It was. A plurality of such small piece substrates have their principal surfaces (all of the principal surfaces have a (11-21) plane orientation and a tilt angle of 73 ° with respect to the (0001) plane) parallel to each other. In order to form a base substrate of a desired size by arranging the side surfaces so as to be adjacent to each other, a GaN crystal (Group III nitride crystal) is grown by HVPE on each of the main surfaces of the small substrate. The group III nitride crystals were joined to each other and the outer peripheral portion was processed to obtain a GaN crystal (group III nitride crystal) of a desired size. The obtained GaN crystal was cut out parallel to the main surface of the base substrate, and a GaN crystal substrate and a semiconductor device having a diameter of 40 mm, a diameter of 100 mm, and a diameter of 150 mm were manufactured in the same manner as in Example II-5. Both the GaN crystal substrate and the semiconductor device obtained the substrate characteristics and device characteristics equivalent to those in Example II-5. Further, these GaN crystal substrates (group III nitride crystal substrates) are used as a base substrate, and crystals are repeatedly grown by the HVPE method to obtain GaN crystals (group III nitride crystals) having a diameter of 40 mm, a diameter of 100 mm, and a diameter of 150 mm, respectively. It was. By processing this GaN crystal in the same manner as described above, a GaN crystal substrate and a semiconductor device having characteristics equivalent to those of Example II-5 were obtained.

It should be considered that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Group III nitride crystal substrate, 1c Any one of (0001) plane and (000-1) plane, 1d, 31d, 32d, 33d, 41d, 42d, 43d, 51d, 52d, 53d Specific parallel crystal lattice plane 1p surface layer, 1q surface adjacent layer, 1r inner layer, 1s, 2s main surface, 2 semiconductor layer, III-layer nitride crystal substrate with epi layer, 4 semiconductor device, 11 incident X-ray, 12 outgoing X-ray, 21 χ Axis, 22 ω axis (2θ axis), 23 φ axis, 30 tensile stress, 202 n-type GaN layer, 204 n-type In _x1 Al _y1 Ga _1-x1-y1 N cladding layer, 206 n-type GaN guide layer, 208 In _x2 Ga1 _-x2 N guide layer, 210 light emitting layer, 222 In _x4 Ga _1-x4 N guide layer, 224 p-type Al _x5 Ga _1-x5 N block layer, 226 p-type GaN layer, 228 p-type In _x6 Al _y6 Ga _1-x6-y6 N _clutch Layer, 230 p-type GaN contact layer, 300 SiO ₂ insulating layer, 400 p-side electrode, 500 n-side electrode.

Claims

The specific parallel crystal lattice obtained from X-ray diffraction measurement that changes the X-ray penetration depth from the main surface of the crystal substrate while satisfying the X-ray diffraction condition of an arbitrary specific parallel crystal lattice plane of the group III nitride crystal substrate | D 1 −d 2 | / d obtained from the surface distance d 1 at the X-ray penetration depth of 0.3 μm and the surface distance d 2 at the X-ray penetration depth of 5 μm. The uniform strain of the surface layer of the crystal substrate represented by the value of 2 is 1.9 × 10 −3 or less,
A group III nitride in which the plane orientation of the main surface is inclined from 10 ° to 81 ° in the <11-20> direction from either the (0001) plane or the (000-1) plane of the crystal substrate Crystal substrate.
The specific parallel crystal lattice obtained from X-ray diffraction measurement that changes the X-ray penetration depth from the main surface of the crystal substrate while satisfying the X-ray diffraction condition of an arbitrary specific parallel crystal lattice plane of the group III nitride crystal substrate In the diffraction intensity profile of the surface, it is obtained from the half width v 1 of the diffraction intensity peak at the X-ray penetration depth of 0.3 μm and the half width v 2 of the diffraction intensity peak at the X-ray penetration depth of 5 μm. The non-uniform distortion of the surface layer of the crystal substrate represented by the value of 1 −v 2 | is 130 arcsec or less,
A group III nitride in which the plane orientation of the main surface is inclined from 10 ° to 81 ° in the <11-20> direction from either the (0001) plane or the (000-1) plane of the crystal substrate Crystal substrate.
The X-ray of 0.3 μm in the rocking curve measured by changing the X-ray penetration depth from the main surface of the crystal substrate with respect to the X-ray diffraction of any specific parallel crystal lattice plane of the group III nitride crystal substrate The crystal substrate represented by the value of | w 1 −w 2 | obtained from the half width w 1 of the diffraction intensity peak at the penetration depth and the half width w 2 of the diffraction intensity peak at the X-ray penetration depth of 5 μm The surface orientation deviation of the specific parallel crystal lattice plane of the surface layer is 350 arcsec or less,
A group III nitride in which the plane orientation of the main surface is inclined from 10 ° to 81 ° in the <11-20> direction from either the (0001) plane or the (000-1) plane of the crystal substrate Crystal substrate.
The group III nitride crystal substrate according to claim 1, wherein the main surface has a surface roughness Ra of 5 nm or less.
The plane orientation of the main surface is the {11-22} plane, {22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {11-22} plane, { The tilt angle is substantially parallel to any one of the 22-4-3} plane, the {11-2-1} plane, and the {22-4-1} plane, in the range of 0 ° to less than 0.1 °. The group III nitride crystal substrate according to claim 1.
The plane orientation of the main surface is {11-22} plane, {22-43} plane, {11-21} plane, {22-41} plane, {11-2-2} plane, {11-22} plane, The first aspect of the present invention is inclined from 0.1 ° to 4 ° from any of the 22-4-3}, {11-2-1}, and {22-4-1} surfaces. A group III nitride crystal substrate as described in 1. above.
The group III nitride crystal substrate according to claim 1, wherein the concentration of oxygen existing on the main surface is 2 atomic% or more and 16 atomic% or less.
The group III nitride crystal substrate according to claim 1, wherein a dislocation density in the main surface is 1 x 10 7 cm -2 or less.
The group III nitride crystal substrate according to claim 1, wherein the diameter is 40 mm or more and 150 mm or less.
A group-III nitride crystal substrate with an epi layer comprising at least one semiconductor layer formed by epitaxial growth on the main surface of the group-III nitride crystal substrate according to claim 1.
A semiconductor device comprising the group III nitride crystal substrate with an epi layer according to claim 10.
The semiconductor device according to claim 11, wherein the semiconductor layer included in the group III nitride crystal substrate with an epi layer includes a light emitting layer that emits light having a peak wavelength of 430 nm or more and 550 nm or less.
The specific parallel crystal lattice obtained from X-ray diffraction measurement that changes the X-ray penetration depth from the main surface of the crystal substrate while satisfying the X-ray diffraction condition of an arbitrary specific parallel crystal lattice plane of the group III nitride crystal substrate | D 1 −d 2 | / d obtained from the surface distance d 1 at the X-ray penetration depth of 0.3 μm and the surface distance d 2 at the X-ray penetration depth of 5 μm. The uniform distortion of the surface layer of the crystal substrate represented by the value of 2 is 1.9 × 10 −3 or less, and the plane orientation of the main surface is (0001) plane and (000-1) plane of the crystal substrate Preparing the crystal substrate inclined from 10 ° to 81 ° in the <11-20> direction from any of the surfaces;
Forming a group III nitride crystal substrate with an epi layer by epitaxially growing at least one semiconductor layer on the main surface of the crystal substrate.
The specific parallel crystal lattice obtained from X-ray diffraction measurement that changes the X-ray penetration depth from the main surface of the crystal substrate while satisfying the X-ray diffraction condition of an arbitrary specific parallel crystal lattice plane of the group III nitride crystal substrate In the diffraction intensity profile of the surface, it is obtained from the half width v 1 of the diffraction intensity peak at the X-ray penetration depth of 0.3 μm and the half width v 2 of the diffraction intensity peak at the X-ray penetration depth of 5 μm. The non-uniform strain of the surface layer of the crystal substrate represented by a value of 1 −v 2 | is 130 arcsec or less, and the plane orientation of the main surface is the (0001) plane and (000-1) plane of the crystal substrate. Preparing the crystal substrate inclined from 10 ° to 81 ° in any of the directions in the <11-20>direction;
Forming a group III nitride crystal substrate with an epi layer by epitaxially growing at least one semiconductor layer on the main surface of the crystal substrate.
The X-ray of 0.3 μm in the rocking curve measured by changing the X-ray penetration depth from the main surface of the crystal substrate with respect to the X-ray diffraction of any specific parallel crystal lattice plane of the group III nitride crystal substrate The crystal substrate represented by the value of | w 1 −w 2 | obtained from the half width w 1 of the diffraction intensity peak at the penetration depth and the half width w 2 of the diffraction intensity peak at the X-ray penetration depth of 5 μm The surface orientation deviation of the specific parallel crystal lattice plane of the surface layer is 350 arcsec or less, and the plane orientation of the main surface is <11 from one of the (0001) plane and the (000-1) plane of the crystal substrate. A step of preparing the crystal substrate tilted in the -20> direction by 10 ° or more and 81 ° or less;
Forming a group III nitride crystal substrate with an epi layer by epitaxially growing at least one semiconductor layer on the main surface of the crystal substrate.
In the step of forming the group III nitride crystal substrate with an epi layer, the semiconductor layer includes a light emitting layer, and the light emitting layer is formed to emit light having a peak wavelength of 430 nm or more and 550 nm or less. 14. A method for manufacturing a semiconductor device according to item 13.