WO2011049428A1

WO2011049428A1 - Inverted isfet

Info

Publication number: WO2011049428A1
Application number: PCT/MY2010/000215
Authority: WO
Inventors: Daniel Chia Sheng Bien; Hing Wah Lee; Mohd Ismahadi Syono
Original assignee: Mimos Bhd
Current assignee: Mimos Bhd
Priority date: 2009-10-20
Filing date: 2010-10-19
Publication date: 2011-04-28
Anticipated expiration: 2012-04-20
Also published as: MY162299A

Abstract

An inverted ion-sensitive field effect transistor (ISFET) (10) comprises a substrate layer (11), a sensing membrane (12) on said substrate layer (11), a layer of field oxide (19 ) on said sensing membrane (12), doped source (13) and drain (14) regions on said layer of field oxide (19), and characterized in that electrical contacts (16, 17) are provided to the respective source (13) and drain (14) regions on the opposing side of said sensing membrane (12) and said substrate layer (11) is windowed with an opening access (18) to said sensing membrane (12) to provide electrical isolation of the electrical contacts (16, 17) from said sensing membrane (12).

Description

Inverted ISFET

Field of Invention

The present invention relates to ion-sensitive field effect transistor ( ISFET ) , more particularly relates to a ISFET having isolation of the fluid interacting sensing membrane area with the electrical conducting area.

Background of Invention

Chemical sensors for detecting chemical compounds are widely used in different field such as medical diagnosis, water treatment system, food processing and the like. Conventional chemical sensor such as glass electrode and spectrophotometer are relatively large in size, difficult to be handled, and expensive as required lots of building parts for construction. In view of this, miniaturized semiconductor sensors were devised and now replacing the use of conventional chemical sensor.

Ion-sensitive field effect transistor (ISFET) is one of the most widely employed semiconductor at present which is incorporated into chemical sensor for chemical compounds detection and specifically for pH sensing. Since fabrication of the ISFET is through integrated circuit process technology, the chemical sensor produced are much smaller in size, easier for standardization with high reproducibility and is ready for mass produce hence reducing the manufacturing cost. Nevertheless, attempts to reduce the manufacturing cost by introducing more functionality and integration with other semiconductor devices,, while further improve the performance of the ISFET, have never end. Reducing the number of substrates or fabrication processes involved are known to be one of the more effective ways to attain the aforesaid purposes. A basic schematic of the ISFET fabricated using micromachining technology is shown in Figure 1.

Recent advancement in technologies generates a strong trend towards miniaturized analysis system. Conventional ISFETs have metal contacts and the sensing gate on the same surface of the wafer hence they require separate packaging module so that only the gate will be in contact with the liquid sample. The metal contacts and the sensing gate are on different thickness level , therefore this creates packaging problem such as alignment during packaging process, leakage, bonding performance, etc₀ Those ISFETs have high current losses and leakage issues as only a minimum part of the substrate itself would be required to build the FET while other large silicon conducting area will be omitted from the device application but which, will indirectly affect the performance of the ISFET. They are also fabricated on bulk thick substrate where it has been associated with problems such as low saturation current and reduced short-channel/floating body effects.

US Patent Publication No. 7321143 discloses an ion-sensitive field effect transistor includes a substrate on which there are formed a source region and a drain region. Above a channel region, the ion-sensitive field effect transistor has a gate with a sensitive layer including a metal oxide nitride mixture and/or a metal oxide nitride mixture compound.

US Patent Publication No. 7321143 discloses an integrated ion sensor, which comprises at least one ion selective membrane sensitive to ions contained in a solution to be measured for detecting the concentration of the ions, a signal processing circuit for inputting a detected signal obtained by the ion selective membrane through a conductive member and fetching the detected signal through MOSFETs or the like included in an input stage to process the same, a reference electrode disposed in the measuring environment made by the solution to be measured and to be set to a predetermined voltage relationship between the reference electrode and the ion selective membrane, and a power supply having negative and positive terminals for supplying a driving power to the signal processing circuit through the terminals, one of the terminals being connected to the reference electrode, wherein the signal processing circuit is set to an active state at a voltage set to the reference electrode, by controlling the threshold value of at least one of the MOSFETs of the signal processing circuit.

From the foregoing, it will be noted that the sensors formed with the contact pad and sensing membrane on same surface and thus requires packaging process to isolate electrical contacts from the sensing area. Further there is no injection or opening window on basic device and thus requires additional passivation layers for isolation of electrical conducting area with fluid interface- The present invention is an inverted ISFET with the sensing membrane and metal contact pads on opposing sides of the substrate₀ This improved configuration allow isolation of the fluid interacting sensing membrane area with the electrical conducting area by reducing the possibility of the electrical circuit being shorted due to the presence of the conducting fluids₀ It is formed with a thin silicon-based substrate for development of the FET region for improved performance as it has been shown that FET made on fully depleted ultra thin films have additional benefits of nearly ideal sub-threshold slope, increased saturation current and reduced short-channel/floating body effects due to the lower effective substrate electric field.

Other objective of the present invention is to provide a more cost effective . ISFET sensor which is integrated or self-formed with sensing window on the sensing membrane hence allowing the elimination of the bonding requirement to attach the sensing window or packaging onto the sensing membrane and therefore fluid leakage problems will be improved and addressed leading to a leakage-free fluid-sensing membrane interface area_Q Still another objective of the present invention is to provide the ISFET sensor which can be microfabricated for miniaturization purpose₀

Other objects of this invention will become apparent on the reading of this entire disclosure.

Summary of Invention

In one aspect of the present invention, an inverted ion-sensitive field effect transistor (ISFET) comprises a substrate layer, a sensing membrane on the substrate layer, a layer of field oxide on the sensing membrane, doped source and drain regions on the layer of field oxide, and characterized in that electrical contacts are provided to the respective source and drain regions on the opposing side of the sensing membrane and the substrate layer is windowed with an opening access to the sensing membrane to provide electrical isolation of the electrical contacts from the sensing membrane .

A method of manufacturing an inverted ISFET comprising the steps of providing a substrate layer, depositing a layer of sensing membrane on the substrate layer, depositing a layer of field oxide on the sensing membrane, depositing a layer of doped polysilicon on the field oxide layer, etching the respective source and drain regions using photoresist, and providing the electrical contacts for the source and drain regions, characterized in that the electrical contacts are provided on the opposing side of the sensing membrane to provide electrical isolation of the electrical contacts from the sensing membrane. Brief Description of the Drawings

Other objects, features, and advantages of the invention will be apparent from the following description when read with reference to the accompanying drawings. In the drawings, wherein like reference numerals denote corresponding parts throughout the several views:

Figure 1 shows a schematic diagram of the ISFET of . (a) basic elements (b) cross sectional view of the microfabricated ISFET and (c) the ISFET device;

Figure 2 depicts an inverted ISFET of the present invention; Figure 3 is a step by step fabrication process flow of the inverted ISFET of the present invention which are shown in Figure 3a to 3m.

De-tailed Description of -the Preferred Embodiments

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known methods, procedures and/or components have not been described in detail so as not to obscure the invention. Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

Referring now to Figures 2 and 3 , an inverted ion-sensitive field effect transistor ( ISFET ) of the present invention generally designated as numeral reference 10₀ Figure 2 shows a cross sectional view of the inverted ISFET ( 10 ) having the desired configuration as obtained when manufactured in accordance to the present invention_Q The substrate ( 11 ) of the inverted ISFET ( 10 ) is a polysilicon layer which is a thin film silicon based layer in order to provide an improved performance of the ISFETo However , the substrate ( 11 ) is not limited to silicon but other types of substrates such as glass , SOI , etc can also be used to realize the device fabrication,,

On the front side of the substrate ( 11 ) , it is deposited with a layer of sensing membrane ( 12 ) which is preferably a nitride sensing membrane such as silicon nitride ( Si₃N₄ ) ₀ The inverted ISFET ( 10 ) is doped to have a source region ( 13 ) and a drain region ( 14 ) o In between the source ( 13 ) and drain ( 14 ) regions there is a doped polysilicon area ( 15 ). The source region ( 13 ) is provided with a metal source contact ( 16 ) and the drain region ( 14 ) is provided with a metal drain contact ( 17 ) ₀ These contacts ( 16 , 17 ) and the sensing membrane ( 12 ) are on the opposing side of the substrate ( 11 ) ₀ The substrate ( 11 ). is windowed with a window opening ( 18 ) towards the sensing membrane ( 12 ) hence allowing the elimination of the bonding requirement to attach the opening window or packaging onto the sensing membrane area₀ The method of manufacturing the inverted ISFET ( 10 ) of the present invention is now describedo The process is started with a wafer of silicon as the substrate ( 11 ) of the inverted ISFET ( 10 ) ₀ The substrate ( 11 ) is then deposited (31) with a layer of sensing membrane ( 12 ) and a layer of field oxide ( 19 ) at the front of the substrate ( 11 ) as shown in Figure 3a₀ The sensing membrane ( 12 ) is a silicon nitride ( Si₃N₄ ) layer and the field oxide layer ( 19 ) is a silicon dioxide ( Si0₂ ) layer₀ A layer of doped polysilicon ( 15 ) is then deposited (32) on the field oxide layer ( 19 ) as shown in Figure 3b. Then a sacrificial layer of field oxide^' ( 20 ) is deposited (33) on the doped polysilicon layer (15) and followed by a layer of silicon nitride ( Si₃N₄ ) (21) as shown in Figure 3c. The sacrificial layer of field oxide (20) is a layer of silicon dioxide (Si0₂) .

The process is then followed with a resist coating and patterning (34) to cover the part that is not to be etched as shown in Figure 3d. The doped polysilicon layer (15) is etched (35) with the source (13) and drain (14) regions using photoresist as shown in Figure 3e. The resist coating is then removed and performed (36) a channeling implant as shown in Figure 3f. The sacrificial layer of field oxide ( 20 ) and the layer of silicon nitride ( Si₃N₄ ) are then removed (37) as shown in Figure 3g. A protective layer of field oxide (23) is then deposited (38) on the wafer as shown in Figure 3h. The protective layer of field oxide (23) is a layer of silicon dioxide (Si0₂) .

A resist coating and patterning (25) for contact pad (22) is then performed (39) on the wafer leaving openings to provide access to the source (13) and drain (14) regions as shown in Figure 3i. The protective layer of silicon dioxide (Si0₂) is etched (40) respectively towards both source (13) and drain (14) regions, to provide contact access to said regions as shown in Figure 3j . The resist coating (23) is then removed and the metal contact pad (22) is sputtered (41) on the wafer as shown in Figure 3k.

A resist coating and patterning (24) for metal etching is then performed (42) on the wafer leaving the center portion uncovered as shown in Figure 31. The middle portion of the metal contact pad

(22) is then etched (43) and leaving the metal source contact ( 16 ) and the metal drain contact (17) in contacts with the source (13) and drain (14) regions respectively as shown in Figure 3m. The resist coating (24) is then removed (44) as shown in Figure 3n.

The middle portion from the back of the substrate (11) is then etched (45) using deep reactive ion etching (DRIE) or wet etching until the sensing membrane layer (12) to provide the window opening (18) to the sensing membrane (12) hence eliminating the requirement of the bonding process and additional substrate or packaging material. The metal contacts (16, 17) are provided on the opposing side of the sensing membrane (12), thus, when user injects samples to the opening window at the sensing membrane (12) the fluid will be isolated from the electrical conducting area hence prevents electrical shorting from occurring as shown in Figure 3o. The present invention is not limited in its present form and can be configured with additional features. For instance, the bottom of the substrate (11) can be etched or constructed with, but not limited to, microfluidic features such as microchannel , reservoir, micromixers, etc near the sensing membrane (12) area upon the formation of the opening window.

As will be readily apparent to those skilled in the art, the present invention may easily be produced in other specific forms without departing from its essential characteristics. The present embodiments is, therefore, to be considered as merely illustrative and not restrictive, the scope of the invention being indicated by the claims rather than the foregoing description, and all changes which come within therefore intended to be embrace therein .

Claims

1. An inverted ion-sensitive field effect transistor (ISFET) (10) comprising :

a substrate layer (11);

a sensing membrane (12) on said substrate layer (11);

a layer of field oxide ( 19 ) on said sensing membrane (12) ; doped source (13) and drain (14) regions on said layer of field oxide (19) ; and

characterized in that electrical contacts (16, 17) are provided to the respective source (13) and drain (14) regions on the opposing side of said sensing membrane (12) and said substrate layer (11) is windowed with an opening access (18) to said sensing membrane (12) to provide electrical isolation of the electrical contacts (16, 17) from said sensing membrane (12) .

2. The inverted ISFET (10) as claimed in claim 1, wherein said substrate layer (11) is a thin film silicon based layer.

3. The inverted ISFET (10) as claimed in claim 2, wherein said substrate layer (11) is a polysilicon layer.

4. The inverted ISFET (10) as claimed in claim 1, wherein said substrate layer (11) could be other types of substrates such as glass , silicon on insulator (SOI) and the likes.

5. The inverted ISFET (10) as claimed in claim 1, wherein said sensing membrane ( 12 ) is a nitride sensing membrane.

6. The inverted ISFET (10) as claimed in claim 5, wherein said sensing membrane ( 12 ) is silicon nitride ( S1₃N₄ ) .

7. The inverted ISFET (10) as claimed in claim 1, wherein said substrate layer (11) can be etched at the bottom of said substrate

(11) with microfludic features such as microchannel , reservoir, micromixers and the likes.

8. A method of manufacturing an inverted ISFET ( 10 ) comprising the steps of:

providing a_. substrate layer (11);

depositing (31) a layer of sensing membrane (12) on said substrate layer (11);

depositing (31) a layer of field oxide (19) on said sensing membrane

(12) ; depositing (32) a layer of doped polysilicon (15) on said field oxide, layer (19) ;

etching (35) the respective source (13) and drain (14) regions using photoresist; and

providing (44) the electrical contacts (16, 17) for said source (13) and drain (14) regions,

characterized in that said electrical contacts (16, 17) are provided on the opposing side of said sensing membrane (12) to provide electrical isolation of the electrical contacts (16, 17) from said sensing membrane (12) .

9. The method as claimed in claim 8, wherein said method further comprising the step of etching (45) a window opening (18) from the back of said substrate (11) to provide opening access to said

•15 sensing membrane (12).

10. The method as claimed in claim 8, wherein said step of etching (35) the respective source (13) and drain (14) regions using photoresist includes the steps of:

20 providing (33) a sacrificial layer of field oxide ( 20 ) on said doped polysilicon layer (15) ; providing (33) a layer of silicon nitride on said sacrificial layer of field oxide (20) ;

patterning and resist coating (34) to cover the part that is not to be etched;

removing (36) said resist coating after said source (13) and drain (14) regions are etched;

removing (37) said sacrificial layer of field oxide (20) and layer of silicon nitride; and

providing (38) a protective layer of field oxide (21) on said ISFET.

11. The method as claimed in claim 8, wherein said providing (44) the electrical contacts (16, 17) for said source (13) and drain (14) regions includes the steps of:

patterning and resist coating (39) to cover the part that is not to be etched;

etching (40) towards said source (13) and drain (14) regions to provide contact access to said regions;

removing (41) said resist coating (23);

sputtering (41) a metal contact pad (22) on said ISFET;

patterning (42) and resist coating (24) for metal etching with the center portion uncovered; and etching (43) said center portion of said metal contact pad (22) for forming said metal source contact (16) and metal drain contact (17) .