WO2011036212A1

WO2011036212A1 - Static frequency divider circuitry

Info

Publication number: WO2011036212A1
Application number: PCT/EP2010/064056
Authority: WO
Inventors: Weiran Cai; Frank Ellinger
Original assignee: Technische Universität Dresden
Priority date: 2009-09-24
Filing date: 2010-09-23
Publication date: 2011-03-31

Abstract

The present invention relates to a static frequency divider circuitry comprising a delay flip-flop related structure. An object of the present invention is to design a frequency divider circuitry that meets upcoming low power requirements without introducing special design constrains, working at supply voltage significantly lower than 3.0V and operation frequencies comparable to the current state of the art. This object is achieved through providing a static frequency comprising a delay flip-flop related structure including a master part and a slave part being operated by clock transistors arranged as emitter followers of the common collector transistors, combined to control both the master part and the slave part of the frequency divider by sharing one clock switch and one inverse clock switch and a latching unit being either a virtual latching unit capable to temporarily store charges or a real latching unit consisting of proper latching devices.

Description

Static frequency divider circuitry The present invention relates to a static frequency divider circuitry comprising a delay flip-flop related structure.

High-speed frequency dividers are widely used as typical basic blocks comprised in optical and wireless systems. For these applications the speed performance is really crucial. At the same time their power consumption has to be kept low to enlarge their power self-sustaining mode as much as possible and prevent these systems from frequent recharging. Two commonly used prototypes of dividers are the static- structure based divider and the dynamic-structure based one. The dynamic divider offers very high speed (see H. Knapp, et al., "A 79GHz dynamic frequency divider in SiGe bipolar technology," ISSCC Dig. Tech. Papers, pp. 208-209, Feb.

2000) . However, the limitation regarding the possible bandwidth restricts the use for many applications.

Exempted from this drawback, static dividers have gained a dominant position therein by demonstrating increasingly higher speeds.

Among different static frequency dividers the delay flip- flop (D flip-flop, DFF) based circuitry is one of the most commonly used ones. It can be realized in CMOS technologies, which are low cost but speed limited technologies, or in different bipolar technologies, like III/V based hetero- junction bipolar transistor (HBT) technologies, which provide much higher speed compared to the CMOS technologies but their realization is very expensive. Thus a good

alternative is the use of BiCMOS technologies, as they offer high speed performance and relatively low costs, being the precondition for mass production.

The above mentioned requirements for low power consumption and for system integration demand for low-voltage solutions.

The continuous scaling in CMOS, enabling signal processing circuits to operate at very low voltages, has been impacting the requirements for bipolar circuits, while bipolar

transistors do not yet possess the capability to scale down the junction voltages. Hence, especially for bipolar

circuits, advanced approaches allowing reduced supply voltages are required. For static frequency dividers, the D flip-flop based circuitries using emitter coupled logic (ECL) have been widely used for decades, and very high speeds up to 100GHz have been reported (see E. Laskin et al . , "Low-power, low-phase noise SiGe HBT Static Frequency Divider Topologies up to 100GHz," Proc. BCTM, pp. 1-4, Oct. 2006 and E. Laskin et al . , "170-GHz transceiver with on-chip antennas in SiGe technology," IEEE RFIC Dig. Tech. Papers, pp. 637-640, Jun. 2008). However, in 0.18pm BiCMOS

technology, for example, the stacks of differential pairs of transistors and loading resistors require a nominal supply voltage ranging from 3.3V to 5.5V. It is therefore necessary to rearrange the transistor stacks in a more proper

topology, while not losing the merit of emitter followers for high speed.

A variety of low-voltage solutions for static dividers have been proposed. But most of them are either operating at low speed or are accompanied by some special design constraints.

The divider using current mode logic (CML) with a single transistor switching stack can operate with a low voltage, but at a rather low speed (see S. Rylov and A. Rylyakov, "Static bipolar 11GHz SiGe divider with IV power supply," Proc. BCTM, pp. 79-81, Sep. 2003) .

Inductive peaking can efficiently improve the speed versus power consumption ratio, however, at the expense of a significantly increased chip area (see J. Kim, et al.,

"Circuit techniques for a 40Gb/s transmitter in 0.13μιη CMOS," ISSCC Dig. Tech. Papers, pp. 150-589, Feb. 2005). Based on clamping devices, a reduction of the supply voltage is possible down to IV with operation in saturation status (see G. Shuppener, C. Pala, and M. Modkhtari, "Investigation on low voltage low-power silicon bipolar design topology for high-speed digital circuits," IEEE J. Solid-State Circuits, vol. 35, pp. 1051-1054, July 2000). Its disadvantage is the considerable degradation in the speed.

The latch-based switched emitter follower (SEF) divider (see D. Kucharski and K. T. Kornegay, "A 40GHz 2.1V static frequency divider in SiGe using a low-voltage latch topology," IEEE RFIC Dig. Tech. Papers, pp. 461-464, Jun . 2005) demands two conditions of competitive currents to guarantee correct operation and thus the current for clock- transistors has to be offered beyond a lower limit.

Current low power high speed static frequency dividers consisting of standard master-slave D flop-flops realized in emitter-coupled logic, using series gating between clock and data input and operating at the optimum current density at which the peak cutoff frequency is found, exhibit operation frequencies such as 15GHz for a supply voltage of 3.6V in a 0,8pm Si bipolar technology (see H. Knapp et al, "A low power 15GHz frequency divider in a 0,8pm Silicon Bipolar Technology", IEEE Transactions on Microwave Theory and

Techniques, Vol. 48, N° 2, pp. 205-208, Febr . 2000) or 38GHz for a supply power of 3.0V in a 0.4pm SiGe bipolar

technology (see G. Ritzberger et al . "38GHz low-power static frequency divider in SiGe bipolar technology", IEEE, IV, pp. 413-416, 2002) . These DFF based ECL dividers can usually operate at around a half of the transition frequency f_t.

Fig. 1 shows a typical example of a frequency divider circuitry used in these cases: It comprises a master latch and a slave latch, each one including a sensing and a latching unit. The master as well as the slave latch is pulsed by its own clock and inverse clock switches, the clock transistors being the emitter followers of the sensing and latching transistors. As already mentioned, frequency divider circuitries have to follow the scaling in CMOS technologies. Therefore, an object of the present invention is to design a frequency divider circuitry that meets upcoming low power requirements without introducing special design constrains, working at supply voltage significantly lower than 3.0V and operation frequencies comparable to the current state of the art.

This object is achieved through providing a static frequency divider circuitry according to claim 1. The claims 2 to 10 reflect preferred embodiments of the invention.

The static frequency divider circuitry according to the invention principally comprises a delay flip-flop related structure, which means that the structure originated from a delay flip-flop structure, but has experienced substantial modifications, including means for signal input and signal output, clock transistors being operated by a clock switch and an inverse clock switch, a clock pulsed master part and a clock pulsed slave part, connections to the ground, each one of the master and the slave parts comprising a sensing unit and a latching unit and two common collector

transistors as to be known from prior art, but the clock transistors are arranged as first and second emitter

follower of the common collector transistors instead of directly following the emitters of the sensing and latching transistors of conventional, prior art static frequency divider circuitries, and they are combined to control both the master part and the slave part of the frequency divider by sharing one clock switch and one inverse clock switch between the master part and the slave part.

The latching unit of the master part and/or the slave part may be either a "virtual" latching unit realized by parts of the circuitry that are capable to temporarily store charges or a "real" latching unit consisting of proper latching devices .

To clarify, the term "master part" and "slave part" is used instead of "master latch" and "slave latch" of the related prior art circuitries, as by the new arrangement of the clock transistors into a so called "clock sharing" structure of the described invention, the "master part" and the "slave part" is an arrangement which is an only derived one from the typical "master latch" and "slave latch" arrangement.

To go now into more detail, the clock transistors are arranged as first and second emitter follower of the common collector transistors such that the first clock transistor follows the first inverse common collector transistor, the first inverse clock transistor follows the first common collector transistor, the second clock transistor follows the second inverse common collector transistor and the second inverse clock transistor follows the second common collector transistor;

and the clock sharing concept between master part and slave part might be described in more detail as follows: The inverse clock switch controls the base of the first clock transistor and the first inverse clock transistor, the clock switch controls the base of the second clock transistor and the second inverse clock transistor; the first clock transistor and the first inverse clock transistor switch the sensing unit of the slave like part and the latching unit of the master part, the second clock transistor and the second inverse clock transistor switch the sensing unit of the master part and the latching unit of the slave part.

Generally explained and compared to prior art cited above, the inverse clock switch of the proposed clock sharing frequency divider circuitry combines the inverse clock switches of the latching unit of the master part and of the sensing unit of the slave part. The clock switch does in the same manner. The feedback from the inverted output is also connected to the input of the latching unit in the master part.

The clock sharing static frequency divider circuitry

described here is of cause not restricted to the use of bipolar technology though used expressions and figures might lead to this impression at a first glance, especially by the use of expressions and symbols for bipolar transistors. For a person skilled in the art it is evident that all bipolar transistors might also be replaced by field-effect

transistors, meaning that the "base" is replaced by the "gate", the "collector" is replaced by the "source" and the "emitter" is replaced by the "drain" respectively.

This static frequency divider circuitry according to the invention offers two major advantages:

Firstly, removing the clock transistors from the sensing unit and the latching unit, which are both realized by transistor pairs in prior art, and inserting them in the middle of the emitter followers of the common collector transistors reduces the number of transistor layers in the sensing and latching units, and consequently offers the possibility to lower the supply voltage.

Inserting the clock transistors in the emitter followers of the common collector transistors offers the possibility to bias the clock transistors at higher voltage than the sensing units. This is due to the fact that the common- collector transistors are biased at higher voltage than the sensing unit and thus make the voltage head room for the clock transistors beneath. Secondly, as the sensing and the latching transistors are not followed anymore by the clock transistors as it is the case in prior art, it is the first step to individually optimize the sensing and latching currents for speed and current consumption.

According to a further aspect of the present invention, the sensing units of the master part as well as of the slave part are individually connected to the ground presenting individual sensing currents. Not coupling the grounding between the sensing unit and the latching unit (if there is any real latching unit as it is obligatory in prior art) thus is the second step to individually optimize the sensing and latching currents for speed and current consumption.

For a further preferred embodiment of the invention the emitters of the first and second clock transistors are combined and commonly connected to the ground, presenting a first tail current being the result of the combination of the individual clock currents of the first and second clock transistors, and/or the emitters of the first inverse and second inverse clock transistors are combined and commonly connected to the ground presenting a second tail current being the result of the combination of the individual clock currents of the first inverse and second inverse clock transistors. This is to keep the clock transistors

differential, that is, to maintain two complementary signals sent on two separate paths and to enhance the common mode rejection.

As the static frequency divider according to the invention allows to optimize individually the sensing and latching currents, the sensing unit as well as the latching unit of the master part and/or of the slave part gain independency from each other. That is, design constrains are minimized. Thus, in a further preferred embodiment the sensing unit of the master part and/or the sensing unit of the slave part can be realized by any kind of a user defined amplifier. As a condition, these substitutive amplifiers only have to offer sufficient gain to the loop.

As an advantageous and certainly commonly used embodiment of the invention, the sensing unit of the master part comprises two master sensing transistors and/or the sensing unit of the slave part comprises two slave sensing transistors arranged in a flip-flop like set-up, and load resistances connected in series to these sensing transistors. This represents the way to constitute comparable static frequency dividers in prior art: A few clear changes in prior designs of static frequency dividers described above lead to a clock sharing static frequency divider design according to this invention, keeping the opportunity to manufacture the new clock sharing static frequency divider using well known semiconductor manufacturing technologies that were also applied to manufacture prior art static frequency dividers. There is no add on to manufacturing complexity for the new clock sharing static frequency divider according to this invention working at same high speed frequencies but

significantly lower supply voltage and thus lower power consumption, with a less complex circuitry design than related prior art static frequency dividers.

In a further preferred embodiment of the clock sharing static frequency divider according to this invention charges are stored by parasitic capacitances of the circuitry, forming a virtual latching unit, without using a real latching unit in the master part and/or in the slave part. It is a further result of the gained freedom in sizing of the sensing unit and the latching unit. This is possible at a sufficiently high operation frequency, which facilitates very fast switching. This advanced clock-sharing structure can further increase the maximum frequency by 10% and reduce the power consumption by 10-20%, compared to a basic version of clock-sharing dividers using real latching units, as the omission of the real latching unit lightens the "tank" of the entire circuitry so that it can work at a higher

frequency . To determine, if the clock sharing static frequency divider circuitry can be applied without a real latching unit, the input power to input frequency diagram has to be simulated for a defined design using the characteristics of defined a manufacturing technology. If the desired working point is within the operation area of this input power to input frequency diagram, the clock sharing static frequency divider circuitry can be used without a real latching unit in the master part and/or the slave part. Otherwise the circuitry design has to be adapted to come to another embodiment of this invention especially applicable to lower operation frequency: For these cases each one of the master and the slave parts also has to comprise a real latching unit individually connected to the ground and presenting individual latching currents as a different embodiment of this invention.

Here again it is advantageous, if the latching unit of the master part contains two latching transistors and/or the latching unit of the slave part contains two slave latching transistors arranged in a flip-flop like set-up by the same argument of using the already existing well known

semiconductor manufacturing technologies that were also applied to manufacture prior art static frequency dividers.

The latter embodiment of the clock sharing static frequency divider circuitry according to the invention is the one to be the most easily comparable to prior art circuitries of static frequency dividers. That is why this circuitry is described in more detail on transistor level here though it has to be pointed out that it is more advantageous than the prior art circuitries, but by far not the most advantageous of the clock sharing static frequency divider circuitries according to the invention.

As a more concretized further embodiment of the static frequency divider circuitry according to the invention described here, it is deducible, that the sizes of the sensing transistors as well the sizes of latching

transistors of both the master part as well as of the slave part are individually adjustable.

Usually, the latching transistors need less current and a smaller size than the sensing transistors or sensing units, because the clamping structure offers positive feedback in the latching units. Reducing the size of the latching transistors would help to decrease the charging time and also the current consumption, which aids to achieve high speed. However, in the conventional approach of the prior art, it is not possible to make the currents flowing through the sensing and the latching transistors unsymmetrical , since they are paired currents for the clock switch and the inverse clock switch transistors. Consequently, the

corresponding transistors of conventional, prior art designs have to be equally sized and biased, as to maintain two complementary signals sent on two separate paths. In

contrast, in the proposed clock sharing static frequency divider circuitry approach according to the invention, the latching current can be made much lower than the sensing current, and thus it is possible to make the size of the latching transistors smaller than that of the sensing transistors .

The invention, as well as further features and advantages of the invention will be best understood by reference to the following detailed description, given purely by way of a non-restrictive indication, to be read in conjunction with the accompanying drawings : Fig. 1 illustrates a static frequency divider circuitry as to be known from prior art.

Fig. 2 illustrates a "generic" clock sharing static

frequency divider circuitry according to this invention, presented in the most general way, using any kind of

amplifier in the sensing units of the master part and the slave part.

Fig. 3 illustrates a clock sharing static frequency divider circuitry according to the invention as of fig. 2 using bipolar transistors in the sensing units of the master part and the slave part, but not using a real latching unit.

Figs. 4a and 4b represent two input power to input frequency diagrams, fig. 4a being the input power to input frequency diagram of a clock sharing static frequency divider

circuitry according to this invention with only a virtual latching unit, fig 4b being the input power to input

frequency diagram of the same circuitry but with an added real latching unit.

Fig. 5 illustrates a clock sharing static frequency divider circuitry according to the invention as of fig. 3 using bipolar transistors in the sensing units of the master part and the slave part and comprising real latching units also realized by bipolar latching transistors.

Fig. 6 shows a chip micrograph of a divide-by-2 frequency divider chip as an illustrative embodiment of the invention realized in a 0,18pm BiCMOS technology: the chip has a total chip area of 720μιη ^χ 800μιη and active area of 300pm ^χ 370pm

Fig. 7 shows the measured output waveform with a 26GHz input for the realized clock sharing static frequency divider circuitry of fig. 6.

Fig. 8 shows the output spectrum of the realized clock sharing static frequency divider circuitry of fig. 6 at 13GHz with a power peak of -12,89dBm.

Fig. 9 represents the conceptual diagram of a low voltage divide by 2/3 with realized the clock sharing static frequency divider circuitry according to the invention. Fig. 10 illustrates how to realize the same clock sharing static frequency divider circuitry as of fig. 5, but using field effect transistors instead of bipolar transistors. As a first description of certain embodiments of the clock sharing static frequency divider circuitry according to the invention and its applications it will be shown in more detail, how to choose the appropriate circuitry for a special application.

Starting with the most generic circuitry design as show in fig. 2, having determined the characteristics of the desired frequency divider and the manufacturing technology to use, the decision on the concrete physical form of the amplifier A_v of the sensing units SI, S2 is taken. For manufacturing and simplicity reasons most commonly sensing transistors D i , DNi , D₂ , DN₂ will be used as shown in fig. 3, which is supposing that it is possible to use the circuitry without a real latching unit LI, L2. Taking into account this concrete circuitry and the characteristics of the devices, an input power to input frequency diagram of this circuitry is simulated. Fig. 4a shows such an input power to input frequency diagram of a clock sharing static frequency divider circuitry according to this invention with only a virtual latching unit in the master part 1 and the slave part 2. The curve indicates the simulated minimum input power for correct operation in dependency from the input frequency. If the desired working point of the frequency divider is situated within the operation area 3, it is possible to use the clock sharing static frequency divider circuitry without a real latching unit LI, L2. Otherwise, the clock sharing static frequency divider circuitry will be redesigned by introducing real latching units LI, L2, mostly each one consisting of two latching transistors Qi, QNi, Q₂, QN₂, and the simulation of the input power to input frequency diagram is redone. Fig. 4b shows the input power to input frequency diagram of the same clock sharing static frequency divider circuitry as for fig. 4a, but with added real latching unit LI, L2 in the master part 1 and the slave part 2. Here again, it is checked if the desired working point is situated within the simulated operation area 3. If this is still not the case, the latching transistors Qi, QNi, Q₂, QN₂ might be adapted in size with reference to the sensing transistors Di, D i , D₂, DN₂.

To very concretely describe the circuitry used for the clock sharing static frequency divider circuitry for the divide- by-2 case, in case of that real latching transistors Qi, QNi, Q₂, QN₂ are necessary, it has to be added to the description already given above that

the first clock transistor Ci switches the slave sensing transistor D₂ as well as master latching transistor Qi, the first inverse clock transistor C i switches the inverse slave sensing transistor DN₂ as well as inverse master latching transistor QNi,

the second clock transistor C₂ switches the inverse master sensing transistor D i as well as the slave latching

transistor Q₂,

and the second inverse clock transistor CN₂ switches the master sensing transistor Di as well as the inverse slave latching transistor QN₂, and

the collector of the master sensing transistor Di as well as the collector of the master latching transistor Qi is

connected to the base of the first common collector

transistor Fi;

the collector of the inverse master sensing transistor D i as well as the collector of the inverse master latching

transistor Q i is connected to the base of the first inverse common collector transistor FNi,

the collector of the slave sensing transistor D₂ as well as the collector of the slave latching transistor Q₂ is

connected to the base of the second common collector

transistor F₂ and

the collector of the inverse slave sensing transistor DN₂ as well as the collector of the of the inverse slave latching transistor QN₂ is connected to the base of the second inverse common collector transistor FN₂.

As already stated, this embodiment of the clock sharing static frequency divider circuitry is not the most

advantageous one concerning power consumption, but the one to be the most easily comparable to prior art delay flip- flop based static frequency divider circuitries as of fig. 1, so to understand the operation mechanism of the clock sharing static frequency divider circuitry according to this invention :

When the inverse clock switch CLKN is ON in the clock sharing static frequency divider, the latching transistor Q i and the inverse latching transistor Q i of the master part 1 store the signal and the sensing transistor D₂ and the inverse sensing transistor DN₂ of the slave part 2 sense the signal passing from the latching transistor Q i and the inverse latching transistor Q i of the master part 1. The sensing transistor D i and the inverse sensing transistor DN1 of the master part 1 and the latching transistor Q₂ and the inverse latching transistor QN₂ of the slave part 2 are in a floating status at that time. Correspondingly, when the inverse master latch clock switch CLKN_m and the inverse slave latch clock switch CLKN_S are ON in a prior art delay flip-flop based static frequency divider circuitry, the master latching transistor Q_m and the inverse master latching transistor QN_m store the signal and the slave sensing transistor Ds and the inverse slave sensing transistor DN_S sense the signal passing from the master latching transistor Q_m and the inverse master latching transistor QN_m. The master sensing transistor D_m and the inverse master sensing transistor DN_m as well as the slave latching transistor Q_s and the inverse slave latching

transistor QN_S are in the floating status at that time.

In the second half clock period, the clock switch CLK is ON. For the clock sharing static frequency divider according to this invention the latching transistor Q₂ and the inverse latching transistor QN₂ of the slave part 2 store the signal from the sensing transistor D₂ and the inverse sensing transistor DN₂ of the slave part 2 of the previous status, and the sensing transistor D i and the inverse sensing

transistor DNi of the master part 1 sense the signal passing from the latching transistor Q₂ and the inverse latching transistor QN₂ of the slave part 2.

Correspondingly, when the master latch clock switch CLK_m and the slave latch clock switch CLK_S are ON in a prior art delay flip-flop static frequency divider circuitry, the slave latching transistor Q_s and the inverse slave latching

transistor QN_S store the signal and the master sensing transistor D_m and the inverse master sensing transistor DN_m sense the signal passing from the slave latching transistor Q_s and the inverse slave latching transistor QN_S .

In terms of functionality, the clock sharing static

frequency divider circuitry can be regarded as a remodeled version of the delay flip-flop based static frequency

divider, with the following simple mapping relations: Ci+C i <—> CN_m+C_s; C₂+CN₂ <—> CN_S+C_m; Ό₁ <—> D_m; DN_X <—> DN_m; D₂ <"> D_s; DN₂ DN_S; Q₁ Q_m; QN_X QN_m; Q₂ Q_s and QN₂

QN_S, with the difference, that there is no individual latch in the clock sharing static frequency dividers according to this invention.

The designed "divide-by-2" frequency divider presented in fig. 6 consists of a clock sharing static frequency divider circuitry core according to an embodiment of the invention shown in fig. 5, whose choice is discussed above, an input buffer and an output buffer to drive a 50Ω load for

measurement purposes. The active area occupies a total of 300pm x 370pm.

The clock sharing static frequency divider circuitry core comprises a master part and a slave part, the second

consecutive to the first one, substituting the master and slave latches in a prior art delay flip-flop static

frequency divider.

The clock transistors Ci, CNi, C₂ and CN₂ are sized to operate at optimum current density, corresponding to the peak cutoff frequency. The current is then determined by the emitter followers, which are designed to offer sufficient current- switching speed. The ratio of currents I _SI / I _LI , I _S2 / I _L2 and the ratio of the sizes of the sensing transistors Di, DNi, D₂, DN₂ versus the latching transistors Qi, QNi, Q₂, QN₂ are both set as 4:1, as to achieve higher speed and to lower the supply current. The supply currents for the sensing transistor pair IS1, IS2, the latching transistor IL1, IL2 pair and the clock transistor pair I_Ci , Ic₂ are 2mA, 0.5mA and 2mA, respectively, which sum up to 9mA for the entire divider core. The current sources are implemented with bipolar transistors F i , FNi , F₂, FN₂ and impedance enhancing resistors RL, which could be replaced by MOSFETs or resistors when even lower voltage operation is required. The divider core consumes 20.7mW from a nominal 2.3V supply and 17.1mW from a 1.9V supply. In the layout aspect, special care has to be taken with respect to the symmetry, since the clock sharing static frequency divider is fully differential.

Furthermore, based on simulations on schematic level, the clock-sharing frequency divider according to the invention is compared to a related prior art delay flip-flop-based divider. The dividers are optimized under the following boundary conditions: As a first condition the same total current of 9mA is applied for the two static frequency divider parts (the master part and the slave part) . As a second condition, input and output buffers contain the same structure for necessary bias adjustment. As a third

condition they present the same output voltage amplitude. And as a forth condition the nominal supply voltages are 2.3V for the clock sharing static frequency divider

according to the invention and 3.5V for a conventional, related prior art delay flip-flop-based static frequency divider. The simulation result indicates that the two approaches yield a very similar maximum frequency.

Nonetheless the clock sharing static frequency divider according to this invention consumes 34% less supply power than the conventional prior art frequency divider. This confirms that the clock sharing static frequency divider has translated the functionality of the conventional prior art delay flip-flop-based frequency dividers to low voltages without loss of speed performance.

The chip was fabricated in an IBM 0.18pm BiCMOS technology featuring hetero- unction bipolar transistors (HBT) with a transit frequency f_T of 60GHz. On-wafer measurements were made at the 50Ω terminations. All results presented

consecutively are not adjusted, in particular by the losses of the measurement setup, mainly determined by cables and probe tips amounting to around 3dB for the input and around 3dB for the output, as the original plots appearing in the measurement devices are shown. Accordingly, at the chip interfaces, the values are more favorable than those

presented . The divider operates up to 26GHz. The consumption of the input and output buffers included, the circuit consumes a total power of only 55mW from a 2.3V supply voltage. At 1.9V supply voltage and 40mW supply power, it can operate up to 25GHz. The input and output waveforms at 26GHz and 2.3V, and the corresponding output spectrum are shown in fig. 7 and fig. 8, respectively.

With both supply voltages, the clock sharing static

frequency divider core according to the invention consumes, as already mentioned, only 9mA. The ratio of maximum

operating frequency versus transit frequency f_op/f_T is 41.7%.

Furthermore, the advanced version of the proposed clock sharing structure without latching components as shown in fig. 3 can even operate at higher speed and consumes less power .

Therefore the clock sharing static frequency divider

circuitry according to the invention showed impressively its ability not only to translate almost all the merits of the conventional prior art delay flip-flop-based static

frequency dividers to low supply voltages, but also to offer a freedom to adjust the currents for sensing and latching units of the master parts and the slave parts separately. This latter characteristic also contributes for both higher speed and lower current consumption. The clock sharing static frequency divider circuitry according to the

invention is free of any special design constraints, which has reduced the design complexity.

The proposed circuitry of clock sharing static frequency dividers is not limited to the design of divide-by-2 clock sharing static frequency dividers. It can be extended to other divider-based circuits, such as divide-by-2 /3 static frequency dividers, which are the key blocks in multi- modulus-dividers (MMD) .

With the clock-sharing static frequency divider circuitry according to this invention, only four clock-sharing static frequency divider circuitry units are needed to be used in realizing a divide-by-2 /3 clock sharing static frequency divider. The concept of sharing the clock transistors has now extended to more neighboring units, as shown in Fig. 9.

Herein, the nodes Modi_n and Mod_out are the input and output nodes for consecutive stages, and R is the control bit. An additional branch with two additional sensing/latching units Qs/_L2 and Ps/_L2 serving as master part 1 and slave part 2 and two additional clock units Clock₃, Clock₄ comprising the common collector transistors and the clock transistors are introduced as an additional feedback loop to the already existing divide-by-2-clock sharing static frequency divider circuitry branch.

The clock unit Clock₃ is thus used to connect the consecutive sensing/latching units QS/_L2 and PS/_L2? while the clock unit Clock₂ now serves not only P_S/LI and QS/LI, but also Q_S/L2 in the lower branch.

That is why the merits discussed above in divide-by-2s can be completely mapped onto divide-by-2/3s, which means that an entire multi-modulus-divider can hence be realized operating at the same low voltage as the described divide- by-2 clock sharing static frequency divider.

Static frequency divider circuitry Reference signs master part

master latch

slave part

slave latch

operation area (of the input power to input frequency diagram)

sensing unit (of the master part)

sensing unit (of the slave part)

real latching unit (of the master part)

real latching unit (of the slave part)

common collector transistor (for the master part) inverse common collector transistor (for the master part )

common collector transistor (for the slave part) inverse common collector transistor (for the slave part )

clock transistor (of the master part)

inverse clock transistor (of the master part) clock transistor (of the slave part)

inverse clock transistor (of the slave part)

clock switch

inverse clock switch

output signal

inverse output signal

amplifier

sensing current (of the master part)

sensing current (of the slave part)

latching current (of the master part)

latching current (of the slave part)

clock tail current (out of the master part)

clock tail current (out of the slave part)

sensing transistor (of the master part)

inverse sensing transistor (of the master part) sensing transistor (of the slave part)

inverse sensing transistor (of the slave part) load resistance

latching transistor (of the master part)

inverse latching transistor (of the master part) latching transistor (of the slave part) inverse latching transistor (of the slave part) master common collector transistor

inverse master common collector transistor

slave common collector transistor

inverse slave common collector transistor

master clock transistor

inverse master clock transistor

slave clock transistor

inverse slave clock transistor

master clock current

slave clock current

master inverse common collector transistor current master common collector transistor current

slave inverse common collector transistor current slave common collector transistor current

master sensing transistor

inverse master sensing transistor

slave sensing transistor

inverse slave sensing transistor

master latching transistor

inverse master latching transistor

slave latching transistor

inverse slave latching transistor

Clock_! first clock unit

Clock₂ second clock unit

Clock₃ third clock unit

Clock₄ forth clock unit

Qs/Ll first master sensing latching/unit

Qs/L2 second master sensing latching/unit

Ps/Ll first slave sensing latching/unit

Ps/L2 second slave sensing latching/unit

MOGlin input node for consecutive stages

MOClout output node for consecutive stages

R control bit

Claims

frequency divider circuitry

A static frequency divider circuitry comprising a delay flip-flop related structure, including means for signal input and signal output, clock transistors (CI, CN1, C2, CN2) being operated by a clock switch (CLK) and an inverse clock switch (CLKN) , a clock pulsed master part (1) and a clock pulsed slave part (2), connections to the ground, each one of the master (1) and the slave parts (2) comprising a sensing unit (SI, S2) and a latching unit and two common collector transistors (FN1, Fl, FN2, F2),

characterized in that

the clock transistors (CI, CN1, C2, CN2) are arranged as first and second emitter follower of the common collector transistors (FN1, Fl, FN2, F2),

combined to control both the master part (1) and the slave part (2) of the frequency divider by sharing one clock switch (CLK) and one inverse clock switch (CLKN) .

The static frequency divider circuitry according to claim 1, characterized in that the latching unit is either a virtual latching unit capable to temporarily store charges or a real latching unit (LI, L2)

consisting of proper latching devices.

The static frequency divider circuitry according to claim 1 or 2, characterized in that the common

collector transistors (Fi, FNi, F₂, FN₂) are biased at higher voltage than the sensing units (SI, S2) .

The static frequency divider circuitry according to any of the claims 1 to 3, characterized in that the sensing units (SI, S2) of the master part (1) as well as of the slave part (2) are individually connected to the ground presenting individual sensing currents (Isi, Is2) ·

The static frequency divider circuitry according to any of the claims 1 to 4, characterized in that the

emitters of the first (Ci) and second clock transistors (C₂) are combined and commonly connected to the ground presenting a first tail current (Ici) and/or that the emitters of the first inverse (CNi) and second inverse clock transistors (CN₂) are combined and commonly connected to the ground presenting a second tail current (Ic2) ·

The static frequency divider circuitry according to any of the claims 1 to 5, characterized in that the sensing unit (SI) of the master part (1) and/or the sensing unit (S2) of the slave part (2) is realized by any kind of a user defined amplifier (A_v) .

The static frequency divider circuitry according to any of the claims 1 to 6, characterized in that the sensing unit (SI) of the master part (1) comprises two master sensing transistors (Di, DNi) and/or the sensing unit (S2) of the slave part (2) comprises two slave sensing transistors (D₂, DN₂) arranged in a flip-flop like set^¬ up, and load resistances (R_L) connected in series to these sensing transistors (Di, DNi, D₂, DN₂) .

The static frequency divider circuitry according to any of the claims 1 to 7, characterized in that the

latching unit is realized by a virtual latching unit storing the charges by parasitic capacitances of the circuit .

The static frequency divider circuitry according to any of the claims 1 to 7, characterized in that each one of the master (1) and the slave parts (2) also comprises a real latching unit (LI, L2) individually connected to the ground and presenting individual latching currents ( ILI IL2 ) ·

The static frequency divider circuitry according to claim 9, characterized in that the latching unit (LI) of the master part (1) contains two latching

transistors (Qi, QNi) and/or the latching unit (L2) of the slave part (2) contains two slave latching

transistors (Q₂, QN₂) arranged in a flip-flop like set^¬ up .

The static frequency divider circuitry according to claim 9 or 10, characterized in that the sizes of the sensing transistors (Di, DNi, D₂, DN₂) as well the sizes of latching transistors (Qi, QNi, Q₂, QN₂) of both the master part (1) as well as of the slave part (2) are adjusted individually.