WO2011034844A2 - Apparatus and method for synchronization of trellis states in a network - Google Patents

Abstract

Communications systems often use networks including separately located transmitters and exciters for signal transmission. An apparatus and method for synchronization of trellis states in a network are provided. The apparatus and method provide for generating a data stream including at least one training sequence (402), generating trellis initialization information based on the data stream (404), inserting the trellis initialization information into the data stream in a predetermined location (406). The present disclosure further provides for inserting in the data stream a packet for determining when to perform a trellis state reset. In certain embodiments, the packet includes a bit for determining when to selectively disable parity replacement of the data stream to synchronize trellis states across multiple exciters.

Description

APPARATUS AND METHOD FOR SYNCHRONIZATION OF

TRELLIS STATES IN A NETWORK

REFERENCE TO RELATED PROVISIONAL APPLICATION

This application claims priority from provisional application No. 60/828,811 fi ed on September 16, 2009, provisional application No. 61/248,626 filed on October 5, 2009, provisional application No. 61/253,244 filed on October 20, 2009 and provisional application No. 61/279,929 filed on October 28, 2009, the contents of which are hereby incorporated by reference in their entities.

TECHNICAL FIELD OF THE INVENTION

The present disclosure generally relates to broadcast systems and signal processing, and more particularly, to an apparatus and method for synchronization of trellis states in a network.

BACKGROUND OF THE INVENTION

Television broadcast systems throughout the world have migrated from the delivery of analog audio and video signals to the delivery of digital audio and video signals using modem digital communications systems. For example, in the United States, the Advanced Television Standards Committee (ATSC) has developed a standard called "ATSC Standard: Digital Television Standard A/53" (the A/53 standard). The A/53 standard defines how data for digital television broadcasts should be encoded and decoded. In addition, the U.S. Federal Communications Commission (FCC) has allocated portions of the electromagnetic spectrum for television broadcasts. The FCC assigns a contiguous 6 Megahertz (MHz) channel within the allocated portion to a broadcaster for transmission of terrestrial (i.e., not cable or satellite) digital television broadcasts. Each 6 MHz channel has a channel capacity of approximately 19 megabit (Mb)/second based on the encoding and modulation format in the A/53 standard. Furthermore, the FCC has mandated that transmissions of terrestrial digital television data through the 6 MHz channel must comply with the A/53 standard. Digital broadcast signal transmission standards, such as the A/53 standard, define how source data (e.g., digital audio and video data) should be processed and modulated into a signal that is transmitted through the channel. The processing adds redundant information to the source data so that a receiver that receives the signal from the channel may recover the source data, even if the channel adds noise and multi-path interference to the transmitted signal. The redundant information added to the source data reduces the effective data rate at which the source data is transmitted but increases the potential for successful recovery of the source data from the transmitted signal.

The A/53 standard development process was focused on high definition television (HDTV) and fixed reception. The system was designed to maximize video bit rate for the large high resolution television screens that were already beginning to enter the market. Transmissions broadcast under the ATSC A/53, or legacy encoding and transmission, standard present difficulties for mobile receivers.

Recognizing this fact, in 2007, the ATSC announced the launch of a process to develop a standard that would enable broadcasters to deliver television content and data to mobile and handheld devices via their digital broadcast signal, commonly known as ATSC mobile/handheld (M/H) or A/153 (the A/153 standard). Changes to the legacy transmission standard include an additional encoding scheme to introduce further data redundancy. The additional encoding has been adapted to better perform with advanced receivers in mobile, handheld and pedestrian devices while still remaining backward compatible with the legacy A 53 standard. The proposed changes also allow operation of existing ATSC services in the same radio frequency (RF) channel without an adverse impact on existing receiving equipment. The proposed changes also encompass use of single frequency networks (SFNs) for broadcasting mobile content. Referring to FIG. 1 , an exemplary ATSC broadcast system 100 including a standard, or main transport stream (TS Main), system 112, i.e., existing or legacy system, and a M/H (mobile/handheld) stream system 14 is illustrated. Each system 112 and 114 feeds a M/H framing or signaling channel 116 which established and controls the specific structure for each system. After the data packets are processed by the M/H framing channel 116, the data packets are passed to a plurality of transmitters or transmission sites 17a - 117n, where each transmitter 17a - 117n includes an exciter 118a - 118n for modulating the data packets onto a carrier signal for transmission via antenna 120a - 120n.

In SFNs, two or more transmitters 117a - 117n with overlapping coverage send the same program content simultaneously on the same frequency. The 8 vestigial sideband (VSB) modulation used by ATSC allows SFN transmissions. To allow regular channel approximation, ATSC M/H provides for additional training sequences. An additional standard, ATSC A/110, defines a method to synchronize the ATSC modulator as part of each transmitter 1 7a - 117n. In systems, such as an ATSC SFN, synchronization through encoder states, such as the trellis encoder states, is usually done. The trellis encoder states of the exciter 118a - 118n at each transmission site need to be identical in order for symbols emitted from each transmitter 117a - 1 7n to be identical.

The A/110 standard sets up the trellis encoder of the exciters 118a - 1 8n in a p re-calculated way for all transmitters 117a - 17n of the SFN. The A 110 standard describes how the trellis state that should exist in the encoder of each exciter 118a - 118n at a specified time can be predicted and sent as ancillary information to the multitude of encoders, i.e., to the encoders used in exciters 118a - 118n at the plurality of transmission sites 117a - 117n. Each of the multitude of encoders in exciters 1 8a - 118n uses this trellis state information to force a known internal trellis state at the predetermined time. Because the bitstream that enters each encoder used in exciters 118a - 118n is identical for all times going forward after the forcing action, the trellis states remain the same for all symbols across all encoders of the exciters 118a - 118n. In such an SFN, the ATSC-M/H multiplexer 116 and exciters 118a - 118n used in transmitters 117a - 117n are synchronized by a global positioning system (GPS) reference. The ATSC-M/H multiplexer 116 operates as a network adapter and inserts time stamps in the transport stream. Each exciter 118a - 118n of the transmitters 117a - 117n analyzes the time stamp and delays the transport stream before it is modulated and transmitted. Eventually, all transmitters 117a - 117n in the SFN generate a synchronized signal.

However, using ATSC A/110 in the ATSC M/H mobile broadcast transmission has shortcomings. For instance, there is significant complexity at the multiplexer (mux) used in the transmitters 117a - 117n (known as a Distributed Transmission (DTx) Adapter or DTxA) to calculate the trellis state needed at the various exciters 118a - 118n in an SFN network. The complexity grows linearly with the number of retransmissions, as each hop requires its own data processing model at the mux/DTxA. Further, as systems such as A/153 (i.e. ATSC mobile) continue expansion of use, certain network topologies relating to the mobile signaling create additional prohibitive complications with such data processing at the mux/DTxA. The complications may include the inability or impossibility to predict the trellis state under the provision that some additional content is multiplexed into the transmission at a point downstream in the system from the central feed to the multitude of encoders.

One possible approach to addressing these problems involves using a mechanism inherent to the A/153 standard to synchronize the trellis state, by modifying a set of predetermined parity bytes at a predetermined time during transmission and synchronization in order to drive the trellis state to a known value, such as zero. However, the process does not work well in conjunction with full legacy (or A/53) transmission, since the prescribed point of synchronization happens within mobile data. The method produces errors inherent in the transmission, although the errors appear in packets that would otherwise be unused by the legacy system, and in bytes that are unused by the mobile system. Including a distinct packet inserted into the legacy stream within which the same trellis synchronization mechanism may address the legacy transmission, but the resulting separate method of synchronization is cumbersome from management, specification, and implementation perspectives. Further, trellis state forcing may produce a disturbance in the encoder trajectory whose effect is difficult to predict. A simpler approach to synchronization of the trellis state in the transmission system is desirable. SUMMARY

An apparatus and method for synchronization of trellis states in a network are provided!

According to one aspect of the present disclosure, a method for synchronization of trellis states in a network is provided, the method including the steps of generating a data stream including at least one training sequence, generating trellis initialization information based on the at least one training sequence in the data stream, and inserting the trellis initialization information into the data stream in a predetermined location.

According to another aspect, an apparatus is provided including a pre- processor that generates a data stream including at least one training sequence, a post-processor, coupled to the pre-processor, that encodes the generated data stream and generates trellis initialization information based on the at least one training sequence in the data stream, and a trellis formatter, coupled to the postprocessor, that inserts the trellis initialization information into the generated data stream in a predetermined location.

According to a further aspect, a method for synchronization of trellis states in a network includes the steps of generating a data stream including at least one training sequence, and inserting a packet in the data stream, the packet for determining when to perform a trellis state reset, the packet including a location in the data stream where the reset is to be applied.

In yet another aspect of the present disclosure, an apparatus is provided including a pre-processor that generates a data stream including at least one training sequence, and a packet multiplexer that inserts a packet in the data stream, the packet for determining when to selectively disable parity replacement of the data stream at each of the plurality of exciters. BRIEF DESCRIPTION OF THE DRAWINGS

These, and other aspects, features and advantages of the present disclosure will be described or become apparent from the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings.

In the drawings, wherein like^■ reference numerals denote similar elements throughout the views:

FIG. 1 is a block diagram of an Advanced Television Standards Committee (ATSC) broadcast system. FIG. 2 is a block diagram of a studio side of a studio transmitter link (STL) in accordance with an embodiment of the present disclosure.

FIG. 3 is a block diagram of an exciter of a STL in accordance with an embodiment of the present disclosure.

FIG. 4 is a flowchart illustrating an exemplary process for synchronizing trellis states in a plurality of exciters in a network in accordance with the present disclosure. FIG. 5 is a table illustrating trellis reset byte storage indexing in accordance with the present disclosure.

FIG. 6 is an illustration of nibble mapping in post-processor input order in accordance with the present disclosure.

FIG. 7 is a block diagram of a trellis encoder in accordance with an embodiment of the present disclosure. FIG. 8 is an illustration of trellis state progression in accordance with an embodiment of the present disclosure.

FIG. 9 is a block diagram of a studio side of a STL in accordance with another embodiment of the present disclosure.

FIG. 10 is a flowchart illustrating an exemplary process for synchronizing trellis states in a plurality of exciters in a network in accordance with another embodiment of the present disclosure.

FIG. 1 1 is an ATSC M/H data stream in accordance with an embodiment of the present disclosure.

It should be understood that the drawing(s) is for purposes of illustrating the concepts of the disclosure and is not necessarily the only possible configuration for illustrating the disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

It should be understood that the elements shown in the FIGS, may be implemented in various forms of hardware, software or combinations thereof. Preferably, these elements are implemented in a combination of hardware and software on one or more appropriately programmed general-purpose devices, which may include a processor, memory and input/output interfaces. Herein, the phrase "coupled" is defined to mean directly connected to or indirectly connected with through one or more intermediate components. Such intermediate components may include both hardware and software based components.

The present description illustrates the principles of the present disclosure. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. All examples and conditional language recited herein are intended for educational purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions.

Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

Thus, for example, it will be appreciated by those skilled in the art that the block diagrams presented herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode, and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term "processor" or "controller" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, read only memory (ROM) for storing software, random access memory (RAM), and nonvolatile storage. Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.

In the claims hereof, any element expressed as a means for performing a specified function is intended to encompass any way of performing that function including, for example, a) a combination of circuit elements that performs that function or b) software in any form, including, therefore, firmware, microcode or the like, combined with appropriate circuitry for executing that software to perform the function. The disclosure as defined by such claims resides in the fact that the functionalities provided by the various recited means are combined and brought together in the manner which the claims call for. It is thus regarded that any means that can provide those functionalities are equivalent to those shown herein.

The present disclosure is directed to an apparatus and method for synchronization of trellis states in a SFN. The teachings of the present disclosure establishes a uniform trellis state "reset" position for each of multiple broadcast transmitters intending to transmit a portion of their broadcast data as identical data streams. To establish the operation, the trellis states are "zeroed" (trellis state value equal 0) at a specific time in each transmitter device, regardless of the other data (e.g. non-identical data also using trellis encoding). The present disclosure also provides a parity replacement disable feature, used for Reed-Solomon (RS) encoding, a signal passed from the encoder portion of the system to the transmitter portion of the system to identify and align the timing of the trellis state reset, and an adaptive pre-modifier for the trellis encoder that allows for a smoother trellis state reset. The embodiments are suitable for use in many networks including the ATSC mobile broadcast network service using a plurality of transmitters intended to deliver content simultaneously to mobile devices. The embodiments may also include features that pertain to systems other than a mobile ATSC standard, such as wireless internet, cellular, or other terrestrial, satellite, and wired communications systems.

FIG. 2 is a block diagram of a studio side of a STL 200. The processing in STL 200 is embedded in the multiplexer or M/H framing channel 116 as shown in FIG. 1. The STL 200 includes a pre-processor 202 for processing data packets from the ATSC systems 1 2 and 114, a post-processor 204 for encoding the data packets and a trellis formatter 206 for inserting trellis initialization bytes into the encoded data stream. The pre-processor 202 and post-processor 204 components are conventional components employed with the A/153 standard and will not be described in detail. The trellis formatter 206 is provided to enable the system to be compliant with A/153 SFNs.

The pre-processor 202 receives a main service multiplex output 208 from system 112 and a M/H service multiplex output 210 from system 114. The main service multiplex output 108 is processed by packet timing and program clock reference (PCR) adjustment module 212 and then transmitted to packet multiplexer 214. M/H service multiplex output 210 is processed by a second pre-processor 216 which includes a M/H frame encoder 218, a block processor 220, a signal encoder 222, a group formatter 224 and packet formatter 226 and is then transmitted to packet multiplexer 214. The main/M/H service multiplex output 228 is then transmitted to the post-processor 204.

The main/M/H service multiplex output 228 is processed through the post- processor chain as described in the A/153 standard. The post-processor 204 includes a modified randomizer 230 for randomizing a data packet, a first systematic/non-systematic RS encoder 232 to perform an RS encoding of the data packet to add parity to the data to correct for errors occurring due to the transmission channel characteristics, an interleaver 234 for interleaving the data output from the first encoder 232, a parity replacer 236 for replacing parity bytes in the data output from the interleaver 234, as determined by a second systematic/non- systematic RS encoder 240, and a modified trellis encoder 242 to perform trellis encoding of the data stream from the interleaver after the data stream has passed through the parity replacer 236.

An output of the modified trellis encoder 242 is transmitted to the trellis formatter 206 which includes a first-in, first-out (FIFO) buffer 244 and a trellis initialization byte inserter 246. As described in the A/153 standard, the modified trellis encoder 242 will determine the bits needed to put the trellis state at zero just prior to each M/H training sequence. These bits are passed to the trellis initialization byte inserter 246, which also receives a delayed copy of the multiplex input to the post-processor 204, i.e., output 228, via the FIFO buffer 244. The trellis initialization byte inserter 246 places trellis initialization bits in their appropriate locations in that the trellis initialization bytes precede each M/H training sequence and outputs modified output 248. More detail on this operation will be described below. It is important to note that all or a portion of STL 200 may be included in either

M/H framing block 116 or each of the exciters 118a - 118n described in FIG. 1. For example, pre-processor 216, packet timing and PCR adjustment 212 and packet mux 214 may be included in M/H framing block 1 6. Post- processor 214 and trellis formatter 206 may be included in each of the exciters 118a - 118n. Other partition configurations and arrangements may also be possible.

FIG. 3 illustrates a block diagram of an exciter 300 using aspects of the present disclosure. Exciter 300 may be included in the transmitter side of the STL and may be part of each transmitter 117a - 117n in an SFN, as described in FIG. 1. Each exciter 300 includes a post-processor 302 which includes some of the components described above for post processor 204 in FIG. 2. The components include a modified randomizer 330, a first systematic/non-systematic RS encoder 332, an interleaver 334 for interleaving the data output from the first encoder 332, a parity replacer 336 for replacing parity bytes in the data output from the interleaver 334, as determined by a second systematic/non-systematic RS encoder 340 and a modified trellis encoder 342 to perform trellis encoding of the data stream from the interleaver after the data stream has passed through the parity replacer 336. The exciter 300 further includes a sync multiplexer 351 , a pilot-inserter 353, a pre- equalizer filter 355, an 8-VSB modulator 357 and an RF up-converter 359 coupled to an antenna 361.

A process 400 for synchronization of trellis states in a network will now be described in relation to FIG. 4. Process 400 will primarily be described with respect to STL 200. Initially, in step, 402, a data stream, i.e., output 228, including a plurality of training sequences is generated by pre-processor 202, where the data stream is to be provided to a plurality of exciters. It is to be appreciated that in certain embodiments only one training sequence may be generated. The main/M/H service multiplex output 228 is processed through the postprocessor chain as described in the A/153 standard. The modified trellis encoder 242 will determine the information or bits needed to put the trellis state at zero just prior to each M/H training sequence, i.e., generate trellis initialization information or bytes, step 404. This trellis initialization information, along with the trellis encoder input data, is passed to the trellis initialization byte inserter 246, at step 406. The trellis initialization information may be in the form of bits, nibbles (i.e., half bytes), bytes, packets or some other similar data format. Note, in step 406, that the operation of the trellis initialization byte inserter 246 is simply to place or insert trellis initialization information derived by the normal A/153 mechanism into their appropriate locations in the STL bitstream, i.e., before ATSC interleaving. The trellis initialization byte inserter 246 does not, on its own, derive any additional trellis state information.

As the trellis reset operation is performed (using trellis feedback mechanisms as per the A/153 standard), sequences of bit-pairs that result in the trellis state being driven to an all-zero state are generated. For each of the 6 M/H training sequences, 24 bit pairs are generated because it takes 2 bit pairs to initialize each of 12 parallel trellis encoders which make up the modified trellis encoder 242. It is important to note here that in order for these bit pairs to drive the state of a trellis encoder to all zeros, the encoder state immediately prior to those bits being put in must be identical to the state of the trellis encoder that generated those bits. The trellis initialization bit pairs are stored into a 72x4 bit storage table where 72 represents the 12 parallel trellis encoder times the 6 M/H training sequences and 4 represents the 2 bit pairs to initialize each of 12 parallel trellis encoders. In the 72x4 bit storage table, each row holds one (upper) nibble of one trellis reset byte (the lower nibble containing known training data). The 72x4 bit storage table can be logically broken into 2 72x2 sub-tables, with column having index 'Ο' holding the upper-most bit pair of the nibble, and the column having index holding the lower bit pair of the upper nibble. A conceptually simple way to store the nibbles in this table is in the order in which their respective bytes appear at the post-processor 104 input. This way, as each trellis reset byte emerges from the delay-matching FIFO 244, the index into the nibble storage table must be simply advanced by one. In order for this simplified access storage to take place, as the trellis initialization bit pairs are being tapped from the trellis encoder, each is mapped into one of the 72 rows and 2 sub-columns of the storage table according to a 12x6x7 bit index table, as shown in FIG. 5. In the 12x6x7 bit index table, the rows represent the 12 parallel trellis encoders, the columns labeled 'Nibble 1" through 'Nibble 6' represent which of the training sequences the bit pairs are being applied to and 7 bits of information are used to index or map the trellis initialization bit pairs to 2 72x2 sub-tables.

The following example will illustrate how the table of FIG. 5 is to be used to store zero-driving bit-pairs for their subsequent insertion in the multiplexer output stream 228. At a particular moment in time, the first bit pair designated as a trellis reset bit-pair arrives at the input of trellis encoder #1 of the 12 parallel trellis encoders which make up the modified trellis encoder 242. Since bit pairs enter encoders most significant bit-first (MSB-first), all even bit-pairs (0, 2, ..) come from the 2 uppermost bits of a trellis reset byte, while the odd ones (1 , 3, ..) come from the second bit pair of the same byte. As a result, bit pair #0 will go into column #0 of the storage table while bit pair #1 will go into column #1 of the same row in the table. To know which particular byte number (i.e. row of the storage table) the new bit pair belongs to, go to row 1 of table of FIG. 5 and in the column 'Nibble V find index 11 (indices in this table are all 1 -based), which means that this first bit pair at the input of a first encoder, such as the encoder used with exciter 118a in FIG. 1 , is to be stored in row 11 , column 0 of the storage table. The second such pair will also go into row 11 , but column 1. The next pair (third) at the input of the first encoder will have come from column 'Nibble 2', so its storage index will be 32, and so on. If the zero-driving bit pairs are stored as per the table of FIG. 5, they can be read in their natural order as they are being re-inserted into the stream by the trellis state inserter. FIG. 6 illustrates an exemplary row mapping corresponding to the first, second, third, and ninth encoder in an SFN system.

It is to be appreciated that the storage table may be stored in the trellis formatter 206 or any conventional storage or memory device known in the art. Further, the implementation of the storage or memory may include several possible embodiments, such as a single memory device or, alternatively, more than one memory circuit communicatively connected, or coupled, together to form a shared or common memory. Still further, the memory may be included with other circuitry, such as portions of bus communications circuitry, in a larger circuit. Finally, the storage or memory may utilize any current storage technology suitable for storing data and/or instruction code including, but not limited to, static RAM (SRAM), ROM, and hard disk drive.

After the trellis initialization bytes are inserted into the data stream as described above, the output data stream 248 is transmitted to each of the plurality of exciters 200, in step 408. At each exciter 300, rather than locally determining what bits are needed to put the trellis state at zero prior to each M/H training sequence, the trellis state is simply forced to zero where the initialization bytes are inserted, in step 410.

Consider the first such zero-forcing instance for a single trellis encoder 342 (of which there are 12). Two scenarios are possible. First, the exciter's trellis encoder state just prior to the first trellis-reset bit pair (designated S_r-i) is the same as the multiplexer's state. Second, and more likely, the exciter state is different from that which existed at the multiplexer or studio-side processing 200. Under the first scenario, the same bit-pairs that forced the multiplexer's encoder 242 to be driven to zero will also drive the exciter state to zero. Under the second scenario, the state of the encoder after the 2 trellis initialization bit pair values will not be zero. Therefore, forcing (rather than naturally driving) the encoder to zero will create a momentary disruption in the encoder's state trajectory. However, from this point on, the output of the encoder 342 in the exciter 300 will be identical to its counterpart in the multiplexer, i.e., encoder 242 (owing to their state being all-zero at the same point in time and the input bit pairs being identical). As a result, the two encoder state sequences become synchronized and identical.

When the next trellis initialization bit pair is about to enter an encoder 342 in the exciter 300, its state will be identical to the one in the multiplexer 200, so the 2 bit pairs embedded in the input data stream will drive the state to zero, just as they did in the multiplexer 200. After the first initial disruption, which happens only after catastrophic events such as power failure, all subsequent zero-forcing events will not alter the natural state trajectory of the encoders. Consequently, after the first forcing operation, the exciter and multiplexer trellis states will be synchronized. The resulting transmitted signal is fully compliant with both A/53 and A/153 specifications and does not suffer from inherent byte errors on any packets.

It is to be appreciated that since the trellis initialization bytes are not changed by the exciter's modified trellis encoder 342, the parity bytes calculated at initial RS encoding are correct, and there is no need to run the parity replacement block, i.e., the parity replacer 336 and non-systematic RS encoder 340 can be removed or disabled. This ensures that the byte stream entering the modified trellis encoder at each exciter is identical.

An example will now be described to clarify the processing operations. FIG. 7 shows the A/53 trellis encoder. The state element resets are not explicitly shown, but the state elements are assumed to be resettable at the appropriate times. FIG. 8 shows the trellis state progression for the case when the trellis state does not initially match between the multiplexer and exciter. The multiplexer state begins at "000", whereas the exciter state begins at "111". As explained above, the parity replace and trellis initialization byte modification mechanisms described in A/153 are disabled at the exciter. Therefore, the exciter trellis encoder input is identical to the multiplexer trellis encoder input.

Until the first M/H training sequence arrives, the multiplexer and exciter trellis states are unsynchronized. When the first M/H training sequence arrives, the exciter (e.g. exciter 118a - 1 8n) forces its trellis state to zero, even though the state resulting from input data may not be zero. Of course, the multiplexer state goes to zero at this point because the normally operating post-processor has inserted the appropriate trellis reset bytes resulting in the state going to zero. On all subsequent M/H training sequences, the exciter is forcing the trellis state to "000", but this is the same state resulting from processing the input data, since the trellis reset bytes calculated at the multiplexer and present in the bitstream delivered to the exciter will also make the trellis state zero at this point in the bitsteam.

The trellis initialization byte insertion operation described above is but one possible implementation of the proposed trellis synchronization mechanism. It is an implementation that has low implementation cost on the multiplexer side. Other possible implementations of varying complexity exist that enable hardware reductions and/or enhanced functionality as described below.

Turning to FIG. 9, another embodiment of an STL 900 using aspects of the present disclosure is shown. In STL 900, the zero-driving bit pairs read from the trellis encoder in the multiplexer, may be placed into the stream leaving the parity replacer block, i.e., after ATSC interleaving. Similar to STL 200 described above, STL 900 includes a pre-processor 902 which receives a main service multiplex output 908 from system 1 2 and a M/H service multiplex output 910 from system 14. The main service multiplex output 108 is processed by packet timing and PCR adjustment module 912 and then transmitted to packet multiplexer 914. M/H service multiplex output 910 is processed by a second pre-processor 916 which includes a M/H frame encoder 918, a block processor 920, a signal encoder 922, a group formatter 924 and packet formatter 926 and is then transmitted to packet multiplexer 914. The main/M/H service multiplex output 928 is then transmitted to the postprocessor 904. The main/M/H service multiplex output 928 is processed through the post-processor chain as described in the A/153 standard. The post-processor 904 includes a modified randomizer 930 for randomizing a data packet, a first systematic/non-systematic RS encoder 932 to perform an RS encoding of the data packet to add parity to the data to correct for errors occurring due to the transmission channel characteristics, an interleaver 934 for interleaving the data output from the first encoder 932, a parity replacer 936 for replacing parity bytes in the data output from the interleaver 934, as determined by a second systematic/non- systematic RS encoder 940, and a modified trellis encoder 942 to perform trellis encoding of the data stream from the interleaver after the data stream has passed through the parity replacer 936.

In this embodiment, the trellis formatter 906 includes a trellis init byte inserter

903, a data deinterleaver 905, a parity remover 907 and a modified data derandomizer 909. The output stream 911 contains both of the correct trellis initialization bytes and reflects the original transport stream. These final operations are inverse operations of those which occur in the normal A/153 post-processor.

The transport stream thus obtained is different from the original Moving Picture Experts Group (MPEG) transport stream in that, first, the trellis reset bytes now contain actual trellis initialization bit pairs instead of all-zero placeholders and, second, valid RS parity bytes are added to the payload to form valid RS codewords. It should be evident from the above discussion that in order for the signals generated by multiple exciters in an SFN network to remain identical, the bit streams that enter trellis encoders between the subsequent zero-forcing events must also remain identical. Any bit-error in the STL will result in drastically varying trellis trajectories and, hence, waveforms. Such a disturbance will be corrected at the next M/H training signal point, but would likely be visible to legacy receivers. It is important to note that adding forward error correction (FEC) to the transport stream carried in the link, for instance, to address the disturbance, is possible and would offer a potential performance. However this FEC addition would increase operating overhead and potentially lower bit rate and transmission efficiency.

The alternate implementation shown in FIG. 9 provides an RS-encoded stream in the natural course of the operation of the multiplexer. Under the A/153 specification, due to the non-systematic nature of the RS code required for the M/H data, the simple legacy RS encoder is likely to be replaced by the RS decoder with erasure capability. Such an RS encoder implemented as an RS decoder with erasures, with only minor control changes, can be used to correct errors in the RS- encoded MPEG stream as seen by the post-processor in the exciter, thus guaranteeing a highly reliable STL under all but the most severe timing and reset signaling conditions.

Under the same topology described above in relation to FIG. 9, the exciter hardware described in post processor 904 can be greatly simplified by removing the RS encoder altogether and directly feeding the RS-encoded stream coming via STL into the ATSC interleaver. As has been noted previously, the RS parity replacer block is also unnecessary due to the fundamental nature of this embodiment. It is possible to build a "hybrid" scheme, which offers exciter hardware complexity reduction with no STL overhead increase. Under this scheme, once the RS-encoded stream is obtained at the ATSC de-interleaver output, the last 20 bytes (i.e. bytes in the legacy ATSC parity byte locations) are removed for both legacy and M/H packets. Thus, a stream of 188-byte-long packets is obtained, eliminating the FEC overhead. Then, at the exciter, a simple legacy ATSC RS encoder can be employed to reconstruct not only the legacy ATSC parity bytes, but also the complete 207-byte-long M/H RS packets out of the 187-byte long "payload" transmitted via the STL. This change, combined with the multiplexer-based trellis reset byte computation, means that, with very small changes, a traditional legacy ATSC encoder can be used to generate A/153-compliant stream. Specifically, the only addition to such legacy encoder is the ability to perform zero-forcing of the trellis state in a sub-set of M/H trellis reset locations, as well as the ability to correctly place M/H groups with respect to odd/even ATSC fields. The hardware overhead for these modifications is very small relative to the size of the conventional A/153 MH encoder. In another embodiment, trellis state calculation at the STL, such as STL 200 or STL 900 is dispensed with altogether. In place of the calculation, the multiplexer in the transmitters/exciters sends zeroes for the trellis state to be forced at the prescribed time, which is indicated in a packet inserted in the data stream, as will be described in relation to FIG. 10. It is to be appreciated that in this embodiment, the STL does not include a trellis formatter, such as trellis formatter 206 since the trellis state calculation is eliminated.

Referring now to FIG. 10, a flowchart illustrating a process 1000 for synchronizing trellis states in a plurality of transmitters using aspects of the present disclosure is shown. Process 1000 will be described with respect to aspects of FIG. 1 and the STL described in FIG. 2. It is important to note that similar functions may be incorporated into exciter 300 described in FIG. 3 and STL 900 described in FIG. 9. In step 1002, a pre-processor 202 of multiplexer 200 generates a data stream including a plurality of training sequences, the data stream to be provided to each of a plurality of exciters, such as exciters 1 18a - 1 18n described in FIG. 1. In step 1004, packet multiplexer 214 inserts in the data stream a packet for determining when to perform a trellis state reset, the packet including a location in the data stream where the reset is to be applied. The location in the data stream where the reset is to be applied is same for each of the plurality of exciters 118a - 118n.

A group of exciters, such as exciters 1 18a - 1 18n, receive the data stream, in step 1006, and force the trellis states (12 parallel) to zero at the prescribed time, in step 1008. It is important to note that the trellis state information may not need to be send at all since it is known a-priori. As a result, the only information to be conveyed is the location in the bitstream at which the forcing state is to be applied. A separate time or location may be addressed to each exciter to account for different STL or transmission delays. In some instances, the identification of the forcing state time and/or the transmission of zeroes may create a discontinuity in the trellis state trajectory. Consequently, inherent errors may exist in the broadcast transmission. However, these errors produce only a small degradation in performance and can be considered acceptable in trade for the simplified implementation simplification that results.

In a further embodiment, the operation or method of the parity replacer 336 in exciter 300, as shown in FIG. 3, is modified. The method is based on not recalculating the legacy RS parity bytes after at least one of the six trellis reset occurrences that precede training data in the M/H encapsulation ( HE) group of the ATSC M/H data structure. The method effectively disables the parity recalculation feedback loop that normally happens as part of each of the trellis reset occurrences, so that the trellis states across multiple exciters will stay synchronized. For example, at the first training sequence in the M/H group, the 12 trellis initialization bytes are processed per the A/153 standard which results in the trellis states arriving at zero just prior to when the training data is encoded. Normally, the 12 packets that contain those trellis initialization bytes would need to have their legacy RS parity bytes recalculated because they were originally calculated using default values of 0 for trellis initialization bits.

It is important to note that the parity bytes that are affected always follow the initialization bytes, so no causality issue is involved. However, the values of the RS parity bytes thus calculated depends on the trellis state existing just prior to determining the values needed for the initialization bytes. As such, two encoders that initially have different trellis states at time A will insert different values for the trellis initialization bytes. The trellis states will match just prior to and throughout the immediately following training bytes, but will again diverge as soon as the recalculated parity bytes begin arriving. However, if the legacy RS parity bytes are not recalculated, say at the first training sequence, then the trellis states will remain synchronized, or equal. At the next training occurrence, the same trellis initialization bits will be calculated by each encoder since their trellis states will be identical at the start of that process.

In general, it is not important which of the six training sequences is chosen to disable the parity recalculation. In general, all the encoders are not required to disable on the same training sequence. This is because once the trellis states at any two encoders match (by definition, zero prior to training data), and then the encoder states must stay identical since the data entering the encoders is also, by definition, identical.

In another embodiment, a method is used to synchronize the trellis states based on manipulation of the parity replacer block. The manipulation includes disabling the parity replacer block during a specified portion of the transport stream. A command may be provided within the stream of data, such as by use of a Distributed Transmission (DTx) packet, to indicate when the parity replacement block is disabled. Alternately, an external control signal may be used to control the replacer block. It is important to note that synchronization is most easily achieved if the parity replacer block manipulation is performed based on a point in the transport stream that is common to each exciter, as opposed to a specific time. As a result of the control information, the exciter is told when not to perform parity byte replacement. For example, the control information identifying a recurrence of a bit for disabling parity replacement may be selectable by an operator of the network and may further only be used at system start or re-start or may be used on a periodic maintenance basis.

It is to be appreciated that the method for disabling the parity byte replacement follows the method shown in FIG. 10. However, in this embodiment, the packet includes information on when to disable the parity replacer to force the synchronization. For example, in one embodiment, the method will include inserting a disable parity replacement bit in the packet, as optional step 1010, the details of which will be described below. In a further embodiment, a similar method could also be used to synchronize trellis states in a pure legacy stream. In this case, the trellis initialization bit calculation is enabled at a prescribed point in the bitstream. This will drive the trellis state of each encoder to zero at the prescribed time. Since the following bitstream input to the encoders will be identical, by similar logic to above, the trellis states remain identical across encoders.

It is important to note that the simplicity inherent in some of the disclosed embodiments may produce errors in transmission. However, the penalty paid for this simplicity of implementation is that for those times when legacy RS parity bytes are not recalculated, 12 packets may be sent and received by a RS decoder in a legacy (i.e. A/53) receiver having a 1 byte error inherently present due to the implementation. Since this condition will happen quite infrequently, it is a negligible disturbance to legacy receivers. Further, the errors are of no consequence at all to M/H decoders in M/H (i.e. A/153) receivers since an M/H decoder may ignore the legacy RS parity information.

In yet another embodiment, an alternate process for synchronizing the trellis states is made possible through the inherent operation of driving the trellis states to zero just prior to processing the embedded M/H training sequences. In this embodiment, a new bit is defined in the M/H packet (MHP) structure. This bit, called mh_trellis_sync, signals to the exciter that synchronization should take place at the next occurring M/H group. The multiplexer does not modify the A/153 bitstream, or perform any other calculations. It is only responsible for identifying trellis synchronization opportunities. For example, the multiplexer might send the MHP with mh_trellis_sync bit set once per second. This would allow synchronization to be established again within one second of any events that caused synchronization to be lost, provided M/H groups occur in the bitstream with reasonable frequency. In the degenerate case where only one M/H group is sent with a parade repetition cycle, identifying the format timing for M/H groups, equal to 7, the synchronization interval would take longer since it is lower bounded by the M/H group spacing. Although possible, such boundary cases are unlikely to cause limitation in a practical sense. It must be stressed that any trellis synchronization method can only recover from synchronization loss. It is not possible to prevent synchronization loss due to the random nature with which errors occur across the STL 200. The network operator is free to choose how often ^synchronization opportunities occur. MHP packets will typically be inserted at regular intervals to establish emission timing. If desired, the mh_trellis_sync bit can be set in every packet, which corresponds to the shortest possible ^synchronization interval. Alternatively, the network operator can choose the recurrence of the bit for disabling parity replacement. The network operator may, for instance, make the ^synchronization interval longer by setting the mh_trellis_sync bit in only a subset of the MHP packets.

The operation of trellis synchronization will be described by showing that when the parity replacer is disabled for RS parity bytes corresponding to the first sequence of M/H trellis initialization bytes, the trellis states across multiple exciters will remain synchronized.

It is important to note the trellis state change in response to the trellis initialization sequence under normal M/H operation. The upper 4 bits of each trellis initialization byte are replaced with values that drive the corresponding trellis encoder's state to zero just prior to processing the training sequence. It is important to note that each trellis initialization byte from this first sequence comes from a different packet prior to interleaving (e.g. bytes 18-29 of segment 51 per Table A.2 of the A/153 standard). Hence, there are 12 packets affected prior to interleaving. The RS parity for each packet would have been initially calculated by the first non- systematic RS encoder with 0 in the upper nibble of the trellis initialization byte. After replacing the upper nibble with the value that drives the corresponding trellis encoder to zero, these RS parity bytes are no longer correct. The second non- systematic RS encoder and parity replacer functions recalculate 20 bytes from each affected packet such that, without channel errors, it will be perceived as error-free by a legacy ATSC decoder. Because the starting trellis state prior to trellis initialization byte calculation is random, the resulting trellis initialization bytes will typically not match between any two exciters processing the same transport stream. This in turn causes the non-systematic RS encoders to derive different bytes to be used by the parity replacer block. This is effectively the situation that is circumvented by momentarily disabling parity byte replacement, as will be shown in the analysis below. It is also helpful to note that the 20 non-systematic RS parity bytes that are to be replaced for each packet are chosen such that they enter the trellis encoder after the trellis init byte which forces them to be recalculated. Otherwise, the system would be infinitely non-causal and non-implementable.

Each trellis initialization byte is chosen to put its corresponding trellis encoder's state at zero just prior to processing the training sequence bytes. This is a special condition that allows immediately following data to be treated as training for the M/H signal, but which also has the effect of determining a common starting state for all exciters in the network. Any two trellis encoders that start at the same state and then proceed to process the same data sequence will exhibit the same state trajectory and generate identical output symbols.

FIG. 1 illustrates an exemplary structure for an M/H data stream using aspects of the present disclosure. FIG. 1 identifies an order for processing the M/H data stream. In FIG. 1 , the first trellis init sequence 1102 is followed by a sequence of known training bytes 1104. The sequence of training bytes 1104 are then followed by a sequence of signaling data 106. Both of these sequences are identical at all of the exciters in the network. The next portion to be trellis encoded is the second trellis init sequence 1108. The trellis states just prior to processing this will be identical for all exciters because, as pointed out above, the starting state at the beginning of the first training sequence is identical (i.e., ΌΟΟ'), and all of the data processed between the first and second trellis init sequences is also identical. Therefore, each exciter will place the exact same bits into the second set of initialization bytes to initialize its trellis encoders. This will in turn cause their non- systematic RS encoders to calculate the exact same bytes to be replaced.

Next, the second training sequence portion 1110 is processed. After the second training sequence 1 10 is processed, a data section 112 is entered. The data sequences between any two exciters will be identical up to the first location where a replaced parity byte from the first trellis initialization operation is encountered. Normally, if this parity byte was replaced, the byte value would be different between any two exciters as explained above. Assuming none of the parity bytes affected by the first trellis init sequence are replaced. Then the data sequence between the two exciters continues to be identical.

Many occurrences of bytes that would have been affected by the first trellis initialization sequence are found, but since they are not replaced, the trellis encoders' inputs remain identical. Some occurrences of bytes that are replaced as a result of the second trellis initialization sequence are also found. But, as explained earlier, these bytes are always identical between any two exciters as a result of normal M/H processing.

Finally, the third trellis init sequence is reached. It is established that the starting trellis states at the beginning of the first training sequence 1104 match across exciters and the input data sequences between that point and the third trellis initialization sequence also match. Therefore, the trellis states prior to processing the third trellis initialization sequence will also be identical. This will make the exciters derive the exact same trellis initialization bytes, which will in turn cause the non-systematic RS encoders to calculate the exact same RS parity replacement bytes.

Following this same byte-for-byte analysis, the data sequences up to the fourth trellis initialization sequence are also identical, which causes the trellis states to once again be identical at the beginning of the fourth trellis initialization sequence. This same situation continues through the last M/H training sequence and into the legacy data section where there is no dispute that the data sequences entering the trellis encoders are identical. The processing remains in the legacy data section until the next occurrence of an M/H group. This time, the trellis states between any two exciters at the start of the first initialization sequence will already be identical because at a prior point (namely, the initialization sequence for which parity replacement was disabled) their initial values were identical and all subsequent input data also remained identical. Therefore, there is no need to disable parity byte replacement again because the calculated trellis initialization sequences will be the same, which will cause the non-systematic RS encoder to calculate the same replacement bytes. It can now be seen that this byte-for-byte comparison will show identical trellis encoder outputs across any two exciters in the SFN. In a preferred embodiment, parity byte replacement would be disabled only once at startup, and would not be needed again. In an alternate embodiment, parity byte replacement may be disabled periodically in order to adjust for, and recover from other uncontrollable system errors, such as unexpected data delivery timing errors across the SFN.

Part or all of the processes described above may be implemented in each exciter 300 as shown in FIG. 3. As such, under normal M/H processing, the first trellis initialization sequence, which is comprised of twelve bytes, causes RS parity byte recalculation and replacement that affects twelve different transport packets (e.g. packets numbered 37-48 in Table A.1 of the A/153 standard). Each of these packets contains 20 RS parity bytes designated by the number '. When instructed to do so, the postprocessor 302 shall maintain the values of these bytes as they were at the output of the first non-systematic RS encoder 332 which precedes the data interleaver 334.

The postprocessor 302 is told when to disable RS parity byte replacer 336 through the bit defined in the MHP structure, i.e. the mh_trellis_sync, when '1' conveys that the RS parity byte replacement disable mechanism shall be executed at the next occurring M/H group. When this bit is 'Ο', no action shall be taken.

In one embodiment, the post processor 302 zeroes the upper nibble of the first twelve trellis initialization bytes while proceeding with parity recalculation and replacement. This zeroing has the desired effect because the recalculated parity bytes will exactly match those calculated the first time. This mechanism requires only a tiny amount of control logic to implement. The multiplexer 351 sets the mh_trellis_sync bit in the MHP at an interval specified by the network operator. As a result, disabling parity byte replacement for the first trellis initialization sequence has the effect of making subsequent states dependant only on the transport stream sequence, not the random initial starting trellis state. This sequence dependence causes any two or more exciters to remain with trellis state synchronization as they process the same input transport stream.

Although embodiments which incorporate the teachings of the present disclosure have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings. Having described preferred embodiments of an apparatus and method for synchronization of trellis states in a network (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments of the disclosure disclosed which are within the scope of the disclosure as outlined by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A method for synchronization of trellis states in a network, the method comprising the steps of:

generating a data stream including at least one training sequence (402); generating trellis initialization information based on the at least one training sequence in the data stream (404); and

inserting the trellis initialization information into the data stream in

predetermined locations (406).

2. The method as in claim 1 , further comprising:

receiving the data stream with inserted trellis initialization information at each of at least two exciters (408); and

forcing a trellis state reset upon receiving the trellis initialization information in the data stream (410).

3. The method as in claim 1 , further comprising storing the generated trellis initialization information in an order of appearance in the data stream, wherein the generated trellis initialization information is inserted in the data stream in the stored order.

4. The method as in claim 1 , wherein the predetermined locations are prior to the at least one training sequence after interleaving.

The method as in claim 4, further comprising: deinterleaving the data stream that includes the trellis initialization information;

removing the parity from the data stream;

derandomizing the data stream; and

outputting the data stream to each of at least two exciters.

6. An apparatus (200) comprising:

a pre-processor (202) that generates a data stream including at least one training sequence;

a post-processor (204), coupled to the pre-processor (202), that encodes the generated data stream and generates trellis initialization information based on the at least one training sequence in the data stream; and

a trellis formatter (206), coupled to the post-processor (204), that inserts the trellis initialization information into the generated data stream in predetermined locations.

7. The apparatus (200) as in claim 6, wherein the trellis formatter (206) stores the trellis initialization information in an order of appearance in the data stream and inserts the trellis initialization information in the data stream in the stored order.

8. The apparatus (200) as in claim 7, wherein the trellis formatter (206) comprises:

a first-in, first out (FIFO) buffer (244) that receives the generated data stream and forwards a delayed copy of the generated data stream to a trellis initialization byte inserter (246); and

the trellis initialization byte inserter (246) that receives the delayed copy of the generated data stream from the FIFO buffer (244) and the trellis initialization information from the post-processor (204) and inserts the trellis initialization information into the delayed copy of generated data stream.

9. The apparatus (200) as in claim 6, wherein the predetermined locations are prior to the at least one training sequence.

10. The apparatus (200) as in claim 9, wherein the trellis formatter (906) comprises:

a trellis initialization byte inserter (903) that receives the generated data stream without encoding from the post-processor (204) and the trellis initialization information from the post-processor (204) and inserts the trellis initialization information into the generated data stream;

a data deinterleaver (905), coupled to the trellis initialization byte inserter (903), that deinterleaves the data stream;

a parity remover (907), coupled to the data deinterleaver (905), that removes parity from the data stream; and

a data derandomizer (909), coupled to the parity remover (907), that derandomizes the data stream. 11. A method for synchronization of trellis states in a network, the method comprising the steps of: generating a data stream including at least one training sequence (1002); and inserting a packet in the data stream, the packet for determining when to perform a trellis state reset, the packet including a location in the data stream where the reset is to be applied (1004). 2. The method as in claim , wherein the location in the data stream where the reset to be applied is the same for each of at least two exciters.

13. The method as in claim 11 , wherein the packet includes a bit for determining when to selectively disable parity replacement of the data stream (1010).

14. The method as in claim 3, wherein the parity replacement is disabled at a first of the at least one training sequence of a mobile/handheld encapsulation (MHE) group.

15. The method as in claim 13, wherein the disabling parity replacement is performed based on a point in the data stream common to each of the at least two exciters.

16. The method as in claim 13, wherein a recurrence of the bit for disabling parity replacement is selectable by an operator of the network.

17. An apparatus (200) comprising:

a pre-processor (202) that generates a data stream including at least one training sequence; and

a packet multiplexer (21 ) that inserts a packet in the data stream, the packet for determining when to selectively disable parity replacement of the data stream at each of at least two exciters.

18. The apparatus as in claim 7, wherein the parity replacement is disabled at a first of the at least one training sequence of a mobile/handheld encapsulation (MHE) group.

19. The apparatus as in claim 17, wherein the disabling parity replacement is performed based on a point in the data stream common to each of the at least two exciters.

20. The apparatus as in claim 17, wherein a recurrence of disabling parity replacement is selectable by an operator of the network.

21. An apparatus for synchronization of trellis states in a network, the apparatus comprising:

means for generating (202) a data stream including at least one training sequence;

means for generating (204) trellis initialization information based on the at least one training sequence in the data stream; and

means for inserting (206) the trellis initialization information into the data stream in a predetermined location.