WO2011024010A2

WO2011024010A2 - Inverter

Info

Publication number: WO2011024010A2
Application number: PCT/GB2010/051427
Authority: WO
Inventors: David Gurwicz; Maurice Plews
Original assignee: Turbo Power Systems Limited
Priority date: 2009-08-29
Filing date: 2010-08-31
Publication date: 2011-03-03
Also published as: WO2011024010A3; GB2474009A; EP2471168A2; GB0915070D0

Abstract

A power inverter arranged to receive input power having an input voltage across first and second input terminals, comprises a first switching arm, a second switching arm,and a voltage divider coupled across the input terminals. The first switching arm comprises first and second switching elements. The second switching arm comprises third and forth switching elements. The first and second switching arms are connected in series across the input terminals. Drive circuitry drives each of the switching elements to produce switching waveforms such that the voltage across each of the switching arms remains below a predetermined proportion of the input voltage.

Description

The present invention generally relates to inverters, particularly to inverters for high power applications.

A problem that can arise particularly in high power applications is that high input voltages may be encountered, particularly transients. The inverter components must be able to withstand the input voltages without damage. Higher voltage requirements impose problems on sourcing suitable semiconductor switching elements. Whereas high power switching elements able to operate at a few hundred volts may be readily available, devices for higher voltages may be much more expensive, often bulkier and sometimes difficult to achieve due to physical constraints. Moreover, where available, switching losses for higher voltage devices are greater and switching times are longer, so they can only be practically used at lower frequencies, leading to a requirement for larger output transformers. The problems of switching of higher voltages are not simply linearly proportional to voltage but due to higher slew rates, junction sizes, capacitance, resistive losses etc the practical switching frequencies drop rapidly with higher voltages. For example a 1200 volt device may be switched at about 20 kHz with acceptable losses but a 2000 volt rated device may only practically be operable at less than 10 kHz before losses become unacceptable. Even at lower voltages, for a given current, it is generally easier and cheaper to find a device with a lower operating voltage with a given switching time.

The problem is particularly acute in the case of inverters for railway applications where large currents and powers are involved and there may be requirements to withstand large transient voltages.

The problem of the low operating voltage constraints of semiconductor switching elements is traditionally solved simply by using a conventional step down transformer on the input where an AC supply is available so that the inverter input is at a convenient level. In a rail application with a DC supply, galvanic isolation is a further important concern and this is conventionally achieved using a low frequency (typically 50Hz) inverter to convert the DC to AC to feed a step down transformer to produce an isolated supply which is rectified. However, particularly in high power applications, such an input transformer adds significant weight, bulk and cost, as well as energy losses.

Particularly in a rail application, an inverter which operates using semiconductors directly coupled to the input would provide an environmental benefit as there would be energy savings due to having a lower mass to move and avoiding input transformer losses.

Aspects of the invention are directed to the above problems.

SUMMARY OF THE INVENTION

A first aspect of the invention provides a power inverter arranged to receive input power having an input voltage across first and second input terminals, comprising: a first switching arm comprising a first switching element connected to conduct current between a first connection and an output of the first arm and a second switching element connected to conduct current between the first arm output and a second connection; a second switching arm comprising a third switching element connected to conduct current between a third connection and an output of the second arm and a fourth switching element connected to conduct current between the second arm output and a fourth connection; wherein the first and second switching arms are connected in series across the input terminals with the first connection of the first arm coupled to the first input terminal, the second connection of the first arm coupled to the third connection of the second arm and the fourth connection of the second arm coupled to the second input terminal; a voltage divider coupled across the input terminals having an output of the voltage divider coupled to the second and third connections; an output coupling connected between the outputs of the first and second switching arms; drive circuitry for driving each of the first, second, third and fourth switching elements to produce switching waveforms such that the voltage across each of the switching arms remains below a predetermined proportion of the input voltage.

With this arrangement, the maximum voltage "seen" by each switching arm is less than the input voltage. Normally the device will be generally symmetrical, i.e. with similar arms, and voltage divider will be arranged to divide the input voltage substantially in half and each arm will see half the input voltage. Preferably the inverter is arranged so that the proportion across each arm is substantially constant.

The inverter is preferably arranged to maintain the proportion across each arm substantially within limits. For example, where the voltage across each arm is arranged to be nominally half, the inverter may be arranged to ensure that the proportion across any one arm does not exceed %, preferably is no greater than 2/3 of the total voltage, and in preferred arrangements will be arranged to ensure the voltage is within 45 and 55% to reduce switching imbalances. The inverter may additionally or alternatively be arranged to ensure that the voltage across each arm does not exceed a given absolute voltage, (which may be related to device breakdown voltages). The inverter may have protection means, which may be hard-wired protection circuitry or logic and/or modifications to the inverter drive circuitry/algorithm to maintain voltage within limits.

The inverter may use a voltage divider which is not capable of passing sustained full power to each arm individually. Because the arms are connected in parallel with the divider, the inverter arms serve to supply current to each other in addition to the voltage divider. Preferably the voltage divider comprises capacitors connected in series which serve to store energy.

Preferably the inverter operates at a higher frequency than the supply frequency (in the case of an AC supply which is rectified in the inverter). In the case of a DC supply which has originated from an AC supply which has been rectified elsewhere, the inverter also preferably operates at higher frequency than the original AC supply. Preferably the inverter operates at at least 10 times the supply frequency, more preferably at least 100 times the supply frequency. Preferably the inverter operates at an ultrasonic frequency (preferably greater than 2OkHz) as this reduces the problem audible noise from components such as transformers or from magnetic fields induced in other components. Preferably the capacitors are sized so that maximum voltage change across an arm during a cycle of the inverter output is no more than 50% of the nominal voltage, preferably less than 20%, preferably less than 1/6, typically less than 10%, ideally less than 5% and in preferred practical arrangements less than 2%, of the order of 1% or less. Preferably the inverter operates at a frequency greater than IkHz (giving a cycle period of 1ms), more preferably at the order of 10kHz or greater, preferably greater than 20 kHz (or at least 15kHz) to reduce audible noise. Higher frequencies reduce both capacitor and output transformer size requirements, although use excessively high frequencies may be problematic to switch and generate radio frequency interference. An operation frequency between about 5 kHz and 100 kHz. preferably between 15kHz and 50kHz is therefore convenient.

Each arm effectively performs two functions, its primary function of switching the output as in a conventional inverter and a secondary function of supplying current to the other arm(s) with which it is connected in series, effectively to "top up" the voltage divider. By appropriate control of the drive, the voltage divider is thus effectively regulated.

There are two common arrangements for inverters, pulse width modulation (PWM) and phase shift modulation. Pulse width modulation controls the output power by adjusting the duty cycle of the switching elements so that they are on for a shorter time when less power is required. A slight drawback of PWM is that at low power settings, the switching elements need to switch on and off very rapidly to give short on times, which imposes a practical lower limit on the output. In phase shift modulation, both arms are driven at 50% duty cycle (although applications are possible where this may vary) with the phase of the arms varying. When the arms are in phase, an output transformer connected between them receives no net signal and when they are in antiphase, maximum signal is delivered to the output transformer, thus the output can be varied smoothly between zero and full power. A phase shift arrangement requires slightly more complex drive circuitry but this can be readily achieved with a digital signal processor and dedicated drive circuits are now becoming available. The invention can be applied to both types of drive arrangement (or modifications).

With a PWM arrangement, provided the arms are driven symmetrically the current taken from each arm balances over a cycle so the voltage divider midpoint should remain approximately constant. Small manufacturing tolerances in the devices will in general tend to balance out as, if one arm is on for slightly longer in a given cycle, the voltage across the corresponding capacitor of the voltage divider will reduce and this will tend to reduce the energy available for that arm to draw in a subsequent cycle so a balance point will occur which may not be exactly at the midpoint but will tend to be relatively stable. The drive circuitry may actively seek to adjust duty cycles finely to take into account imbalances if desired. Protection circuitry or algorithm may be included to adjust duty cycles if voltage deviates too far from a target point. This may be as simple as hardwired logic which prevents one arm from conducting at all while the voltage across the other arm exceeds a threshold.

In a phase shift arrangement, however, imbalances will tend to build up (other than at zero and full power) as the arm which leads may systematically take more current from the upper side than the arm which lags (or vice versa depending on the point in the cycle) and the voltage at the divider junction will tend to drift up or down. Thus the arrangement at first sight seems unsuited to phase shift modulation. According to a preferred arrangement in a further inventive development, however, it has been proposed to adjust the phase shift, and preferably in particular the order in which the arms lead and lag, to keep the divider voltage within limits. This can be done dynamically in response to measurement of voltage. A simple first order correction can be achieved however simply by allowing one arm to "lead" for one or more cycles and then allowing the other to lead for a similar number of cycles. It has been found that switching the order in which arms lead and lag can be done without producing unacceptable transients. Switching between lead and lag can be achieved by adjusting one waveform only (preferably smoothly, for example by compressing or expanding the drive waveform) one (i.e. increasing frequency) while expanding the other (i.e. decreasing frequency))

The invention has been described in the context of dividing the voltage into two. However, for higher input voltages and/or lover device voltage limits, the voltage may be further divided, for example there may be division into 4 or more. Where the input voltage is divided into multiples, the output transformer may be coupled in a variety of ways, including multiphase arrangements.

The inverter preferably includes a capacitor coupled in series between the first and second arms and a primary winding of an output transformer. The capacitor serves to block DC current from flowing through the primary (due to the different voltage levels of the arms). Preferably the capacitor is sized so that at the switching frequency of the inverter, the voltage across the capacitor changes by no more than about 10%, preferably no more than 5% during a cycle of the inverter under normal current flow. However,

Embodiments of the invention will now be described with reference to the accompanying drawings in which:

Figure 1 is a circuit schematic for a circuit comprising an inverter according to a first embodiment;

Figure 2 is a circuit schematic for a circuit comprising an inverter according to a second embodiment;

Figures 3a and 3b show circuit schematics for transformer output configurations; Figure 4 shows a current vs. time plot in a transformer primary. Figure 1 illustrates an inverter circuit 1 according to one embodiment of the present invention. The inverter is powered by a voltage source 3. The voltage source 3 provides a DC voltage with a magnitude of V. It will be appreciated that an AC voltage source can simply be rectified to provide this DC voltage source but in a railway application a DC source is provided.

The inverter comprises two switching arms. The first switching arm has a first IGBT 5 and a second ΪGBT 7. The first IGBT 5 connects between an anode terminal of the power source 3 and an output of the first arm. The second IGBT 7 connects between point 21 and the output of the first arm. The second switching arm has a third IGBT 9 and a forth IGBT 11. The third IGBT 9 connects between the point 21 and an output of the second arm. The forth IGBT 11 connects between the output of the second arm and a cathode terminal of the power source 3. The IGBTs behave as switching elements. As those skilled in the art will appreciate, an IGBT allows a current between its emitter and collector once a voltage applied to its gate terminal exceeds a threshold voltage, and blocks any current if the gate voltage is below the threshold voltage.

The output of the first switching arm and the output of the second switching arm are coupled together by a primary winding 13 and a capacitor 15. The capacitor 15 is used as a bypass capacitor which permits the transmission of AC signals and blocks any DC offsets. A transformer scales the voltage of the primary winding and provides an output voltage.

The inverter uses a voltage divider which does not need to be capable of passing sustained full power to each arm individually. The voltage divider comprises capacitors 17 and 19 connected in series and both coupled to the point 21. Capacitors are used to store energy to maintain voltage across each arm. Each arm effectively performs two functions, its primary function of switching the output as in a conventional inverter and a secondary function of supplying current to the other arm(s) with which it is connected in series, effectively to "top up" the voltage divider. By appropriate control of the drive, the voltage divider is thus effectively regulated. Thus, whilst the capacitors will initially charge to equal voltages, the DC current cannot flow through them but by having each switching arm serve a dual function as both a switching arm of the inverter and as a current source for the other arm the need for a separate supply or means to supply current

With this arrangement, the maximum voltage "seen" by each switching arm is less than the input voltage. Normally the device will be generally symmetrical, i.e. with similar arms, and voltage divider will be arranged to divide the input voltage substantially in half and each arm will see half the input voltage. Preferably the inverter is arranged so that the proportion across each arm is substantially constant. The inverter is preferably arranged to maintain the proportion across each arm substantially within limits. For example, where the voltage across each arm is arranged to be nominally half, the inverter may be arranged to ensure that the proportion across any one arm does not exceed %, preferably is no greater than 2/3 of the total voltage. In practical arrangements, these limits may be much tighter, typically within 5% or 1% of the nominal value, to equalise switching losses in the switching elements.

The inverter may additionally or alternatively be arranged to ensure that the voltage across each arm does not exceed a given absolute voltage, (which may be related to device breakdown voltages). The inverter comprises diodes 23, 25, 27 and 29 to pass reverse currents.

Protection means may be used, such as hard-wired protection circuitry or logic and/or modifications to the inverter drive circuitry/algorithm to maintain voltage within limits. There are two common arrangements for inverters, pulse width modulation (PWM) and phase shift modulation. Pulse width modulation controls the output power by adjusting the duty cycle of the switching elements so that they are on for a shorter time when less power is required. A slight drawback of PWM is that at low power settings, the switching elements need to switch on and off very rapidly to give short on times, which imposes a practical lower limit on the output. In phase shift modulation, both arms are driven at 50% duty cycle (although applications are possible where this may vary) with the phase of the arms varying. When the arms are in phase, an output transformer connected between them receives no net signal and when they are in antiphase, maximum signal is delivered to the output transformer, thus the output can be varied smoothly between zero and full power. A phase shift arrangement requires slightly more complex drive circuitry but this can be readily achieved with a digital signal processor and dedicated drive circuits are now becoming available. The invention can be applied to both types of drive arrangement (or modifications).

With a PWM arrangement, provided the arms are driven symmetrically the current taken from each arrn balances over a cycle so the voltage divider midpoint should remain approximately constant. Small manufacturing tolerances in the devices will in general tend to balance out as, if one arm is on for slightly longer in a given cycle, the voltage across the corresponding capacitor of the voltage divider will reduce and this will tend to reduce the energy available for that arm to draw in a subsequent cycle so a balance point will occur which may not be exactly at the midpoint but will tend to be relatively stable. The drive circuitry may actively seek to adjust duty cycles finely to take into account imbalances if desired. Protection circuitry or algorithm may be included to adjust duty cycles if voltage deviates too far from a target point. This may be as simple as hardwired logic which prevents one arm from conducting at all while the voltage across the other arm exceeds a threshold.

In a phase shift arrangement, however, imbalances will tend to build up (other than at zero and full power) as the arm which leads may systematically take more current than the arm which lags (or vice versa depending on the point in the cycle) as the lagging arm imposes a higher load on the supply than the leading arm. For example, if IGBTs 9 and 11 lag IGBTs 5 and 7, the load appearing on capacitor 19 is higher than the load appearing on capacitor 17 and the voltage of point 21 will migrate downwards. If the situation is reversed the voltage of point 21 would migrate upwards.

This problem can be addressed by alternating the lead and lag function between the arms at a sub-multiple of the inversion frequency. For example, if the required phase difference to achieve the required output is Φ and the inversion frequency is 1OkHz, IGBTs 9 and 11 are set to lag IGBTs 5 and 7 by Φ for ten cycles and then to lead IGBTs 5 and 7 by Φ for the following ten cycles, this maintains the voltage of point 21 at the required V/2. Alternatively a closed loop control could be incorporated correcting the deviation of the voltage of point 21 from the mid-point by changing the requisite arm from lead to lag to correct the error.

To allow operation up to 3kV with 1000V rated devices a four level phase shift inverter may be used, an embodiment of a four level phase shifter is illustrated in Figure 2

As will be appreciated the example of Figure 2 may be assembled by suitable adaptation of two circuits according to Figure 1. Therefore, corresponding elements have been marked with corresponding reference numerals. Reference numerals marked with a prime symbol indicate elements performing related function. E.g. the IGBT 9' performs a related function to the IGBT 9 as described above with reference to Figure 1.

In this configuration two approaches are combined, two transformers provide four level switching and with 1200 volt rated devices 3.6kV continuous operation is possible. In a non operating condition inverters according to this example can withstand surges on the order of 7.2 kV.

It has been found that with devices rated to 1200 volts, ultrasonic switching frequencies are possible, that is switching frequencies of the order of 20 kHz or greater. Thus with the invention it has become possible to produce an inverter which will reliably withstand transients on a 600 volt nominal DC rail line with direct high frequency conversion at ultrasonic switching frquencies, providing galvanic isolation of output without the need for a low frequency transformer.

The arrangement of Figure 2 can provide a conversion efficiency (not including transformer losses) of 96%. It should be noted that due to the phase changes required to balance the input capacitor voltage levels, during operation, the addition of "snubbers" to further improve the conversion efficiency or to suppress ("snub") voltage transients is not straightforward.

Output rectification can be conventional; however there may be a need to consider rectifier diode voltage ratings when operating over a wide range of supply voltages. Optionally, in the LVPS, high voltage diodes may be employed to cope with the peak input voltage conditions. Two examples of output configurations are shown in Figures 3a and 3b.

In the drawing of Figure 3 a connection HVPSout is coupled to a first plate of capacitor Cl. The second plate of capacitor Cl is coupled to connection HVPSret. HVPSret is connected to diode D9 which provides a forward conducting path.

The connection between diode D9 and coupling HVPSret is connected to diode configuration D5, D6, D7, D8, in which: diodes D7 and D8 are coupled in parallel with D5 and D6 respectively. Inductances SEClbxTl and SEClbT2 are connected in series between the cathodes of D6 and D8 (and the anodes of D5 and D7). The cathodes of D7 and D5 are mutually coupled to the anodes of D2 and D4 (which are mutually coupled together) and which form part of a second diode configuration Dl, D2, D3, D4. Inductances SEClaxTl and SEClaT2 are connected in series between the cathodes of D2 and D4 (and the anodes of Dl and D3). The cathodes of Dl and D3 are mutually coupled together. In the drawing of Figure 3b connection LVPSout is connected to a first plate of capacitor C2 and to a connection of inductance Lout. The other connection of inductance Lout is connected to the cathodes of diodes DlO and DIl. The anode of DlO is connected to the anode of DI l via four inductances arranged in series SEC2aT2, SEC2axTl, SEC2bxTl and SEC2bT2. The connection between SEC2axT2, SEC2bxT2 is connected to LVPSret.

To summarise, multi-level Phase Shift Inverter topology isolated DC/DC converters can be configured to satisfy the operating conditions presented by Rail Supply Networks over the range 600V - 1500V nominal including transient voltages, without the need for system interruptions during surge and transient conditions.

Typical requirements which the embodiments of the circuit of Figures 1 and 2 can be configured to operate with are:

1. 600 / 750 volts dc input +25% -30% Working range 1000 / 500v Transients to

2. 1500 volts dc input +25% -30% Working range 2000 / 100Ov Transients to

Under transient conditions there may be a requirement to make decisions on whether to shut down or not, but it is preferable to keep running if possible. This minimises the system stop/starts and any delay time associated with getting the system on line again.

The most common power ratings are for a three phase inverter for air conditioning etc. and a DC to DC converter for the Low Voltage Power Supplies. Typically inverters are three phase 230v or 415v at 5OkVa output. With DOL motor starting, optionally a 415v 3 phase 5OkW supply at 0.8p.f. is provided. To reduce the size of the filter components the modulation frequency is preferably 5kHz and output distortion preferably less than 8%THD. LVPS can be up to 2OkW with voltages between 24 and 11Ov in which case a 1OkW unit at 37.5V may be provided. In these examples a DC/DC converter may therefore be rated at 6OkW operating at 2OkHz and producing two isolated DC supplies, 660V at 5OkW and 1OkW at 37.5V. Converter output control can be to regulate the LVPS with the HV DC slaved to it.

In general there exists a requirement for an ambient temperature in the range: -25Deg C to +50 Deg C. Most cooling requirements are for natural air cooling. An overall efficiency target, measured from the DC in to the output is generally specified at 92% at full load.

The plot shown in Figure 4 shows the effect of the changes from lead to lag and vice versa on the transformer primary current

It is preferred to switch the phase from lead to lag at a time when there is no voltage across the transformer. This reduces transients. This can be achieved by synchronizing the lead-lag switch with the main inverter drive, which is generally straightforward as both will be under the control of a common microcontroller. Switching from lead to lag and vice versa may be carried out at regular absolute intervals, for example every millisecond, every given number of inverter cycles, or in response to voltage drift of the midpoint or a combination. For example, the drive may be programmed to swap from lead to lag every 1 ms or if the voltage drifts from the midpoint by more than 1 %, whichever is sooner, with the capacitors typically being sized so that, under full load, in the absence of transients, a drift of 1% typically takes at least about 10 cycles at 2OkHz or 500 microseconds,

As will be appreciated in the context of the present application, when using a simple choke/capacitor output filter on the rectified secondaries, current continues to circulate in the transformer primary. This may result in increased transformer and IGBT loss, methods may be employed to cause the inter-pulse current to decay more rapidly, thereby reducing this effect. As will be appreciated by the skilled practitioner in the context of the present application where electronic components have been depicted as discrete or separate elements they may be provided by integrated or inherent components for example capacitors may be provided by any appropriate capacitance and inductors may be provided by any appropriate inductance. Diodes have been shown as separate components but as will be appreciated these may be separate components or may be inherent or body diodes associated with transistor or other semiconductor structures.

This invention has been explained with reference to specific embodiments. As can be understood by those skilled in the art, the invention can be implemented using equivalent means without deviating from the scope of the invention. For example, the switching elements used in the inverter may be other kinds of semiconductor switches, such as MOSFETs or any other voltage controlled impedance,

Claims

1. A power inverter arranged to receive input power having an input voltage across first and second input terminals, comprising:

a first switching arm comprising a first switching element connected to conduct current between a first connection and an output of the first arm and a second switching element connected to conduct current between the first arm output and a second connection;

a second switching arm comprising a third switching element connected to conduct current between a third connection and an output of the second arm and a fourth switching element connected to conduct current between the second arm output and a fourth connection;

wherein the first and second switching arms are connected in series across the input terminals with the first connection of the first arm coupled to the first input terminal, the second connection of the first arm coupled to the third connection of the second arm and the fourth connection of the second arm coupled to the second input terminal;

a voltage divider coupled across the input terminals having an output of the voltage divider coupled to the second and third connections; an output coupling connected between the outputs of the first and second switching arms;

drive circuitry for driving each of the first, second, third and fourth switching elements to produce switching waveforms such that the voltage across each of the switching arms remains below a predetermined proportion of the input voltage.

2. A power inverter according to Claim 1 arranged so that the proportion of the input voltage across each arm is substantially constant.

3. A power inverter according to Claim 1 or 2 arranged to maintain the proportion of input voltage across each arm substantially within limits.

4. A power inverter according to any preceding claim wherein the voltage divider is arranged to divide the input voltage substantially in half.

5. A power inverter according to any preceding claim arranged ensure that the proportion across any one arm does not exceed %, preferably is no greater than 2/3 of the total voltage,

6. A power inverter according to any preceding claim arranged to ensure that the voltage across each arm does not exceed a given absolute voltage.

7. A power inverter according to any preceding claim having protection means to adjust the switching waveforms to maintain voltage within limits.

8. A power inverter according to any preceding claim wherein voltage divider which is not capable of passing sustained full power to each arm.

9. A power inverter according to Claim 8 wherein the inverter arms serve to supply current to each other in addition to the voltage divider.

10. A power inverter according to any preceding claim wherein the voltage divider comprises capacitors connected in series.

11. A power inverter according to any preceding claim arranged to operate at a switching frequency of at least 1 kHz.

12. A power inverter according to Claim 10 wherein the capacitors are sized so that maximum voltage change across an arm during a cycle of the inverter output is no more than 10% of the nominal voltage.

13. A power inverter according to Claim 11 arranged to operate at a switching frequency greater than 15kHz i?

14. A power inverter according to any preceding claim wherein the drive circuitry is arranged to drive the switching elements in a phase shift mode wherein the first and second arms are driven with similar waveforms and the magnitude of the relative phase difference between the arms is adjusted to control the output.

15. A power inverter according to Claim 14 wherein the drive circuitry is arranged to adjust the sign of the relative phase shift of the first arm with respect to the second arm to reduce imbalances in the voltage across each arm.

16. A power inverter according to Claim 15 arranged to alternate lead and lag of the first and second arms substantially every predetermined number of cycles.

17. A power inverter according to Claim 15 arranged to adjust relative phase shift sign in response to measured voltage across each arm.

18. A power inverter according to any of Claims 14 to 17 in which both arms are driven with a substantially square wave drive signal with a duty cycle of substantially

50%.

19. A power inverter according to Claim 18 wherein a switching time of one of the arms is advanced or retarded at a designated cycle to adjust the sign of the phase shift from lag to lead or vice versa.

20. A power inverter according to Claim 19 wherein a switching time of the other of the arms is respectively retarded or advanced at the same designated cycle.

21. A power inverter according to Claim 20 wherein a designated cycle occurs every predetermined number of switching cycles.

22. A power inverter according to Claim 21 wherein the predetermined number is between about 5 and 50 inclusive.

23. A power inverter according to any preceding claim wherein the drive circuitry is arranged to drive the switching elements in a pulse width modulation mode in which the duty cycle of switching is adjusted to control the output.

24. A power inverter according to Claim 23 arranged to adjust duty cycles to reduce imbalances in voltage across the arms.

25. A power inverter according to any preceding claim having protection circuitry for reducing a conduction duty cycle across one arm if the voltage across the other arm

26. A power inverter according to any preceding claim having at least one further switching arm coupled in series with the first and second switching arms.

27. A power inverter according to any preceding claim wherein the switching elements comprise IGBTs.

28. A power inverter according to any preceding claim arranged to receive an input voltage in excess of 500 volts and to withstand an input voltage transient in excess of 1000 volts.

29. A power inverter according to Claim 28 for a railway power application arranged to receive track voltage from a railway line power supply nominally in the range of 600 to 750 volts DC and to withstand transients up to 1500 volts, wherein the track voltage is supplied to the input terminals and wherein the switching elements have a rated voltage of at least 500 volts but less than 1500 volts, wherein the drive circuitry is arranged to adjust the switching waveforms to control the output voltage substantially to a desired level within a workable input voltage range of 500 to 1000 volts and wherein the drive circuitry is arranged to adjust the switching waveform to prevent the switching elements ige in the event of said transients

30. A power inverter according to Claim 29 for a railway power application arranged to operate at a switching frequency of at least 15 kHz, having an output transformer arranged to provide galvanic isolation of the output from the input arranged to operate at the switching frequency.

31. A power inverter according to any preceding claim wherein the switching arms are arranged to switch input currents to the primary winding of an output transformer and wherein the secondary winding provides an output galvanically isolated from the input

32. A power inverter according to Claim 31 wherein the output of the secondary winding is rectified to provide a DC supply galvanically isolated from the input DC

33. A power inverter according to Claim 32 arranged to operate from a DC supply having a nominal input voltage of at least 600 volts DC at a switching frequency of at least 10 kHz to provide a DC to DC converter with galvanic isolation.

34. A DC-DC power converter for a railway application substantially as any one herein described, with reference to Fig.l or Fig. 2 of the accompanying drawings.