WO2011008451A3 - Système et procédé réagissant à un taux de changement d'un paramètre de performances d'une mémoire - Google Patents

Système et procédé réagissant à un taux de changement d'un paramètre de performances d'une mémoire Download PDF

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Publication number
WO2011008451A3
WO2011008451A3 PCT/US2010/039710 US2010039710W WO2011008451A3 WO 2011008451 A3 WO2011008451 A3 WO 2011008451A3 US 2010039710 W US2010039710 W US 2010039710W WO 2011008451 A3 WO2011008451 A3 WO 2011008451A3
Authority
WO
WIPO (PCT)
Prior art keywords
rate
change
performance parameter
memory
method responsive
Prior art date
Application number
PCT/US2010/039710
Other languages
English (en)
Other versions
WO2011008451A2 (fr
Inventor
Manuel Antonio D'abreu
Stephen Skala
Dana Lee
Original Assignee
Sandisk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk Corporation filed Critical Sandisk Corporation
Priority to EP10728542A priority Critical patent/EP2449556A2/fr
Publication of WO2011008451A2 publication Critical patent/WO2011008451A2/fr
Publication of WO2011008451A3 publication Critical patent/WO2011008451A3/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

Abstract

L'invention porte sur des systèmes et des procédés qui réagissent à un taux de changement d'un paramètre de performances d'une mémoire. Dans un mode de réalisation particulier, un taux de changement d'un paramètre de performances d'une mémoire rémanente est déterminé. Le taux de changement est comparé à un seuil, et une action est effectuée en réponse à la détermination du fait que le taux de changement satisfait au seuil.
PCT/US2010/039710 2009-06-29 2010-06-23 Système et procédé réagissant à un taux de changement d'un paramètre de performances d'une mémoire WO2011008451A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP10728542A EP2449556A2 (fr) 2009-06-29 2010-06-23 Systeme et procede reagissant a un taux de changement d'un parametre d'une memoire

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/494,222 2009-06-29
US12/494,222 US8321727B2 (en) 2009-06-29 2009-06-29 System and method responsive to a rate of change of a performance parameter of a memory

Publications (2)

Publication Number Publication Date
WO2011008451A2 WO2011008451A2 (fr) 2011-01-20
WO2011008451A3 true WO2011008451A3 (fr) 2011-06-16

Family

ID=42752909

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/039710 WO2011008451A2 (fr) 2009-06-29 2010-06-23 Système et procédé réagissant à un taux de changement d'un paramètre de performances d'une mémoire

Country Status (5)

Country Link
US (1) US8321727B2 (fr)
EP (1) EP2449556A2 (fr)
KR (1) KR20120111937A (fr)
TW (1) TW201110131A (fr)
WO (1) WO2011008451A2 (fr)

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Also Published As

Publication number Publication date
EP2449556A2 (fr) 2012-05-09
US20100332923A1 (en) 2010-12-30
TW201110131A (en) 2011-03-16
KR20120111937A (ko) 2012-10-11
US8321727B2 (en) 2012-11-27
WO2011008451A2 (fr) 2011-01-20

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