WO2010150465A1

WO2010150465A1 - Av (audio visual) data playback circuit, av data playback device, integrated circuit, and av data playback method

Info

Publication number: WO2010150465A1
Application number: PCT/JP2010/003630
Authority: WO
Inventors: 音村英二; 中嶋廣二
Original assignee: パナソニック株式会社
Priority date: 2009-06-25
Filing date: 2010-05-31
Publication date: 2010-12-29

Abstract

An acquisition unit (120) acquires the parameters of AV data. A control unit (210), on the basis of the acquired parameters, selects from among three processors (200.1, 200.2, 200.3) the processor which executes processing C included in playback processing for playing AV data, and, on the basis of the acquired parameters, selects from among the three processors (200.1,200.2,200.3) the processor which executes processing E. The control unit (210) makes the processor selected to execute processing C execute processing C, and makes the processor selected to execute processing E execute processing E.

Description

AV (Audio Visual) data reproduction circuit, AV data reproduction device, integrated circuit, and AV data reproduction method

The present invention relates to an AV data reproducing circuit, an AV data reproducing device, an integrated circuit, and an AV data reproducing method for performing processing for reproducing AV data using a plurality of processors.

In recent years, there has been a growing demand for realizing an apparatus for processing AV data (hereinafter referred to as AV (Audio Visual) apparatus) which is high-quality video and high-quality sound data at a low cost. In order to realize a low-cost AV device, it is conceivable to perform video processing and audio processing by software in the AV device. In the following, video processing and audio processing are collectively referred to as AV data processing.

Patent Document 1 discloses a technique for processing a moving image by software.

JP 2001-245294 A

When executing AV data processing with software, a processor or the like is usually used. However, when AV data processing is executed by software, it is not practical unless a very high performance processor is used or processing is distributed to a plurality of processors.

When processing is distributed to a plurality of processors, the AV data processing is generally divided into a plurality of processes, and the plurality of processes are generally assigned to a plurality of processors so as not to overlap.

However, in this method, the processing executed by each of the plurality of processors is generally fixed. Therefore, depending on the parameters of the AV data to be reproduced, there is a process that may not be executed. In this case, the usage rate of a processor to which processing that need not be executed is assigned becomes low, and the processor is not effectively used.

The present invention has been made to solve the above-described problems, and an object of the present invention is to enable effective use of a processor when reproducing AV data using a plurality of processors. An AV data reproducing circuit and the like are provided.

In order to solve the above-described problem, an AV data reproduction circuit according to an aspect of the present invention performs reproduction processing for reproducing AV (Audio Visual) data using N (integer of 2 or more) processors. . The reproduction process includes K (an integer greater than or equal to 2) processes. The AV data reproduction circuit includes an obtaining unit that obtains parameters of AV data to be reproduced in the reproduction process, and first processing that is one of K processes based on the obtained parameters. A processing execution control unit that causes at least one of the processors to execute the processing. The process execution control unit selects a processor for executing the first process from among the N processors based on the acquired parameters, and selects K of the N processors based on the acquired parameters. A processor that executes a second process that is a process other than the first process is selected. The process execution control unit causes the processor selected to execute the first process to execute the first process, and causes the selected processor to execute the second process to execute the second process.

That is, the acquisition unit acquires AV data parameters. The process execution control unit executes a first process that is one of the K processes included in the reproduction process for reproducing AV data among the N processors based on the acquired parameters. A processor is selected, and a processor for executing the second process is selected from the N processors based on the acquired parameters. The process execution control unit causes the processor selected to execute the first process to execute the first process, and causes the selected processor to execute the second process to execute the second process.

That is, based on the parameters of the AV data, the selected processor is caused to execute each of the first process and the second process included in the reproduction process for reproducing the AV data. That is, the processor that executes each of the first process and the second process included in the reproduction process is dynamically changed based on the parameters of the AV data.

Therefore, when reproducing AV data using a plurality of processors, the processors can be used effectively.

Preferably, the predetermined processor of the N processors can execute the predetermined process of the K processes, and the parameter of the AV data needs to be executed. If the AV data parameter indicates that the predetermined process does not need to be executed, the process execution control unit instructs the predetermined processor to execute the predetermined process among the K processes. A process requiring a calculation amount equal to or less than the calculation amount is executed.

Thus, when it is not necessary to execute a predetermined process, the predetermined processor can execute another process, and the usage rate of the predetermined processor can be prevented from becoming extremely small. That is, when reproducing AV data using a plurality of processors, the processors can be used effectively.

Preferably, the AV data includes audio data and video data, the first process is an audio reproduction process for reproducing the audio data, and the second process is an image reproduction process for reproducing the video data. The AV data reproduction circuit further includes a separation unit that separates the AV data into audio data and video data.

Also preferably, the acquisition unit acquires video data parameters, and the process execution control unit causes one of the N processors to execute audio reproduction processing based on the video data parameters.

Preferably, the first processor, which is one of the N processors, executes the video playback process, and the video playback process includes the third process, and the audio playback process as the first process is performed. The amount of calculation required for execution is less than or equal to the amount of calculation required for execution of the third process, and the parameter of the video data indicates whether the third process needs to be executed on the video data. When the parameter of the video data indicates that the third process does not need to be executed, the execution control unit causes the first processor to execute the audio reproduction process and does not cause the first processor to execute the third process.

Thus, when the third process does not need to be executed, the first processor can execute the audio reproduction process, and the usage rate of the first processor can be prevented from becoming extremely small. That is, when reproducing AV data using a plurality of processors, the processors can be used effectively.

Preferably, the AV data includes video data, and the second process is a video playback process for playing back the video data. The acquisition unit acquires a parameter of the video data. 3 processing, 4th processing, and 5th processing are included, the amount of calculation required for execution of the 5th processing is less than the amount of calculation required for execution of the 4th processing, and the amount of calculation required for execution of the 4th processing is , The amount of calculation is less than or equal to the amount of computation required for execution of the third process, and the video data parameter indicates whether or not the third process needs to be executed. When indicating that the process needs to be executed, the first processor, which is one of the N processors, executes the third process and the fifth process, and the N processors other than the first processor Processor When a certain second processor executes the fourth process, and the process execution control unit causes the first processor to execute the fourth process when the parameter of the video data indicates that the third process does not need to be executed, The second processor is caused to execute the fifth process.

Thereby, when the third process does not need to be executed, the first processor can be caused to execute the fourth process, and the usage rate of the first processor can be prevented from becoming extremely small. That is, when reproducing AV data using a plurality of processors, the processors can be used effectively.

Also preferably, the video playback process is a playback process using correlation between frames, the fourth process is a luminance motion compensation process, and the fifth process is a color difference motion compensation process.

Also preferably, the video reproduction process further includes a variable length decoding process, and the process execution control unit causes the second processor to execute the variable length decoding process.

Also preferably, the video playback processing is performed by H.264. The reproduction process conforms to the H.264 / AVC standard, and the third process is a deblocking filter process.

Also preferably, the AV data includes video data, and the parameter of the AV data is a size of a frame constituting the video data.

Also preferably, the AV data includes video data, and the parameter of the AV data is a frame rate of the video data.

Also preferably, the AV data includes video data, and the parameter of the AV data is a bit rate of the video data.

Also preferably, the AV data includes video data, the video data is compressed by a predetermined encoding method, and the parameter of the AV data is a type of the encoding method.

Also preferably, the parameter of the AV data is an arithmetic processing capability value necessary for processing the AV data.

An AV data reproducing device according to another aspect of the present invention is an AV data reproducing device including the AV data reproducing circuit. The AV data reproducing apparatus further includes a memory for storing audio data and video data, and a decoded data obtained by the audio data reproducing circuit performing audio reproducing processing for reproducing the audio data on the audio data. An audio output device that outputs audio based on the audio data of the video and an AV data reproduction circuit that is based on decoded video data obtained by performing video reproduction processing for reproducing the video data on the video data And a display device for displaying.

An integrated circuit according to still another aspect of the present invention performs reproduction processing for reproducing AV (Audio Visual) data using N (integer of 2 or more) processors. The reproduction process includes K (integer greater than or equal to 2) processes, and the integrated circuit obtains a parameter of AV data to be reproduced in the reproduction process, and K pieces based on the obtained parameters. A process execution control unit that causes at least one of the N processors to execute a first process that is one of the processes, and the process execution control unit includes the N processors based on the acquired parameters. The processor that selects the processor that executes the first process, and executes the second process that is a process other than the first process among the K processes, among the N processors, based on the acquired parameters. The process execution control unit causes the processor selected to execute the first process to execute the first process and causes the processor selected to execute the second process to execute the second process. To be executed.

The AV data reproduction method according to still another aspect of the present invention is performed by an AV data reproduction circuit that performs reproduction processing for reproducing AV (Audio Visual) data using N (integer of 2 or more) processors. The reproduction process includes K (integer of 2 or more) processes, and the AV data reproduction circuit obtains a parameter of AV data to be reproduced in the reproduction process, and K based on the obtained parameter. A process execution control unit that causes at least one of the N processors to execute a first process that is one of the processes. In the AV data reproduction method, the acquisition unit acquires a parameter of AV data, and the process execution control unit selects a processor for executing the first process among the N processors based on the acquired parameter. Then, based on the acquired parameter, a processor that executes a second process that is a process other than the first process among the K processes among the N processors is selected, and the process execution control unit selects the first process Causing the processor selected to execute the process to execute the first process and causing the selected processor to execute the second process to execute the second process.

Note that the present invention may be realized not only as such an AV data reproduction method but also as a program for causing a computer to execute each step included in such an AV data reproduction method. Such a program may be distributed via a recording medium such as a CD-ROM or a transmission medium such as the Internet.

According to the present invention, when reproducing AV data using a plurality of processors, the processors can be used effectively.

FIG. 1 is a diagram showing a configuration of an AV data reproducing circuit according to the first embodiment. FIG. 2 is a flowchart of the reproduction execution process. FIG. 3 is a diagram illustrating a configuration of an AV data reproducing circuit according to the second embodiment. FIG. 4 is a diagram illustrating a configuration of an AV data reproducing circuit according to the third embodiment. FIG. 5 is a diagram showing a configuration of an AV data reproducing apparatus according to the fourth embodiment. FIG. 6 is a block diagram showing a characteristic functional configuration of the AV data reproducing circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of an AV data reproducing circuit 1000 according to the first embodiment. The AV data reproduction circuit 1000 is an integrated circuit such as an LSI (Large Scale Integration). Although details will be described later, the AV data reproduction circuit 1000 performs a reproduction process for reproducing AV data using N (integer of 2 or more) processors.

Referring to FIG. 1, the AV data reproduction circuit 1000 includes a separation unit 110, an acquisition unit 120, a parameter storage unit 130, and processors 200.1, 200.2, 200.3.

The separation unit 110 acquires AV (Audio Visual) data from the outside. AV data is data encoded by a predetermined encoding method. AV data includes audio data, video data, and parameter information.

The audio data included in the AV data is, for example, data encoded by an encoding method according to the MPEG (Moving Picture Experts Group) standard. The video data included in the AV data is, for example, H.264. It is data encoded by an encoding method according to the H.264 / AVC standard. That is, the video data is compressed by a predetermined encoding method.

Note that the audio data is not limited to the MPEG standard, and may be data encoded by another encoding method such as AAC (Advance Audio Coding) or AC3 (Audio Code 3). The video data is H.264. The data is not limited to the H.264 / AVC standard, and may be data encoded by another encoding method such as MPEG2 or MPEG4.

AV data is data stored in a memory (not shown). The AV data may be data received as a broadcast wave.

The separation unit 110 separates the acquired AV data into audio data and video data. Then, the separation unit 110 transmits the audio data and the video data to the processor 200.1.

The parameter storage unit 130 is a memory that stores parameter information.

The acquisition unit 120 acquires AV data from the outside, and acquires parameter information included in the AV data from the AV data. The parameter information indicates a plurality of parameters of corresponding AV data. The parameters of the AV data are, for example, a frame size, a frame rate, a bit rate, the number of channels, a codec type, an arithmetic processing capability value, deblocking filter necessary information, and the like.

The frame size is the size of the frame constituting the corresponding video data. That is, the frame size as a parameter of AV data is the size of a frame constituting video data. The frame rate is the frame rate of the corresponding video data. That is, the frame rate as a parameter of AV data is the frame rate of video data. The bit rate is the bit rate of the corresponding audio data and the corresponding video data. That is, the bit rate as a parameter of AV data is the bit rate of video data. The number of channels is the number of channels of corresponding audio data.

The codec type is the type of encoding method used when generating corresponding audio data and corresponding video data. That is, the codec type as a parameter of AV data is the type of encoding method. The codec type is, for example, H.264. H.264 / AVC, MPEG2, and the like. The arithmetic processing capability value is a value of the arithmetic processing capability required to normally reproduce the corresponding video data. That is, the arithmetic processing capability value as a parameter of AV data is an arithmetic processing capability value necessary for processing AV data. The arithmetic processing capability value is, for example, a MIPS (Million Instructions Per Per Second) value.

The deblocking filter necessary information indicates whether or not the deblocking filter processing as the in-loop filter needs to be executed when the corresponding video data is reproduced. That is, the deblocking filter necessary information indicates whether or not the deblocking filter processing as the in-loop filter is necessary when the corresponding video data is reproduced. That is, the deblocking filter necessary information as a parameter of AV data indicates whether or not a predetermined process (deblocking filter process) needs to be executed.

The acquisition unit 120 causes the parameter storage unit 130 to store the acquired parameter information.

Processors 200.1, 200.2, and 200.3 perform reproduction processing for reproducing AV data. The reproduction process includes a plurality of processes (processes A, B, C, D, and E in FIG. 1).

Each of the processors 200.1, 200.2, and 200.3 is assigned in advance a plurality of program modules for executing some or all of the plurality of processes included in the reproduction process.

The processor 200.1 includes a control unit 210. The control unit 210 is an arithmetic processing circuit such as a CPU (Central Processing Unit) and a DSP (Digital Signal Processing). A program module for executing each of the processes A, B, C, D, and E is assigned to the control unit 210 in advance. Thereby, the control unit 210 can execute the processes A, B, C, D, and E. The control unit 210 is a process execution control unit that performs processing for causing a processor to execute processing.

A program module for executing each of the processes B, C, D, and E is assigned to the processor 200.2 in advance. Thereby, the processor 200.2 can execute the processes B, C, D, and E.

A program module for executing each of the processes C, D, and E is allocated to the processor 200.3 in advance. Thereby, the processor 200.3 can execute the processes C, D, and E.

That is, a predetermined processor (for example, the processor 200.3) among N (integers greater than or equal to 2) processors performs a predetermined process (of integers greater than or equal to 2) included in the reproduction process ( For example, the processes C, D, and E) can be executed.

Thus, for example, only the processor 200.1 can execute the process A. Note that the assignment of program modules in each of the processors 200.1, 200.2, 200.3 is not limited to the above. For example, the program module assigned to each of the processors 200.1, 200.2, 200.3 may be a program module for executing different processes.

Next, processing for reproducing AV data (hereinafter referred to as reproduction execution processing) performed by the AV data reproduction circuit 1000 will be described. Assume that the processor 200.1 receives the above-described audio data and video data from the separation unit 110 by a process independent of the reproduction execution process.

FIG. 2 is a flowchart of the reproduction execution process.

In step S111, parameter acquisition processing is performed. In the parameter acquisition process, the acquisition unit 120 acquires AV data from the outside, and acquires parameter information included in the AV data from the AV data. The acquisition unit 120 causes the parameter storage unit 130 to store the acquired parameter information.

That is, in the parameter acquisition process, the acquisition unit 120 acquires AV data parameters. That is, the acquisition unit 120 acquires AV data parameters to be played back in the playback process.

In step S112, a process execution control process is performed. In the process execution control process, the control unit 210 reads parameter information stored in the parameter storage unit 130. Here, it is assumed that the parameter information indicates the above-described frame size, frame rate, bit rate, number of channels, codec type, arithmetic processing capability value, deblocking filter necessary information, and the like as parameters.

Then, the control unit 210 performs each process (for example, processes A, B, C, D, and E) included in the reproduction process based on at least one of the plurality of parameters of the corresponding AV data indicated by the parameter information. Select a processor to run.

In addition, when the control part 210 selects the processor which performs each process, the processing load (henceforth a utilization rate) of each processor (processor 200.1, 200.2, 200.3) becomes substantially equivalent. Like that. That is, a processor whose usage rate is significantly smaller than other processors among a plurality of processors is not generated.

Then, the control unit 210 causes the processor selected to execute the process to execute the process.

Next, the process execution control process will be described in detail with an example.

Here, as an example, video data of AV data is H.264. It is assumed that the data is encoded by an encoding method according to the H.264 / AVC standard. In this case, the process of reproducing AV data in the AV data reproducing circuit 1000 is H.264. H.264 / AVC standard reproduction processing.

Further, the processes A, B, C, D, and E shown in FIG. 1 are, for example, a variable length decoding process, an inverse quantization process, an inverse DCT process, a speech decoding process, and a deblocking filter process, respectively. To do. That is, it is assumed that the process E is a deblocking filter process. Since the variable-length decoding process, the inverse quantization process, the inverse DCT process, and the deblocking filter process are well-known processes, detailed description thereof will not be repeated. The audio decoding process is a process for decoding audio data.

In addition, the amount of calculation processing necessary for executing both the processing C and the processing D is set to be equal to or less than the amount of calculation processing required for executing the deblocking filter processing. Further, the parameter used by the control unit 210 for selecting a processor is, for example, deblocking filter necessary information indicated by the parameter information.

In this case, in the process execution control process, when the control unit 210 indicates that the deblocking filter necessary information indicates that the deblocking filter process is not necessary, that is, the deblocking filter process is not necessary, as an example, the process C , D is selected as a processor 200.3. In this case, as an example, the control unit 210 selects the processor 200.1 as the processor that executes the process A. In this case, as an example, the control unit 210 selects the processor 200.2 as the processor that executes the process B.

In other words, in the process execution control process, the process execution control unit (the control unit 210) performs a first process (for example, processes C and D) out of N (integer of 2 or more) processors based on the acquired parameters. ) Is selected. In addition, the process execution control unit is a process other than the first process among the K (integers greater than or equal to 2) processes included in the reproduction process among the N processors based on the acquired parameters. A processor for executing a process (for example, process A) is selected.

In the process execution control process, the control unit 210 transmits a command for executing each process to the processor selected to execute each of the processes A, B, C, and D. For example, the control unit 210 transmits a command for executing the processes C and D to the processor 200.3.

Thereby, the processor 200.1 executes the variable length decoding process as the process A. In addition, the processor 200.2 that has received the instruction executes an inverse quantization process as the process B. In addition, the processor 200.3 that has received the instruction executes an inverse DCT process as the process C and a speech decoding process as the process D. That is, the control unit 210 causes a processor selected to execute each process (for example, processes A, B, C, and D) to execute a corresponding process.

That is, in the process execution control process, the process execution control unit (control unit 210) causes the processor selected to execute the first process to execute the first process and causes the processor selected to execute the second process to The second process is executed. That is, the process execution control unit (control unit 210) causes at least one of the N processors to execute the first process, which is one of the K processes, based on the acquired parameter.

Note that, as described above, when the processor that executes each process is selected, the control unit 210 makes the usage rate of each processor almost equal.

The processor 200.1 transmits the data and audio data obtained by the processing (processing A) performed on the received video data to the processor 200.2. The processor 200.2 transmits data and audio data obtained by the executed processing to the processor 200.3. The processor 200.3 outputs decoded audio data (hereinafter referred to as decoded audio data) and decoded video data (hereinafter referred to as decoded video data) obtained by the executed processing to the outside.

Further, when the deblocking filter necessary information indicates that the deblocking filter process is necessary, the control unit 210 selects the processor 200.3 as a processor that executes the process E as an example. In this case, as an example, the control unit 210 selects the processor 200.1 as the processor that executes the processes A and B. In this case, as an example, the control unit 210 selects the processor 200.2 as a processor that executes the processes C and D. Then, the control unit 210 transmits a command for executing each process to the processor selected to execute each of the processes A, B, C, and D.

Note that the processing in each processor that has received the command is the same as the processing described when the deblocking filter necessary information indicates that the deblocking filter processing is not necessary, and therefore detailed description will not be repeated.

The AV data that is the encoded data is decoded by the above processing. That is, AV data is reproduced.

As another example of the process execution control process, the parameter used by the control unit 210 to select a processor is one of the frame size, the frame rate, the bit rate, the codec type, and the arithmetic processing capability value indicated by the parameter information. There may be.

Regardless of the parameters used for selecting a processor, the control unit 210 makes the usage rate of each processor substantially equal when selecting a processor to execute each process. .

As described above, in the present embodiment, in the reproduction of AV data, a parameter used for selecting a processor indicates whether or not a predetermined process (for example, deblocking filter process) is necessary.

In this case, when the predetermined process (for example, deblocking filter process) is unnecessary, the process execution control unit (control unit 210) performs a calculation necessary for executing the predetermined process on a processor capable of executing the predetermined process. A process that requires a calculation amount equal to or less than the amount is executed. That is, when the AV data parameter indicates that the predetermined process does not need to be executed, the process execution control unit (control unit 210) sends a predetermined processor to the predetermined process among the K processes included in the reproduction process. The processing that requires a calculation amount equal to or less than the calculation amount necessary for executing this process is executed.

Thus, when the predetermined process is unnecessary, the processor capable of executing the predetermined process can execute another process, and the usage rate of the processor can be prevented from becoming extremely small. That is, when reproducing AV data using a plurality of processors, the processors can be used effectively.

Therefore, it is possible to improve the processing of the plurality of processors as a whole, and to improve the processing amount per unit time of the AV data reproducing circuit 1000. That is, the performance of the AV data reproduction circuit 1000 can be improved.

Further, in this embodiment, when reproducing AV data, when the control unit 210 selects a processor to execute each process, the usage rate of each processor is made substantially equal. Thereby, it is possible to prevent the usage rate of the processor from becoming extremely small.

In this embodiment, the control unit 210 that causes each processor to execute processing is included in the processor. However, the present invention is not limited to this, and the control unit 210 may be provided outside the processor. Good.

In addition, although the separation unit 110, the acquisition unit 120, and the parameter storage unit 130 are provided outside the processor, the separation unit 110, the acquisition unit 120, and the parameter storage unit 130 are partly or entirely included in the processor. (For example, the processor 200.1) may be provided.

In the process execution control process, parameters used for selecting a processor are not limited to those described above. For example, it may be information (eg, playback time) included in audio data, information (eg, playback time) included in video data, and the like.

In the present embodiment, the processing to be executed by each processor is switched based on the parameter indicated by the parameter information included in the AV data. However, the present invention is not limited to this. The information for switching the processing to be executed by each processor may be, for example, information related to multiplexing of AV data or information given from the outside.

In the present embodiment, the processing when the number of processing (processing A, B, C, D, E) included in the playback processing is five has been described, but the present invention is limited to this. There is no. The number of processes included in the reproduction process may be 4 or less or 6 or more.

In the present embodiment, the processing using three processors has been described when reproducing AV data. However, the present invention is not limited to this. When reproducing AV data, two or less or four or more processors may be used.

<Second Embodiment>
FIG. 3 is a diagram showing the configuration of the AV data reproducing circuit 1000A in the second embodiment. The AV data reproduction circuit 1000A is an integrated circuit such as an LSI (Large Scale Integration).

Referring to FIG. 3, AV data reproduction circuit 1000A is further provided with a control unit 210 as compared with AV data reproduction circuit 1000 in FIG. 1, and a program module corresponding to each process is assigned to control unit 210. The difference is that the processor 200.1A, 200.2A is provided instead of the processor 200.1, 200.2, 200.3. Since the other configuration is the same as that of the AV data reproducing circuit 1000, detailed description will not be repeated.

The separation unit 110 transmits audio data and video data obtained by separating the AV data to the control unit 210.

The control unit 210 transmits the received audio data to one of the processors 200.1A and 200.2A by a process described later. Further, the control unit 210 transmits the received video data to the processor 200.2A.

The processors 200.1A and 200.2A perform a reproduction process A for reproducing AV data. The reproduction process A includes an audio reproduction process and a video reproduction process. The audio reproduction process is a process for decoding the encoded audio data. The video reproduction process is a process for decoding the encoded video data.

Hereinafter, the sound reproduction process is also referred to as a first process. Hereinafter, the video reproduction process is also referred to as a second process. That is, the first process (audio reproduction process) is a process for reproducing audio data. The second process (video playback process) is a video playback process for playing back video data.

In the following, the processor 200.2A is also referred to as a first processor.

A program module for executing a sound reproduction process is assigned to the processor 200.1A in advance. As a result, the processor 200.1A can execute the audio reproduction process. A program module for executing each of the audio reproduction process and the video reproduction process is allocated in advance to the processor 200.2A. Thereby, the processor 200.2A can execute the audio reproduction process and the video reproduction process.

Note that the assignment of program modules in each of the processors 200.1A and 200.2A is not limited to the above.

Next, a process (playback execution process) for playing back AV data performed by the AV data playback circuit 1000A will be described. Note that the video reproduction process is preset so that the processor 200.2A executes. That is, the first processor (processor 200.2A), which is one of the N processors, is executing the video reproduction process.

Further, the control unit 210 transmits the video data received from the separation unit 110 to the processor 200.2A by a process independent of the reproduction execution process. Further, it is assumed that control unit 210 transmits a command for executing video reproduction processing to processor 200.2A. Receiving the command, the processor 200.2A executes video reproduction processing independently of other processing.

Referring to FIG. 2 again, in step S111, the same processing as in the first embodiment is performed, and thus detailed description will not be repeated. Through this process, the acquisition unit 120 acquires parameter information included in the AV data, and causes the parameter storage unit 130 to store the parameter information included in the AV data. That is, the acquisition unit 120 acquires audio data and video data parameters included in the AV data.

In step S112, the process execution control process is performed in the same manner as in the first embodiment, and thus detailed description will not be repeated.

By this process, the control unit 210 reads the parameter information stored in the parameter storage unit 130. Here, it is assumed that the parameter information indicates the above-described frame size, frame rate, bit rate, number of channels, codec type, arithmetic processing capability value, deblocking filter necessary information, and the like as parameters.

In the process execution control process, the control unit 210 selects a processor for executing the audio reproduction process included in the reproduction process A based on at least one of the plurality of parameters of the corresponding AV data indicated by the parameter information. .

Next, the process execution control process in the second embodiment will be described in detail with an example.

Here, as an example, video data of AV data is H.264. It is assumed that the data is encoded by an encoding method according to the H.264 / AVC standard. In this case, the video reproduction processing for reproducing video data in the AV data reproduction circuit 1000A is H.264. H.264 / AVC standard reproduction processing.

Further, as an example, it is assumed that the video reproduction process includes a deblocking filter process as an in-loop filter. Hereinafter, the deblocking filter process is also referred to as a third process. That is, the video reproduction process includes a third process.

Note that the video reproduction processing includes variable length decoding processing, inverse quantization processing, inverse DCT processing, and the like in addition to the deblocking filter processing.

In addition, the parameter used by the control unit 210 for selecting a processor is, for example, deblocking filter necessary information indicated by the parameter information. Further, it is assumed that the calculation processing amount necessary for executing the audio reproduction processing is equal to or less than the calculation processing amount required for executing the deblocking filter processing.

That is, the amount of calculation necessary for executing the audio reproduction process as the first process is less than the amount of calculation required for executing the third process (deblocking filter process). The video data parameter (deblocking filter necessary information) indicates whether or not the third process needs to be executed on the video data.

In this case, in the process execution control process, when the deblocking filter necessity information indicates that the deblocking filter process is not necessary, that is, the deblocking filter process is not necessary, the control unit 210 executes the sound reproduction process. The processor 200.2A is selected as the processor to be executed.

Then, the control unit 210 instructs the processor 200.2A selected to execute the audio reproduction process to execute the audio reproduction process, an instruction not to execute the deblocking filter process, and the separation unit 110 The received audio data is transmitted.

Thereby, the processor 200.2A that has received the command executes a sound reproduction process for decoding the received sound data. The processor 200.2A outputs decoded audio data (hereinafter referred to as decoded audio data) obtained by the executed audio reproduction process to the outside.

That is, the process execution control unit (control unit 210) causes the first processor (processor 200.2A) to execute the audio reproduction process when the parameter of the video data indicates that the third process need not be executed. The first processor is not allowed to execute the third process. In other words, in the process execution control process according to the second embodiment, the process execution control unit (control unit 210) assigns one of N (an integer greater than or equal to 2) processors to the processor based on the video data parameters. Perform audio playback processing.

As described above, the processor 200.2A executes the video reproduction process independently of the other processes. Therefore, when receiving an instruction not to execute the deblocking filter process, the processor 200.2A executes processes other than the deblocking filter process among a plurality of processes included in the video reproduction process. Then, the processor 200.2A outputs decoded video data (hereinafter referred to as decoded video data) obtained by each process included in the executed video reproduction process to the outside.

Since the processor 200.2A does not need to execute the deblocking filter process included in the video reproduction process, the amount of calculation required to execute the deblocking filter process is reduced. Therefore, the processor 200.2A can execute an audio reproduction process that requires a calculation amount equal to or less than the calculation amount necessary for executing the deblocking filter process. That is, the processor 200.2A can be effectively used.

In the process execution control process, when the deblocking filter necessary information indicates that the deblocking filter process is necessary, the control unit 210 selects the processor 200.1A as the processor for executing the audio reproduction process.

Then, the control unit 210 transmits a command for executing the audio reproduction process and the audio data received from the separation unit 110 to the processor 200.1A selected to execute the audio reproduction process.

Thereby, the processor 200.1A that has received the command executes a sound reproduction process for decoding the sound data. The processor 200.1A outputs the decoded audio data obtained by the executed audio reproduction process to the outside.

As another example of the process execution control process, the parameter used by the control unit 210 to select a processor may be any of a frame size, a frame rate, a bit rate, a codec type, and an arithmetic processing capability value. .

In this case, when the usage rate of the processor 200.2A becomes larger than a predetermined value (for example, 80%) when the processor 200.2A executes both the video reproduction process and the audio reproduction process, the control unit 210 performs the audio reproduction. The processor 200.1A is selected as a processor for executing processing.

For example, it is assumed that the parameter used by the control unit 210 to select a processor is a frame size. In this case, when the frame size is larger than a predetermined size (for example, a size of 640 pixels in the horizontal direction and 480 pixels in the vertical direction), the control unit 210 selects the processor 200.1A as a processor for executing the audio reproduction process.

Further, when the frame size is equal to or smaller than a predetermined size (for example, a size of 640 pixels in the horizontal direction and 480 pixels in the vertical direction), the control unit 210 selects the processor 200.2A as a processor for executing the audio reproduction process. Note that the processing after selecting a processor is the same as the processing described above in the case where the parameter used for selecting the processor is deblocking filter necessary information, so detailed description will not be repeated.

Also, for example, it is assumed that the parameter used by the control unit 210 to select a processor is a bit rate. In this case, when the bit rate of the video data is greater than a predetermined value (for example, 10 Mbps), the control unit 210 selects the processor 200.1A as a processor for executing the audio reproduction process.

Further, when the bit rate of the video data is equal to or less than a predetermined value (for example, 10 Mbps), the control unit 210 selects the processor 200.2A as a processor for executing the audio reproduction process. Note that the processing after selecting a processor is the same as the processing described above in the case where the parameter used for selecting the processor is deblocking filter necessary information, so detailed description will not be repeated.

As described above, in the present embodiment, in the reproduction of AV data, a parameter used for selecting a processor is a parameter indicating whether or not a predetermined process (for example, deblocking filter process) is necessary. . In addition, when a predetermined process (for example, deblocking filter process) is unnecessary, a processor capable of executing the predetermined process is caused to execute a process that requires a calculation amount equal to or less than the calculation amount necessary for executing the predetermined process. .

Thereby, when the predetermined process is unnecessary, the processor capable of executing the predetermined process can execute another process. That is, when reproducing AV data using a plurality of processors, the processors can be used effectively.

Therefore, it is possible to improve the processing of the plurality of processors as a whole, and to improve the processing amount per unit time of the AV data reproduction circuit 1000A. That is, the performance of the AV data reproduction circuit 1000A can be improved.

In addition, when the usage rate of the processor 200.2A becomes larger than a predetermined value when the processor 200.2A executes both the video reproduction process and the audio reproduction process, the control unit 210 performs the audio reproduction process as a processor. The processor 200.1A is selected.

As a result, the usage rate of the processor 200.2A can be prevented from exceeding a predetermined value, and the audio reproduction process and the video reproduction process can be executed in parallel by two different processors. . Therefore, even when the arithmetic processing capability of the processor 200.2A is low, the audio reproduction process and the video reproduction process can be executed in parallel by two different processors. That is, the audio reproduction process and the video reproduction process can be congested.

In the present embodiment, the control unit 210 that causes each processor to execute processing is provided outside the processor. However, the present invention is not limited to this, and the control unit 210 is provided inside the processor. May be.

In addition, although the separation unit 110, the acquisition unit 120, and the parameter storage unit 130 are provided outside the processor, the separation unit 110, the acquisition unit 120, and the parameter storage unit 130 are partly or entirely included in the processor. (For example, the processor 200.1A) may be provided.

In the process execution control process, parameters used for selecting a processor are not limited to those related to video data as described above. The parameter used for selecting the processor may be, for example, a bit rate, the number of channels, a codec type, an arithmetic processing capability value, etc. in audio data. Further, the parameter used for selection by the processor may be, for example, information (for example, reproduction time) included in the audio data.

In this embodiment, the example in which the processor for executing the audio reproduction process is switched based on the parameter of the video data included in the AV data has been described, but the present invention is not limited to this. For example, the present invention may switch the processor that executes the video reproduction process.

In the present embodiment, the number of processors to be selected as a processor for executing the audio reproduction processing is two, but the present invention is not limited to this. Three or more processors may be selected as a target for selecting a processor that executes the audio reproduction process.

<Third Embodiment>
FIG. 4 is a diagram showing a configuration of the AV data reproducing circuit 1000B according to the third embodiment. The AV data reproduction circuit 1000B is an integrated circuit such as an LSI (Large Scale Integration).

Referring to FIG. 4, AV data reproduction circuit 1000B is different from AV data reproduction circuit 1000A in FIG. 3 in that processors 200.1B, 200.2B, 200.3B are used instead of processors 200.1A, 200.2A. Is different. Since the other configuration is the same as that of AV data reproducing circuit 1000A, detailed description will not be repeated.

The separation unit 110 transmits the audio data obtained by separating the AV data to the processor 200.1B. Further, the separation unit 110 transmits the video data obtained by separating the AV data to the processor 200.2B.

The processors 200.1B, 200.2B and 200.3B perform a reproduction process B for reproducing AV data. The reproduction process B includes an audio reproduction process and a video reproduction process. The audio reproduction process in the present embodiment is the same process as the process described in the second embodiment. The video reproduction process in the present embodiment is a process for decoding the encoded video data.

Hereinafter, the processor 200.3B and the processor 200.2B are also referred to as a first processor and a second processor, respectively.

A program module for executing a sound reproduction process is allocated to the processor 200.1B in advance. As a result, the processor 200.1B can execute the audio reproduction process.

The video playback processing in this embodiment is H.264. Assume that the video data reproduction processing conforms to the H.246 / AVC standard. That is, the video playback process is a playback process that uses the correlation between frames. Note that the video reproduction process is H.264. It is not limited to the H.246 / AVC standard, but may be a video data reproduction process according to the MPEG2 standard, for example.

The video playback processing in this embodiment includes header analysis processing, variable length decoding processing, motion vector calculation processing, luminance motion compensation processing, color difference motion compensation processing, inverse quantization processing, inverse DCT processing, intra prediction processing, and image reconstruction. Processing and deblocking filtering.

The variable-length decoding process, the inverse quantization process, the inverse DCT process, the intra prediction process, and the deblocking filter process are well-known processes and will not be described in detail.

The header analysis process is a process for analyzing header information of video data.

The motion vector calculation process in the present embodiment is a process for calculating a motion vector between frames. The luminance motion compensation processing is processing for performing luminance motion compensation based on the motion vector calculated by the motion vector calculation processing. The color difference motion compensation process is a process of performing color difference motion compensation based on the motion vector calculated by the motion vector calculation process. Note that motion compensation is a well-known technique and will not be described in detail.

The intra prediction process is executed when the macro block type analyzed by the header analysis process is an intra macro block.

Image reconstruction processing is processing for reconstructing an image from data obtained by luminance motion compensation processing, color difference motion compensation processing, inverse DCT processing, intra prediction processing, and the like. The deblocking filter process is an in-loop filter process. The deblocking filter process is performed on the image obtained by the image reconstruction process.

Motion vector calculation processing, luminance motion compensation processing, and chrominance motion compensation processing are executed when the macro block type analyzed by the header analysis processing is an inter macro block.

It should be noted that the order in which each process included in the video playback process in this embodiment is performed is H.264. Since it is the same as the order according to the H.246 / AVC standard, detailed description will not be given.

A program module for executing each of header analysis processing, variable length decoding processing, motion vector calculation processing, luminance motion compensation processing, and chrominance motion compensation processing is assigned in advance to the processor 200.2B. Thus, the processor 200.2B can execute header analysis processing, variable length decoding processing, motion vector calculation processing, luminance motion compensation processing, and color difference motion compensation processing.

The processor 200.2B transmits the data obtained by executing the variable length decoding process (hereinafter referred to as variable length decoded data) to the processor 200.3B.

The processor 200.3B previously has a program module for executing each of inverse quantization processing, inverse DCT processing, intra prediction processing, luminance motion compensation processing, color difference motion compensation processing, image reconstruction processing, and deblocking filter processing. Is assigned. Thereby, the processor 200.3B can execute the inverse quantization process, the inverse DCT process, the intra prediction process, the luminance motion compensation process, the color difference motion compensation process, the image reconstruction process, and the deblocking filter process.

When the processor 200.3B receives the variable-length decoded data from the processor 200.2B, the processor 200.3B performs an inverse quantization process on the received variable-length decoded data.

Note that the assignment of program modules in each of the processors 200.1B, 200.2B, and 200.3B is not limited to the above.

Next, a process (playback execution process) for playing back AV data performed by the AV data playback circuit 1000B will be described.

Note that it is assumed that the separation unit 110 transmits audio data to the processor 200.1B. Further, it is assumed that the separating unit 110 transmits the video data to the processor 200.2B.

Also, the audio playback process is preset so that the processor 200.1B executes. In addition, it is assumed that the processor 200.1B executes a sound reproduction process independently of other processes in response to reception of sound data. Therefore, the processor 200.1B outputs the decoded audio data to the outside as in the second embodiment.

Further, it is assumed that the control unit 210 transmits an instruction for executing a header analysis process and a variable length decoding process to the processor 200.2B at a predetermined timing. The processor 200.2B that has received the instruction executes header analysis processing and variable length decoding processing at a predetermined timing. For example, the processor 200.2B sequentially executes a header analysis process and a variable length decoding process in response to reception of video data.

That is, the process execution control unit (control unit 210) causes the second processor (processor 200.2B) to execute variable-length decoding processing.

In addition, when the macro block type analyzed by the header analysis process is an inter macro block, the processor 200.2B executes the motion vector calculation process at a predetermined timing.

Further, it is assumed that the processor 200.3B executes the image reconstruction process at a predetermined timing.

Referring to FIG. 2 again, in step S111, the same processing as in the first embodiment is performed, and thus detailed description will not be repeated. By this processing, parameter information included in the AV data is stored in the parameter storage unit 130. That is, the acquisition unit 120 acquires audio data and video data parameters included in the AV data.

By this process, the control unit 210 reads the parameter information stored in the parameter storage unit 130. The parameter information is assumed to indicate the aforementioned frame size, frame rate, bit rate, number of channels, codec type, arithmetic processing capability value, deblocking filter necessary information, and the like as parameters.

Then, the control unit 210 selects a processor that executes each of the luminance motion compensation processing and the chrominance motion compensation processing based on at least one of the plurality of parameters of the corresponding AV data indicated by the parameter information.

Next, the process execution control process in the present embodiment will be described in detail with an example.

Here, as an example, video data of AV data is H.264. It is assumed that the data is encoded by an encoding method according to the H.264 / AVC standard. In this case, the video playback processing for playing back video data in the AV data playback circuit 1000B is H.264. H.264 / AVC standard reproduction processing. Further, as an example, it is assumed that the macro block type analyzed by the header analysis process is an inter macro block.

In addition, the parameter used by the control unit 210 for selecting a processor is, for example, deblocking filter necessary information indicated by the parameter information. Further, it is assumed that the calculation processing amount necessary for executing the color difference motion compensation processing is less than the calculation processing amount required for executing the luminance motion compensation processing. Further, it is assumed that the calculation processing amount necessary for executing the luminance motion compensation processing is equal to or less than the calculation processing amount required for executing the deblocking filter processing.

Hereinafter, the deblocking filter process is also referred to as a third process. In the following, the luminance motion compensation process is also referred to as a fourth process. In the following, the color difference motion compensation process is also referred to as a fifth process.

That is, the calculation amount necessary for executing the fifth process (color difference motion compensation process) is less than the calculation amount required for executing the fourth process (luminance motion compensation process). In addition, the amount of calculation required for executing the fourth process (luminance motion compensation process) is less than the amount of calculation required for executing the third process (deblocking filter process).

Note that the video reproduction process includes a third process, a fourth process, and a fifth process.

In this case, in the process execution control process, the control unit 210 performs the luminance motion compensation process when the deblocking filter necessary information indicates that the deblocking filter process is not required, that is, the deblocking filter process is not necessary. The processor 200.3B is selected as the processor to be executed, and the processor 200.2B is selected as the processor that executes the color difference motion compensation processing.

And the control part 210 transmits the command for performing a luminance motion compensation process to the processor 200.3B selected in order to perform a luminance motion compensation process. In addition, the control unit 210 transmits a command for executing the color difference motion compensation process to the processor 200.2B selected to execute the color difference motion compensation process.

Thus, the processor 200.3B that has received the command executes luminance motion compensation processing, and the processor 200.2B that has received the command executes color difference motion compensation processing.

That is, when the parameter of the video data indicates that the third process (deblocking filter process) does not need to be executed, the process execution control unit (control unit 210) causes the first processor (processor 200.3B) to 4 processing (luminance motion compensation processing) is executed, and the second processor (processor 200.2B) is caused to execute fifth processing (color difference motion compensation processing).

As described above, since the macro block type analyzed by the header analysis process is the inter macro block, the processor 200.2B executes the motion vector calculation process, and uses the motion vector obtained by the motion vector calculation process as the processor. Send to 200.3B.

The processor 200.3B executes luminance motion compensation processing based on the received motion vector. The processor 200.2B executes a color difference motion compensation process based on the motion vector obtained by the motion vector calculation process, and transmits data obtained by the execution of the color difference motion compensation process to the processor 200.3B.

The processor 200.3B executes the image reconstruction process, thereby obtaining data obtained by executing the luminance motion compensation process, data obtained by executing the color difference motion compensation process, and data obtained by the inverse DCT process. And reconstruct the image.

The processor 200.3B outputs data indicating the reconstructed image to the outside as decoded video data.

In the process execution control process, when the deblocking filter necessary information indicates that the deblocking filter process is necessary, the control unit 210 selects the processor 200.2B as the processor that executes the luminance motion compensation process. At the same time, the processor 200.3B is selected as a processor for executing the color difference motion compensation processing.

And the control part 210 transmits the command for performing a luminance motion compensation process to the processor 200.2B selected in order to perform a luminance motion compensation process. The control unit 210 also instructs the processor 200.3B selected to execute the color difference motion compensation process to execute the color difference motion compensation process and an instruction to execute the deblocking filter process at a predetermined timing. And send.

Thus, the processor 200.2B that has received the command executes luminance motion compensation processing, and the processor 200.3B that has received the command executes color difference motion compensation processing and deblocking filter processing.

That is, when the parameter of the video data indicates that the third process (deblocking filter process) needs to be executed, the process execution control unit (control unit 210) causes the first processor (processor 200.3B) to The third process and the fifth process (color difference motion compensation process) are executed, and the fourth process (luminance motion compensation process) is executed by a second processor (processor 200.2B) other than the first processor among the N processors. .

The processor 200.2B executes luminance motion compensation processing based on the motion vector obtained by the motion vector calculation processing, and transmits data obtained by execution of the luminance motion compensation processing to the processor 200.3B. The processor 200.3B executes color difference motion compensation processing based on the received motion vector.

Then, the processor 200.3B performs deblocking filter processing on the reconstructed image. Then, the processor 200.3B outputs the data obtained by the deblocking filter process to the outside as decoded video data.

As described above, in this embodiment, when the deblocking filter process is not necessary, the processor 200.3B executes the luminance motion compensation process, and the processor 200.2B executes the color difference motion compensation process. The amount of calculation processing necessary for executing the color difference motion compensation processing is less than the amount of calculation processing required for executing the luminance motion compensation processing. Further, the calculation processing amount necessary for executing the luminance motion compensation processing is equal to or less than the calculation processing amount required for executing the deblocking filter processing.

In other words, it is not necessary to execute the deblocking filter process, and the processor 200.3B, which has sufficient capacity for executing the calculation process, has a luminance motion larger than the color difference motion compensation process. The compensation process is executed. In addition, the processor 200.2B is caused to execute a color difference motion compensation process in which the calculation processing amount (usage rate) required at the time of execution is smaller than the luminance motion compensation process.

Thus, the usage rate of the processor 200.3B can be prevented from becoming extremely small, and the processor 200.3B can be used effectively.

Further, when the deblocking filter process is necessary, the processor 200.2B is caused to execute the luminance motion compensation process, and the processor 200.3B is caused to execute the color difference motion compensation process and the deblocking filter process.

That is, the processor 200.2B is caused to execute a luminance motion compensation process in which the calculation processing amount (usage rate) required at the time of execution is larger than the color difference motion compensation process. In addition, the processor 200.3B that needs to execute the deblocking filter process is caused to execute a chrominance motion compensation process in which the calculation processing amount (usage rate) required at the time of execution is smaller than the luminance motion compensation process.

Thereby, the processor 200.2B and the processor 200.3B can be effectively used.

As described above, when reproducing AV data using a plurality of processors, the processors can be used effectively.

Therefore, it is possible to improve the processing of the plurality of processors as a whole, and to improve the processing amount per unit time of the AV data reproduction circuit 1000B. That is, the performance of the AV data reproduction circuit 1000B can be improved.

In addition, although the separation unit 110, the acquisition unit 120, and the parameter storage unit 130 are provided outside the processor, the separation unit 110, the acquisition unit 120, and the parameter storage unit 130 are partly or entirely included in the processor. (For example, the processor 200.2B) may be provided.

In the present embodiment, the motion compensation processing is divided into chrominance motion compensation processing and luminance motion compensation processing, and processing in which each of the chrominance motion compensation processing and luminance motion compensation processing is executed by different processors has been described. The present invention is not limited to this. For example, the processes other than the color difference motion compensation process and the luminance motion compensation process shown in FIG. 4 (for example, variable length decoding process, deblocking filter process, etc.) are divided into a plurality of processes. Each may be executed by a different processor.

In the present embodiment, the processes to be executed by a plurality of processors are the processes included in the video reproduction process and the audio reproduction process. However, the present invention is not limited to this. For example, processing to be executed by a plurality of processors may be media processing such as video shooting processing and audio recording processing, file container processing such as multiplexing processing and demultiplexing processing, OS processing, application processing, etc. Good.

In the present embodiment, the processing for executing each processing by a plurality of processors has been described. However, the present invention is not limited to this. For example, by causing the deblocking filter process to include a plurality of processes respectively corresponding to a plurality of parameters, the plurality of processes included in the deblocking filter process may be switched according to the parameters of the AV data. Good.

<Fourth embodiment>
FIG. 5 is a diagram illustrating a configuration of an AV data reproducing device 2000 according to the fourth embodiment. Referring to FIG. 5, AV data reproducing device 2000 includes a memory 410, an AV data reproducing circuit 1000, an audio output device 420, and a video display device 430. Note that the AV data reproduction device 2000 may include an AV data reproduction circuit 1000A or an AV data reproduction circuit 1000B instead of the AV data reproduction circuit 1000.

The audio output device 420 is a speaker. The video display device 430 is, for example, a liquid crystal monitor. The video display device 430 is not limited to a liquid crystal monitor, and may be any device as long as it can display video.

AV data playback device 2000 stores AV data received from the outside in memory 410. AV data is, for example, data received as a broadcast wave. As described above, the AV data includes audio data, video data, and parameter information.

The AV data reproduction circuit 1000 reproduces (decodes) the audio data by performing the above-described processing (for example, audio reproduction processing) on the audio data included in the AV data stored in the memory 410. As a result, the AV data reproduction circuit 1000 obtains decoded audio data. That is, the AV data reproduction circuit 1000 obtains decoded audio data by performing audio reproduction processing on the audio data.

Then, the AV data reproducing circuit 1000 transmits the obtained decoded audio data to the audio output device 420.

The AV data reproduction circuit 1000 reproduces (decodes) the video data by performing the above-described processing (for example, video reproduction processing) on the video data included in the AV data stored in the memory 410. As a result, the AV data reproduction circuit 1000 obtains decoded video data. That is, the AV data playback circuit 1000 obtains decoded video data by performing video playback processing on the video data.

Then, the AV data reproduction circuit 1000 transmits the obtained decoded video data to the video display device 430.

The audio output device 420 outputs audio based on the received decoded audio data. The video display device 430 displays a video based on the received decoded video data.

In the present embodiment, the processing performed by the AV data reproducing circuit 1000 may be performed by the AV data reproducing circuit 1000A or the AV data reproducing circuit 1000B.

As described above, it is possible to construct the AV data reproducing apparatus 2000 that performs the process of reproducing the AV data according to the parameters of the AV data using the AV data reproducing circuit of the present invention.

As described above, in the present embodiment, an AV data reproducing apparatus that reproduces AV data can be constructed using the AV data reproducing circuit of the present invention.

In the present embodiment, the process of storing AV data in the memory 410 has been described, but the present invention is not limited to this. For example, the AV data may be directly received by the AV data reproducing circuit without storing the AV data in the memory 410.

In the present embodiment, the audio output device 420 has described the process of outputting audio based on the decoded audio data, but the present invention is not limited to this. For example, the decoded audio data may be stored in an external memory.

In the present embodiment, the video display device 430 has described the process of displaying video based on the decoded video data, but the present invention is not limited to this. For example, the decoded video data may be stored in an external memory.

(Function block diagram)
FIG. 6 is a block diagram showing a characteristic functional configuration of the AV data reproduction circuit 3000. The AV data reproduction circuit 3000 is one of the AV

data reproduction circuits

1000, 1000A, and 1000B.

That is, FIG. 6 is a block diagram showing the main functions related to the present invention among the functions of any one of the AV

data reproduction circuits

1000, 1000A, and 1000B.

The AV data reproduction circuit 3000 performs reproduction processing for reproducing AV data using N (an integer of 2 or more) processors. The reproduction process includes K (an integer greater than or equal to 2) processes.

As shown in FIG. 6, the AV data reproduction circuit 3000 includes an acquisition unit 120 and a process execution control unit 400.

The acquisition unit 120 acquires AV data parameters to be reproduced in the reproduction process. The acquisition unit 120 corresponds to the acquisition unit 120 of FIGS. 1, 3, and 4 that performs the process of step S <b> 111 of FIG. 2.

The process execution control unit 400 causes at least one of the N processors to execute the first process, which is one of the K processes, based on the acquired parameter.

The process execution control unit 400 selects a processor for executing the first process from among the N processors based on the acquired parameters, and selects the K of the N processors based on the acquired parameters. A processor that executes a second process, which is a process other than the first process, is selected.

The process execution control unit 400 causes the processor selected to execute the first process to execute the first process and causes the processor selected to execute the second process to execute the second process.

The process execution control unit 400 corresponds to the control unit 210 of FIGS. 1, 3, and 4 that performs the process of step S112 of FIG.

Note that all or part of the acquisition unit 120 and the processing execution control unit 400 in FIG. 6 may be configured by hardware such as an LSI (Large Scale Integration). All or part of the acquisition unit 120 and the process execution control unit 400 may be a module of a program executed by a processor such as a CPU.

In the first to fourth embodiments, the process of executing a plurality of software processes using a plurality of processors has been described. The processor is a computer such as a DSP, a microcomputer, a CPU, and a media processor that operates software installed on an LSI.

Although the first to fourth embodiments have been described on the premise of processing by software, the present invention can be similarly implemented even when realized by hardware processing. As described above, the first to fourth embodiments of the present invention are intended to explain the present invention, and do not limit the contents of the present invention.

Further, all or some of the plurality of constituent elements constituting any one of the AV

data reproducing circuits

1000, 1000A, and 1000B may be configured by hardware. Further, all or a part of the constituent elements constituting any of the AV

data reproduction circuits

1000, 1000A, and 1000B may be a module of a program executed by a CPU (Central Processing Unit) or the like.

data reproduction circuits

1000, 1000A, and 1000B may be configured by one system LSI (Large Scale Integration). Good. The system LSI is an ultra-multifunctional LSI manufactured by integrating a plurality of components on one chip. Specifically, a microprocessor, a ROM (Read Only Memory), a RAM (Random Access Memory), etc. It is a computer system comprised including.

Further, the present invention may be realized as an AV data reproduction method in which the operation of a characteristic component included in any one of the AV

data reproduction circuits

1000, 1000A, and 1000B is a step. The present invention may also be realized as a program that causes a computer to execute each step included in such an AV data reproduction method. Further, the present invention may be realized as a computer-readable recording medium that stores such a program. The program may be distributed via a transmission medium such as the Internet.

The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

The present invention can be used as an AV data reproducing circuit that makes it possible to effectively use a processor.

110 Separation unit 120 Acquisition unit 200.1, 200.2, 200.3, 200.1A, 200.2A, 200.1B, 200.2B, 200.3B Processor 210 Control unit 400 Processing execution control unit 410 Memory 420 Audio Output device 430

Video display device

1000, 1000A, 1000B, 3000 AV data playback circuit 2000 AV data playback device

Claims

An AV data reproduction circuit that performs reproduction processing for reproducing AV (Audio Visual) data using N (integer of 2 or more) processors,
The reproduction process includes K (integer of 2 or more) processes,
The AV data reproduction circuit includes:
An acquisition unit for acquiring parameters of AV data to be reproduced in the reproduction process;
A process execution control unit that causes at least one of the N processors to execute a first process that is one of the K processes based on the acquired parameter;
The process execution control unit selects a processor for executing the first process among the N processors based on the acquired parameters, and the N processors based on the acquired parameters Out of the K processes, a processor that executes a second process that is a process other than the first process is selected,
The process execution control unit causes the processor selected to execute the first process to execute the first process, and causes the processor selected to execute the second process to execute the second process;
AV data reproduction circuit.
A predetermined processor of the N processors can execute a predetermined process of the K processes.
The parameter of the AV data indicates whether the predetermined process needs to be executed,
When the AV data parameter indicates that the predetermined process does not need to be executed, the process execution control unit is required for the predetermined processor to execute the predetermined process among the K processes. To execute a process that requires a calculation amount less than or equal to
The AV data reproducing circuit according to claim 1.
The AV data includes audio data and video data,
The first process is an audio reproduction process for reproducing the audio data,
The second process is a video reproduction process for reproducing the video data,
The AV data reproduction circuit further includes:
A separation unit that separates the AV data into the audio data and the video data;
The AV data reproducing circuit according to claim 1 or 2.
The acquisition unit acquires parameters of the video data,
The process execution control unit causes one of the N processors to execute the audio reproduction process based on the parameter of the video data.
The AV data reproducing circuit according to claim 3.
A first processor, which is one of the N processors, executes the video reproduction process;
The video reproduction process includes a third process,
The amount of computation required for executing the audio reproduction processing as the first processing is equal to or less than the amount of computation required for executing the third processing,
The parameter of the video data indicates whether the third process needs to be executed on the video data,
When the parameter of the video data indicates that the third process does not need to be executed, the process execution control unit causes the first processor to execute the audio reproduction process and causes the first processor to execute the third process. Do not execute the process,
The AV data reproducing circuit according to claim 4.
The AV data includes video data,
The second process is a video reproduction process for reproducing the video data,
The acquisition unit acquires parameters of the video data,
The video reproduction process includes a third process, a fourth process, and a fifth process,
The amount of calculation required for executing the fifth process is less than the amount of calculation required for executing the fourth process,
The amount of calculation required for executing the fourth process is equal to or less than the amount of calculation required for executing the third process,
The parameter of the video data indicates whether the third process needs to be executed,
When the parameter of the video data indicates that the third process needs to be executed, the process execution control unit sends the third process and the first processor, which is one of the N processors, to the first processor. Causing the fifth process to be executed, and causing the second processor, which is a processor other than the first processor, of the N processors to execute the fourth process,
The process execution control unit causes the first processor to execute the fourth process and the second processor to execute the second process when the parameter of the video data indicates that the third process does not need to be executed. 5 process is executed,
The AV data reproducing circuit according to claim 1.
The video playback process is a playback process using a correlation between frames,
The fourth process is a luminance motion compensation process,
The fifth process is a color difference motion compensation process.
The AV data reproducing circuit according to claim 6.
The video reproduction process further includes a variable length decoding process,
The process execution control unit causes the second processor to execute the variable length decoding process.
The AV data reproducing circuit according to claim 6 or 7.
The video reproduction process is the same as in H.264. H.264 / AVC standard reproduction processing,
The third process is a deblocking filter process.
The AV data reproducing circuit according to any one of claims 5 to 8.
The AV data includes video data,
The parameter of the AV data is a size of a frame constituting the video data.
The AV data reproducing circuit according to claim 1.
The AV data includes video data,
The parameter of the AV data is a frame rate of the video data.
The AV data reproducing circuit according to claim 1.
The AV data includes video data,
The parameter of the AV data is a bit rate of the video data.
The AV data reproducing circuit according to claim 1.
The AV data includes video data,
The video data is compressed by a predetermined encoding method,
The parameter of the AV data is the type of the encoding method.
The AV data reproducing circuit according to claim 1.
The parameter of the AV data is an arithmetic processing capability value necessary for processing the AV data.
The AV data reproducing circuit according to claim 1.
An AV data reproducing device including the AV data reproducing circuit according to any one of claims 3 to 14,
The AV data reproducing device further includes:
A memory for storing audio data and video data;
An audio output device for outputting audio based on decoded audio data obtained by the audio data reproduction circuit performing audio reproduction processing for reproducing the audio data with respect to the audio data;
The AV data playback circuit includes a display device for displaying video based on decoded video data obtained by performing video playback processing for playing back the video data with respect to the video data;
AV data playback device.
An integrated circuit that performs playback processing for playing back AV (Audio Visual) data using N (integer greater than or equal to 2) processors,
The reproduction process includes K (integer of 2 or more) processes,
The integrated circuit comprises:
An acquisition unit for acquiring parameters of AV data to be reproduced in the reproduction process;
A process execution control unit that causes at least one of the N processors to execute a first process that is one of the K processes based on the acquired parameter;
The process execution control unit selects a processor for executing the first process among the N processors based on the acquired parameters, and the N processors based on the acquired parameters Out of the K processes, a processor that executes a second process that is a process other than the first process is selected,
The process execution control unit causes the processor selected to execute the first process to execute the first process, and causes the processor selected to execute the second process to execute the second process;
Integrated circuit.
An AV data reproduction method performed by an AV data reproduction circuit that performs reproduction processing for reproducing AV (Audio Visual) data using N (integer of 2 or more) processors,
The reproduction process includes K (integer of 2 or more) processes,
The AV data reproduction circuit includes:
An acquisition unit for acquiring parameters of AV data to be reproduced in the reproduction process;
A process execution control unit that causes at least one of the N processors to execute a first process that is one of the K processes based on the acquired parameter;
The AV data reproduction method includes:
The obtaining unit obtaining parameters of the AV data;
The process execution control unit selects a processor for executing the first process from the N processors based on the acquired parameters, and the N processors based on the acquired parameters Out of the K processes, a processor that executes a second process that is a process other than the first process is selected, and the process execution control unit selects a processor that is selected to execute the first process. Including causing the processor selected to execute the first process and causing the processor selected to execute the second process to execute the second process.
AV data playback method.