WO2010141624A3 - Modified pillar design for improved flip chip packaging - Google Patents

Modified pillar design for improved flip chip packaging Download PDF

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Publication number
WO2010141624A3
WO2010141624A3 PCT/US2010/037120 US2010037120W WO2010141624A3 WO 2010141624 A3 WO2010141624 A3 WO 2010141624A3 US 2010037120 W US2010037120 W US 2010037120W WO 2010141624 A3 WO2010141624 A3 WO 2010141624A3
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WO
WIPO (PCT)
Prior art keywords
pillar
flip chip
electrically conductive
conductive material
chip packaging
Prior art date
Application number
PCT/US2010/037120
Other languages
French (fr)
Other versions
WO2010141624A2 (en
Inventor
Omar J. Bchir
Lily Zhao
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of WO2010141624A2 publication Critical patent/WO2010141624A2/en
Publication of WO2010141624A3 publication Critical patent/WO2010141624A3/en

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    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

A pillar for flip chip interconnect in an electronic package. The pillar includes an electrically conductive material and a solder wicking inhibitor deposited on the sides of the pillar. The pillar also includes an exposed face for contacting the electrically conductive material and solder material on the substrate. In another embodiment, a method of forming a pillar composed of an electrically conductive material which inhibits solder wicking is provided. The method includes coating the pillar with a solder wicking inhibitor and polishing a face of the pillar to expose the underlying electrically conductive material.
PCT/US2010/037120 2009-06-02 2010-06-02 Modified pillar design for improved flip chip packaging WO2010141624A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/476,928 2009-06-02
US12/476,928 US20100300743A1 (en) 2009-06-02 2009-06-02 Modified Pillar Design for Improved Flip Chip Packaging

Publications (2)

Publication Number Publication Date
WO2010141624A2 WO2010141624A2 (en) 2010-12-09
WO2010141624A3 true WO2010141624A3 (en) 2011-03-03

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/037120 WO2010141624A2 (en) 2009-06-02 2010-06-02 Modified pillar design for improved flip chip packaging

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US (1) US20100300743A1 (en)
TW (1) TW201108375A (en)
WO (1) WO2010141624A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8970034B2 (en) 2012-05-09 2015-03-03 Micron Technology, Inc. Semiconductor assemblies and structures
CN107086213A (en) * 2013-07-19 2017-08-22 日月光半导体制造股份有限公司 Package substrate, flip-chip type package and its manufacture method
US10403591B2 (en) * 2017-10-31 2019-09-03 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same

Citations (5)

* Cited by examiner, † Cited by third party
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