WO2010125852A1

WO2010125852A1 - Semiconductor device

Info

Publication number: WO2010125852A1
Application number: PCT/JP2010/053397
Authority: WO
Inventors: 和夫小埜; 尊之河原; 知紀関口; 靖永井
Original assignee: 株式会社日立製作所
Priority date: 2009-04-27
Filing date: 2010-03-03
Publication date: 2010-11-04
Also published as: JP5337239B2; JPWO2010125852A1

Abstract

In order to reduce memory power consumption during operation and standby, a memory block (MB) including a variable resistance memory element comprises: an address transformation circuit (ATC) for performing a conversion between a logical address and a physical address on the basis of an address transformation table (ATT); and a bank control circuit (BCC) for individually controlling the power supplies to memory banks (BANK). The ATC performs the address conversion, for example, so that external memory accesses are localized to a specific BANK. Consequently, an unused BANK can be secured and the power supply to the periphery circuit of the unused BANK can be blocked through the BCC.

Description

Semiconductor device

The present invention relates to a semiconductor device having a resistance change type memory cell, and particularly to a technique for realizing a low power consumption and secure semiconductor device.

Dynamic type random access memory (DRAM) is being miniaturized in order to achieve high integration, but it is difficult to manufacture a capacitor that secures a sufficient signal amount. In order to advance further miniaturization, a resistance change type memory in which a memory cell is configured using a resistance change element that can operate even if it is finely formed instead of a capacitor, and the magnitude of the resistance value corresponds to

logic information

1 and 0 Has been devised. As examples of the resistance change type memory, a phase change memory, a Resistive RAM (ReRAM), a solid electrolyte memory, and a magnetic RAM (MRAM) have been devised. Non-Patent Document 1 describes a phase change memory, Non-Patent Document 2 describes a ReRAM, Non-Patent Document 3 describes a solid electrolyte memory, and Non-Patent Document 4 describes an MRAM.

A preferable point common to all the resistance change elements is that the stored logic information is non-volatile so as to be retained for 10 years or more unless rewriting operation is performed. Therefore, it is expected that the resistance change type memory can reduce the power consumption in the memory cell array during standby as compared with a DRAM that requires a refresh operation to hold information. DRAM is used not only for PCs and servers, but also for mobile devices and digital home appliances. It keeps power consumption low during both operation and standby, extending the driving time in battery-powered devices and the global environment. It is also desired for conservation.

2 to 4 are explanatory diagrams showing a configuration example and an operation example of a generally known resistance change type memory element. As shown in FIG. 2A, the phase change memory has a structure in which a chalcogenide film is sandwiched between the upper electrode UL and the lower electrode LL. The chalcogenide film is controlled to be in an amorphous state or a crystalline state by heat transmitted from the LL. Heat generation efficiency can be improved by reducing the area of LL. When the chalcogenide film immediately above LL is in an amorphous state, the resistance between UL and LL is large, and when in a crystalline state, the resistance between UL and LL is small. FIG. 2B shows the current-voltage characteristics of the phase change memory, with the horizontal axis representing the potential difference V1 between UL and LL and the vertical axis representing the current I1 flowing from LL to UL. The direction of V1 is the same between the case of rewriting from the low resistance state (ON state) to the high resistance state (OFF state) and the case of rewriting from the OFF state to the ON state, and the sizes are different. High power when rewriting from ON to OFF.

3A shows a structure example of a solid electrolyte memory, FIG. 3B shows a ReRAM, and FIG. 4 shows an example of a structure of an MRAM. FIG. 4B shows a typical current-voltage characteristic of each memory shown in FIGS. In FIG. 4B, the horizontal axis of the graph is the current I1 between UL and LL, and the vertical axis is the electrical resistance R1 between UL and LL. The direction of current is different between when rewriting from the OFF state to the ON state and when rewriting from the ON state to the OFF state. For example, when a current is passed from LL to UL, it is turned on, and when a current is passed from LL to UL, it is turned off.

As shown in FIG. 3A, the solid electrolyte memory has a structure in which a solid electrolyte membrane EL that is a compound of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te) is sandwiched between UL and LL. Have. By applying an electric field from the UL to the LL direction to the EL, a metal conductive path is formed and turned on. On the other hand, when the electric field in the LL to UL direction is applied, the conductive path disappears and is turned off. Information is recorded using the magnitude of the resistance value between UL and LL. The solid electrolyte memory also has a second form in which EL has a multilayer structure. The above structure has better controllability of metal ions than the structure of FIG. The solid electrolyte memory operates in a small area at the atomic level, and has a feature of excellent scaling. High power when rewriting from ON to OFF.

As shown in FIG. 3B, the ReRAM has a structure in which, for example, a perovskite type manganese oxide is sandwiched between UL and LL. For example, the fact that the resistance value changes corresponding to the change in the state of the defect level in the material is used for recording. When electrons are not captured at the defect level, the state is OFF, and when the electrons are captured, the state is ON. High rewriting power.

As shown in FIG. 4A, the MRAM is a memory having a structure in which a magnetic film, a tunnel film, and a magnetic film are sandwiched between UL and LL, and the magnitude of the tunnel current flowing between UL and LL is used for recording. When the magnetization directions of the two magnetic films sandwiching the tunnel film are parallel, they are in the ON state, and when they are antiparallel, they are in the OFF state. When rewriting, a magnetic field is generated near the MRAM element to reverse the magnetization in the magnetic film. Since the current required to generate the magnetic field is large, the rewriting power is large.

As described with reference to FIGS. 2 to 4, various types of resistance change type memories that perform rewriting by passing a current have been devised, but a common problem is high rewriting power. This means that operating power is increased in the memory chip.

On the other hand, memory manufacturing rules have been miniaturized in order to reduce manufacturing costs and improve operating speed. As a result, the gate insulating film of the MOS transistor becomes thinner, and the leakage power of the logic circuit and the switch circuit is also increasing. The resistance change type memory is characterized in that the standby power is small, but in order to take advantage of this, it is desirable that the leakage power of the unused circuit portion is as small as possible. Furthermore, as described above, since the resistance change type memory has a large rewriting power, it is preferable to reduce the leakage power of the circuit portion not involved in the rewriting as much as possible in order to reduce the peak power during operation of the entire memory chip.

In addition, it is preferable to use a resistance change type memory instead of the DRAM from the viewpoint of power consumption reduction. However, since security information remains on the memory even when the power is turned off, there is a risk of being stolen by a third party. Sex is conceivable. For example, there is a non-volatile memory in which data is erased by performing address conversion by an MMU (memory management unit) and erasing a logical address entry, but data remains on an actual chip. The danger of being read out does not disappear. In order to solve the above, a method of overwriting meaningless information is effective. However, it is not preferable to perform overwriting operations one after another on information that is randomly present on the chip, resulting in an increase in power consumption. . Therefore, it is considered beneficial to incorporate a batch erasing function into the resistance change memory so that data can be overwritten at high speed while suppressing power consumption as much as possible.

Furthermore, in a large-scale system such as a server or a data center, since the continuous operation time of the apparatus is long, there is a problem in that fragmented unnecessary data accumulates in a memory, resulting in performance degradation. When the resistance change type memory is applied instead of the DRAM, the memory information is not lost even when the power is shut down, so that the task operating on the system is not interrupted even when the power is shut off. This means that unnecessary data is more likely to accumulate. Furthermore, the operation itself of searching for and deleting the fragmented unnecessary data is a system load. It is important to automatically create a batch erase map and perform batch erase in a short time to reduce the load on large-scale systems and to operate continuously for a long time.

The present invention has been made in view of the above, and the above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Among the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

The semiconductor device according to the present embodiment has a mechanism for converting a logical address and a physical address in a chip or on a memory controller, and performs defragmentation in the chip by the above mechanism, thereby causing a specific area (for example, a memory on the chip). An unused area is created in the entire bank), and power supply to the unused area is stopped. Further, each bit line or the like is provided with a batch erase driver.

The effects obtained by the representative embodiments of the invention disclosed in the present application will be briefly described. The memory power consumption during operation and standby can be reduced. In addition, data can be erased at a time with low power consumption, and the load on the system can be reduced and a secure memory can be realized.

1 is a block diagram showing a configuration example of a main part of a semiconductor device according to a first embodiment of the present invention. (A), (b) is explanatory drawing which shows the structural example and operation example of a well-known resistance change type memory element. (A), (b) is explanatory drawing which shows the structural example and operation example of a well-known resistance change type memory element. (A), (b) is explanatory drawing which shows the structural example and operation example of a well-known resistance change type memory element. (A) is the schematic diagram which showed the example of the state of each memory bank in the memory part of FIG. 1, (b) is explanatory drawing which showed the effect corresponding to (a). (A)-(c) is explanatory drawing which shows the operation example of the defragmentation function with which the memory part of FIG. 1 is provided. FIG. 2 is a diagram illustrating a configuration example of an address conversion table in the memory unit of FIG. 1. (A)-(c) is explanatory drawing which shows an example of a respectively different data movement method, when defragmenting using the memory part of FIG. (A), (b) is a figure which shows the example of a circuit structure of the principal part of the memory cell array in the memory part of FIG. 1, and the operation example at the time of batch erase operation. (A) to (c) are schematic diagrams illustrating layout configuration examples of a semiconductor chip including the memory unit of FIG. FIG. 11 is a schematic diagram illustrating a layout configuration example of a memory bank in FIG. 10. It is a block diagram which shows the example of a structure of a part of control circuit in FIG. It is a circuit diagram which shows the structural example of the bank control circuit in FIG. (A)-(c) is a block diagram which shows the structural example of the memory cell array in FIG. FIG. 11 is a block diagram illustrating a more detailed configuration example of a memory bank and an input / output circuit in FIG. 10. (A), (b) is a circuit diagram which shows the detailed structural example of the local bit line selection switch row | line | column and local source line selection switch row | line | column in FIG. FIG. 16 is a circuit diagram showing a detailed configuration example of a sub memory cell array in FIG. 15. (A) to (d) are circuit diagrams showing various configuration examples of the memory cell in FIG. FIG. 16 is a circuit diagram illustrating a configuration example of a sense amplifier in FIG. 15. FIG. 16 is a circuit diagram illustrating a configuration example of a sub word driver row in FIG. 15. FIG. 16 is a circuit diagram illustrating a configuration example of a row control circuit in FIG. 15. FIG. 16 is a circuit diagram illustrating a configuration example of an array control circuit in FIG. 15. FIG. 23 is a waveform diagram showing an operation example when information stored in a memory cell is read using the circuits shown in FIGS. 19 to 22; FIG. 23 is a waveform diagram showing an operation example when information is written in a memory cell using the circuits shown in FIGS. 19 to 22; (A), (b) is the wave form diagram which showed each different sequence at the time of switching a low power mode and a normal mode in the memory part of FIG. FIG. 18 is a waveform diagram showing a first control sequence when performing batch erasure on the sub memory cell array of FIG. 17. It is a wave form diagram which shows the 2nd control sequence different from FIG. FIG. 18 is a plan view showing a layout configuration example of main parts when the memory cell of FIG. 18A or FIG. 18C is applied to the sub memory cell array of FIG. 17; (A) to (c) are cross-sectional views showing examples of different structures between A and A ′ in FIG. In the semiconductor device by Embodiment 2 of this invention, it is a block diagram which shows the structural example of the principal part.

In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, a MOS (Metal Oxide Semiconductor) transistor is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor). In the drawing, a P-channel MOS transistor (PMOS transistor) is distinguished from an N-channel MOS transistor (NMOS transistor) by adding a circle symbol to the gate. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration example of a main part of a semiconductor device according to the first embodiment of the present invention. FIG. 1 shows a memory unit MB included in the semiconductor device, and this memory unit MB is mainly provided with an address conversion mechanism. In the MB of FIG. 1, the addresses A0 to An are input to the row address buffer XAB and the column address buffer YAB. The address conversion circuit ATC receives addresses from XAB and YAB, and acquires real addresses from the address conversion table ATT using these as logical addresses. The ATC sends this real address to the row decode circuit XDEC and the column decode circuit YDEC.

Thereby, a memory cell array MCA in a predetermined memory bank (for example, BANK0) is accessed, and data DQ0 to DQn are exchanged with the outside through the input / output buffer I / OB. As described in FIGS. 2 to 4, the MCA includes a plurality of resistance change type memory elements. In addition, the ATC grasps the usage status of each BANK, and controls the supply of power to the unused BANK via the bank control circuit BCC. The BCC is configured to be able to control the presence or absence of power supply independently for each BANK. Although details will be described later, a memory that can operate at low power consumption and at high speed can be realized by realizing BANK power supply control, batch erase control, and defragmentation that moves data according to the usage status of the real address.

FIG. 5A is a schematic diagram showing an example of the state of each memory bank in the memory unit MB of FIG. 1, and FIG. 5B is an explanatory diagram showing an effect corresponding to FIG. 5A. is there. The memory unit MB shown in FIG. 5A includes 8BANK as an example, and can set a normal mode in which all BANKs are turned on and a low power mode in which power is partially turned on. Yes. In this example, the power supply of 4BANK is turned off as an example of the low power mode, but the number can be increased or decreased depending on the BANK power supply control. In order to turn off the power of the BANK, the memory unit MB stops the power supply to the amplifier circuit, the decode circuit, the driver circuit, and the like via the bank control circuit BCC with a switch. As shown in FIG. 5B, in the low power mode, the leakage power can be reduced as compared with the normal mode, and the power consumption of the entire memory unit can be reduced.

FIGS. 6A to 6C are explanatory diagrams showing an operation example of the defragmentation function provided in the memory unit MB of FIG. FIG. 6A shows an operation of erasing a part of the address space and automatically rewriting data existing at the end of the address space to the erased address. The load on the external system side can be reduced by providing the automatic defragmentation function in the address conversion circuit ATC in the memory unit MB, for example, instead of using a command from the external system. Although the real address where the data actually exists on the memory cell array MCA changes, the logical address-real address (physical address) conversion is performed by the address conversion table ATT, and the real address information indicated by the logical address is rewritten. The location of the data as seen from the external system does not change. Another feature is that defragmentation is performed so that the real address space is used locally and the location of data is biased. By performing defragmentation as described above, an unused memory bank (in this case, BANKn) can be created, and the power can be cut off or erased at once. As a result, lower power consumption and improved security of the memory unit MB are expected.

For address conversion, various methods such as a paging method and a segmentation method for performing management in units of block areas including a plurality of continuous memory addresses are known. There is no special limitation. A conversion method between a logical address and a real address (physical address) can be applied to this embodiment, including a new method that will appear in the future. Since the resistance change type memory element has no limit on the number of rewrites, it is not destroyed even if rewrite concentrates on the same element. Similarly, there is a flash memory as a memory that performs logical address-physical address conversion. Since the memory has a limited number of rewrites, the address conversion is performed in order to average the number of cell rewrites, which is opposite to the purpose of address conversion (that is, localization) performed in this embodiment. .

FIG. 6B is a diagram showing that the defragmentation operation is controlled from the external system side. By performing defragmentation under the control of the operating system OS, it is possible to give more flexibility to the chip operation.

FIG. 6C shows a case where defragmentation is performed in order to move data to the batch erase area or the power shutdown area. First, a case where data is moved to the batch erase area will be described. In the defragmentation operation associated with batch erase, the real address space is managed by being divided into a plurality of batch erase regions (memory banks in this example). Each batch erase area is composed of a plurality (four in this example) of block areas (for example, pages). In this batch erase area, security information and system log information scattered in the real address space are centrally moved, and these pieces of information are targeted for batch erase as needed. As a specific management method, for example, a method of setting a flag for relevant information and identifying and managing the flag at the time of address conversion can be considered. By localizing information in the batch erase area, it is possible to reduce the power and time required for erase. In addition, it is possible to reduce the load when an address map for batch erasing is created by an external system.

Next, the case where data is moved to the power shutdown area will be described. In the defragmentation operation that accompanies power shutdown, the address conversion circuit ATC or an external system (such as an OS) monitors access to each data (each block area), and the memory that performs power shutdown for data that has been determined to have little access Move to the bank. Since the data is not frequently accessed, the power supply to the memory bank in which the data is placed is not shut down, so that the latency is not lowered. Further, since the resistance change type memory is non-volatile, there is no fear that data will be lost even if the power source of the memory bank is cut off. When access is made, the memory bank is turned on so that it can be read and written.

FIG. 7 is a diagram showing a configuration example of the address conversion table ATT in the memory unit MB of FIG. The address translation table ATT is referenced and updated by the address translation circuit ATC or an external system (such as OS), and has at least a logical address entry, a physical address (real address) entry, and a data flag entry. The logical address entry and the physical address entry hold the relationship between the logical address and the physical address for each block area (for example, page). The data flag entry becomes, for example, “1” when data is written to the corresponding physical address, and becomes “0” when nothing is written. In addition, the address conversion table ATT has, for each block area, an access protection entry indicating that it is a protection area or security information, and an access counter entry for managing access frequency. Also good.

By referring to the data flag entry, it is possible to detect a physical address that is not used, and it is possible to perform defragmentation using an area having a flag of “0” as a data movement destination. At this time, the data flag entry corresponding to the physical address of the data movement source is returned to ‘0’. When actual defragmentation is performed, data is moved so that data flag entries corresponding to successive physical address spaces are continuously set to “1” (that is, used data is localized). Then, as an opposite effect, an area where data flag entries corresponding to consecutive physical address spaces respectively become “0” is generated (that is, unused data is localized). Can be a target of batch erasure or a power-off target. In particular, when the system that accesses the memory unit MB uses only a part of the physical address space of the MB, the power supply is shut down by localizing the used data (unused data). Can increase the possible area. Further, for example, by performing batch erasure on the area where the power can be cut off before the power is cut off, the data that is the transfer source is actually erased, leading to an improvement in security.

Also, as shown in FIG. 6C, when defragmenting to positively extract security information or the like and delete it at once, referring to the access protection entry, the data in which the entry is made is It is sufficient to erase the area at once. Furthermore, when defragmenting based on the access frequency, it is only necessary to localize data with a low access frequency by referring to the access counter entry and to shut off the power supply to that area.

FIGS. 8A to 8C are explanatory diagrams showing examples of different data movement methods when defragmenting is performed using the memory unit MB of FIG. FIG. 8A shows the data flow when defragmenting between different memory banks, such as from the memory bank BANKn to BANKm. Each BANK includes a memory cell array MCA, a sense amplifier SA, and a main amplifier MA. Data read from the BANKn MCA is amplified and transferred in the order of SA and MA, and is latched by the data buffer DB. The latch information is written to the MCA via the BANKm MA and SA. Data transfer may be performed sequentially according to the order of addresses, or may be performed simultaneously by a plurality of bits using a plurality of SAs, MAs, and DBs. When it is performed sequentially, it takes time, but the peak power can be kept low. When performing a plurality of bits simultaneously, as an example, if the defragment unit is a word line, a plurality of SAs and MAs can be used at the same time, and the time required for defragmentation can be shortened.

FIG. 8B shows the data flow when defragmenting within the same memory bank. Information of MCAn is read by SAn and latched in MA. Data is written from SAm to MCAm using the latch information. By the defragmentation operation, an MCA in which no data is stored can be created, and power consumption can be reduced by turning off the power of the MCA. As an example, it is possible to turn off the power of the SA adjacent to the MCA and the sub word driver circuit. FIG. 8C shows the data flow when defragmenting within the same memory cell array MCA. Data in the memory cell MCn is once latched in SA, and the latch information is written in MCm. By the above defragmentation, as one example, it is possible to collect batch erase blocks, and there is an advantage that the time required for batch erase can be shortened.

FIGS. 9A and 9B are diagrams showing a circuit configuration example of a main part of the memory cell array MCA in the memory unit MB of FIG. 1 and an operation example at the time of batch erase operation. FIG. 9A shows the electrical characteristics of the resistance change memory element. In the figure, the horizontal axis represents current, and the vertical axis represents resistance. For example, the batch erase in the resistance change type memory element may be performed by writing the OFF state to all the memory cells. Since the resistance value is high in the OFF state, the current flowing at the end of rewriting can be reduced. In addition, batch erasing can be performed with smaller power consumption. Further, since the erasing power per memory cell is reduced, an erasing operation can be executed for a plurality of memory cells at a time within the range of the current driving capability of the driver, and a high-speed batch erasing operation can be performed.

A method for realizing the batch erase operation will be described together with the main circuit configuration using FIG. The memory cell array MCA includes a plurality of word lines WL arranged in parallel to each other, a plurality of bit lines BL and source lines SL extending in a direction crossing the word lines WL, and a plurality of memory cells arranged at intersections thereof. Consists of MC. The memory cell MC includes a resistance change type memory element and a memory cell transistor having a drain connected to one end thereof and a gate connected to a corresponding WL. BL and SL are arranged in parallel, BL is connected to the other end of the resistance change type memory element, and SL is connected to the source of the memory cell transistor.

Further, the memory cell array MCA includes a bit line batch erase driver BMED at one end of each BL, and a source line batch erase driver SMED at one end of each SL. Each BMED is configured by, for example, one PMOS transistor having a source connected to the power supply voltage VDD and a drain connected to BL, and is turned on / off in accordance with a bit line batch erase signal BMES. Each SMED is configured by, for example, one NMOS transistor having a source connected to the ground voltage VSS and a drain connected to SL, and the ON / OFF of the SMED is controlled according to the source line batch erase signal SMES. By providing BMES and SMES as described above, even with an array configuration in which one sense amplifier is shared by a plurality of BLs and SLs, batch erasure can be performed for each BL and SL. Can be reduced.

In the batch erase operation, first, BMES and SMES are driven ON, and BMED and SMED are activated. While the BMES and SMES are ON, the plurality of WLs are activated in order. When the OFF state is written as batch erase as shown in FIG. 9A, the rewrite current can be reduced, so that a plurality of WLs can be activated at a time. The number of WLs that can be activated at one time is determined by the amount of current that can flow through BL and SL. However, caution is required because the peak power increases when too many WLs are activated. If the batch erasing operation is performed by the above method, the number of times of charging / discharging BMES and SMES can be reduced, and the power consumption can be reduced. Furthermore, since a simple operation of sequentially activating WLs is required, a high-speed batch erase operation can be realized. For example, the batch erasure may be performed autonomously at a constant cycle by providing a timer in the memory unit MB, or may be performed at the timing of data movement, or when managed by the OS. The OS may be performed in cooperation with the system at the timing of page replacement as an example.

10 (a) to 10 (c) are schematic views showing layout configuration examples of the semiconductor chip provided with the memory unit MB of FIG. 1, respectively. The semiconductor chip CHIP shown in FIGS. 10A to 10C is roughly divided into, for example, a control circuit CNTL, an input / output circuit DQC, an address conversion table ATT, and a memory bank BANK. The control circuit CNTL receives a clock, an address, and a control signal from outside the CHIP, and determines the operation mode of the CHIP, predecodes the address, and the like. The input / output circuit DQC includes an input / output buffer and the like, and receives write data from the outside of the CHIP and outputs read data to the outside of the CHIP.

In the example of FIG. 10A, one BANK is assigned as ATT. In addition, as a method of assigning ATTs, there are a method of assigning a part of BANK as ATT as shown in FIG. 10B and a method of assigning a part of plural BANKs as shown in FIG. The method of address decoding and the like is simplified in the method of FIG. 10A. However, depending on the method of address conversion, the ATT area can be reduced, and in order to increase the actually usable chip capacity, FIG. There may be a case where the assignment method of 10 (b) or FIG. 10 (c) is preferable. When a part of BANK is ATT, it is preferable to provide ATT near the CNTL in order to shorten the access time.

FIG. 11 is a schematic diagram showing a layout configuration example of the memory bank BANK in FIG. In the memory bank BANK, a plurality of memory cell arrays MCA are arranged in an array, and a sub word driver column SWDA, a sense amplifier column SAA, and a row control circuit XP are arranged around each MCA. Further, on the outer periphery of the memory bank BANK, a column decode circuit YDEC, an array control circuit ACC, and a main amplifier row MAA are arranged in parallel with the sense amplifier row SAA, and a row decode circuit XDEC is arranged in parallel with the sub word driver row SWDA. . A bank control circuit BCC is arranged at the intersection of MAA and XDEC.

FIG. 12 is a block diagram showing a configuration example of a part of the control circuit CNTL in FIG. In FIG. 12, the voltage generation circuit VG generates, for example, a memory cell write voltage VBH, a peripheral circuit power supply voltage VDD, a ground voltage VSS, a word line boost voltage VPP, a negative voltage VKK, and a read driver control voltage SAPG. The timing control signal generation circuit TCG includes a column selection enable signal YSE, a sense amplifier enable source signal SAE0, a read enable signal RE, a peripheral circuit power source control source signal PSSb0, a write enable signal WE, a word line enable source signal WLE0, and a batch erase signal MEST. Is generated. An address (logical address) from the outside of the memory is input to the address conversion circuit ATC in CNTL. In response to this, the ATC refers to the address conversion table ATT and outputs a real address (physical address). Further, when PSSb0 is 'L', the chip power shut-off mechanism does not work.

FIG. 13 is a circuit diagram showing a configuration example of the bank control circuit BCC in FIG. BCC is a circuit that controls power supply to a driver circuit and an amplifier circuit included in the memory bank BANK. For example, the bank peripheral circuit power supply voltage VDDb, the bank memory cell write voltage VBHb, and the bank word line boost voltage VPPb are supplied from VDD, VBH, and VPP via the power switch PSW, respectively. PSW is composed of a PMOS transistor, and its gate is controlled by the AND logic of the peripheral circuit power source control source signal PSSb0 and the mat selection inversion signal MSB. MSB is a signal that becomes ‘L’ when the row address of the corresponding memory bank is decoded. The memory cell array selection signal MCAS becomes ‘H’ when the row address of the corresponding memory cell array MCA is decoded, and the peripheral circuit power supply control signal PSSb is generated by the inverted signal.

Thus, during the period when PSSb0 and MSB are 'H' (that is, the period when the corresponding memory bank is not selected), the power source of the memory bank is cut off. As described above, since the used data (unused data) can be localized by using the defragmentation function, the memory bank to which the unused data is allocated can maintain the power-off state, and the power consumption can be reduced. The PSSb is used when power is shut off in units of the memory cell array MCA in the corresponding memory bank itself although power is supplied to the corresponding memory bank itself.

FIGS. 14A to 14C are block diagrams showing a configuration example of the memory cell array MCA in FIG. In the configuration example shown in FIG. 14A, a local bit line selection switch row LBLSA is arranged beside the sub memory cell array SMCA, and the local source line selection switch row LSLSA is placed on the opposite side across the SMCA so as to face LBLSA. Is placed. With the above structure, the bit lines and source lines can be hierarchized, and the cell occupancy of the chip can be increased. In the configuration example shown in FIG. 14B, the SMCA is divided into two parts, LBLSA and LSLSA are arranged on one side of each SMCA and the other side facing each other, and the LSLSA of the two SMCAs are arranged adjacent to each other. ing. Note that LBLSA and LSLSA in FIG. 14B may be interchanged so that two LBLSAs are adjacent to each other.

FIG. 14C is a diagram in which the configuration example shown in FIG. 14B is repeated a plurality of times. By adopting the structure as shown in FIGS. 14B and 14C, it becomes possible to efficiently route control signals for LSLSA and LBLSA, and the chip area can be reduced. Further, by setting SMCA as a small unit, the bit line and the source line can be shortened, so that the delay and increase in power consumption due to the parasitic resistance and parasitic capacitance of the wiring can be reduced. However, in this case, the size of one SMCA must be selected in consideration of the possibility that the cell occupancy rate decreases.

FIG. 15 is a block diagram showing a more detailed configuration example of the memory bank BANK and the input / output circuit DQC in FIG. The DQC includes, for example, a data buffer DB and a verify control circuit VCTL that controls data movement in BANK units as shown in FIG. BANK includes a sub memory cell array SMCA, a local bit line selection switch column LBLSA, a local source line selection switch column LSLSA, a main amplifier column MAA, a sense amplifier column SAA, a row control circuit XP, and a sub word driver column SWDA. Composed. Here, SMCA, LBLSA, and LSLSA have a configuration corresponding to FIG.

The main amplifier row MAA includes a plurality of main amplifiers MA, and MA and VCTL are connected by a global input / output line GIO. The row control circuit XP includes a main input / output gate RGC, and MA and RGC are connected by a main input / output line MIO. The sense amplifier array SAA includes a plurality of sense amplifiers SA, and SA and RGC are connected by a local input / output line LIO. The SA has a structure shared by adjacent memory cell arrays MCA adjacent to each other. With the above structure, the area of the SAA can be reduced. LBLSA includes a plurality of local bit line selection switches LBLS, and SA and LBLS are connected by a global bit line GBL. The LSLSA arranged opposite to the LBLSA across the SMCA includes a plurality of local source line selection switches LSLS, and the LSLS is connected to the same SA as the paired LBLS by the global source line GSL.

The SMCA extends in a direction intersecting with a plurality of word lines WL arranged in parallel with each other, a plurality of local bit lines LBL and local source lines LSL arranged in parallel with each other, and each WL and each LBL (and LSL) includes a plurality of memory cells MC arranged at intersections with each other, a bit line batch erase driver BMED connected to one end of each LBL, and a source line batch erase driver SMED connected to one end of each LSL. Is done. Each WL is driven by each sub word driver SWD included in the SWDA. Each LBL is connected to the SA via the corresponding LBLS and can be driven by the corresponding BMED. Each LSL is connected to the SA via the corresponding LSLS and can be driven by the corresponding SMED. Further, XP includes a batch erase driver drive circuit MESD. The MESD collectively drives a plurality of BMDED and SMED included in the corresponding SMCA by a bit line batch erase signal BMES and a source line batch erase signal SMES extending in the same direction as WL.

Here, the configuration of one BMED for one LBL and one SMED for one LSL has been described. However, in order to improve the current drive capability during batch erase, a plurality of BMEDs and SMEDs are connected. May be. By adopting the above configuration, it is possible to improve the batch erase speed. In addition, each SWD included in the SWDA is shared by SMCA adjacent vertically. With the above structure, the area of the SWDA can be reduced, and the WL having two SMCA lengths is driven from the center, so that the WL can be driven at high speed.

16A and 16B are circuit diagrams showing detailed configuration examples of the local bit line selection switch row LBLSA and the local source line selection switch row LSLSA in FIG. In the LBLSA shown in FIG. 16A, when a predetermined bit line selection signal BLS is selected via the column decode circuit YDEC, a predetermined switch in the corresponding local bit line selection switch LBLS is selected, The connected local bit line LBL is connected to the global bit line GBL. Further, the power supply voltage accompanying the control of this switch is supplied via the power supply switch PSW, and on / off of the PMOS transistor constituting the PSW is controlled by the peripheral circuit power supply control signal PSSb described in FIG. With the above-described defragmentation function, power consumption can be reduced by shutting off the power supply to the unused array portion using PSSb. In the example of FIG. 16 (a), one GBL is assigned to eight LBLs. Of course, the number is not limited to eight, but various such as four, two, and sixteen. Examples are possible. By adopting the configuration as described above, it is possible to cope with multi-bit simultaneous rewriting.

In the LSLSA shown in FIG. 16B, when a predetermined source line selection signal SLS is selected via the column decode circuit YDEC, a predetermined switch in the corresponding local source line selection switch LSLS is selected, The connected local source line LSL is connected to the global source line GSL. Further, the power supply voltage accompanying the control of this switch is supplied via the power supply switch PSW, and on / off of the PMOS transistor constituting the PSW is controlled by the peripheral circuit power supply control signal PSSb described in FIG. With the above-described defragmentation function, power consumption can be reduced by shutting off the power supply to the unused array portion using PSSb. In the example of FIG. 16 (b), one GSL is assigned to eight LSLs. Of course, the number is not limited to eight, but various such as four, two, and sixteen. Examples are possible. By adopting the configuration as described above, it is possible to cope with multi-bit simultaneous rewriting.

FIG. 17 is a circuit diagram showing a detailed configuration example of the sub memory cell array SMCA in FIG. The sub memory cell array SMCA is a memory cell arranged at a desired intersection of m word lines WL, n local bit lines LBL, n local source lines LSL, WL and LBL (and LSL). From MC, bit line batch erase signal BMED arranged at a desired intersection of bit line batch erase signals BMES and LBL, and source line batch erase driver SMED arranged at a desired intersection of source line batch erase signals SMES and LSL Composed. Each MC is composed of a memory cell transistor composed of an NMOS transistor and a resistance change type memory element having one end connected to its drain. The other end of the memory element is connected to the corresponding LBL, and the source of the memory cell transistor is connected to the corresponding LSL.

The memory element has electrical characteristics as shown in FIG. 2 (b) and FIG. 4 (b). The arrow shown in the memory element indicates the direction of the current that flows to change the memory cell to the logic value “1” state. In the memory cell using the resistance change type memory element having the current-voltage characteristics shown in FIG. 2B, a current is passed from LBL to LSL, and the potential difference between LBL and LSL exceeds the low resistance (ON) threshold voltage. In this case, a current is passed from LBL to LSL, and it is turned OFF when the potential difference between LBL and LSL exceeds the high resistance (OFF) threshold voltage. On the other hand, in the memory cell using the resistance change type memory element having the electrical characteristics as shown in FIG. 4B, when a current flows from LBL to LSL and the potential difference between LBL and LSL exceeds the ON threshold voltage, On the other hand, when the current flows from LSL to LBL and the potential difference between LSL and LBL exceeds the OFF threshold voltage, the OFF state is entered.

FIGS. 18A to 18D are circuit diagrams showing various configuration examples of the memory cell MC in FIG. In FIG. 18, the gate of the memory cell transistor is G, the source is S, and the drain is D. In FIG. 18A, the gate G is connected to the WL, the drain D is connected to the LBL, the source S is connected to the resistance change type memory element, and the memory element is arranged so that the resistance is reduced when a current flows from the LBL to the LSL. . In FIG. 18B, the gate G is WLm, the source S is LSL, the drain D is connected to the resistance change memory element, and the memory element is arranged so that the resistance is reduced when a current flows from LBL to LSL. In FIG. 18C, the gate G is connected to the WL, the source S is connected to the resistance change memory element, the drain D is connected to the LBL, and the memory element is arranged so as to reduce the resistance when a current is passed from the LSL to the LBL. In FIG. 18D, the gate G is WLm, the source S is LSL, the drain D is connected to the resistance change type memory element, and the memory element is arranged so that the resistance is reduced when a current flows from LSL to LBL. .

FIG. 19 is a circuit diagram showing a configuration example of the sense amplifier SA in FIG. The sense amplifier SA shown in FIG. 19 includes a read unit RAMP, a write unit WAMP (U / L), and a local input / output line switch IOG. RAMP and IOG are shared by the write unit WAMPU that drives the global bit line GBLU above the sense amplifier and the write unit WAMPL that drives the global bit line GBLL below the sense amplifier. The RAMP is shared by the upper and lower memory cell arrays, which is useful for reducing the area of the sense amplifier circuit. WAMP and RAMP are connected by an active high sense amplifier out signal line SAOt and a global bit line GBL. IOG and RAMP are connected by SAOt and SAOb. IOG and WAMP are connected by SAOt.

The read unit RAMP includes, for example, a read switch RSW (U / L), two read drivers RD, a cross couple CC, a precharge circuit PCC, and a read reference circuit RRC. The RRC is composed of, for example, two MOS transistors and a reference load REF, and is controlled by a read enable signal RET and a word line enable signal WLE. RSWU is controlled by an upper memory cell read enable line RETU. RSWL is controlled by a lower memory cell read enable line RETL. CC is controlled by a sense amplifier enable signal SAE. RD is controlled by a read current control line SAPG. PCC is controlled by a sense amplifier equalize signal SAEQ. PCC is a precharge circuit for charging SAOt and SAOb to VBH during standby, and is controlled by SAEQ.

The operation of RAMP at the time of reading will be described below. First, the sense amplifier equalize signal SAEQ changes from low to high and precharge ends. Next, a read current is passed through the memory cell. The read current is determined by a PMOS load (RD) whose gate potential is controlled by the power supply voltages VDD and SAPG. When reading memory cells above SA, RETU is selected, and when reading memory cells below SA, RETL is selected. The read current flows from the power supply VDD via the load PMOS, through the sense node SN, and to the global bit line selected by RETU or RETL. The reference current flows from VDD through the load PMOS, through the reference sense node SNREF, and through the reference load REF simulating a current path to the memory cell to the ground voltage VSS. When the resistance value of the memory cell to be read is high, that is, when the logic value is “0”, the potential of SN becomes higher than the potential of SNREF. This is because the voltage drop at the memory cell is larger than the voltage drop at REF.

The potential difference between SN and SNREF is amplified by SAOt to voltage VBH and SAOb to VSS by the cross latch activated by sense amplifier enable SAE. When the resistance value of the memory cell to be read is low, that is, when the logical value is “1”, the potential of SN is lower than the potential of SNREF. This is because the voltage drop at the memory cell is smaller than the voltage drop at REF. In the potential difference between SN and SNREF, SAOt is amplified to VSS and SAOb is amplified to VBH in the cross couple. Memory information read to SAOt and SAOb by column selection line YS is read to local input / output lines LIOt and LIOb.

The operation of the write circuit WAMP will be described below. When the memory cell is brought into a high resistance state, that is, when writing to the logic value “0”, when the column selection line YS is selected, SAOt is charged toward the ground potential by LIOt, and SAOb is directed toward VBH by LIOb. Charged. Since RET is low, SN and SNREF are charged to a potential close to VDD. When SAE is turned ON, SAOt is charged to VSS and SAOb is charged to VBH by the cross latch. When the active high write enable signal WET and the active low write enable signal WEB are activated, since SAOt is low, GBL is charged to VSS by WAMP. When the potential of GSL is set to, for example, VBH, a current flows from GSL to GBL. As a result, the logical value “0” is written in the memory cell.

When the memory cell is put into a low resistance state, that is, when writing to the logic value “1”, when the column selection line YS is selected, SAOt is charged toward VBH by LIOt, and SAOb is charged toward VSS by LIOb. Is done. Since RET is low, SN and SNREF are charged to a potential close to VDD. When SAE is turned on, SAOt is charged to VBH and SAOb is charged to VSS by the cross latch. When the active high write enable signal WET and the active low write enable signal WEB are activated, since SAOt is high, GBL is charged to VBH by WAMP. When the potential of GSL is set to, for example, VBH / 2, a current flows from GBL to GSL. As a result, a logical value “1” is written in the memory cell.

FIG. 20 is a circuit diagram showing a configuration example of the sub word driver array SWDA in FIG. As shown in FIG. 15, the SWDA is arranged around the memory cell array MCA, and the word line WL in the memory cell array MCA is driven from one of the upper and lower SWDAs, so the sub word driver SWD included in one SWDA. May be half of the number of WLs included in the MCA. The SWD is composed of one PMOS transistor and two NMOS transistors. The PMOS transistor has a gate connected to the main word line MWLB, a source connected to the sub word driver selection line FX, and a drain connected to the word line WL. One of the NMOS transistors has a gate connected to MWLB, a source equal to or lower than VSS, a negative voltage VKK, and a drain connected to WL. The other of the NMOS transistors has a gate connected to an inverted subword driver selection line FXB, a source connected to VKK, and a drain connected to WL.

FIG. 21 is a circuit diagram showing a configuration example of the row control circuit XP in FIG. XP is a main input for connecting the equalizing circuit REQ for precharging the local input / output lines LIOt and LIOb, the bit line selection signal driver BLSD, the source line selection signal driver SLSD, LIOt (LIOb) and the main input / output line MIOt (MIOb). The output gate RGC, source line selection signal driver SLSD, column selection line driver YSD, batch erase driver drive circuit MESD, and sub word driver selection line driver FXD. REQ is composed of, for example, three PMOS transistors, and charges LIOt and LIOb to voltage VBH when sense amplifier equalize signal SAEQ is turned off. The RGC is composed of, for example, two NMOS transistors and connects LIOt and MIOt, and LIOb and MIOb when SAEQ is turned on.

BLSD generates a bit line selection signal BLS by a read enable signal RET, a write enable signal WET, and a column address decode signal FY. For example, a circuit configuration in which BLS is generated by taking the OR logic of RET and WET and the AND logic of FY can be considered. The SLSD generates a source line selection signal SLS by a read enable signal RET, a write enable signal WET, and a column address decode signal FY. For example, a circuit configuration that generates an SLS by taking the OR logic of RET and WET and the AND logic of FY can be considered. YSD drives the column selection line YS from the column selection enable signal YSE and the column predecode signal CF. For example, a circuit configuration that takes the AND logic of YSE and CF and outputs YS can be considered.

MESD generates a source line batch erase signal SMES and a bit line batch erase signal BMES from the active high batch erase signal MEST. For example, a circuit configuration in which the MEST two-stage NOT logic is output and SMES is output, and the MEST NOT logic is output and BMES is output is conceivable. FXD generates a sub word driver selection line FX from the inverted sub word driver selection line FXB. For example, it is composed of the same number of NOT logic circuits as FXB. In this FXD, the 'H' side power supply of all NOT logic circuits (inverter circuits) is controlled by a power switch PSW. The source of PSW is connected to VDDb and the gate is connected to the peripheral circuit power supply control signal PSSb. With the above-described defragmentation function, the power supply of the sub-word driver selection line in the array portion that has not been used is cut off by the PSW, so that power consumption can be reduced.

FIG. 22 is a circuit diagram showing a configuration example of the array control circuit ACC in FIG. The ACC generates a signal group for controlling the sense amplifier from the timing signal generated by the control circuit CNTL shown in FIG. The ACC includes a sense amplifier equalize signal SAEQ from the mat selection inversion signal MSB, a sense amplifier enable signal SAE from the MSB and the sense amplifier enable source signal SAE0, a read enable signal RET for controlling the sense amplifier from the read enable signal RE, and a word line. A word line enable signal WLE is generated from the enable source signal WLE0, and a write enable signal WET for controlling the sense amplifier is generated from the write enable signal WE. For example, SAEQ is generated by inverting MSB. SAE is generated by taking the AND logic of the inverted signal of MSB and SAE0. RET is generated by taking the AND logic of the inverted signal of MSB and RE. WLE is generated by taking the AND logic of the inverted signal of MSB and WLE0. WET is generated by taking the AND logic of the inverted signal of MSB and WE.

FIG. 23 is a waveform diagram showing an operation example when information stored in a memory cell is read using the circuits shown in FIGS. First, the standby state will be described. In the standby state, the sense node SN and the reference sense node SNREF in FIG. 19 are charged to VDD. The sense amplifier out signal line SAO and the local input / output line LIO are charged to VBH. When an ACT command is input in synchronization with the clock CLK, SAEQ and RET created by ACC shown in FIG. 22 are charged from VSS to VDD. The word line WL and the bit line selection signal BLS are charged from the negative voltage VKK lower than the ground potential to the boost voltage VPP at the timing when the RET and the word line enable signal WLE are synchronized. As a result, the memory cell specified by the input address is selected, and a read current flows.

When WLE is charged from VKK to VPP, the reference sense node SNREF decreases from VDD toward the reference potential set by the reference load. When the reference potential is set to VDD / 2, for example, the read margin can be set large. When the read current flows, the sense node SN changes according to the resistance state of the memory cell. When the memory cell is in a low resistance state, that is, in an ON state, the potential is close to VSS, and when the memory cell is in a high resistance state, that is, in an OFF state, the potential is not much lower than VDD. At this time, the potentials of the sense amplifier out signal lines SAOt and SAOb do not drop much from VBH when the memory cell is in the ON state, and drop toward VSS when the memory cell is in the OFF state according to the potentials of SN and SNREF. Go. The sense amplifier enable signal SAE is turned ON at the timing when the SN state becomes a steady state. Then, if the state of SAOt is ON according to the state of the memory cell, it is charged to VBH, and if it is OFF, it is charged to VSS.

In this way, when the READ command is input while the memory cell state is latched by the read section of the sense amplifier, the column selection signal YS is charged from VKK to VPP, and the memory information is stored in the local input / output line LIO. Is output. When a PRE command is subsequently input, WL and BLS change from VPP to VKK, then SAE decreases from VDD to VSS, SAEQ and RET decrease from VDD to VSS, and WLE decreases from VPP to VKK. As a result, SN and SNREF become VDD, SAOt and SAOb are precharged to VBH, return to the standby state, and the read operation ends.

FIG. 24 is a waveform diagram showing an operation example when information is written in the memory cell using the circuits shown in FIGS. The standby state is the same as the state described in FIG. When the ACT command is input in synchronization with the clock CLK, the sense amplifier equalization signal SAEQ changes from VSS to VDD in synchronization with the timing generated by the control circuit CNTL shown in FIG. 12, and the equalization of the sense amplifier is completed. . When the word line WL rises from the negative voltage VKK lower than VSS to the boosted voltage VPP, preparation for writing information into the memory cell is completed. When the column selection line YS is selected, a sense amplifier that performs writing is determined, and the sense amplifier out signal line SAO starts to be charged to a desired level by the local input / output line LIO that is charged according to the information to be written. When the sense amplifier enable signal changes from VSS to VDD, the latch portion of the sense amplifier is turned ON, and the write information is latched. When SAO writes the ON state, it is determined as VBH, and when the OFF state is written, it is determined as VSS. .

When the write enable signal WET changes from VSS to VDD, the writing unit of the sense amplifier is turned on, and VBH is output when writing the ON state to the global bit line GBL, and VSS is output when writing the OFF state. Thereby, desired digital information is written in the memory cell. When the PRE command is input in synchronization with the clock, the word line WL changes from VPP to VKK, and in response, SAE changes from VDD to VSS. Thereafter, SAEQ changes from VSS to VDD, and at the same time, SAO is precharged to VBH. Thus, the standby state is restored and the write operation is completed.

In the automatic defragmentation shown in FIG. 6A and the defragmentation to the batch erase block shown in FIG. 6C, after the entry of the address conversion table ATT is referred to, the information to be defragmented is controlled by the control shown in FIG. Is read and the information is written to a new real address by the control shown in FIG. In the defragmentation by the command from the external system shown in FIG. 6B, after the defragmentation command is input, the information to be defragmented is read by the control shown in FIG. 23, and the new real address is obtained by the control shown in FIG. This information is written in

25 (a) and 25 (b) are waveform diagrams showing different sequences when the low power mode and the normal mode are switched in the memory unit MB of FIG. FIG. 25A is a sequence for performing power control for the entire memory bank, and FIG. 25B is a sequence for performing power control for the sense amplifier SA and the sub word driver SWD.

First, the waveform of FIG. 25A will be described with reference to FIG. If the initial state is the low power mode, then the peripheral circuit power source control source signal PSSb0 and the mat selection inversion signal MSB are VDD. When the MSB is discharged to VSS from this state, it shifts to the normal mode. In response, bank peripheral circuit power supply voltage VDDb is charged from VSS to peripheral circuit power supply voltage VDD, and bank memory cell write voltage VBHb is charged from VSS to memory cell write voltage VBH. Subsequently, a waveform when the normal mode is changed to the low power mode will be described. Since the low power mode is used, PSSb0 remains charged to VDD. When MSB is charged from VSS to VDD, the AND logic of PSSb0 and MSB is taken. As a result, VDDb and VBHb are discharged to VSS and shift to the low power mode. When there is no driver for discharging VDDb and VBHb, VDDb and VBHb are naturally discharged. As a result, power supply to memory banks not selected by the MSB is cut off.

Next, the waveform of FIG. 25B will be described with reference to FIG. The initial state is the low power mode described in FIG. 25A, and the voltage levels of the MSB, VDDb, and VBHb at that time are the same as those in FIG. When the memory cell array selection signal MCAS is charged from VSS to VDD, since MSB is inevitably selected before that, VDDb and VBHb are charged to VDD and VBH. When MCAS is charged to VDD, PSSb is discharged from VDD to VSS. As a result, as shown in FIGS. 16 and 21, only the power supply to the driver related to the selected memory cell array is performed, and the normal mode is entered. Since only the power source of the driver of the selected memory cell array is supplied, it is possible to reduce the power consumption when active.

FIG. 26 is a waveform diagram showing a first control sequence when batch erasure is performed on the sub memory cell array SMCA of FIG. In FIG. 21, when the batch erase signal MEST is charged from VSS to VDD, the bit line batch erase signal BMES is discharged from VDD to VSS, and the source line batch erase signal SMES is charged from VSS to VDD. Accordingly, in FIG. 17, the local bit line LBL is charged from VSS to VDD, and the local source line LSL is clamped to VSS. In this state, as shown in FIG. 26, the word lines WL are pulse-driven one after another from VKK to VPP. After all the WLs included in the batch erase block are pulse-driven, MEST is discharged to VSS. As a result, BMES is charged from VSS to VDD, and SMES is discharged from VDD to VSS. In response to this, LBL is discharged from VDD to VSS, and batch erasure is completed.

FIG. 27 is a waveform diagram showing a second control sequence different from FIG. The second control sequence shown in FIG. 27 is similar in operation to MEST, BMES, SMES, LBL, and LSL as compared to the first control sequence shown in FIG. 26, but is different in the number of WLs activated at one time. ing. For example, activation is simultaneously performed in units of k + 1 from WL0 to WLk at a time. Thus, by simultaneously activating a plurality of WLs within the range allowed by the current driving capability of the driver, the time required for batch erasing can be shortened.

FIG. 28 is a plan view showing a layout configuration example of main parts when the memory cell MC of FIG. 18A or FIG. 18C is applied to the sub memory cell array SMCA of FIG. In the SMCA shown in FIG. 28, a dummy word line DWL is provided for every two word lines WL. As a result, the mask of the diffusion layer N + that becomes the source / drain region of the memory cell transistor can be simplified. The bit line contact BLC is shared by two memory cells MC arranged adjacent to each other in the direction in which the local bit line LBL extends between the dummy word lines DWL. The local bit line LBL and the local source line LSL are formed in parallel, but have different layer heights. A portion surrounded by a dotted square represents a 1-bit memory cell MC, and its cell area is 6F2 when the process node is F, which is the same level as the cell area of the latest DRAM. However, the resistance change type memory element is easier to manufacture than the DRAM capacitor, and the 1T1R type memory can be manufactured even in a fine process in which the 1T1C type DRAM is difficult to manufacture.

29 (a) to 29 (c) are cross-sectional views showing examples of different structures between A and A 'in FIG. FIG. 29A shows an example in which the local bit line LBL is arranged in a layer above the local source line LSL, and FIG. 29B shows a resistance change type in which LBL is a layer below the LSL. This is an example in which the memory element MD is arranged in a layer above the LBL. FIG. 29C shows an example in which LBL is arranged in a layer below LSL and the resistance change type memory element MD is arranged in a layer below LBL. 29A to 29C, STI formed below the dummy word line DWL is an insulating film for element isolation, SLC is a source line contact, SUB is a semiconductor substrate, and CONT Is a contact. The structure shown in FIG. 29B is considered to improve the yield because there are few manufacturing processes in the layer above the resistance change type memory element MD.

(Embodiment 2)
FIG. 30 is a block diagram showing a configuration example of main parts of the semiconductor device according to the second embodiment of the present invention. Compared to the semiconductor device shown in FIG. 1, the semiconductor device shown in FIG. 30 has the above-described address conversion function (address conversion circuit ATC and address conversion table ATT) provided in a memory controller provided outside the memory chip. The feature is that. By using the above configuration, the structure of the memory chip can be simplified, and the storage capacity of the memory chip can be increased. The address conversion table ATT in the memory controller may not be composed of resistance change elements. However, it is desirable to be composed of a non-volatile memory element. By making the ATT non-volatile, there is an advantage that the address translation information is retained even when the memory controller is turned off. In addition, there is an advantage that power consumption during standby can be reduced.

Further, the bank control circuit BCC described above and each circuit for batch erasure as described in FIG. 17 and the like are provided in the memory chip. Since the address space output from the memory controller to the memory chip is localized by the defragmentation function described above, the memory chip can cut off the power supply of the memory bank that is not accessed using the BCC. Note that when performing batch erase, for example, a command or address for batch erase may be separately issued from the memory controller to the memory chip, and the memory chip may be operated in response thereto.

As described above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention.

The semiconductor device of the present invention is a technology that is particularly useful when applied to a memory chip having a resistance change type memory, and is not limited to this, and is an on-chip incorporated in a logic chip such as a microprocessor or a DSP (Digital Signal Processor). It can also be applied to a chip memory or the like.

A0 to An address ACC array control circuit ATC address conversion circuit ATT address conversion table BANK memory bank BCC bank control circuit BLC bit line contact BLS bit line selection signal BMED bit line batch erase driver BMES bit line batch erase signal CC cross couple CF column pre Decode signal CNTL Control circuit CONT Diffusion layer contact DB Data buffer DQ0 to DQn Data DQC I / O circuit DWL Dummy word line EL Solid electrolyte FX Subword driver selection signal FXB Inverted subword driver selection signal FY Column decode signal GBL Global bit line GSL Global source line I / O CTL I / O control circuit I / OB I / O buffer IOG I / O gate LBL Local bit line LBLS Local bit line selection switch LBLSA Local bit line selection switch row LBLSA Local bit line selection switch row LIO Local I / O line LIOb Inverted local I / O line LIOt Local I / O line LL Lower electrode LSL Local source line LSLS Local source line selection switch LSLSA Local Source line selection switch row LSLSA Local source line selection switch row MA main amplifier MAA main amplifier row MB memory unit MCA memory cell array MCAS memory cell array selection signal MD resistance change type memory element MEST batch erase signal MSB mat selection inversion signal MWLB inversion main Word line Metal Metal atom N + Diffusion layer PCC Precharge circuit PSSb Peripheral circuit power supply control signal PSSb0 Peripheral circuit power supply control source No. PSW Power switch RAMP Read unit RD Read driver RE Read enable signal REB Inverted read enable signal REF Reference load circuit REQ Equalize circuit RET Read enable signal RGC Main input / output gate RRC Read reference circuit RSW read switch SA sense amplifier SAA sense amplifier array SAE0 Sense amplifier enable source signal SAEQ Sense amplifier equalize signal SAOb Inverted sense amplifier out signal line SAOt Sense amplifier out signal line SAPG Read driver control voltage SLC Source line contact SLS Source line selection signal SMCA Sub memory cell array SMED Source line batch erase driver SMES Source Line batch erase signal SN Sense node SNREF Referen SENSE NODE STI Isolation film for element isolation SUB Semiconductor substrate SWD Sub word driver SWDA Sub word driver array UL Upper electrode VBH Memory cell write voltage VBHb Bank memory cell write voltage VDD Peripheral circuit power supply voltage VDDb Bank peripheral circuit power supply voltage VKK Negative power supply VPP Word line boost voltage VPPb Bank word line boost voltage VSS Ground voltage WAMP Write unit WE Write enable signal WEB Inverted write enable signal WET Write enable signal WLE Word line enable signal WLE0 Word line enable source signal XAB Row address buffer XDEC X decode circuit XP Row control circuit YAB Column address buffer YDEC Y decode circuit YS Column selection signal YSE Column selection enable signal

Claims

A first memory region having a plurality of first memory cells;
A plurality of second memory cells having the same configuration as the plurality of first memory cells, and a second memory region formed on the same semiconductor chip as the first memory region;
A power control circuit for independently controlling power supply to the first memory area and power supply to the second memory area;
An address conversion circuit for converting a logical address input from the outside into a physical address of the first and second memory areas;
Holding a correspondence relationship between the logical address and the physical address, and comprising an address conversion table read and written by the address conversion circuit;
The address conversion circuit further detects the first memory cell in an unwritten state from within the first memory region, and detects the second memory cell in a written state from within the second memory region, It has a defragmentation function that controls to move the data of the second memory cell in the written state to the first memory cell in the unwritten state and updates the contents of the address conversion table in accordance with this movement. A featured semiconductor device.
The semiconductor device according to claim 1,
Each of the plurality of first memory cells and the plurality of second memory cells is a nonvolatile memory cell.
The semiconductor device according to claim 2,
The semiconductor device, wherein each of the first memory area and the second memory area is a memory bank.
The semiconductor device according to claim 3.
A data buffer for temporarily holding access data between the first memory area or the second memory area and the outside is formed on the semiconductor chip,
The semiconductor device according to claim 1, wherein the defragmentation function controls to move the data through the data buffer.
The semiconductor device according to claim 2,
The semiconductor device, wherein the first memory area and the second memory area are different memory arrays in the same memory bank.
The semiconductor device according to claim 5.
On the semiconductor chip, further
A first sense amplifier for amplifying data of the first memory cell;
A second sense amplifier for amplifying data of the second memory cell;
A main amplifier circuit for further amplifying data of the first sense amplifier or the second sense amplifier;
The semiconductor device according to claim 1, wherein the defragmenting function performs control to move the data through the main amplifier circuit.
The semiconductor device according to claim 1,
The address conversion table holds a correspondence relationship between the logical address and the physical address in units of block areas including a plurality of consecutive memory addresses, and further indicates whether the physical address is in the unwritten state or the written state. A semiconductor device having a flag to represent.
3. The semiconductor device according to claim 2, further comprising:
A batch erase control circuit for writing the same data to the plurality of first memory cells in the first memory region or the plurality of second memory cells in the second memory region collectively. Semiconductor device.
A first memory region having a plurality of first memory cells;
A plurality of second memory cells having the same configuration as the plurality of first memory cells, and a second memory region formed on the same semiconductor chip as the first memory region;
A semiconductor device comprising: a power supply control circuit that independently controls power supply / non-supply to the first memory area and power supply / non-supply to the second memory area.
The semiconductor device according to claim 9.
Each of the plurality of first memory cells and the plurality of second memory cells is a nonvolatile memory cell.
The semiconductor device according to claim 10.
The semiconductor device, wherein each of the first memory area and the second memory area is a memory bank.
The semiconductor device according to claim 10.
The semiconductor device, wherein the first memory area and the second memory area are different memory arrays in the same memory bank.
First and second memory regions each having a plurality of non-volatile memory cells;
A batch erase control circuit that writes the same data to the plurality of nonvolatile memory cells in the first memory region or the plurality of nonvolatile memory cells in the second memory region in a batch;
An address conversion circuit for converting a logical address input from the outside into a physical address of the first and second memory areas;
Holding a correspondence relationship between the logical address and the physical address, and comprising an address conversion table read and written by the address conversion circuit;
The address conversion circuit detects the non-volatile memory cell in an unwritten state from the first memory area, detects the non-volatile memory cell in a write state from the second memory area, and Control is performed to move the data of the nonvolatile memory cell in the second memory area to the nonvolatile memory cell in the first memory area in the unwritten state, and the address conversion is performed according to the movement A semiconductor device having a defragmenting function for updating contents of a table.
The semiconductor device according to claim 13.
Each of the plurality of nonvolatile memory cells includes a resistance change type memory element.
The semiconductor device according to claim 14.
The batch erase control circuit writes the resistance change type memory element in a high resistance state.
The semiconductor device according to claim 13.
Each of the first and second memory regions includes a plurality of word lines, a plurality of bit lines and a plurality of source lines extending in a direction intersecting with the plurality of word lines, the plurality of word lines and the plurality of bits. A plurality of nonvolatile memory cells disposed at intersections of a line and the plurality of source lines;
Each of the plurality of nonvolatile memory cells includes:
A resistance change type memory element having one end connected to one of the plurality of bit lines or one of the plurality of source lines;
On / off is controlled by one of the plurality of word lines, one end is connected to the other end of the memory element, and the other end is connected to one of the plurality of source lines or one of the plurality of bit lines. A memory cell transistor,
Each of the first and second memory areas further includes:
A plurality of first switches for simultaneously applying a first voltage to the plurality of bit lines when driven on;
A plurality of second switches for simultaneously applying a second voltage to the plurality of source lines when driven on;
With the plurality of first switches and the plurality of second switches turned on, the plurality of word lines are activated to write the same data to the entire first memory area or the entire second memory area. A semiconductor device having a batch erase function.
The semiconductor device according to claim 13.
The address conversion table holds a correspondence relationship between the logical address and the physical address in units of block areas including a plurality of continuous memory addresses, and indicates whether the physical address is in the unwritten state or the written state A semiconductor device comprising:
Each of a plurality of word lines, a plurality of bit lines and a plurality of source lines extending in a direction intersecting with the plurality of word lines, an intersection of the plurality of word lines and the plurality of bit lines and the plurality of source lines First and second memory regions including a plurality of nonvolatile memory cells disposed in
Each of the plurality of nonvolatile memory cells includes:
A resistance change type memory element having one end connected to one of the plurality of bit lines or one of the plurality of source lines;
On / off is controlled by one of the plurality of word lines, one end is connected to the other end of the memory element, and the other end is connected to one of the plurality of source lines or one of the plurality of bit lines. A memory cell transistor,
Each of the first and second memory areas further includes:
A plurality of first switches for simultaneously applying a first voltage to the plurality of bit lines when driven on;
A plurality of second switches for simultaneously applying a second voltage to the plurality of source lines when driven on;
With the plurality of first switches and the plurality of second switches turned on, the plurality of word lines are activated to write the same data to the entire first memory area or the entire second memory area. A semiconductor device having a batch erase function.
The semiconductor device according to claim 18.
The batch erasing function writes the resistance change type memory element in a high resistance state.
The semiconductor device according to claim 19, wherein
The batch erase function sequentially activates the plurality of word lines in units of several.