WO2010123750A1 - Multiple vt field-effect transistor devices - Google Patents
Multiple vt field-effect transistor devices Download PDFInfo
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- WO2010123750A1 WO2010123750A1 PCT/US2010/031224 US2010031224W WO2010123750A1 WO 2010123750 A1 WO2010123750 A1 WO 2010123750A1 US 2010031224 W US2010031224 W US 2010031224W WO 2010123750 A1 WO2010123750 A1 WO 2010123750A1
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- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 206
- 239000002184 metal Substances 0.000 claims abstract description 206
- 238000000034 method Methods 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 29
- 125000006850 spacer group Chemical group 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 7
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 7
- 239000011777 magnesium Substances 0.000 claims description 5
- 229910000480 nickel oxide Inorganic materials 0.000 claims description 5
- 229910052765 Lutetium Inorganic materials 0.000 claims description 4
- 229910052788 barium Inorganic materials 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 229910052746 lanthanum Inorganic materials 0.000 claims description 4
- 229910052749 magnesium Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052702 rhenium Inorganic materials 0.000 claims description 4
- 229910052712 strontium Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910052684 Cerium Inorganic materials 0.000 claims description 3
- 229910052777 Praseodymium Inorganic materials 0.000 claims description 3
- 229910052769 Ytterbium Inorganic materials 0.000 claims description 3
- 229910000428 cobalt oxide Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010948 rhodium Substances 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 239000004408 titanium dioxide Substances 0.000 claims description 3
- 229910052727 yttrium Inorganic materials 0.000 claims description 3
- 229910052692 Dysprosium Inorganic materials 0.000 claims description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- VXAUWWUXCIMFIM-UHFFFAOYSA-M aluminum;oxygen(2-);hydroxide Chemical compound [OH-].[O-2].[Al+3] VXAUWWUXCIMFIM-UHFFFAOYSA-M 0.000 claims description 2
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 claims description 2
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- KBQHZAAAGSGFKK-UHFFFAOYSA-N dysprosium atom Chemical compound [Dy] KBQHZAAAGSGFKK-UHFFFAOYSA-N 0.000 claims description 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 2
- OHSVLFRHMCKCQY-UHFFFAOYSA-N lutetium atom Chemical compound [Lu] OHSVLFRHMCKCQY-UHFFFAOYSA-N 0.000 claims description 2
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims description 2
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium atom Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 claims description 2
- WUAPFZMCVAUBPE-UHFFFAOYSA-N rhenium atom Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052703 rhodium Inorganic materials 0.000 claims description 2
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 claims description 2
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 claims description 2
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 2
- IVMYJDGYRUAWML-UHFFFAOYSA-N cobalt(ii) oxide Chemical compound [Co]=O IVMYJDGYRUAWML-UHFFFAOYSA-N 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000009977 dual effect Effects 0.000 description 20
- 238000013461 design Methods 0.000 description 15
- 230000008569 process Effects 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 229910003468 tantalcarbide Inorganic materials 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- 150000002739 metals Chemical class 0.000 description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000002207 thermal evaporation Methods 0.000 description 7
- 239000002243 precursor Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 229910052735 hafnium Inorganic materials 0.000 description 5
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 206010010144 Completed suicide Diseases 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- -1 HfZrO4 Inorganic materials 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- 229910052784 alkaline earth metal Inorganic materials 0.000 description 2
- 150000001342 alkaline earth metals Chemical class 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052747 lanthanoid Inorganic materials 0.000 description 2
- 150000002602 lanthanoids Chemical class 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- KAGOZRSGIYZEKW-UHFFFAOYSA-N cobalt(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Co+3].[Co+3] KAGOZRSGIYZEKW-UHFFFAOYSA-N 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7856—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present invention relates to field-effect transistor (FET) devices, and more particularly, to multiple threshold voltage (Vt) FET devices and techniques for the fabrication thereof.
- FET field-effect transistor
- Vt threshold voltage
- FETs Field-effect transistors
- a FET includes a source region and a drain region connected by a channel, and a gate that regulates electron flow through the channel between the source and drain regions.
- the channel can include an n-type or p-type semiconductor material, forming an n-channel FET (NFET) or a p-channel FET (PFET), respectively.
- NFET n-channel FET
- PFET p-channel FET
- a finFET One particular type of FET, a finFET, is favored in some applications due to its fast switching times and high current densities.
- a finFET includes a source region, a drain region and one or more fin-shaped channels between the source and drain regions.
- a gate electrode over the fin(s) regulates electron flow between the source and the drain.
- Vdd is determined empirically once the final design is made.
- conventional devices will almost always have higher design costs to ensure the circuit design functions at lower V dd - This cost arises from both checking the design itself over a wider range of voltages, as well as ensuring the model itself is well calibrated across this range of V d d's, which is often non-trivial. Plus, there is also the risk that if these tasks are not performed correctly, the costs associated with a re-design cycle might also be incurred.
- the present invention provides multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof.
- a FET device including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
- a method for fabricating a FET device includes the following steps.
- a plurality of fins is patterned in a silicon-on- insulator (SOI) layer each fin having a first side and a second side opposite the first side.
- a dielectric layer is formed over each of the fins.
- a gate is formed that surrounds at least a portion of each of the fins and is separated from the fins by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
- a source region and a drain region are formed interconnected by the fins.
- a base is patterned in a SOI layer having a first side, a second side opposite the first side and a top.
- a dielectric layer is formed over the base.
- a gate is formed that surrounds at least a portion of the base and is separated from the base by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
- a source region and a drain region are formed on opposite sides of the gate.
- FIG. 1 is a schematic diagram illustrating an exemplary fin field-effect transistor (finFET) device according to an embodiment of the present invention
- FIGS. 2A and 2B are cross-sectional diagrams illustrating the formation of fins (channels) and a gate dielectric of the finFET device of FIG. 1 according to an embodiment of the present invention
- FIGS. 2C-F are cross-sectional diagrams illustrating the creation of a dual Vt gate of the finFET device of FIG. 1 according to an embodiment of the present invention
- FIGS. 2G-I are cross-sectional diagrams illustrating the formation of source/drain regions of the finFET device of FIG. 1 according to an embodiment of the present invention
- FIG. 3 is a schematic diagram illustrating an exemplary metal-oxide semiconductor field-effect transistor (MOSFET) device according to an embodiment of the present invention
- FIGS. 4A and 4B are cross-sectional diagrams illustrating the creation of a base and gate dielectric for the MOSFET device of FIG. 3 according to an embodiment of the present invention
- FIGS. 4C-L are cross-sectional diagrams illustrating the creation of a dual Vt gate of the MOSFET device of FIG. 3 according to an embodiment of the present invention
- FIGS. 4M-0 are cross-sectional diagrams illustrating the formation of source/drain regions of the MOSFET device of FIG. 3 according to an embodiment of the present invention.
- FIG. 5 is a table illustrating performance of two single Vt FET devices and a dual Vt FET device according to an embodiment of the present invention.
- FET Field-effect transistor
- Vt' s threshold voltages
- a number of different FET device designs will be presented each of which is configured with a multiple Vt gate due to the selective placement of one or more band edge metals throughout the gate (see below).
- the first devices presented are dual Vt finFET devices.
- FIG. 1 is a schematic diagram illustrating an exemplary finFET device 100.
- FinFET device 100 includes a source region 106, a drain region 108 and a plurality of fins 110 interconnecting the source and drain regions. Fins 110 are patterned in a silicon-on-insulator (SOI) layer wherein the insulator is a buried oxide (BOX) 104.
- SOI silicon-on-insulator
- BOX buried oxide
- a gate 112 surrounds at least a portion of each of fins 110.
- Fins 110 serve as channels of the device.
- Each fin has two sides (a first side and a second side opposite the first side).
- a portion of the gate adjacent to the first side of each fin is configured to have a threshold voltage Vt 1 and a portion of the gate adjacent to the second side of each fin is configured to have a threshold voltage Vt 2 , wherein Vt 2 is different from Vt 1 (i.e., a differential threshold voltage) due to at least one band edge metal being present in the portion of the gate adjacent to the first side of each fin.
- FIGS. 2A-I are diagrams illustrating an exemplary methodology for fabricating a finFET device, such as finFET device 100 described in conjunction with the description of FIG. 1, above.
- FIGS. 2A and 2B highlight, by way of reference to cross-sectional views through plane A (see FIG. 1), the formation of fins (channels) and a gate dielectric.
- FIGS. 2C-F highlight, by way of reference to cross-sectional views through plane A (see FIG. 1), the creation of a dual Vt gate over the fins.
- FIGS. 2G-I highlight, by way of reference to views from vantage point B (see FIG. 1), the formation of source/drain regions of the device.
- the starting platform for the device is a conventional SOI wafer having a SOI layer over a BOX.
- a substrate is typically present adjacent to a side of the BOX opposite the SOI layer (not shown in the instant diagrams).
- a plurality of fins 202 are patterned, i.e., using standard patterning techniques, in the SOI layer over the BOX, i.e., BOX 204.
- Each fin 202 patterned in this manner will have two sides (opposite one another) and a top.
- the sides are hereinafter referred to as a first side and a second side, with the first side arbitrarily referring to a left side of each fin and the second side arbitrarily referring to a right side of each fin (based on the representations shown in FIG. 2A). Further, as shown in FIG 2 A, all of the fins have a common orientation wherein the first side of each fin faces one direction (e.g., to the left) and the second side of each fin faces the opposite direction (e.g., to the right).
- dielectric layer 206 is formed over exposed portions of BOX 204 and over each fin 202 patterned in the SOI layer.
- Dielectric layer 206 can include one or more of silicon dioxide (SiO 2 ) and silicon oxynitride (SiON) and can be deposited using standard thermal oxidation or rapid thermal process (RTP) oxidation to a thickness of from about 0.7 nanometers (run) to about three nm.
- RTP rapid thermal process
- dielectric layer 206 can include a hafnium-based high-k material, such as hafnium oxide (HfO 2 ), hafnium zirconate (HfZrO 4 ), hafnium silicate (HfSiO) and/or nitrided hafnium silicate (HfSiON), and can be deposited using a suitable high-k material deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), to a thickness of from about one nm to about five nm.
- CVD chemical vapor deposition
- ALD atomic layer deposition
- Dielectric layer 206 will separate each fin 202 from a gate of the device, and thus dielectric layer 206 serves as a gate dielectric.
- the formation of the gate begins, as shown in FIG. 2C, with the deposition of a first metal layer 208 over the dielectric layer.
- the first metal layer can include titanium nitride (TiN), tantalum nitride (TaN) and/or tantalum carbide (TaC) and can be deposited using ALD to a thickness of from about five nm to about 50 nm.
- the first metal layer does not include any band edge metal.
- a concentration of the band edge metal in the first metal layer is less than a concentration of a band edge metal in the second metal layers, see FIG. 2D, described below.
- a series of second metal layers 210 are selectively deposited over portions of first metal layer 208 at the top and at one of the sides of each fin. While FIG. 2D depicts selective deposition on the second side of each fin, this is merely exemplary, as the series of second metal layers 210 can, alternatively, be selectively deposited on the first side of each fin.
- This selective deposition can be achieved using directional deposition techniques and/or differential deposition techniques (e.g., as illustrated by arrows 211).
- second metal layers 210 can be deposited using thermal evaporation or electron- beam (e-beam) evaporation.
- second metal layers 210 include a conventional gate metal, such as TiN, TaN and/or TaC, doped with at least one band edge metal.
- the particular band edge metal(s) used in second metal layers 210 can vary depending on whether the finFET device being fabricated is an n-channel finFET (abbreviated herein as "NFET”) or a p-channel finFET (abbreviated herein as "PFET").
- the band edge metal(s) can include any group HA (alkaline earth metals)/group HIB (lanthanides) column element, such as one or more of magnesium (Mg), barium (Ba), strontium (Sr) (group HA), lanthanum (La), yttrium (Y), dysprosium (Dy), cerium (Ce), praseodymium (Pr), ytterbium (Yb) and lutetium (Lu) (group IIIB).
- group HA alkaline earth metals
- group HIB lanthanides
- the band edge metal(s) can include one or more of aluminum (Al), rhodium (Rh), rhenium (Re), platinum (Pt), tungsten (W), nickel (Ni), cobalt (Co), aluminum dioxide (AlO 2 ), titanium dioxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), nickel oxide (NiO) and cobalt oxide (Co 2 O 3 ).
- second metal layers 210 are formed by first depositing the conventional gate metal onto the desired side (i.e., either first side or second side) of each fin over first metal layer 208 using, e.g., thermal evaporation or e-beam evaporation to a thickness of from about five nm to about 50 nm.
- the appropriate band edge metal(s) is then deposited over the conventional gate metal again using, e.g., thermal evaporation or e-beam evaporation to a thickness of from about one angstrom (A) to about 20 A (the thickness depending on the desired concentration of the band edge metal in the second metal layers).
- the conventional and band edge metals are then interdiffused throughout second metal layers 210 using an annealing process which can be conducted immediately after the metal depositions, or alternatively, after completion of the gate as a final source/drain activation anneal (see below).
- the parameters used for such annealing processes are well known to those of skill in the art and thus are not described further herein.
- a portion of the gate adjacent to the first side of each fin will have a threshold voltage Vt i due to the presence of first metal layer 208 (e.g., a non-band edge metal) in the portion of the gate adjacent to the first side of each fin, and the second side of each fin will have a threshold voltage Vt 2 , wherein Vt 2 is different from Vt 1 due to the presence of second metal layer 210 (e.g., having a band edge metal) in the portion of the gate adjacent to the second side of each fin.
- a width of each fin (labeled w in FIG. 2D) is generally small enough that any Vt contribution from a portion of the gate adjacent to the top of each fin can be neglected.
- Vt 2 ⁇ Vt 1 because the band edge metal(s) will typically lower the Vt. Therefore, as highlighted above, if a band edge metal is present in both the first and the second metal layers and if more band edge metal is present in the second metal layers, then the portion of the gate adjacent to the second side of each fin will have a lower Vt than the portion of the gate adjacent to the first side of each fin.
- a finFET device with these properties will operate excellently in low supply voltage (V dd ) (Vt 2 > V dd > Vt 1 ), low power mode. When the Vdd is increased above Vt 2 , the device will operate in a high performance mode.
- third metal layer 212 is deposited over first metal layer 208 and second metal layers 210.
- Third metal layer 212 can include TiN, TaN and/or TaC and can be deposited using CVD or ALD to a thickness of from about five ran to about 50 nm.
- a polysilicon layer i.e., polysilicon layer 214
- polysilicon layer 214 can optionally be deposited over third metal layer 212.
- Polysilicon makes the gate compatible with subsequent self-aligned silicidation (when the source/drain regions are suicided).
- a contact scheme that is compatible with a metal gate would eliminate the need for the polysilicon layer.
- some metal gates such as TiN/ TaN
- Polysilicon layer 214 can be deposited using CVD, plasma enhanced chemical vapor deposition (PECVD) or rapid thermal chemical vapor deposition (RTCVD) to a thickness of from about 30 nm to about 150 nm.
- any further standard processing of the gate may then be carried out, if required.
- the fins can be annealed, e.g., to interdiffuse the metals in the metal layers as described above.
- the gate is now completed.
- FIG. 2G shows completed gate 216 formed over fins 202 as described above.
- FIGS. 2G-I illustrate the formation of either a source region or a drain region on one side of the gate, however it is to be understood that the same processes apply to forming the counterpart source region or drain region on the opposite side of the gate.
- offset spacers 218 are formed on either side of gate 216.
- the offset spacers include silicon nitride (SiN).
- Extension implants into fins 202 in the source/drain regions is also performed. As shown in FIG. 21, epitaxial Si 220 is grown over fins 202. Offset spacers 218 (see FIG. 2H) are removed and replaced by final spacers 222. Source/drain implants are then introduced to the region, followed by a rapid thermal anneal. As a result, source/drain region 224 is formed. Suicide contacts (not shown) to the source/drain regions may also be formed. The specific parameters for source region/drain region and suicide formation techniques are well known to those of skill in the art and thus are not described further herein.
- MOSFET metal-oxide semiconductor field-effect transistor
- FIG. 3 is a schematic diagram illustrating exemplary MOSFET device 300.
- MOSFET device 300 includes a source region 302, a drain region 304, a channel 306 interconnecting source region 302 and drain region 304 and a gate 308 surrounding at least a portion of channel 306.
- gate 308 has a dual Vt design, wherein two sides of gate 308 have a first threshold voltage Vt 1 and a top of gate 308 has a second threshold voltage Vt 2 due to the selective placement of one or more band edge metals throughout the gate.
- the use of a dual Vt gate design allows MOSFET device 300 to be run in either a low active power mode or a high performance mode, thus providing savings through an overall reduced power consumption without undesirable performance degradation.
- FIGS. 4A-0 are cross-sectional diagrams illustrating an exemplary methodology for forming a MOSFET device, such as MOSFET device 300 described in conjunction with the description of FIG. 3, above.
- FIGS. 4A and 4B highlight, by way of reference to cross-sectional views through plane a (see FIG. 3), the creation of a base for the device and a gate dielectric layer over the base that will separate a portion of the base that will serve as a channel of the device from a gate of the device. See below.
- FIGS. 4C-L highlight, by way of reference to cross-sectional views through plane a (see FIG. 3), the creation of a dual Vt gate.
- the MOSFET devices described herein are trigate devices.
- a trigate includes three active portions, in this case a top surface and two sides.
- the sides of the trigate are both configured to have a same threshold voltage Vt 1 while the top is configured to have a different threshold voltage Vt 2 (this configuration is referred to herein as a "dual Vt" configuration).
- a device with these properties will operate excellently in a low power mode when a low supply voltage (V 1Jd ) is provided, i.e., Vt 2 >V dd > Vt 1 .
- V 1Jd a low supply voltage
- Vt 2 >V dd > Vt 1 a low supply voltage
- V dd is increased above Vt 2
- the device will operate in a high performance mode.
- Trigate devices are receiving substantial attention as candidates for 22 nm technologies and beyond. Trigate devices offer better electrostatic control, permitting gate length scaling.
- the current available per planar layout increases (i.e., as compared to conventional planar configurations), as the sides are now gated regions.
- the starting platform for the device can be a SOI wafer or a bulk silicon wafer.
- a SOI wafer having an SOI layer over a BOX is chosen for use in the instant description.
- the SOI layer of the wafer is patterned, e.g., using standard lithography techniques, to form a base 402 for the device over the BOX, i.e., BOX 404.
- An SOI wafer commonly also includes a substrate adjacent to a side of the BOX opposite the SOI layer, which is not shown in the instant diagrams.
- a source region, a drain region and a gate will be formed over base 402 with a portion of the base between the source and drain regions and under the gate serving as a channel of the device.
- the gate will be configured as a trigate having two sides (a first side and a second side opposite the first side) and a top. Accordingly, base 402 has a first side, a second side opposite the first side and a top which will correspond to the first side, second side and top of the gate, respectively, adjacent thereto.
- the starting SOI wafer can be partially or fully depleted.
- a SOI wafer having a thicker SOI layer is used (SOI thickness Tsoi is greater than or equal to 30 nm) or when a bulk silicon wafer is used, the wafer is preferably partially depleted.
- a SOI wafer having a thinner SOI layer is used (Tsoi is less than or equal to 30 nm) the wafer is preferably fully depleted.
- dielectric layer 406 is then formed over base 402 and exposed portions of BOX 404.
- Dielectric layer 406 will separate the channel of the device from a gate of the device and thus dielectric layer 406 serves as a gate dielectric.
- Dielectric layer 406 can include one or more of SiO 2 and SiON and can be formed using standard thermal or RTP oxidation to a thickness of from about 0.7 nm to about three nm.
- dielectric layer 406 can include a hafnium-based high-k material, such as HfO 2 , HfZrO 4 , HfSiO and/or HfSiON and can be formed using CVD or ALD to a thickness of from about one nm to about five nm.
- a high-k dielectric is preferable in situations where metal gates are used and/or when a dielectric with scaling properties advantageous to SiO 2 is required.
- metal layer 408 includes a conventional gate metal, such as TiN, TaN and/or TaC, doped with at least one band edge metal.
- the particular band edge metal(s) used in metal layer 408 can vary depending on whether the MOSFET device being formed is an n-channel MOSFET (NMOSFET) or a p-channel MOSFET device (PMOSFET).
- the band edge metal(s) can include a group HA (alkaline earth metals)/group IHB (lanthanides) column element, such as one or more of Mg, Ba, Sr (group HA), La, Y, Dy, Ce, Pr, Yb and Lu (group IHB).
- group HA alkaline earth metals
- group IHB group IHB
- the band edge metal(s) can include one or more of Al, Rh, Re, Pt, W, Ni, Co, AlO 2 , TiO 2 , Ta 2 O 5 , NiO and Co 2 O 3 .
- metal layer 408 is formed by first depositing the conventional gate metal over dielectric layer 406 using CVD, ALD, sputtering or thermal evaporation to a thickness of from about five run to about 50 nm.
- the appropriate band edge metal(s) is then deposited over the conventional gate metal again using CVD, ALD, sputtering or thermal evaporation to a thickness of from about two A to about three A.
- the conventional and band edge metals are then interdiffused throughout metal layer 408 using an annealing process which can be conducted immediately after the metal depositions, or alternatively, after completion of the gate as part of a final source/drain activation anneal.
- the parameters used for such annealing processes are well known to those of skill in the art and thus are not described further herein.
- an offset spacer precursor layer 410 is deposited over metal layer 408.
- Spacer precursor layer 410 can include one or more of polysilicon or amorphous silicon and can be conformally deposited over metal layer 408 using CVD, PECVD or RTCVD to a thickness of from about three nm to about 15 nm.
- Spacer precursor layer 410 can be predoped in situ with phosphorus (P) or arsenic (As) for NMOSFET or boron (B) for PMOSFET if an additional band edge metal layer is going to be used (see, for example, FIGS. 4G-I, described below).
- spacer precursor layer 410 may also include a non-conductive dielectric, such as SiN, since the offset spacers formed therefrom will be subsequently removed during processing, see below.
- offset spacers 412 and 414 are then formed from spacer precursor layer 410 on each side of base 402 adjacent to metal layer 408.
- RIE reactive ion etching
- the portion of metal layer 408 exposed by the RIE is selectively removed from the top of base 402 (i.e., from over a portion of the dielectric layer on top of the base), for example, using wet etching.
- This process essentially forms two separate layers from metal layer 408, one on each side (i.e., on the first side and second side) of base 402 (referred to hereinafter as a first metal layer 408a and a second metal layer 408b).
- first metal layer will be used to refer to the portion of metal layer 408 that remains to a left (first) side of base 402 adjacent to the dielectric layer and the term “second metal layer” will be used to refer to the portion of metal layer 408 that remains to a right (second) side of base 402 adjacent to the dielectric layer. This name assignment is however arbitrary.
- first metal layer 408a and second metal layer 408b originate from the same metal layer (metal layer 408), first metal layer 408a and second metal layer 408b have a same (or approximately the same) composition and physical properties, such as thickness.
- the steps taken can vary depending on whether or not another metal layer, i.e., a third metal layer including a different band edge metal(s) is employed.
- FIGS. 4G-I depict the use of a third metal layer in the trigate
- FIGS. 4J-L depict a trigate without a third metal layer.
- Either configuration depicted in FIGS. 4G-I or in FIGS. 4J-L will achieve a dual Vt trigate.
- a third metal layer with its associated band edge metal to aid in "fine-tuning" the threshold voltages of the sides of the trigate relative to the top of the trigate, and vice versa.
- most metal gates typically have mid-gap workfunctions.
- the channel doping has to be greatly reduced as compared to a band edge device, i.e., typically reduced by from about 30 percent (%) to about 60%. The reduced channel doping degrades the short channel response. If the channel doping is not reduced, the Vt will be typically too high.
- band edge metals at the sides and top of the gate could still be used, but the likelihood increases that the band edge metal at the top of the gate could be omitted, as this Vt would not be as high in a fully depleted device.
- the band edge metal(s) would be used only at the sides of the gate (FIGS. 4J-L). Incentives to omit the additional band edge metal would be lower process costs and process simplification.
- a third metal layer 416 is deposited over a portion of dielectric layer 406 on top of base 402 and over offset spacers 412/414. Like first and second metal layers 408a and 408b, third metal layer 416 also includes a conventional gate metal, such as TiN, TaN and/or TaC, doped with at least one band edge metal. However, the band edge metal in third metal layer 416 is different from the band edge metal in first and second metal layers 408a and 408b (in order to achieve a dual Vt trigate).
- a conventional gate metal such as TiN, TaN and/or TaC
- Third metal layer 416 can include one or more of the following band edge metals, Mg, Ba, Sr (group HA), La, Y Dy, Ce, Pr, Yb and Lu (group IIIB) for NMOSFET, and Al, Rh, Re, Pt, W, Ni, Co, AlO 2 , TiO 2 , Ta 2 O 5 , NiO and Co 2 O 3 for PMOSFET.
- third metal layer 416 is formed by first depositing the conventional gate metal over the top of the gate stack, offset spacers 412/414 and dielectric layer 406 using CVD, ALD, sputtering or thermal evaporation to a thickness of from about five nm to about 50 nm.
- the appropriate band edge metal(s) is then deposited over the conventional gate metal again using CVD, ALD, sputtering or thermal evaporation to a thickness of from about two A to about three A.
- the conventional and band edge metals are then interdiffused throughout third metal layer 416 using an annealing process which can be conducted immediately after the metal depositions, or alternatively, after completion of the gate as part of a final source/drain activation anneal.
- top electrode layer 418 is deposited over third metal layer 416.
- Top electrode layer 418 can include one or more of TiN, TaC and TaN, and can be deposited over third metal layer 416 using ALD to a thickness of from about five nm to about 50 nm.
- polysilicon layer 420 may be deposited over top electrode layer 418. This step is optional.
- a polysilicon layer may be used to make the gate compatible with subsequent self-aligned silicidation (i.e., when the source/drain regions of the device are suicided).
- a contact scheme that is compatible with a metal gate would eliminate the need for the polysilicon layer.
- some metal gates such as TiN/TaN have lower conductance than suicided polysilicon, so the polysilicon gate that received subsequent silicidation might have lower resistance along the gate.
- Polysilicon layer 420 can be deposited over top electrode layer 418 using CVD, PECVD or RTCVD to a thickness of from about 30 nm to about 150 nm. Polysilicon layer 420 can be either pre- doped or doped later during source/drain formation.
- the gate will have a dual Vt configuration with the sides (i.e., Sl and S2) of the gate both having a first threshold voltage, i.e., threshold voltage Vt 1 , and the top (i.e., T) of the gate having a second threshold voltage, i.e., threshold voltage Vt 2 , wherein Vt 2 > Vtj.
- Vt 1 can be varied relative to Vt 2 and vice versa, e.g., by varying one or more of the content and thickness of first metal layer/second metal layer and/or the third metal layer.
- FIGS. 4J-L depict a trigate without a second band edge metal.
- offset spacers 412 and 414 which were left undoped (see above), are removed. Offset spacers 412 and 414 can be removed using wet etching or a silicon-specific RIE.
- top electrode layer 422 is deposited over first and second metal layers 408a and 408b/dielectric layer 406 (i.e., over a portion of the dielectric layer on top of the base).
- Top electrode layer 422 can include doped polysilicon or a metal, such as TiN, TaC or TaN.
- top electrode layer 422 includes TiN and is deposited using ALD to a thickness of from about five nm to about 50 nm.
- a polysilicon layer 424 may be deposited over top electrode layer 422. This step is optional. As highlighted above, a polysilicon layer may be used to make the gate compatible with subsequent self-aligned silicidation (i.e., when the source/drain regions of the device are suicided). Like polysilicon layer 420, described above, polysilicon layer 424 can be deposited using CVD, PECVD or RTCVD to a thickness of from about 30 nm to about 150 nm. Polysilicon layer 424 can be either pre-doped or doped later during source/drain formation.
- the gate will have a dual Vt configuration with the sides (i.e., Sl and S2) of the gate both having a first threshold voltage, i.e., threshold voltage Vt 1 , and the top (i.e., T) of the gate having a second threshold voltage, i.e., threshold voltage Vt 2 , wherein Vt 2 > Vt 1 .
- Vt 1 can be varied relative to Vt 2 and vice versa, e.g., by varying one or more of the content and thickness of first and second band edge metal layers 408a and 408b.
- gate lithography and subsequent etch processes are used to form the gate stack. These lithography and etching steps are known to those of skill in the art and thus are not described further herein.
- the gate is self-aligned, in that the top and sides of the gate are preferably formed with only one lithography and subsequent etch step. Therefore, the top and sides are aligned to each other.
- any further standard processing of the gate may then be carried out, if required.
- the gate can be annealed, e.g., to interdiffuse the metals in the metal layers as described above. The gate is now completed.
- FIG. 4M shows a completed trigate formed as described above.
- the particular trigate shown in this example does not have a second band edge metal, however, either trigate configuration (with or without a second band edge metal) applies to this description.
- FIGS. 4N-0 illustrate the formation of either a source region or a drain region on one side of the trigate, however it is to be understood that the same processes apply to forming the counterpart source region or drain region on the opposite side of the trigate.
- offset spacers 428 are formed on either side of the trigate.
- the offset spacers include SiN. Dopants are introduced into BOX 404 in the source/drain regions (and into the polysilicon layer if not pre-doped (see above)). As shown in FIG. 40, epitaxial silicon 430 is grown in the source/drain regions and offset spacers 428 (see FIG. 4N) are removed and replaced by final spacers 432. Source/drain implants are introduced to the region, followed by a rapid thermal anneal. As a result, the source/drain regions are formed. Suicide contacts (not shown) to the source/drain regions may also be formed. The specific parameters for source region/drain region and suicide formation techniques are well known to those of skill in the art and thus are not described further herein. As highlighted above, the channel formed from the base extends between the source and drain regions.
- a trigate device having a thick base e.g., a Tsoi or X s iii con of greater than or equal to about 25 run, to not use an epitaxial source/drain region.
- the epitaxially grown source/drain growth may not be needed and this region may instead be directly implanted (see above) and suicided to form the source/drain region.
- the trigate has a side:top:side aspect ratio of about 1 :1 :1.
- the top of the gate will contribute about 1/3 of the total MOSFET contribution.
- it is assumed that the top of the gate has a significant importance, relative to the sides of the gate.
- Other configurations are presented in the Examples below, however wherein the aspect ratio is scaled.
- a dual Vt finFET device e.g., fabricated according to the methodology outlined in FIGS. 2A-I, above
- a conventional single Vt finFET device were compared at two V 4J d levels, i.e., a V ⁇ d i of one V and a V dd2 of 0.5V (wherein a ⁇ Vt, i.e., a difference between Vt 1 and Vt 2 , of about 400 mV was assumed).
- Vd d 1 V or 0.5 V.
- Vt 1 300 mV
- Vt 2 600 mV.
- constant device widths which means no re-design of existing device designs. Namely, it is assumed that the circuit and device design itself remains constant.
- the integration of trigates can easily be accomplished without altering masks, the same masks are simply implemented using different processes to get a trigate.
- a migration re-map would require circuit designers to modify circuits and the resulting physical layout (masks). Remaps are typically very costly and time consuming, whereas an integration solution (such as with the present techniques) that does not alter the physical masks has a much quicker turnaround time and less associated costs.
- Drive current I is normalized to be one V drive of the 300 mV single Vt case (see above and FIG. 5 (described below)). 3) A 10% drive loss per 100 mV overdrive is assumed. Overdrive is the amount of gate voltage greater than Vt.
- the present dual Vt FET designs advantageously, for low V dd operation, one can get the same performance with half of the active power, with a one V performance penalty, assuming front end of line (FEOL) dominated performance.
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Abstract
Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
Description
MULTIPLE Vt FIELD-EFFECT TRANSISTOR DEVICES
Field of the Invention
[0001] The present invention relates to field-effect transistor (FET) devices, and more particularly, to multiple threshold voltage (Vt) FET devices and techniques for the fabrication thereof.
Background of the Invention
[0002] Field-effect transistors (FETs) are used in many integrated circuit designs as switches to open and close the circuits. In general, a FET includes a source region and a drain region connected by a channel, and a gate that regulates electron flow through the channel between the source and drain regions. The channel can include an n-type or p-type semiconductor material, forming an n-channel FET (NFET) or a p-channel FET (PFET), respectively.
[0003] One particular type of FET, a finFET, is favored in some applications due to its fast switching times and high current densities. In its basic form, a finFET includes a source region, a drain region and one or more fin-shaped channels between the source and drain regions. A gate electrode over the fin(s) regulates electron flow between the source and the drain.
[0004] With continued scaling of electronics technologies, power, performance and density trade-offs become increasingly challenging to manage. Many strategies exist to manage power at the chip level, such as powering down non-active blocks or reducing supply voltage (Vdd) during a sleep mode. However, most of these approaches involve design overhead in terms of either managing the power-down and/or designing the circuits robustly so that they will maintain state at a lowered Vdd (where compact models typically have poor accuracy).
[0005] Often, the lower Vdd is determined empirically once the final design is made. As a result, conventional devices will almost always have higher design costs to ensure the circuit design functions at lower Vdd- This cost arises from both checking the design itself over a wider range of voltages, as well as ensuring the model itself is well calibrated across this range of Vdd's, which is often non-trivial. Plus, there is also the risk that if these tasks are not performed correctly, the costs associated with a re-design cycle might also be incurred.
[0006] Therefore, FET devices that provide power savings through low active power operations that can be easily and economically implemented with available processing technology would be desirable.
Summary of the Invention
[0007] The present invention provides multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof. In one aspect of the invention, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
[0008] In another aspect of the invention, a method for fabricating a FET device is provided. The method includes the following steps. A plurality of fins is patterned in a silicon-on- insulator (SOI) layer each fin having a first side and a second side opposite the first side. A dielectric layer is formed over each of the fins. A gate is formed that surrounds at least a portion of each of the fins and is separated from the fins by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate. A source region and a drain region are formed interconnected by the fins.
[0009] In yet another aspect of the invention, another method for fabricating a FET device is provided. The method includes the following steps. A base is patterned in a SOI layer having a first side, a second side opposite the first side and a top. A dielectric layer is formed over the base. A gate is formed that surrounds at least a portion of the base and is separated from the base by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate. A source region and a drain region are formed on opposite sides of the gate.
[0010] A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
Brief Description of the Drawings
[0011] FIG. 1 is a schematic diagram illustrating an exemplary fin field-effect transistor (finFET) device according to an embodiment of the present invention;
[0012] FIGS. 2A and 2B are cross-sectional diagrams illustrating the formation of fins (channels) and a gate dielectric of the finFET device of FIG. 1 according to an embodiment of the present invention;
[0013] FIGS. 2C-F are cross-sectional diagrams illustrating the creation of a dual Vt gate of the finFET device of FIG. 1 according to an embodiment of the present invention;
[0014] FIGS. 2G-I are cross-sectional diagrams illustrating the formation of source/drain regions of the finFET device of FIG. 1 according to an embodiment of the present invention;
[0015] FIG. 3 is a schematic diagram illustrating an exemplary metal-oxide semiconductor field-effect transistor (MOSFET) device according to an embodiment of the present invention;
[0016] FIGS. 4A and 4B are cross-sectional diagrams illustrating the creation of a base and gate dielectric for the MOSFET device of FIG. 3 according to an embodiment of the present invention;
[0017] FIGS. 4C-L are cross-sectional diagrams illustrating the creation of a dual Vt gate of the MOSFET device of FIG. 3 according to an embodiment of the present invention;
[0018] FIGS. 4M-0 are cross-sectional diagrams illustrating the formation of source/drain regions of the MOSFET device of FIG. 3 according to an embodiment of the present invention; and
[0019] FIG. 5 is a table illustrating performance of two single Vt FET devices and a dual Vt FET device according to an embodiment of the present invention.
Detailed Description of Preferred Embodiments
[0020] Field-effect transistor (FET) devices having multiple threshold voltages (Vt' s) and techniques for the fabrication thereof are provided herein. A number of different FET device designs will be presented each of which is configured with a multiple Vt gate due to the selective placement of one or more band edge metals throughout the gate (see below). The first devices presented are dual Vt finFET devices.
[0021] FIG. 1 is a schematic diagram illustrating an exemplary finFET device 100. FinFET device 100 includes a source region 106, a drain region 108 and a plurality of fins 110 interconnecting the source and drain regions. Fins 110 are patterned in a silicon-on-insulator
(SOI) layer wherein the insulator is a buried oxide (BOX) 104. A gate 112 surrounds at least a portion of each of fins 110.
[0022] Fins 110 serve as channels of the device. Each fin has two sides (a first side and a second side opposite the first side). As will be described in detail below, according to the present teachings, a portion of the gate adjacent to the first side of each fin is configured to have a threshold voltage Vt1 and a portion of the gate adjacent to the second side of each fin is configured to have a threshold voltage Vt2, wherein Vt2 is different from Vt1 (i.e., a differential threshold voltage) due to at least one band edge metal being present in the portion of the gate adjacent to the first side of each fin.
[0023] FIGS. 2A-I are diagrams illustrating an exemplary methodology for fabricating a finFET device, such as finFET device 100 described in conjunction with the description of FIG. 1, above. Namely, FIGS. 2A and 2B highlight, by way of reference to cross-sectional views through plane A (see FIG. 1), the formation of fins (channels) and a gate dielectric. FIGS. 2C-F highlight, by way of reference to cross-sectional views through plane A (see FIG. 1), the creation of a dual Vt gate over the fins. FIGS. 2G-I highlight, by way of reference to views from vantage point B (see FIG. 1), the formation of source/drain regions of the device.
[0024] According to an exemplary embodiment, the starting platform for the device is a conventional SOI wafer having a SOI layer over a BOX. A substrate is typically present adjacent to a side of the BOX opposite the SOI layer (not shown in the instant diagrams). As shown in FIG. 2A, a plurality of fins 202 are patterned, i.e., using standard patterning techniques, in the SOI layer over the BOX, i.e., BOX 204. Each fin 202 patterned in this manner will have two sides (opposite one another) and a top. For ease and consistency of description, the sides are hereinafter referred to as a first side and a second side, with the first side arbitrarily referring to a left side of each fin and the second side arbitrarily referring to a right side of each fin (based on the representations shown in FIG. 2A). Further, as shown in FIG 2 A, all of the fins have a common orientation wherein the first side of each fin faces one direction (e.g., to the left) and the second side of each fin faces the opposite direction (e.g., to the right).
[0025] As shown in FIG. 2B, dielectric layer 206 is formed over exposed portions of BOX 204 and over each fin 202 patterned in the SOI layer. Dielectric layer 206 can include one or more of silicon dioxide (SiO2) and silicon oxynitride (SiON) and can be deposited using standard thermal oxidation or rapid thermal process (RTP) oxidation to a thickness of from
about 0.7 nanometers (run) to about three nm. Alternatively, dielectric layer 206 can include a hafnium-based high-k material, such as hafnium oxide (HfO2), hafnium zirconate (HfZrO4), hafnium silicate (HfSiO) and/or nitrided hafnium silicate (HfSiON), and can be deposited using a suitable high-k material deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), to a thickness of from about one nm to about five nm. The use of a high-k dielectric is preferable in situations where metal gates are used and/or when a dielectric with scaling properties advantageous to SiO2 is required. Dielectric layer 206 will separate each fin 202 from a gate of the device, and thus dielectric layer 206 serves as a gate dielectric.
[0026] The formation of the gate begins, as shown in FIG. 2C, with the deposition of a first metal layer 208 over the dielectric layer. The first metal layer can include titanium nitride (TiN), tantalum nitride (TaN) and/or tantalum carbide (TaC) and can be deposited using ALD to a thickness of from about five nm to about 50 nm. According to an exemplary embodiment, the first metal layer does not include any band edge metal. On the other hand, if a band edge metal is present in the first metal layer, then according to the present teachings a concentration of the band edge metal in the first metal layer is less than a concentration of a band edge metal in the second metal layers, see FIG. 2D, described below.
[0027] As shown in FIG. 2D, a series of second metal layers 210 are selectively deposited over portions of first metal layer 208 at the top and at one of the sides of each fin. While FIG. 2D depicts selective deposition on the second side of each fin, this is merely exemplary, as the series of second metal layers 210 can, alternatively, be selectively deposited on the first side of each fin. This selective deposition can be achieved using directional deposition techniques and/or differential deposition techniques (e.g., as illustrated by arrows 211). For example, second metal layers 210 can be deposited using thermal evaporation or electron- beam (e-beam) evaporation. According to the present teachings, second metal layers 210 include a conventional gate metal, such as TiN, TaN and/or TaC, doped with at least one band edge metal. The particular band edge metal(s) used in second metal layers 210 can vary depending on whether the finFET device being fabricated is an n-channel finFET (abbreviated herein as "NFET") or a p-channel finFET (abbreviated herein as "PFET"). When an NFET device is being fabricated, the band edge metal(s) can include any group HA (alkaline earth metals)/group HIB (lanthanides) column element, such as one or more of magnesium (Mg), barium (Ba), strontium (Sr) (group HA), lanthanum (La), yttrium (Y), dysprosium (Dy), cerium (Ce), praseodymium (Pr), ytterbium (Yb) and lutetium (Lu) (group
IIIB). On the other hand, when a PFET device is being fabricated, the band edge metal(s) can include one or more of aluminum (Al), rhodium (Rh), rhenium (Re), platinum (Pt), tungsten (W), nickel (Ni), cobalt (Co), aluminum dioxide (AlO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5), nickel oxide (NiO) and cobalt oxide (Co2O3). According to an exemplary embodiment, second metal layers 210 are formed by first depositing the conventional gate metal onto the desired side (i.e., either first side or second side) of each fin over first metal layer 208 using, e.g., thermal evaporation or e-beam evaporation to a thickness of from about five nm to about 50 nm. The appropriate band edge metal(s) is then deposited over the conventional gate metal again using, e.g., thermal evaporation or e-beam evaporation to a thickness of from about one angstrom (A) to about 20 A (the thickness depending on the desired concentration of the band edge metal in the second metal layers). The conventional and band edge metals are then interdiffused throughout second metal layers 210 using an annealing process which can be conducted immediately after the metal depositions, or alternatively, after completion of the gate as a final source/drain activation anneal (see below). The parameters used for such annealing processes are well known to those of skill in the art and thus are not described further herein.
[0028] According to the configuration shown illustrated in FIG. 2D, a portion of the gate adjacent to the first side of each fin will have a threshold voltage Vt i due to the presence of first metal layer 208 (e.g., a non-band edge metal) in the portion of the gate adjacent to the first side of each fin, and the second side of each fin will have a threshold voltage Vt2, wherein Vt2 is different from Vt1 due to the presence of second metal layer 210 (e.g., having a band edge metal) in the portion of the gate adjacent to the second side of each fin. A width of each fin (labeled w in FIG. 2D) is generally small enough that any Vt contribution from a portion of the gate adjacent to the top of each fin can be neglected. According to an exemplary embodiment, Vt2 < Vt1 because the band edge metal(s) will typically lower the Vt. Therefore, as highlighted above, if a band edge metal is present in both the first and the second metal layers and if more band edge metal is present in the second metal layers, then the portion of the gate adjacent to the second side of each fin will have a lower Vt than the portion of the gate adjacent to the first side of each fin. A finFET device with these properties will operate excellently in low supply voltage (Vdd) (Vt2 > Vdd > Vt1), low power mode. When the Vdd is increased above Vt2, the device will operate in a high performance mode.
[0029] As shown in FIG. 2E, third metal layer 212 is deposited over first metal layer 208 and second metal layers 210. Third metal layer 212 can include TiN, TaN and/or TaC and can be deposited using CVD or ALD to a thickness of from about five ran to about 50 nm.
[0030] As shown in FIG. 2F, a polysilicon layer, i.e., polysilicon layer 214, can optionally be deposited over third metal layer 212. Polysilicon makes the gate compatible with subsequent self-aligned silicidation (when the source/drain regions are suicided). Alternatively, a contact scheme that is compatible with a metal gate would eliminate the need for the polysilicon layer. Additionally, some metal gates (such as TiN/ TaN) have lower conductance than suicided polysilicon, so the polysilicon gate that received subsequent silicidation might have lower resistance along the gate. Polysilicon layer 214 can be deposited using CVD, plasma enhanced chemical vapor deposition (PECVD) or rapid thermal chemical vapor deposition (RTCVD) to a thickness of from about 30 nm to about 150 nm.
[0031] Any further standard processing of the gate may then be carried out, if required. By way of example only, the fins can be annealed, e.g., to interdiffuse the metals in the metal layers as described above. The gate is now completed.
[0032] Standard processing can then also be used to form source and drain regions at opposite ends of the gate and interconnected by the fins. For example, switching now to a view from vantage point B (see, for example, FIG. 1), FIG. 2G shows completed gate 216 formed over fins 202 as described above. FIGS. 2G-I illustrate the formation of either a source region or a drain region on one side of the gate, however it is to be understood that the same processes apply to forming the counterpart source region or drain region on the opposite side of the gate. As shown in FIG. 2H, offset spacers 218 are formed on either side of gate 216. According to an exemplary embodiment, the offset spacers include silicon nitride (SiN). Extension implants into fins 202 in the source/drain regions is also performed. As shown in FIG. 21, epitaxial Si 220 is grown over fins 202. Offset spacers 218 (see FIG. 2H) are removed and replaced by final spacers 222. Source/drain implants are then introduced to the region, followed by a rapid thermal anneal. As a result, source/drain region 224 is formed. Suicide contacts (not shown) to the source/drain regions may also be formed. The specific parameters for source region/drain region and suicide formation techniques are well known to those of skill in the art and thus are not described further herein.
[0033] The next devices presented are dual Vt metal-oxide semiconductor field-effect transistor (MOSFET) devices. By comparison with the finFET devices presented above,
these MOSFET devices are trigate devices with a top and two sides of the gate contributing to the Vt of the device.
[0034] FIG. 3 is a schematic diagram illustrating exemplary MOSFET device 300. MOSFET device 300 includes a source region 302, a drain region 304, a channel 306 interconnecting source region 302 and drain region 304 and a gate 308 surrounding at least a portion of channel 306. As will be described in detail below, gate 308 has a dual Vt design, wherein two sides of gate 308 have a first threshold voltage Vt1 and a top of gate 308 has a second threshold voltage Vt2 due to the selective placement of one or more band edge metals throughout the gate. The use of a dual Vt gate design allows MOSFET device 300 to be run in either a low active power mode or a high performance mode, thus providing savings through an overall reduced power consumption without undesirable performance degradation.
[0035] FIGS. 4A-0 are cross-sectional diagrams illustrating an exemplary methodology for forming a MOSFET device, such as MOSFET device 300 described in conjunction with the description of FIG. 3, above. Namely, FIGS. 4A and 4B highlight, by way of reference to cross-sectional views through plane a (see FIG. 3), the creation of a base for the device and a gate dielectric layer over the base that will separate a portion of the base that will serve as a channel of the device from a gate of the device. See below. FIGS. 4C-L highlight, by way of reference to cross-sectional views through plane a (see FIG. 3), the creation of a dual Vt gate. FIGS. 4M-0 highlight, by way of reference to views from vantage point b (see FIG. 3), the formation of source/drain regions of the device. As highlighted above, the MOSFET devices described herein are trigate devices. As the name implies, a trigate includes three active portions, in this case a top surface and two sides. As will be described in detail below, with the present techniques, the sides of the trigate are both configured to have a same threshold voltage Vt1 while the top is configured to have a different threshold voltage Vt2 (this configuration is referred to herein as a "dual Vt" configuration). A device with these properties will operate excellently in a low power mode when a low supply voltage (V1Jd) is provided, i.e., Vt2>Vdd >Vt1. When Vdd is increased above Vt2, the device will operate in a high performance mode. Trigate devices are receiving substantial attention as candidates for 22 nm technologies and beyond. Trigate devices offer better electrostatic control, permitting gate length scaling. In addition, the current available per planar layout increases (i.e., as compared to conventional planar configurations), as the sides are now gated regions.
[0036] The starting platform for the device can be a SOI wafer or a bulk silicon wafer. A SOI wafer having an SOI layer over a BOX is chosen for use in the instant description. As
shown in FIG. 4A, the SOI layer of the wafer is patterned, e.g., using standard lithography techniques, to form a base 402 for the device over the BOX, i.e., BOX 404. An SOI wafer commonly also includes a substrate adjacent to a side of the BOX opposite the SOI layer, which is not shown in the instant diagrams. Later in the process, a source region, a drain region and a gate will be formed over base 402 with a portion of the base between the source and drain regions and under the gate serving as a channel of the device. The gate will be configured as a trigate having two sides (a first side and a second side opposite the first side) and a top. Accordingly, base 402 has a first side, a second side opposite the first side and a top which will correspond to the first side, second side and top of the gate, respectively, adjacent thereto.
[0037] The starting SOI wafer can be partially or fully depleted. When a SOI wafer having a thicker SOI layer is used (SOI thickness Tsoi is greater than or equal to 30 nm) or when a bulk silicon wafer is used, the wafer is preferably partially depleted. When a SOI wafer having a thinner SOI layer is used (Tsoi is less than or equal to 30 nm) the wafer is preferably fully depleted.
[0038] As shown in FIG. 4B, dielectric layer 406 is then formed over base 402 and exposed portions of BOX 404. Dielectric layer 406 will separate the channel of the device from a gate of the device and thus dielectric layer 406 serves as a gate dielectric. Dielectric layer 406 can include one or more of SiO2 and SiON and can be formed using standard thermal or RTP oxidation to a thickness of from about 0.7 nm to about three nm. Alternatively, dielectric layer 406 can include a hafnium-based high-k material, such as HfO2, HfZrO4, HfSiO and/or HfSiON and can be formed using CVD or ALD to a thickness of from about one nm to about five nm. The use of a high-k dielectric is preferable in situations where metal gates are used and/or when a dielectric with scaling properties advantageous to SiO2 is required.
[0039] The formation of the gate begins, as shown in FIG. 4C, with the deposition of a metal layer 408 over dielectric layer 406. According to the present teachings, metal layer 408 includes a conventional gate metal, such as TiN, TaN and/or TaC, doped with at least one band edge metal. The particular band edge metal(s) used in metal layer 408 can vary depending on whether the MOSFET device being formed is an n-channel MOSFET (NMOSFET) or a p-channel MOSFET device (PMOSFET). When an NMOSFET is being formed, the band edge metal(s) can include a group HA (alkaline earth metals)/group IHB (lanthanides) column element, such as one or more of Mg, Ba, Sr (group HA), La, Y, Dy, Ce, Pr, Yb and Lu (group IHB). Alternatively, when a PMOSFET is being formed, the band edge
metal(s) can include one or more of Al, Rh, Re, Pt, W, Ni, Co, AlO2, TiO2, Ta2O5, NiO and Co2O3. According to an exemplary embodiment, metal layer 408 is formed by first depositing the conventional gate metal over dielectric layer 406 using CVD, ALD, sputtering or thermal evaporation to a thickness of from about five run to about 50 nm. The appropriate band edge metal(s) is then deposited over the conventional gate metal again using CVD, ALD, sputtering or thermal evaporation to a thickness of from about two A to about three A. The conventional and band edge metals are then interdiffused throughout metal layer 408 using an annealing process which can be conducted immediately after the metal depositions, or alternatively, after completion of the gate as part of a final source/drain activation anneal. The parameters used for such annealing processes are well known to those of skill in the art and thus are not described further herein.
[0040] As shown in FIG. 4D, an offset spacer precursor layer 410 is deposited over metal layer 408. Spacer precursor layer 410 can include one or more of polysilicon or amorphous silicon and can be conformally deposited over metal layer 408 using CVD, PECVD or RTCVD to a thickness of from about three nm to about 15 nm. Spacer precursor layer 410 can be predoped in situ with phosphorus (P) or arsenic (As) for NMOSFET or boron (B) for PMOSFET if an additional band edge metal layer is going to be used (see, for example, FIGS. 4G-I, described below). Alternatively, if an additional band edge metal layer is not going to be used (see, for example, FIGS. 4J-L, described below), then spacer precursor layer 410 may also include a non-conductive dielectric, such as SiN, since the offset spacers formed therefrom will be subsequently removed during processing, see below.
[0041] As shown in FIG. 4E, offset spacers 412 and 414 are then formed from spacer precursor layer 410 on each side of base 402 adjacent to metal layer 408. According to an exemplary embodiment, reactive ion etching (RIE) is used to form offset spacers 412 and 414, which will remove spacer precursor layer 410 from all horizontal surfaces, including from over a top of base 402 which exposes a portion of metal layer 408.
[0042] As shown in FIG. 4F, the portion of metal layer 408 exposed by the RIE is selectively removed from the top of base 402 (i.e., from over a portion of the dielectric layer on top of the base), for example, using wet etching. This process essentially forms two separate layers from metal layer 408, one on each side (i.e., on the first side and second side) of base 402 (referred to hereinafter as a first metal layer 408a and a second metal layer 408b). For consistency of description the term "first metal layer" will be used to refer to the portion of metal layer 408 that remains to a left (first) side of base 402 adjacent to the dielectric layer
and the term "second metal layer" will be used to refer to the portion of metal layer 408 that remains to a right (second) side of base 402 adjacent to the dielectric layer. This name assignment is however arbitrary.
[0043] Since first metal layer 408a and second metal layer 408b originate from the same metal layer (metal layer 408), first metal layer 408a and second metal layer 408b have a same (or approximately the same) composition and physical properties, such as thickness. At this point in the process, the steps taken can vary depending on whether or not another metal layer, i.e., a third metal layer including a different band edge metal(s) is employed. Namely, FIGS. 4G-I depict the use of a third metal layer in the trigate, whereas FIGS. 4J-L depict a trigate without a third metal layer.
[0044] Either configuration depicted in FIGS. 4G-I or in FIGS. 4J-L will achieve a dual Vt trigate. However, it may be desirable to use a third metal layer with its associated band edge metal to aid in "fine-tuning" the threshold voltages of the sides of the trigate relative to the top of the trigate, and vice versa. Namely, most metal gates typically have mid-gap workfunctions. With a short channel length MOSFET device (i.e., having a channel length that is less than 0.1 micrometers (μm)) that has a base of either partially depleted SOI or bulk silicon with a SOI thickness Tsoi (see FIG. 1) or a silicon thickness TSji;con, respectively of > 30 nm, there is a penalty in terms of short channel control for being off band edge. In order to control Vt to an acceptable loss, the channel doping has to be greatly reduced as compared to a band edge device, i.e., typically reduced by from about 30 percent (%) to about 60%. The reduced channel doping degrades the short channel response. If the channel doping is not reduced, the Vt will be typically too high.
[0045] Alternatively, for a MOSFET device with a thinner base, such as fully depleted SOI (i.e., Tsoi ≤ 30 nm) doping no longer sets the Vt. In this regime of device thickness, a quarter gap and/or mid-gap metal would provide acceptable Vt in many cases. Therefore, by way of example only, for the thicker, partially depleted SOI (or bulk silicon)-based devices, the top and sides of the gate would probably need band edge metals applied (FIGS. 4G-I), unless a very much larger Vt (e.g., from about 800 millivolts (mV) to about one volt (V)) for the top of the gate is needed. For the thinner, fully depleted SOI-based devices, band edge metals at the sides and top of the gate could still be used, but the likelihood increases that the band edge metal at the top of the gate could be omitted, as this Vt would not be as high in a fully depleted device. Thus, the band edge metal(s) would be used only at the sides of the gate
(FIGS. 4J-L). Incentives to omit the additional band edge metal would be lower process costs and process simplification.
[0046] As shown in FIG. 4G, a third metal layer 416 is deposited over a portion of dielectric layer 406 on top of base 402 and over offset spacers 412/414. Like first and second metal layers 408a and 408b, third metal layer 416 also includes a conventional gate metal, such as TiN, TaN and/or TaC, doped with at least one band edge metal. However, the band edge metal in third metal layer 416 is different from the band edge metal in first and second metal layers 408a and 408b (in order to achieve a dual Vt trigate). The portions of third metal layer 416 in contact with offset spacers 412/414 would not impact the Vt of the sides of the gate because offset spacers 412/ '414 protect the sides of the gate from the effects of the band edge metal in third metal layer 416. Third metal layer 416 can include one or more of the following band edge metals, Mg, Ba, Sr (group HA), La, Y Dy, Ce, Pr, Yb and Lu (group IIIB) for NMOSFET, and Al, Rh, Re, Pt, W, Ni, Co, AlO2, TiO2, Ta2O5, NiO and Co2O3 for PMOSFET. According to an exemplary embodiment, third metal layer 416 is formed by first depositing the conventional gate metal over the top of the gate stack, offset spacers 412/414 and dielectric layer 406 using CVD, ALD, sputtering or thermal evaporation to a thickness of from about five nm to about 50 nm. The appropriate band edge metal(s) is then deposited over the conventional gate metal again using CVD, ALD, sputtering or thermal evaporation to a thickness of from about two A to about three A. The conventional and band edge metals are then interdiffused throughout third metal layer 416 using an annealing process which can be conducted immediately after the metal depositions, or alternatively, after completion of the gate as part of a final source/drain activation anneal.
[0047] As shown in FIG. 4H, a top electrode layer 418 is deposited over third metal layer 416. Top electrode layer 418 can include one or more of TiN, TaC and TaN, and can be deposited over third metal layer 416 using ALD to a thickness of from about five nm to about 50 nm.
[0048] As shown in FIG. 41, polysilicon layer 420 may be deposited over top electrode layer 418. This step is optional. For example, a polysilicon layer may be used to make the gate compatible with subsequent self-aligned silicidation (i.e., when the source/drain regions of the device are suicided). Alternatively, a contact scheme that is compatible with a metal gate would eliminate the need for the polysilicon layer. Additionally, some metal gates (such as TiN/TaN) have lower conductance than suicided polysilicon, so the polysilicon gate that received subsequent silicidation might have lower resistance along the gate. Polysilicon layer
420 can be deposited over top electrode layer 418 using CVD, PECVD or RTCVD to a thickness of from about 30 nm to about 150 nm. Polysilicon layer 420 can be either pre- doped or doped later during source/drain formation.
[0049] Due to the presence of one band edge metal at the sides of the gate and a second band edge metal on the top of the gate, the gate will have a dual Vt configuration with the sides (i.e., Sl and S2) of the gate both having a first threshold voltage, i.e., threshold voltage Vt1, and the top (i.e., T) of the gate having a second threshold voltage, i.e., threshold voltage Vt2, wherein Vt2 > Vtj. Vt1 can be varied relative to Vt2 and vice versa, e.g., by varying one or more of the content and thickness of first metal layer/second metal layer and/or the third metal layer.
[0050] As highlighted above, FIGS. 4J-L depict a trigate without a second band edge metal. As shown in FIG. 4 J, offset spacers 412 and 414, which were left undoped (see above), are removed. Offset spacers 412 and 414 can be removed using wet etching or a silicon-specific RIE.
[0051] As shown in FIG. 4K, a top electrode layer 422 is deposited over first and second metal layers 408a and 408b/dielectric layer 406 (i.e., over a portion of the dielectric layer on top of the base). Top electrode layer 422 can include doped polysilicon or a metal, such as TiN, TaC or TaN. According to an exemplary embodiment, top electrode layer 422 includes TiN and is deposited using ALD to a thickness of from about five nm to about 50 nm.
[0052] As shown in FIG. 4L, a polysilicon layer 424 may be deposited over top electrode layer 422. This step is optional. As highlighted above, a polysilicon layer may be used to make the gate compatible with subsequent self-aligned silicidation (i.e., when the source/drain regions of the device are suicided). Like polysilicon layer 420, described above, polysilicon layer 424 can be deposited using CVD, PECVD or RTCVD to a thickness of from about 30 nm to about 150 nm. Polysilicon layer 424 can be either pre-doped or doped later during source/drain formation.
[0053] As above, due to the presence of a band edge metal only at the sides of the gate (i.e., there is no band edge metal present at the top of the gate), the gate will have a dual Vt configuration with the sides (i.e., Sl and S2) of the gate both having a first threshold voltage, i.e., threshold voltage Vt1, and the top (i.e., T) of the gate having a second threshold voltage, i.e., threshold voltage Vt2, wherein Vt2 > Vt1. Vt1 can be varied relative to Vt2 and vice versa,
e.g., by varying one or more of the content and thickness of first and second band edge metal layers 408a and 408b.
[0054] After the dielectric plus metal and/or polysilicon is deposited, gate lithography and subsequent etch processes are used to form the gate stack. These lithography and etching steps are known to those of skill in the art and thus are not described further herein. The gate is self-aligned, in that the top and sides of the gate are preferably formed with only one lithography and subsequent etch step. Therefore, the top and sides are aligned to each other.
[0055] Any further standard processing of the gate may then be carried out, if required. By way of example only, the gate can be annealed, e.g., to interdiffuse the metals in the metal layers as described above. The gate is now completed.
[0056] Standard processing can then also be used to form source and drain regions on opposite sides of the gate. For example, switching now to a view from vantage point B (see, for example, FIG. 3), FIG. 4M shows a completed trigate formed as described above. The particular trigate shown in this example does not have a second band edge metal, however, either trigate configuration (with or without a second band edge metal) applies to this description. FIGS. 4N-0 illustrate the formation of either a source region or a drain region on one side of the trigate, however it is to be understood that the same processes apply to forming the counterpart source region or drain region on the opposite side of the trigate. As shown in FIG. 4N, offset spacers 428 are formed on either side of the trigate. According to an exemplary embodiment, the offset spacers include SiN. Dopants are introduced into BOX 404 in the source/drain regions (and into the polysilicon layer if not pre-doped (see above)). As shown in FIG. 40, epitaxial silicon 430 is grown in the source/drain regions and offset spacers 428 (see FIG. 4N) are removed and replaced by final spacers 432. Source/drain implants are introduced to the region, followed by a rapid thermal anneal. As a result, the source/drain regions are formed. Suicide contacts (not shown) to the source/drain regions may also be formed. The specific parameters for source region/drain region and suicide formation techniques are well known to those of skill in the art and thus are not described further herein. As highlighted above, the channel formed from the base extends between the source and drain regions.
[0057] It is also possible for a trigate device having a thick base, e.g., a Tsoi or Xsiiicon of greater than or equal to about 25 run, to not use an epitaxial source/drain region. Thus, for base thicknesses of greater than or equal to about 25 nm, the epitaxially grown source/drain
growth may not be needed and this region may instead be directly implanted (see above) and suicided to form the source/drain region.
[0058] According to an exemplary embodiment, the trigate has a side:top:side aspect ratio of about 1 :1 :1. In that instance, the top of the gate will contribute about 1/3 of the total MOSFET contribution. Namely, with a trigate, it is assumed that the top of the gate has a significant importance, relative to the sides of the gate. Other configurations are presented in the Examples below, however wherein the aspect ratio is scaled.
[0059] The present techniques are further described by reference to the following non- limiting Examples:
Example 1
[0060] A dual Vt finFET device (e.g., fabricated according to the methodology outlined in FIGS. 2A-I, above) and a conventional single Vt finFET device were compared at two V4Jd levels, i.e., a V^di of one V and a Vdd2 of 0.5V (wherein a ΔVt, i.e., a difference between Vt1 and Vt2, of about 400 mV was assumed). For the dual Vt finFET device, active power consumption at 0.5V was about five times lower than at one V (i.e., capacitance (C) χ V2 = 0.18). By comparison, with the single Vt device, there was no drop in C, so active power consumption at 0.5 V was only about 2.5 times lower than at one V. The active power of the dual Vt finFET device at a higher Vdd is comparable to the active power of the single Vt device.
Example 2
[0061] In this example, existing MOSFET device designs were chosen (for example, to address situations when re-designing is not an option) and it was assumed that gate load dominates performance, i.e., the total device load is primarily gate-load dominated. However, it was desired that a device be produced that can operate at a low Vdd (e.g., 0.5 V) and exhibit lower active power, with an acceptable drop in performance of about 20 % at one V Vdd.
[0062] The following parameters were used:
1) Assume Vdd equals one V or 0.5 V. Assume Vt1 = 300 mV, Vt2 = 600 mV. Then assume constant device widths which means no re-design of existing device designs. Namely, it is assumed that the circuit and device design itself remains constant. The integration of trigates can easily be accomplished without altering masks, the same masks are simply implemented
using different processes to get a trigate. A migration re-map, on the other hand, would require circuit designers to modify circuits and the resulting physical layout (masks). Remaps are typically very costly and time consuming, whereas an integration solution (such as with the present techniques) that does not alter the physical masks has a much quicker turnaround time and less associated costs. 2) Drive current I is normalized to be one V drive of the 300 mV single Vt case (see above and FIG. 5 (described below)). 3) A 10% drive loss per 100 mV overdrive is assumed. Overdrive is the amount of gate voltage greater than Vt.
[0063] FIG. 5 is table 500 illustrating performance of two single Vt FET devices, i.e., having Vt] and Vt2, respectively, wherein Vt1 = 300 mV and Vt2 = 600 mV, and a dual Vt finFET device. In table 500, capacitance (C), drive current (I), power and performance are shown for both a Vdd of one V and a Vdd of 0.5 V for Case 1 (single Vt1 = 300 mV), Case 2 (single Vt2 = 600 mV) and Case 3 (dual Vt). Thus with the present dual Vt FET designs, advantageously, for low Vdd operation, one can get the same performance with half of the active power, with a one V performance penalty, assuming front end of line (FEOL) dominated performance.
[0064] Although illustrative embodiments of the present invention have been described herein, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope of the invention.
Claims
1. A field-effect transistor (FET) device comprising: a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
2. The FET device of claim 1, further comprising: a plurality of fins interconnecting the source and drain regions that serve as the channels of the device, each fin having a first side and a second side opposite the first side; and a dielectric layer separating the fins from the gate.
3. The FET device of claim 2, wherein the gate further comprises: a first metal layer over the dielectric layer; and a series of second metal layers comprising the at least one band edge metal over the first metal layer at the second side of each fin.
4. The FET device of claim 3, wherein the gate surrounds at least a portion of each of the fins, and wherein a portion of the gate adjacent to the first side of each of the fins is configured to have a threshold voltage Vt i and a portion of the gate adjacent to the second side of each of the fins is configured to have a threshold voltage Vt2, wherein Vt2 is different from Vt] due to the at least one band edge metal being present in the portion of the gate adjacent to the second side of each of the fins.
5. The FET device of claim 3, wherein the first metal layer comprises the at least one band edge metal at a lower concentration than in the second metal layer.
6. The FET device of claim 5, wherein the gate surrounds at least a portion of each of the fins, and wherein a portion of the gate adjacent to the first side of each of the fins is configured to have a threshold voltage Vt1 and a portion of the gate adjacent to the second side of each of the fins is configured to have a threshold voltage Vt2, wherein Vt2 is different from Vt1 due to the at least one band edge metal being present at a greater concentration in the portion of the gate adjacent to the second side of each of the fins.
7. The FET device of claim 1, wherein the device comprises an n-channel FET (NFET) and the at least one band edge metal comprises one or more of a group HA element, a group HIB element, magnesium, barium, strontium, lanthanum, yttrium, dysprosium, cerium, praseodymium, ytterbium and lutetium.
8. The FET device of claim 1, wherein the device comprises a p-channel FET (PFET) and the at least one band edge metal comprises one or more of aluminum, rhodium, rhenium, platinum, tungsten, nickel, cobalt, aluminum dioxide, titanium dioxide, tantalum oxide, nickel oxide and cobalt oxide.
9. The FET device of claim 3, further comprising: a third metal layer over the first and second metal layers; and a polysilicon layer over the third metal layer.
10. The FET of claim 1, further comprising: a base, a portion of which serves as the channel of the device, having a first side, a second side opposite the first side and a top; and a dielectric layer separating the portion of the base which serves as the channel from the gate.
1 1. The FET device of claim 10, wherein the gate further comprises: a first metal layer adjacent to the dielectric layer at the first side of the base; and a second metal layer adjacent to the dielectric layer at the second side of the base, wherein both the first metal layer and the second metal layer comprise the at least one band edge metal.
12. The FET device of claim 11, wherein the gate surrounds at least a portion of the base, and wherein portions of the gate adjacent to the first and second sides of the base are each configured to have a threshold voltage Vt1 and a portion of the gate adjacent to the top of the base is configured to have a threshold voltage Vt2, wherein Vt2 is different from Vt1 due to the at least one band edge metal being present at the sides of the gate and absent at the top of the gate.
13. The FET device of claim 11, wherein the gate further comprises: a third metal layer adjacent to the dielectric layer at the top of the base, the third metal layer comprising at least one band edge metal that is different from the band edge metal in the first and second metal layers; a top electrode layer over the third metal layer; and a polysilicon layer over the top electrode layer.
14. The FET device of claim 11, wherein the gate further comprises: a top electrode layer adjacent to the first and second metal layers and the dielectric layer at the top of the base; and a polysilicon layer over the top electrode layer.
15. A method for fabricating a FET device, comprising the steps of: patterning a plurality of fins in a silicon-on-insulator (SOI) layer each fin having a first side and a second side opposite the first side; forming a dielectric layer over each of the fins; forming a gate that surrounds at least a portion of each of the fins and is separated from the fins by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate; and forming a source region and a drain region interconnected by the fins.
16. The method of claim 15, wherein the step of forming the gate further comprises the steps of: depositing a first metal layer over the dielectric layer; and selectively depositing a series of second metal layers over portions of the first metal layer at the second side of each fin.
17. The method of claim 16, wherein the step of selectively depositing the series of second metal layers, further comprises the steps of: depositing a gate metal over the portions of the first metal layer at the second side of each of the fins; depositing the at least one band edge metal over the gate metal; and interdiffusing the gate metal and the band edge metal throughout the second metal layers.
18. The method of claim 16, further comprising the steps of: depositing a third metal layer over the first and second metal layers; and depositing a polysilicon layer over the third metal layer.
19. A method for fabricating a FET device comprising the steps of: patterning a base in a SOI layer having a first side, a second side opposite the first side and a top; forming a dielectric layer over the base; forming a gate that surrounds at least a portion of the base and is separated from the base by the dielectric layer, the gate being configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate; and forming a source region and a drain region on opposite sides of the gate.
20. The method of claim 19, wherein the step of forming the gate further comprises the steps of: forming a first metal layer and a second metal layer on opposite sides of the base, the first and second metal layers both comprising the at least one band edge metal; and forming offset spacers on each side of the base adjacent to the first and second metal layers.
21. The method of claim 20, wherein the step of forming the first and second metal layers further comprises the steps of: depositing a metal layer over the dielectric layer, wherein the metal layer comprises the band edge metal; and selectively removing the metal layer from over a portion of the dielectric layer on top of the base.
22. The method of claim 20, further comprising the steps of: removing the offset spacers; and depositing a top electrode layer over the first and second metal layers and over a portion of the dielectric layer on top of the base.
23. The method of claim 22, further comprising the step of: depositing a polysilicon layer over the top electrode layer.
24. The method of claim 20, further comprising the steps of: depositing a third metal layer over the offset spacers and over a portion of the dielectric layer on top of the base, wherein the third metal layer comprises a band edge metal that is different from the band edge metal in the first and second metal layers; and depositing a top electrode layer over the third metal layer.
25. The method of claim 24, further comprising the step of: depositing a polysilicon layer over the top electrode layer.
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102956496A (en) * | 2011-08-30 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and manufacturing method thereof |
US9287408B2 (en) | 2011-03-25 | 2016-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Field-effect transistor, and memory and semiconductor circuit including the same |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8422273B2 (en) * | 2009-05-21 | 2013-04-16 | International Business Machines Corporation | Nanowire mesh FET with multiple threshold voltages |
US8426923B2 (en) * | 2009-12-02 | 2013-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-gate semiconductor device and method |
US8753942B2 (en) | 2010-12-01 | 2014-06-17 | Intel Corporation | Silicon and silicon germanium nanowire structures |
KR20120125017A (en) * | 2011-05-06 | 2012-11-14 | 삼성전자주식회사 | Semiconductor device and method for fabricating the device |
US8969154B2 (en) * | 2011-08-23 | 2015-03-03 | Micron Technology, Inc. | Methods for fabricating semiconductor device structures and arrays of vertical transistor devices |
US8637931B2 (en) * | 2011-12-27 | 2014-01-28 | International Business Machines Corporation | finFET with merged fins and vertical silicide |
US8643120B2 (en) * | 2012-01-06 | 2014-02-04 | International Business Machines Corporation | FinFET with fully silicided gate |
US20130241007A1 (en) * | 2012-03-15 | 2013-09-19 | International Business Machines Corporation | Use of band edge gate metals as source drain contacts |
KR101909205B1 (en) * | 2012-04-20 | 2018-10-17 | 삼성전자 주식회사 | Semiconductor device including fin-type field effect transistor |
US8802535B2 (en) | 2012-05-02 | 2014-08-12 | International Business Machines Corporation | Doped core trigate FET structure and method |
KR101909091B1 (en) | 2012-05-11 | 2018-10-17 | 삼성전자 주식회사 | Semiconductor device and fabricating method thereof |
US8962434B2 (en) | 2012-07-10 | 2015-02-24 | International Business Machines Corporation | Field effect transistors with varying threshold voltages |
US9093556B2 (en) | 2012-08-21 | 2015-07-28 | Stmicroelectronics, Inc. | Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods |
US8999831B2 (en) | 2012-11-19 | 2015-04-07 | International Business Machines Corporation | Method to improve reliability of replacement gate device |
US9633835B2 (en) * | 2013-09-06 | 2017-04-25 | Intel Corporation | Transistor fabrication technique including sacrificial protective layer for source/drain at contact location |
EP3050088A4 (en) | 2013-09-25 | 2017-05-03 | Intel Corporation | Isolation well doping with solid-state diffusion sources for finfet architectures |
US9373720B2 (en) * | 2013-10-14 | 2016-06-21 | Globalfoundries Inc. | Three-dimensional transistor with improved channel mobility |
US9112030B2 (en) * | 2013-11-04 | 2015-08-18 | United Microelectronics Corp. | Epitaxial structure and process thereof for non-planar transistor |
US9219155B2 (en) * | 2013-12-16 | 2015-12-22 | Intel Corporation | Multi-threshold voltage devices and associated techniques and configurations |
US9590105B2 (en) * | 2014-04-07 | 2017-03-07 | National Chiao-Tung University | Semiconductor device with metal alloy over fin, conductive layer over channel region of fin, and semiconductive layer over conductive layer and formation thereof |
US9484205B2 (en) | 2014-04-07 | 2016-11-01 | International Business Machines Corporation | Semiconductor device having self-aligned gate contacts |
WO2016003602A1 (en) * | 2014-07-03 | 2016-01-07 | Applied Materials, Inc. | Method and apparatus for selective deposition |
US9484270B2 (en) | 2014-09-16 | 2016-11-01 | International Business Machines Corporation | Fully-depleted silicon-on-insulator transistors |
US9553092B2 (en) | 2015-06-12 | 2017-01-24 | Globalfoundries Inc. | Alternative threshold voltage scheme via direct metal gate patterning for high performance CMOS FinFETs |
WO2017052612A1 (en) | 2015-09-25 | 2017-03-30 | Intel Corporation | Methods of doping fin structures of non-planar transistor devices |
US9543297B1 (en) * | 2015-09-29 | 2017-01-10 | Globalfoundries Inc. | Fin-FET replacement metal gate structure and method of manufacturing the same |
US10290634B2 (en) | 2016-01-20 | 2019-05-14 | Globalfoundries Inc. | Multiple threshold voltages using fin pitch and profile |
US9806078B1 (en) * | 2016-11-02 | 2017-10-31 | Globalfoundries Inc. | FinFET spacer formation on gate sidewalls, between the channel and source/drain regions |
US10002791B1 (en) | 2017-04-06 | 2018-06-19 | International Business Machines Corporation | Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS |
US10522643B2 (en) * | 2017-04-26 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate |
US10886393B2 (en) * | 2017-10-17 | 2021-01-05 | Mitsubishi Electric Research Laboratories, Inc. | High electron mobility transistor with tunable threshold voltage |
US10446400B2 (en) | 2017-10-20 | 2019-10-15 | Samsung Electronics Co., Ltd. | Method of forming multi-threshold voltage devices and devices so formed |
US10461078B2 (en) * | 2018-02-26 | 2019-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Creating devices with multiple threshold voltage by cut-metal-gate process |
KR102481284B1 (en) * | 2018-04-10 | 2022-12-27 | 삼성전자주식회사 | A method of manufacturing semiconductor device |
US10985075B2 (en) | 2018-10-11 | 2021-04-20 | International Business Machines Corporation | Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5352624A (en) * | 1992-01-23 | 1994-10-04 | Sony Corporation | SOI type semiconductor device and manufacturing method therefor |
US6448590B1 (en) * | 2000-10-24 | 2002-09-10 | International Business Machines Corporation | Multiple threshold voltage FET using multiple work-function gate materials |
US20060289948A1 (en) * | 2005-06-22 | 2006-12-28 | International Business Machines Corporation | Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof |
Family Cites Families (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003124463A (en) * | 1994-09-14 | 2003-04-25 | Toshiba Corp | Semiconductor device |
US6146970A (en) * | 1998-05-26 | 2000-11-14 | Motorola Inc. | Capped shallow trench isolation and method of formation |
US6492212B1 (en) * | 2001-10-05 | 2002-12-10 | International Business Machines Corporation | Variable threshold voltage double gated transistors and method of fabrication |
US20030151077A1 (en) * | 2002-02-13 | 2003-08-14 | Leo Mathew | Method of forming a vertical double gate semiconductor device and structure thereof |
US6853020B1 (en) * | 2002-11-08 | 2005-02-08 | Advanced Micro Devices, Inc. | Double-gate semiconductor device |
US7388259B2 (en) * | 2002-11-25 | 2008-06-17 | International Business Machines Corporation | Strained finFET CMOS device structures |
US6720619B1 (en) * | 2002-12-13 | 2004-04-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices |
US6885055B2 (en) * | 2003-02-04 | 2005-04-26 | Lee Jong-Ho | Double-gate FinFET device and fabricating method thereof |
US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
EP1519420A2 (en) * | 2003-09-25 | 2005-03-30 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | Multiple gate semiconductor device and method for forming same |
JP4216676B2 (en) * | 2003-09-08 | 2009-01-28 | 株式会社東芝 | Semiconductor device |
US6855989B1 (en) * | 2003-10-01 | 2005-02-15 | Advanced Micro Devices, Inc. | Damascene finfet gate with selective metal interdiffusion |
KR100521384B1 (en) * | 2003-11-17 | 2005-10-12 | 삼성전자주식회사 | Method for fabricating a finfet in a semiconductor device |
US20070029623A1 (en) * | 2003-12-05 | 2007-02-08 | National Inst Of Adv Industrial Science And Tech | Dual-gate field effect transistor |
US7224029B2 (en) * | 2004-01-28 | 2007-05-29 | International Business Machines Corporation | Method and structure to create multiple device widths in FinFET technology in both bulk and SOI |
KR100574971B1 (en) | 2004-02-17 | 2006-05-02 | 삼성전자주식회사 | Semiconductor device having multi-gate structure and method of manufacturing the same |
US7332386B2 (en) * | 2004-03-23 | 2008-02-19 | Samsung Electronics Co., Ltd. | Methods of fabricating fin field transistors |
US7300837B2 (en) * | 2004-04-30 | 2007-11-27 | Taiwan Semiconductor Manufacturing Co., Ltd | FinFET transistor device on SOI and method of fabrication |
WO2005119532A2 (en) * | 2004-06-04 | 2005-12-15 | The Regents Of The University Of California | Low-power fpga circuits and methods |
US7348284B2 (en) * | 2004-08-10 | 2008-03-25 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
KR100598109B1 (en) * | 2004-10-08 | 2006-07-07 | 삼성전자주식회사 | Non-volatile memory devices and methods of the same |
KR100612419B1 (en) * | 2004-10-19 | 2006-08-16 | 삼성전자주식회사 | Semiconductor devices having a fin transistor and a plannar transistor and methods of forming the same |
US7288805B2 (en) * | 2005-02-24 | 2007-10-30 | International Business Machines Corporation | Double gate isolation |
KR100724563B1 (en) * | 2005-04-29 | 2007-06-04 | 삼성전자주식회사 | MOS transistors having a multi-work function metal nitride gate electrode, CMOS integrated circuit devices employing the same, and methods of fabricating the same |
US7382162B2 (en) * | 2005-07-14 | 2008-06-03 | International Business Machines Corporation | High-density logic techniques with reduced-stack multi-gate field effect transistors |
DE102005039365B4 (en) * | 2005-08-19 | 2022-02-10 | Infineon Technologies Ag | Gate-controlled fin resistive element operating as a pinch - resistor for use as an ESD protection element in an electrical circuit and a device for protecting against electrostatic discharges in an electrical circuit |
US20070048984A1 (en) * | 2005-08-31 | 2007-03-01 | Steven Walther | Metal work function adjustment by ion implantation |
US8188551B2 (en) * | 2005-09-30 | 2012-05-29 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
US7462538B2 (en) * | 2005-11-15 | 2008-12-09 | Infineon Technologies Ag | Methods of manufacturing multiple gate CMOS transistors having different gate dielectric materials |
JP2007165772A (en) * | 2005-12-16 | 2007-06-28 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
CN101375399B (en) * | 2006-01-30 | 2010-09-01 | Nxp股份有限公司 | MOS device and method of fabricating a MOS device |
JP2007207994A (en) * | 2006-02-01 | 2007-08-16 | Toshiba Corp | Semiconductor device manufacturing method |
US7354832B2 (en) * | 2006-05-03 | 2008-04-08 | Intel Corporation | Tri-gate device with conformal PVD workfunction metal on its three-dimensional body and fabrication method thereof |
US20080050898A1 (en) * | 2006-08-23 | 2008-02-28 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
KR100748261B1 (en) * | 2006-09-01 | 2007-08-09 | 경북대학교 산학협력단 | Fin field effect transistor haiving low leakage current and method of manufacturing the finfet |
US7700470B2 (en) * | 2006-09-22 | 2010-04-20 | Intel Corporation | Selective anisotropic wet etching of workfunction metal for semiconductor devices |
US20080111185A1 (en) * | 2006-11-13 | 2008-05-15 | International Business Machines Corporation | Asymmetric multi-gated transistor and method for forming |
US7678632B2 (en) * | 2006-11-17 | 2010-03-16 | Infineon Technologies Ag | MuGFET with increased thermal mass |
WO2008072164A1 (en) * | 2006-12-15 | 2008-06-19 | Nxp B.V. | Transistor device and method of manufacturing such a transistor device |
FR2910999B1 (en) * | 2006-12-28 | 2009-04-03 | Commissariat Energie Atomique | MEMORY CELL WITH DOUBLE-GRID TRANSISTORS, INDEPENDENT AND ASYMMETRIC GRIDS |
US7859081B2 (en) * | 2007-03-29 | 2010-12-28 | Intel Corporation | Capacitor, method of increasing a capacitance area of same, and system containing same |
US8124483B2 (en) * | 2007-06-07 | 2012-02-28 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
JP4459257B2 (en) * | 2007-06-27 | 2010-04-28 | 株式会社東芝 | Semiconductor device |
JP2009026997A (en) | 2007-07-20 | 2009-02-05 | Renesas Technology Corp | Semiconductor device, and manufacturing method thereof |
US20090134469A1 (en) * | 2007-11-28 | 2009-05-28 | Interuniversitair Microelektronica Centrum (Imec) Vzw | Method of manufacturing a semiconductor device with dual fully silicided gate |
US7781274B2 (en) * | 2008-03-27 | 2010-08-24 | Kabushiki Kaisha Toshiba | Multi-gate field effect transistor and method for manufacturing the same |
-
2009
- 2009-04-21 US US12/427,247 patent/US8110467B2/en active Active
-
2010
- 2010-04-14 TW TW099111648A patent/TWI476918B/en active
- 2010-04-15 EP EP10767544.9A patent/EP2396812B1/en active Active
- 2010-04-15 CN CN201080017383.3A patent/CN102405516B/en active Active
- 2010-04-15 WO PCT/US2010/031224 patent/WO2010123750A1/en active Application Filing
- 2010-04-15 JP JP2012507269A patent/JP5552155B2/en active Active
-
2012
- 2012-01-09 US US13/346,165 patent/US8878298B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5352624A (en) * | 1992-01-23 | 1994-10-04 | Sony Corporation | SOI type semiconductor device and manufacturing method therefor |
US6448590B1 (en) * | 2000-10-24 | 2002-09-10 | International Business Machines Corporation | Multiple threshold voltage FET using multiple work-function gate materials |
US6797553B2 (en) * | 2000-10-24 | 2004-09-28 | International Business Machines Corporation | Method for making multiple threshold voltage FET using multiple work-function gate materials |
US20060289948A1 (en) * | 2005-06-22 | 2006-12-28 | International Business Machines Corporation | Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof |
Non-Patent Citations (1)
Title |
---|
See also references of EP2396812A4 * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9287408B2 (en) | 2011-03-25 | 2016-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Field-effect transistor, and memory and semiconductor circuit including the same |
US9548395B2 (en) | 2011-03-25 | 2017-01-17 | Semiconductor Energy Laboratory Co., Ltd. | Field-effect transistor including oxide semiconductor, and memory and semiconductor circuit including the same |
US9859443B2 (en) | 2011-03-25 | 2018-01-02 | Semiconductor Energy Laboratory Co., Ltd. | Field-effect transistor, and memory and semiconductor circuit including the same |
CN102956496A (en) * | 2011-08-30 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Fin type field effect transistor and manufacturing method thereof |
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Publication number | Publication date |
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JP5552155B2 (en) | 2014-07-16 |
TWI476918B (en) | 2015-03-11 |
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TW201110347A (en) | 2011-03-16 |
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US20100264497A1 (en) | 2010-10-21 |
US8110467B2 (en) | 2012-02-07 |
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US20120175712A1 (en) | 2012-07-12 |
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