WO2010123573A1 - Channel-sensitive power control - Google Patents

Channel-sensitive power control Download PDF

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Publication number
WO2010123573A1
WO2010123573A1 PCT/US2010/001208 US2010001208W WO2010123573A1 WO 2010123573 A1 WO2010123573 A1 WO 2010123573A1 US 2010001208 W US2010001208 W US 2010001208W WO 2010123573 A1 WO2010123573 A1 WO 2010123573A1
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WO
WIPO (PCT)
Prior art keywords
signal
block
receiver
signal strength
signals
Prior art date
Application number
PCT/US2010/001208
Other languages
French (fr)
Inventor
James Qiu
Sridhar Ramesh
Sheng Ye
Curtis Ling
Original Assignee
Maxlinear, Inc.
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Publication date
Application filed by Maxlinear, Inc. filed Critical Maxlinear, Inc.
Publication of WO2010123573A1 publication Critical patent/WO2010123573A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
    • H04W52/0245—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal according to signal strength
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/109—Means associated with receiver for limiting or suppressing noise or interference by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the invention relates to an architecture and methods for a communication receiver to adjust consumed power according to the received signal condition, and more particularly to techniques and algorithms for controlling receiver performance and power consumption as a function of a number of receive signal factors.
  • Communication systems typically face a range of signal conditions, including communication channel quality as well as the transmitted modulation scheme and code rate which may vary with time and make the desired signal easier or harder to receive. These different conditions require different levels of performance for satisfactory reception of the signal; in well-designed systems, higher performance generally requires more power consumption.
  • Conventional communication systems do not account for these variations by trading off power consumption for system performance when the signal becomes easier to receive.
  • the minimum performance of the system required to receive the desired signal (“minimum required performance", or MRP) can vary quite a bit, depending on the aforementioned characteristics.
  • U.S. Patents and a U.S. Patent Application relating to the present invention are: [003]
  • U. S. Patent 7,457,607 (Krivokapic) teaches minimization of mobile station power consumption through dynamic optimization of amplifier linearity and frequency synthesizer single sideband phase noise across a wide range of input signal levels and gain settings.
  • U. S. Patent 7,229,021 (Parssinen et al.) describes an apparatus, a method and an algorithm for controlling the dynamic range of a radio receiver.
  • the invention provides a monitoring circuit and associated logic to control the dynamic range of a radio receiver based on several parameters making it possible to continuously optimize the receiver performance.
  • U. S. Patent Application 2008/0080597 (Rofougaran) teaches a radio transceiver that optimizes power consumption by selectively attenuated interferers. Optimizing power consumption involves comparing the transmit power level with two or thee thresholds. Depending on the outcome, the blocking circuit is either disabled, enabled or the system increases the linearity of the low noise amplifier, the blocking circuit and other parameters.
  • receiver performance parameters such as RF dynamic range, baseband dynamic range, channel equalization performance, system phase noise, and channel decoder performance.
  • It is a further object of the present invention is to include, in the reception of wireless signals in a mobile environment, signal processing in the receiver which counteracts the effects of changing channel conditions. [0012] It is yet a further object of the present invention is to gauge how much excess performance the system has over and above the minimum required performance.
  • It is still a further object of the present invention is to provide a feedback mechanism during the adjustment of the receiver performance parameters.
  • receiver front end circuit which processes the received signal and then passes it on to a signal strength detectors circuit which analyzes the signal strength.
  • the Receive Signal Factors estimator then processes that information and passes it on to the receiver performance parameters control which combines the information and adjusts the power consumption of the receiver front end circuits.
  • FIG. 1 is a block diagram of the channel-sensitive power control according to a preferred embodiment of the present invention.
  • FIG. 2 is a block diagram of the Receive Signal Factors estimator and Receiver Performance Parameter control blocks according to a preferred embodiment of the present invention.
  • FIG. 3a is a graph illustrating the computation for Mode QPSK of the present invention.
  • FIG. 3b is a graph illustrating the computation for Mode 16QAM of the present invention.
  • FIG. 4 is a graph illustrating the function of M4 of the present invention.
  • FIG. 5 is a graph illustrating the computation performed in M2 of a preferred embodiment of the present invention.
  • FIG. 6 is a flowchart illustrating the general operation of a preferred embodiment the present invention.
  • FIG. 7 is a block diagram of a first method of the present invention.
  • FIG. 8 is a block diagram of a second method of the present invention.
  • the goal of this invention is to optimize receiver power consumption as a function of signal conditions, adapting the receiver's performance (and hence its power consumption) when signal conditions make the desired signal easier or more difficult to receive.
  • the preferred embodiment of the present invention comprises a set of techniques and algorithms for controlling receiver performance and power consumption as a function of the following receive signal factors (which we refer to as "factors", or RSF):
  • Signal characteristics a. Modulation scheme being received, such as OFDM or 16QAM, b. Code rate received, such as convolutional coding or rate 2/3.
  • the receiver performance parameters (parameters", or RPP) that are traded off as the receive signal factors vary include the following:
  • Baseband dynamic range including signal path noise and bandwidth
  • the invention comprises a system for quantitatively estimating each of the factors, and a general algorithm for mapping these estimated factors to settings for the receiver performance parameters to minimize power under these conditions.
  • the Channel- Sensitive Power Control 10 comprises a Receiver Front End Fl (12) and a Back End Bl (14).
  • Receiver Front End Fl typically comprises blocks Ll, L2, L3, L4, and L5.
  • Back End Bl typically comprises blocks El, E2, and E3.
  • Ll is an amplifier which typically has low noise and variable gain. Ll may also perform filtering and attenuation functions.
  • L2 is a mixer for performing frequency conversion of the received signal.
  • L3 is a filter which may also have variable gain control.
  • L4 is a data converter to convert S3 from analog to digital domain.
  • L5 is a frequency synthesizer block.
  • E4 senses the signal levels out of each block Ll - L4. .
  • L1-L4 select a signal received by antenna Al, amplify, filter, frequency- convert, and data-convert the signal so that it can be demodulated or otherwise processed by other systems.
  • Signals received by antenna Al are passed on to a low-noise variable gain amplifier Ll of Fl .
  • Ll feeds via signal Sl the mixer L2,
  • L2 feeds via signal S2 the baseband amplifier L3, and L3 feeds via signal S3 the analog-to-digital converter (ADC) L4.
  • ADC analog-to-digital converter
  • the output of L4 is digital signal S4 named "received signal”.
  • Synthesizer L5 local oscillator LO
  • Signals Sl, S2, S3, and S4 feed the Signal Strength Detectors block E4.
  • Signal S4 also feeds RSF estimator El of Back End Bl. El also receives signal Dl (dashed lines) generated by E4.
  • El and Demodulator E2 are coupled via 2-way signal S6, El also feeds via signal bus D2 (dashed lines) the RPP Control E3.
  • Demodulator E2 and RPP Control E3 are coupled via 2-way signal D3 (dashed lines).
  • the output of RPP Control E3 couples to Receiver Front End Fl via block control signals Cl, C2, C3, C4, and C5 (dashed lines).
  • Signal Cl feeds Ll
  • signal C2 feeds L2
  • signal C3 feeds L3, signal C4 feeds L4, and signal C5 feeds L5.
  • RSF Receiver Performance Parameter
  • the RSF estimator (El) typically comprises, but is not limited to, blocks Al, A2, A3, and A4.
  • the RPP control (E3) typically comprises, but is not limited to, blocks Ml , M2,
  • Blocker discriminator Al receives signal Dl from Signal Strength Detectors block E4, as already mentioned above.
  • Blocker discriminator Al produces signal Yl .
  • Digital signal S4 from analog-to-digital converter (ADC) L4 is received (named “received signal") by: Doppler and Fading estimator A2, Received Signal Mode detection A3, and Signal Strength and SNR detection A4.
  • A2 generates signals Y2 and S6.
  • A3 generates signal Y3 and A4 generates signal Y4.
  • Signals Yl, Y2, Y3, and Y4 are part of signal bus D2.
  • Ml receives signals Yl and Y3 from Al and A3, respectively, and is coupled to M2, to M4 via signal Y6 and via 2- way signal D3 to Demodulator E2.
  • Ml is a map of signal mode, blocker amplitudes & locations to required linearity and synthesizer performance.
  • M2 receives signals Y2 and Y3 from A2 and A3, respectively, and is coupled to Ml as already mentioned.
  • M2 is a map of signal mode and channel quality to channel estimation performance requirements.
  • M3 receives signal Y3 and Y4 from A3 and A4, respectively, and sends signal Y5 to M4.
  • M3 is a map of SNR, signal strength and signal mode to the required sensitivity, i.e. of how sensitivity of the receiver varies with the power control of blocks Ll - L4.
  • M4 receives signals Y5 and Y6 from M3 and Ml, respectively, and generates block control signals Cl to C5.
  • M4 is a map of linearity and sensitivity requirements to signal
  • Fl comprises blocks Ll, L2, L3, L4 and L5 and represents the receiver front end signal path of a receiver connected to antenna Al .
  • Block L5 represents a frequency synthesizer block.
  • LO local oscillator
  • S5 a local oscillator
  • f L o which is the same frequency (fr f ) as the desired signal
  • L2 the mixer
  • This invention is of course not restricted to direct conversion receiver architectures but is shown here, by way of illustration and not of limitation.
  • Signals Sl, S2, S3 and S4 are sent to a Signal Strength Detectors block E4 which passes signal strength information via signal Dl to block Al of RSF estimator El.
  • the information contained in signal Dl is used by Al to calculate the frequency location and amplitude of interfering signals (blockers).
  • Al sends this frequency location and amplitude information via signal Yl to block Ml of the RPP control (E3), which uses this information to adjust the power consumption of the blocks in Receiver Front End Fl through signals C1-C5.
  • blockers When strong undesired signals (“blockers”), i.e. interfering signals, are present at frequencies close to the desired signal's frequency, more linearity is required. This can be achieved by increasing power to the system at certain locations in the signal path such as the mixer L2, low-noise amplifier Ll or baseband amplifiers L3.
  • the sensitivity of the system to these blockers is dependent on several factors: 1. Frequency locations of the blocker signals and their signal strengths. This is conveyed in signal Yl from block Al, the Blocker discriminator. 2. The modulation scheme and coding present in the desired signal (i.e. the mode of the system).
  • the Received Signal Mode detection which detects important characteristics in the received signal such as modulation order OFDM or 16QAM, the type of coding scheme used, such as convolutional coding or rate 2/3.
  • phase noise of the system which is typically limited by synthesizer L5.
  • the phase noise of L5 is typically optimized for other constraints like the total integrated phase noise, to improve received signal quality.
  • the level of the phase noise produced by synthesizer L5 far from fLo needs to be reduced to eliminate the well-known problem of reciprocal mixing.
  • Existing receivers do not control phase noise in response to blocker location.
  • the system adjusts the raw phase noise of synthesizer L5 in response to blocker levels and locations by, for example, adjusting VCO bias and swing using techniques known by those skilled in the art.
  • the system also can exercise the tradeoff of making phase noise close to f L o worse in order to improve phase noise far from f L o This can be achieved by adjusting the component values or bias levels in parts of synthesizer L5 in order to change the bandwidth of the loop filter in L5 in a manner well known by those skilled in the art of this field. 2. Determining Receiver Performance Settings
  • Fig. 3a and Fig. 3b are graphs illustrating examples of the computations performed in Ml for the signal path. Similar graphs exist for the synthesizer including VCO. These graphs may be implemented using an LUT or a mathematical model.
  • the horizontal axis gives the frequency of the blocker location, the vertical axis is a measure of the amplitude of the blocker. High power is Area 1, medium power is Area 2, and low power is Area 3.
  • Block Ml contains the algorithm that determines how to set the phase noise and linearity of the receiver front end given locations and levels of the blocker, and the modulation and coding scheme of the received signal, as discussed above. It feeds this setting requirement to block M4 by signal Y6.
  • Fig. 3a and Fig. 3b illustrate the computations that Ml implements; the example used has two modes: QPSK rate 2/3 for Fig. 3a, and 16QAM rate % for Fig. 3b. Theses graphs can be implemented using a lookup-table (LUT) or using equations based on a mathematical model of the receiver.
  • LUT lookup-table
  • Block A4 estimates the signal strength and signal to noise ratio (using well- known techniques such as signal strength detectors, or calculating and averaging the error vector magnitude of the received signal), and feeds this information to Block M3.
  • Fig. 4 is a graph illustrating an embodiment of the computations performed in M4, for one particular block control signal Cl. Each block has its own graph. This may be implemented using an LUT or a mathematical model, or by feedback mechanisms from the receiver. The origin of the horizontal axis is Low power, High power is to the right. The vertical axis displays the signal strength in dB, where Low signal strength is at the origin and High signal strength is at the top.
  • Curve 1 is a graph of the Noise figure
  • Curve 2 is a graph of the Linearity.
  • M3 receives the system BER/PER received from signal D3 and sends signal Y5 to M4 to reduce the power in all blocks fed by block control signal Ci (Cl to C5) until a target system BER/PER is achieved.
  • M3 is a simple feedback controller.
  • Signals C1-C5 control the noise figure, linearity, maximum signal swing, and phase noise of blocks L1-L5.
  • Block M4 obtains the required phase noise and linearity settings as well as the required SNR level and maps these (by a look-up table, for example) to actual block control signal settings C1-C5, which control blocks L1-L5.
  • Fig. 5 is a graph illustrating an embodiment of the computations performed in M2. . This may be implemented using an LUT or a mathematical model.
  • the horizontal axis indicates the Channel quality or Signal quality from Poor at the origin of the axis to Good at the right, the vertical axis is a measure of the Channel Estimation Activity starting from Low at the origin of the axis to High at the top.
  • Mode: 16QAM rate 3 A is represented by Curve 4.
  • Curve 4 In the reception of wireless signals in a mobile environment, it is desirable to include signal processing in the receiver, which counteracts the effects of the changing channel conditions.
  • Block A2 takes the received signal and estimates the Doppler frequency of the signal.
  • Block M2 uses this estimate Y2 together with modulation and coding scheme Y3, and an estimate of the signal quality such as can be obtained from commonly-available SNR estimators (signal Y4) or the BER/PER (via D3) from the demodulator to determine how frequently to perform functions such as updating channel estimation or equalization which consume power. This allows the system to reduce power consumption of the demodulator block E2 under low Doppler conditions, when the wireless channel is changing at a slow rate.
  • BER/PER (transmitted from the Demodulator E2 to the RPP control E3 via D3) is used in the following manner: 1. To gauge of how much excess performance the system has over and above the minimum required performance is the bit error rate or packet error rate of the system. i. If BER/PER is well below the system target level for a certain grade of performance, the receiver performance parameters can be adjusted to trade off BER/PER. 2. As a feedback mechanism during the adjustment of the RPP Control. i. If BER/PER is poor, E3 can combine BER/PER information together with blocker detection to adjust signals C1-C5 in a manner to minimize the BER/PER under the given channel conditions. ii. It achieves this BER/PER minimization using any number of standard search techniques that are already available.
  • Fig. 6 is an overall flowchart illustrating the general operation of a preferred embodiment of the present invention:
  • Block 1 determines the signal mode by sensing/demodulation or by a database
  • Block 2a senses the channel quality, for example Doppler and system BER/PER;
  • Block 2b senses blocker amplitudes and frequency offsets;
  • Block 3 sets the power mode for the signal path and synthesizer
  • Block 4 sets the Channel Estimation performance level, for example the frequency.
  • Block 4 feeds back to Blocks 2a and 2b.
  • Block 1 detects the presence and magnitude of blockers
  • Block 2 determines the sensitivity to frequency location and signal strength of blocker signals;
  • Block 3 estimates the changing channel and fading conditions;
  • Block 4 detects the signal to noise ratio and a signal strength of said desired signal
  • Block 5 detects the received modulation scheme and order and coding scheme and code rate
  • Block 6 optimizes the receiver power consumption based on processed information from steps l) to 5); and;
  • Block 7 adjusts the receiver performance parameters according to a system bit error rate or packet error rate.
  • Block 1 processes the incoming signal in a receiver front end circuit
  • Block 2 generates a digital signal from said processed incoming signal
  • Block 3 analyzes the processed incoming signals in a Signal Strength Detectors block;
  • Block 4 passes signal strength information and said digital signal to a back end circuit;
  • Block 5 processes the signal strength information and said digital signal in said back end circuit
  • Block 6 sends processed information from said back end circuit to said receiver front end circuit to optimize receiver power consumption of said receiver front end circuit as a function of said incoming signal conditions
  • Block 7 adjusts receiver performance parameters according to a system bit error rate or packet error rate.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
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Abstract

A communication receiver which applies signal processing for quantitatively estimating receive signal factors such as communication channel quality, signal characteristics, and overall system received bit error rate (BER)or packet error rate (PER) and which applies a general algorithm for mapping these estimated factors to control receiver performance and minimize power consumption.

Description

CHANNEL-SENSITIVE POWER CONTROL
BACKGROUND OF THE INVENTION
1. Field of the Invention
[001] The invention relates to an architecture and methods for a communication receiver to adjust consumed power according to the received signal condition, and more particularly to techniques and algorithms for controlling receiver performance and power consumption as a function of a number of receive signal factors.
2. Description of the Related Art [002] Communication systems typically face a range of signal conditions, including communication channel quality as well as the transmitted modulation scheme and code rate which may vary with time and make the desired signal easier or harder to receive. These different conditions require different levels of performance for satisfactory reception of the signal; in well-designed systems, higher performance generally requires more power consumption. Conventional communication systems do not account for these variations by trading off power consumption for system performance when the signal becomes easier to receive. In fact, the minimum performance of the system required to receive the desired signal ("minimum required performance", or MRP) can vary quite a bit, depending on the aforementioned characteristics.
U.S. Patents and a U.S. Patent Application relating to the present invention are: [003] U. S. Patent 7,457,607 (Krivokapic) teaches minimization of mobile station power consumption through dynamic optimization of amplifier linearity and frequency synthesizer single sideband phase noise across a wide range of input signal levels and gain settings.
[004] U. S. Patent 7,229,021 (Parssinen et al.) describes an apparatus, a method and an algorithm for controlling the dynamic range of a radio receiver. The invention provides a monitoring circuit and associated logic to control the dynamic range of a radio receiver based on several parameters making it possible to continuously optimize the receiver performance.
[005] U. S. Patent Application 2008/0080597 (Rofougaran) teaches a radio transceiver that optimizes power consumption by selectively attenuated interferers. Optimizing power consumption involves comparing the transmit power level with two or thee thresholds. Depending on the outcome, the blocking circuit is either disabled, enabled or the system increases the linearity of the low noise amplifier, the blocking circuit and other parameters.
[006] It should be noted that none of the above-cited examples of the related art provide the advantages of the below described invention.
SUMMARY OF THE INVENTION [007] It is an object of at least one embodiment of the present invention to provide for a communication receiver a system for quantitatively estimating each of receive signal factors , and a general algorithm for mapping these estimated receive signal factors to settings for receiver performance parameters to minimize power under these conditions.
[008] It is another object of the present invention to determine these receive signal factors such as communication channel quality, signal characteristics, and overall system received bit error rates or packet error rates.
[009] It is yet another object of the present invention to trade off, as the receive signal factors vary, receiver performance parameters such as RF dynamic range, baseband dynamic range, channel equalization performance, system phase noise, and channel decoder performance.
[0010] It is still another object of the present invention to provide more linearity when strong undesired signals ("blockers") are present at frequencies close to the desired signal's frequency.
[0011] It is a further object of the present invention is to include, in the reception of wireless signals in a mobile environment, signal processing in the receiver which counteracts the effects of changing channel conditions. [0012] It is yet a further object of the present invention is to gauge how much excess performance the system has over and above the minimum required performance.
[0013] It is still a further object of the present invention is to provide a feedback mechanism during the adjustment of the receiver performance parameters.
[0014] These and many other objects have been achieved by providing a receiver front end circuit which processes the received signal and then passes it on to a signal strength detectors circuit which analyzes the signal strength. The Receive Signal Factors estimator then processes that information and passes it on to the receiver performance parameters control which combines the information and adjusts the power consumption of the receiver front end circuits.
BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a block diagram of the channel-sensitive power control according to a preferred embodiment of the present invention.
[0016] FIG. 2 is a block diagram of the Receive Signal Factors estimator and Receiver Performance Parameter control blocks according to a preferred embodiment of the present invention. [0017] FIG. 3a is a graph illustrating the computation for Mode QPSK of the present invention.
[0018] FIG. 3b is a graph illustrating the computation for Mode 16QAM of the present invention.
[0019] FIG. 4 is a graph illustrating the function of M4 of the present invention.
[0020] FIG. 5 is a graph illustrating the computation performed in M2 of a preferred embodiment of the present invention.
[0021] FIG. 6 is a flowchart illustrating the general operation of a preferred embodiment the present invention.
[0022] FIG. 7 is a block diagram of a first method of the present invention.
[0023] FIG. 8 is a block diagram of a second method of the present invention.
Use of the same reference number and letters in different figures indicates similar or like elements.
DESCRIPTION OF THE PREFERRED EMBODIMENT [0024] The goal of this invention is to optimize receiver power consumption as a function of signal conditions, adapting the receiver's performance (and hence its power consumption) when signal conditions make the desired signal easier or more difficult to receive.
[0025] The preferred embodiment of the present invention comprises a set of techniques and algorithms for controlling receiver performance and power consumption as a function of the following receive signal factors (which we refer to as "factors", or RSF):
1. Communication channel quality a. Presence, magnitude, and specific frequency location of blockers, b. Doppler frequency, c. Fading conditions such as the presence of multipath, d. Signal to noise ratio and signal strength of the desired signal.
2. Signal characteristics a. Modulation scheme being received, such as OFDM or 16QAM, b. Code rate received, such as convolutional coding or rate 2/3.
3. Overall system received bit error rate (BER) or packet error rate (PER).
[0026] The receiver performance parameters ("parameters", or RPP) that are traded off as the receive signal factors vary include the following:
1. RF dynamic range,
2. Baseband dynamic range including signal path noise and bandwidth,
3. Channel equalization performance, 4. System phase noise,
5. Channel decoder performance.
[0027] The invention comprises a system for quantitatively estimating each of the factors, and a general algorithm for mapping these estimated factors to settings for the receiver performance parameters to minimize power under these conditions.
1. Presence, Magnitude, And Specific Frequency Location Of Blockers
[0028] In a preferred embodiment of the present invention as shown in Fig. 1, we describe an embodiment of the Channel-Sensitive Power Control 10. The Channel- Sensitive Power Control 10 comprises a Receiver Front End Fl (12) and a Back End Bl (14). Receiver Front End Fl typically comprises blocks Ll, L2, L3, L4, and L5. Back End Bl typically comprises blocks El, E2, and E3. Ll is an amplifier which typically has low noise and variable gain. Ll may also perform filtering and attenuation functions. L2 is a mixer for performing frequency conversion of the received signal. L3 is a filter which may also have variable gain control.
L4 is a data converter to convert S3 from analog to digital domain.
L5 is a frequency synthesizer block.
E4 senses the signal levels out of each block Ll - L4. . Together, L1-L4 select a signal received by antenna Al, amplify, filter, frequency- convert, and data-convert the signal so that it can be demodulated or otherwise processed by other systems. [0029] Signals received by antenna Al are passed on to a low-noise variable gain amplifier Ll of Fl . Ll feeds via signal Sl the mixer L2, L2 feeds via signal S2 the baseband amplifier L3, and L3 feeds via signal S3 the analog-to-digital converter (ADC) L4. The output of L4 is digital signal S4 named "received signal". Synthesizer L5 (local oscillator LO) couples via signal S5 to L2. Signals Sl, S2, S3, and S4 (dashed lines) feed the Signal Strength Detectors block E4. Signal S4 also feeds RSF estimator El of Back End Bl. El also receives signal Dl (dashed lines) generated by E4. El and Demodulator E2 are coupled via 2-way signal S6, El also feeds via signal bus D2 (dashed lines) the RPP Control E3. Demodulator E2 and RPP Control E3 are coupled via 2-way signal D3 (dashed lines). The output of RPP Control E3 couples to Receiver Front End Fl via block control signals Cl, C2, C3, C4, and C5 (dashed lines). Signal Cl feeds Ll, signal C2 feeds L2, signal C3 feeds L3, signal C4 feeds L4, and signal C5 feeds L5.
[0030] In a preferred embodiment of the present invention as shown in Fig. 2 and referring to the Receive Signal Factors estimator 20 and the Receiver Performance
Parameter control 22, respectively, we describe embodiments of the Receive Signal
Factors (RSF) estimator El and the Receiver Performance Parameter (RPP) control E3.
The RSF estimator (El) typically comprises, but is not limited to, blocks Al, A2, A3, and A4. The RPP control (E3) typically comprises, but is not limited to, blocks Ml , M2,
M3 and M4. [0031] Referring to Receive Signal Factors estimator 20, Blocker discriminator Al receives signal Dl from Signal Strength Detectors block E4, as already mentioned above.
Blocker discriminator Al produces signal Yl . Digital signal S4 from analog-to-digital converter (ADC) L4 is received (named "received signal") by: Doppler and Fading estimator A2, Received Signal Mode detection A3, and Signal Strength and SNR detection A4. A2 generates signals Y2 and S6. A3 generates signal Y3 and A4 generates signal Y4. Signals Yl, Y2, Y3, and Y4 are part of signal bus D2.
[0032] Referring to Receiver Performance Parameter control 22 and blocks Ml, M2, M3, and M4.
Ml receives signals Yl and Y3 from Al and A3, respectively, and is coupled to M2, to M4 via signal Y6 and via 2- way signal D3 to Demodulator E2. Ml is a map of signal mode, blocker amplitudes & locations to required linearity and synthesizer performance.
M2 receives signals Y2 and Y3 from A2 and A3, respectively, and is coupled to Ml as already mentioned. M2 is a map of signal mode and channel quality to channel estimation performance requirements.
M3 receives signal Y3 and Y4 from A3 and A4, respectively, and sends signal Y5 to M4.
M3 is a map of SNR, signal strength and signal mode to the required sensitivity, i.e. of how sensitivity of the receiver varies with the power control of blocks Ll - L4. M4 receives signals Y5 and Y6 from M3 and Ml, respectively, and generates block control signals Cl to C5. M4 is a map of linearity and sensitivity requirements to signal
Cl to C5 settings. [0033] Providing a more detailed description we again refer to Figs. 1 and 2. Fl comprises blocks Ll, L2, L3, L4 and L5 and represents the receiver front end signal path of a receiver connected to antenna Al . Block L5 represents a frequency synthesizer block. In a direct conversion receiver, it generates a local oscillator (LO) signal S5 at a frequency fLo which is the same frequency (frf) as the desired signal, and sends the signal to the mixer (L2) which downconverts the desired signal to baseband (zero-IF) to facilitate filtering and demodulation. This invention is of course not restricted to direct conversion receiver architectures but is shown here, by way of illustration and not of limitation. Signals Sl, S2, S3 and S4 are sent to a Signal Strength Detectors block E4 which passes signal strength information via signal Dl to block Al of RSF estimator El. The information contained in signal Dl is used by Al to calculate the frequency location and amplitude of interfering signals (blockers). Al sends this frequency location and amplitude information via signal Yl to block Ml of the RPP control (E3), which uses this information to adjust the power consumption of the blocks in Receiver Front End Fl through signals C1-C5.
[0034] When strong undesired signals ("blockers"), i.e. interfering signals, are present at frequencies close to the desired signal's frequency, more linearity is required. This can be achieved by increasing power to the system at certain locations in the signal path such as the mixer L2, low-noise amplifier Ll or baseband amplifiers L3. The sensitivity of the system to these blockers is dependent on several factors: 1. Frequency locations of the blocker signals and their signal strengths. This is conveyed in signal Yl from block Al, the Blocker discriminator. 2. The modulation scheme and coding present in the desired signal (i.e. the mode of the system).
This is conveyed in signal Y3 from block A3, the Received Signal Mode detection, which detects important characteristics in the received signal such as modulation order OFDM or 16QAM, the type of coding scheme used, such as convolutional coding or rate 2/3.
[0035] A second consideration is the phase noise of the system, which is typically limited by synthesizer L5. In the absence of blockers, the phase noise of L5 is typically optimized for other constraints like the total integrated phase noise, to improve received signal quality. In the presence of blockers, the level of the phase noise produced by synthesizer L5 far from fLo needs to be reduced to eliminate the well-known problem of reciprocal mixing. Existing receivers do not control phase noise in response to blocker location. This invention introduces the following algorithm innovations:
1. The system adjusts the raw phase noise of synthesizer L5 in response to blocker levels and locations by, for example, adjusting VCO bias and swing using techniques known by those skilled in the art.
2. The system also can exercise the tradeoff of making phase noise close to fLo worse in order to improve phase noise far from fLo This can be achieved by adjusting the component values or bias levels in parts of synthesizer L5 in order to change the bandwidth of the loop filter in L5 in a manner well known by those skilled in the art of this field. 2. Determining Receiver Performance Settings
[0036] We now refer to Fig. 3a and Fig. 3b, which are graphs illustrating examples of the computations performed in Ml for the signal path. Similar graphs exist for the synthesizer including VCO. These graphs may be implemented using an LUT or a mathematical model. The horizontal axis gives the frequency of the blocker location, the vertical axis is a measure of the amplitude of the blocker. High power is Area 1, medium power is Area 2, and low power is Area 3.
[0037] Block Ml contains the algorithm that determines how to set the phase noise and linearity of the receiver front end given locations and levels of the blocker, and the modulation and coding scheme of the received signal, as discussed above. It feeds this setting requirement to block M4 by signal Y6. Fig. 3a and Fig. 3b illustrate the computations that Ml implements; the example used has two modes: QPSK rate 2/3 for Fig. 3a, and 16QAM rate % for Fig. 3b. Theses graphs can be implemented using a lookup-table (LUT) or using equations based on a mathematical model of the receiver.
[0038] Block A4 estimates the signal strength and signal to noise ratio (using well- known techniques such as signal strength detectors, or calculating and averaging the error vector magnitude of the received signal), and feeds this information to Block M3. Fig. 4 is a graph illustrating an embodiment of the computations performed in M4, for one particular block control signal Cl. Each block has its own graph. This may be implemented using an LUT or a mathematical model, or by feedback mechanisms from the receiver. The origin of the horizontal axis is Low power, High power is to the right. The vertical axis displays the signal strength in dB, where Low signal strength is at the origin and High signal strength is at the top. Curve 1 is a graph of the Noise figure, Curve 2 is a graph of the Linearity.
[0039] In one preferred embodiment, M3 receives the system BER/PER received from signal D3 and sends signal Y5 to M4 to reduce the power in all blocks fed by block control signal Ci (Cl to C5) until a target system BER/PER is achieved. In this embodiment M3 is a simple feedback controller.
[0040] Signals C1-C5 control the noise figure, linearity, maximum signal swing, and phase noise of blocks L1-L5. Block M4 obtains the required phase noise and linearity settings as well as the required SNR level and maps these (by a look-up table, for example) to actual block control signal settings C1-C5, which control blocks L1-L5.
3. Doppler and Fading Conditions [0041] We next refer to Fig. 5, which is a graph illustrating an embodiment of the computations performed in M2. . This may be implemented using an LUT or a mathematical model. The horizontal axis indicates the Channel quality or Signal quality from Poor at the origin of the axis to Good at the right, the vertical axis is a measure of the Channel Estimation Activity starting from Low at the origin of the axis to High at the top. Mode: QPSK r=2/3 is represented by Curve 3, Mode: 16QAM rate 3A is represented by Curve 4. [0042] In the reception of wireless signals in a mobile environment, it is desirable to include signal processing in the receiver, which counteracts the effects of the changing channel conditions. The rate at which these changes occur is technically referred to as the Doppler frequency. Block A2 takes the received signal and estimates the Doppler frequency of the signal. Block M2 uses this estimate Y2 together with modulation and coding scheme Y3, and an estimate of the signal quality such as can be obtained from commonly-available SNR estimators (signal Y4) or the BER/PER (via D3) from the demodulator to determine how frequently to perform functions such as updating channel estimation or equalization which consume power. This allows the system to reduce power consumption of the demodulator block E2 under low Doppler conditions, when the wireless channel is changing at a slow rate.
4. Bit Error Rate (BER)/Packet Error Rate (PER)
[0043] In a preferred embodiment of the present invention, BER/PER (transmitted from the Demodulator E2 to the RPP control E3 via D3) is used in the following manner: 1. To gauge of how much excess performance the system has over and above the minimum required performance is the bit error rate or packet error rate of the system. i. If BER/PER is well below the system target level for a certain grade of performance, the receiver performance parameters can be adjusted to trade off BER/PER. 2. As a feedback mechanism during the adjustment of the RPP Control. i. If BER/PER is poor, E3 can combine BER/PER information together with blocker detection to adjust signals C1-C5 in a manner to minimize the BER/PER under the given channel conditions. ii. It achieves this BER/PER minimization using any number of standard search techniques that are already available.
5. Summary [0044] Fig. 6 is an overall flowchart illustrating the general operation of a preferred embodiment of the present invention:
Block 1 determines the signal mode by sensing/demodulation or by a database;
Block 2a senses the channel quality, for example Doppler and system BER/PER; Block 2b senses blocker amplitudes and frequency offsets;
Block 3 sets the power mode for the signal path and synthesizer;
Block 4 sets the Channel Estimation performance level, for example the frequency.
The output of Block 4 feeds back to Blocks 2a and 2b.
[0045] We now describe a first method of optimizing receiver power consumption of the preferred embodiment of the present invention with reference to the block diagram of Fig. 7:
Block 1 detects the presence and magnitude of blockers;
Block 2 determines the sensitivity to frequency location and signal strength of blocker signals; Block 3 estimates the changing channel and fading conditions;
Block 4 detects the signal to noise ratio and a signal strength of said desired signal;
Block 5 detects the received modulation scheme and order and coding scheme and code rate;
Block 6 optimizes the receiver power consumption based on processed information from steps l) to 5); and;
Block 7 adjusts the receiver performance parameters according to a system bit error rate or packet error rate.
[0046] Next we describe a second method of optimizing receiver power consumption of the preferred embodiment of the present invention with reference to the block diagram of Fig. 8:
Block 1 processes the incoming signal in a receiver front end circuit;
Block 2 generates a digital signal from said processed incoming signal;
Block 3 analyzes the processed incoming signals in a Signal Strength Detectors block; Block 4 passes signal strength information and said digital signal to a back end circuit;
Block 5 processes the signal strength information and said digital signal in said back end circuit;
Block 6 sends processed information from said back end circuit to said receiver front end circuit to optimize receiver power consumption of said receiver front end circuit as a function of said incoming signal conditions; and
Block 7 adjusts receiver performance parameters according to a system bit error rate or packet error rate. [0047] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
What is claimed is:

Claims

1. An architecture for a channel-sensitive power control, said architecture comprising: a Receiver Front End, for receiving an incoming signal from a communication channel and for processing said incoming signal in a plurality of circuits to determine communication channel quality, signal characteristics and overall system received bit error rate/packet error rate, and generating a digital signal;
Signal Strength Detectors for receiving signals from said plurality of circuits, said signal strength detectors sensing the signal strength of each of said signals and generating signal strength information; and
a Back End for estimating receive signal factors based on said signal strength information, and for mapping via an algorithm said receive signal factors and sending control signals based on said receive signal factors to said receiver for optimizing power consumption of said receiver front end.
2. The architecture of claim 1, wherein said Receiver Front End is coupled to an antenna and where said plurality of circuits further comprises:
an amplifier coupled to said antenna, to provide an amplified incoming signal;
a mixer coupled to said amplifier, to perform a frequency conversion of said amplified incoming signal; a baseband amplifier coupled to said mixer, to filter out and amplify signals of the desired frequency spectrum;
an analog-to-digital converter coupled to said baseband amplifier, to convert said signals of the desired frequency spectrum from the analog to the digital domain, to generate said digital signal; and
a frequency synthesizer block, coupled to said mixer, to generate a local oscillator signal for said mixer.
3. The architecture of claim 1, wherein said Signal Strength Detectors receive the output signals of said amplifier, said mixer, said baseband amplifier, and said analog-to-digital converter, said signal strength detectors detecting the signal strength of said output signals.
4. The architecture of claim 1, wherein said Back End further comprises: a Receive Signal Factors estimator providing a blocker discriminator, Block Al, to calculate the frequency location and amplitude of interfering signals; a Doppler and fading estimator, Block A2, to estimate the Doppler frequency of said digital signal; received signal mode detection, Block A3, to detect characteristics in said digital signal such as modulation order and the type of coding scheme used; signal strength and signal to noise ratio (SNR) detection, Block A4, to estimate the signal strength and signal to noise ratio; and a Receiver Performance Parameter control receiving signals from said Receive Signal Factors estimator and providing: a map of signal mode, blocker amplitudes and locations to required linearity and synthesizer performance, Block Ml : a map of signal mode and channel quality to channel estimation performance requirements, Block M2; a map of signal to noise ratio, signal strength and signal mode to required sensitivity, Block M3; . a map of linearity and sensitivity requirements, Block M4; and a Demodulator to transmit a bit error rate/packet error rate (BER/PER) to said Receiver Performance Parameter control.
5. The architecture of claim 4, wherein said block discriminator, Block Al , receives said signal strength information and said digital signal.
6. The architecture of claim 4, wherein said Doppler and fading estimator, Block A2, receives said digital signal and estimates fading conditions such as the presence of multipath.
7. The architecture of claim 4, wherein said received signal mode detection, Block A3, receives said digital signal.
8. The architecture of claim 4, wherein said signal strength and signal to noise ratio detection, Block A4, receives said digital signal.
9. The architecture of claim 4, wherein said Block Ml receives signals from said blocker discriminator, Block Al, and said Doppler and fading estimator, Block A2, where said Block Ml contains an algorithm that determines how to set phase noise and linearity of said receiver front end and modulation and coding scheme of said digital signal.
10. The architecture of claim 4, wherein said Block M2 receives signals from said blocker discriminator, Block A2, and said received signal mode detection, Block A3, where said Block M2 determines how frequently to perform the functions of updating channel estimation or equalization.
1 1. The architecture of claim 4, wherein said Block M3 receives signal inputs from said received signal mode detection, Block A3, and said signal strength and signal to noise ratio detection, Block A4, where said Block M3 maps these signal inputs to a required signal to noise ratio SNR level for demodulation.
12. The architecture of claim 4, wherein said Block M4 receives signals from said Block Ml and Block M3 and where said Block M4 obtains required phase noise settings, linearity settings, and a required SNR level and maps these said settings and said SNR level to signals to control said receiver front end.
13. The architecture of claim 4, wherein said demodulator is in communication with said Block Ml and receives signals from said Block M3.
14. A method for optimizing receiver power consumption as a function of receive signal factors, comprising: a) detecting presence of blockers; b) detecting magnitude of said blockers; c) determine sensitivity to frequency location and signal strength of blocker signals; d) estimating changing channel and fading conditions; e) detecting a signal to noise ratio and a signal strength of a desired signal; f) detecting received modulation scheme and order, such as OFDM or 16QAM; g) detecting received coding scheme and code rate, such as convolutional coding or rate 2/3; h) optimizing receiver power consumption based on processed information from steps a) to g); and i) adjusting receiver performance parameters according to a system bit error rate/packet error rate .
15. A method for optimizing receiver power consumption as a function of signal conditions, comprising the steps of: a) processing an incoming signal in a receiver front end circuit; b) generating a digital signal in the receiver front end circuit; c) analyzing said processed incoming signals in a Signal Strength Detectors block; d) passing signal strength information and said digital signal to a back end circuit; e) processing said signal strength information and said digital signal in said back end circuit; f) sending processed information from said back end circuit to said receiver front end circuit to optimize receiver power consumption of said receiver front end circuit as a function of said incoming signal conditions; and g) adjusting receiver performance parameters according to a system bit error rate/packet error rate.
16. The method of claim 15, wherein said receiver front end comprises a low-noise variable gain amplifier.
17. The method of claim 15, wherein said receiver front end comprises a mixer coupled to a local oscillator.
18. The method of claim 15, wherein said receiver front end comprises a baseband amplifier.
19. The method of claim 15, wherein said receiver front end comprises an analog-to- digital converter.
20. The method of claim 15, wherein said back end circuit comprises a Receive Signal Factors estimator which calculates the frequency location and amplitude of interfering signals and passes that information on to a Receiver Performance Parameters control.
21. The method of claim 20, wherein the sensitivity of said receiver front end to said interfering signals depends on the frequency location, frequency amplitude, and signal strength of said interfering signals.
22. The method of claim 20, wherein the sensitivity of said receiver front end to said interfering signals depends on the modulation scheme and coding in the desired signal.
23. The method of claim 15, wherein said back end circuit comprises a Receiver Performance Parameters control which uses frequency location and amplitude information of interfering signals to adjust the power consumption of components of the receiver front end circuit.
24. A method for optimizing receiver power consumption as a function of receive signal conditions, comprising the steps of: a) processing a signal in a receiver front end circuit, further comprising the components: I a variable gain amplifier; II a mixer coupled to a local oscillator;
III a filter; and
IV an analog-to-digital-converter providing a digital signal; b) sending a signal from said variable gain amplifier to a Signal Strength Detectors block; c) sending a signal from said mixer to said Signal Strength Detectors block; d) sending a signal from the filter to said Signal Strength Detectors block; e) sending said digital signal from said analog-to-digital-converter to said Signal Strength Detectors block; f) passing signal strength information from said Signal Strength Detectors block and said digital signal to a Receive Signal Factors estimator in a back end circuit; g) calculating the frequency location and amplitude of interfering signals in said Receive Signal Factors estimator; and h) using frequency location and amplitude information in a Receiver Performance
Parameters control of said back end circuit to adjust the power consumption of the components of said receiver front end circuit of steps I to FV.
25. The method of claim 24, wherein said Receive Signal Factors estimator further comprises: a) a Blocker discriminator to calculate the frequency location and amplitude of interfering signals; b) a Doppler and fading estimator to take the received digital signal and estimate the
Doppler frequency of the digital signal; c) a Received signal mode detection block to detect characteristics in the received signal such as modulation order and the type of coding scheme used; and d) Signal strength and signal to noise ratio detection block to estimate signal strength and signal to noise ratio.
26. The method of claim 24, wherein said Receiver Performance Parameters control further comprises: a) a map of signal mode, blocker amplitudes and locations to required linearity and synthesizer performance, Block Ml, where said Block Ml contains an algorithm which determines how to set phase noise and linearity of said receiver front end circuit and modulation and coding scheme of said digital signal; b) a map of signal mode and channel quality to channel estimation performance requirements, Block M2, where said Block M2 determines how frequently to perform the functions of updating channel estimation or equalization; c) a map of signal inputs comprising: signal to noise ratio, signal strength and signal mode to required sensitivity, Block M3; where said Block M3 maps these signal inputs to a required signal to noise ratio SNR level for demodulation; and d) a map of linearity and sensitivity requirements, Block M4, where said Block M4 obtains required phase noise settings, linearity settings, and a required SNR level and maps these said settings and said SNR level to signals to control said receiver front end circuit.
27. The method of claim 26, wherein said algorithm is a look-up table.
28. A method for optimizing receiver power consumption as a function of signal conditions, comprising the steps of: a) determining the signal mode by sensing/demodulation or by a database; b) sensing the channel quality, blocker amplitudes and frequency offsets; c) setting the power mode for the signal path and synthesizer; d) setting the Channel Estimation performance level; and e) repeating steps b) through d).
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US20180262990A1 (en) 2018-09-13
US20150023237A1 (en) 2015-01-22
US8798211B2 (en) 2014-08-05
US20170311263A1 (en) 2017-10-26
US20130216009A1 (en) 2013-08-22
US8442154B2 (en) 2013-05-14
US9609599B2 (en) 2017-03-28
US9974025B2 (en) 2018-05-15
US20100296567A1 (en) 2010-11-25
US10645653B2 (en) 2020-05-05
TW201101712A (en) 2011-01-01

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