WO2010116402A1 - Information processor - Google Patents

Information processor Download PDF

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Publication number
WO2010116402A1
WO2010116402A1 PCT/JP2009/001464 JP2009001464W WO2010116402A1 WO 2010116402 A1 WO2010116402 A1 WO 2010116402A1 JP 2009001464 W JP2009001464 W JP 2009001464W WO 2010116402 A1 WO2010116402 A1 WO 2010116402A1
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WO
WIPO (PCT)
Prior art keywords
data
memory area
update information
virtual machine
information
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PCT/JP2009/001464
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French (fr)
Japanese (ja)
Inventor
稲垣淳一
大塚裕朗
Original Assignee
富士通株式会社
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Priority to PCT/JP2009/001464 priority Critical patent/WO2010116402A1/en
Publication of WO2010116402A1 publication Critical patent/WO2010116402A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Abstract

Provided is an information processor equipped with a virtual information processor implementation means that implements one or more virtual information processors by managing hardware resources; a data transmission means that transmits data directly from an input-output device that controls data input-output with an external device to the first memory area assigned to the virtual information processor, by converting an address in a first memory area assigned virtually to a virtual information processor to an address in a second memory area that is the real memory of the first memory area; a transmitted data detection means that detects data directly transmitted from the input-output device to the first memory area assigned to the virtual information processor; an update information registration means that generates update information pertaining to the first memory area which is modified by the data detected with the transmitted data detecting means, and stores the update information in an update information storage means; and an update information output means that outputs the update information stored with the update information storage means.

Description

The information processing apparatus

The present invention relates to an information processing apparatus for realizing one or more virtual machines.

Conventionally, a plurality of VM on the server as an information processing apparatus: a server virtualization technique for operating a virtual server called a (Virtual Machine virtual machine) is known.
Figure 1 is a diagram showing an outline of server virtualization technology.

In the server 101, it is running software called VMM (Virtual Machine Monitor) 102. This VMM102 a memory or IO server 101: Manage hardware resources for such (Input / Output O). Also, VMM 102 provides hardware resources required by each VM for each VM # 0 ~ # 2 emulates to.

When operating the plurality of VM, a plurality of VM is to not use duplicate storage area at the same address in the physical memory provided in the server 101, the exclusive control of the memory is performed. This exclusive control is performed by the memory management of VMM 102.

Figure 2 is a diagram showing an overview of the memory management by VMM 102.
VM recognizes the memory is referred to as a guest physical memory. The guest physical memory is grasped as contiguous memory area from VM. On the other hand, the guest physical memory when viewed from VM102 is grasped as separate memory space exists for each VM.

Figure 2 shows a guest physical memory when the two VM the VM # 0 and VM # 1 is running on VMM 102. In this case, two guest physical memory of the guest physical memory # 1 of guest physical memory # 0 and VM # 1 VM # 0 is present.

For example, the address X is present one each guest physical memory # 0 and # 1. Real memory provided this address X as the server 101, i.e. a contention occurs allocated to host physical memory.

Therefore, VMM 102 assigns the address X of the guest physical memory # 0 to address Z of the host physical memory, allocates the guest physical memory # 1 address X to address Y of the host physical memory. Thus, VMM 102, by assigning the host physical memory on separate host physical memory to avoid memory conflicts.

VM is also required similar memory management when starting a DMA (Direct Memory Access).
For example, VM # 0 is, by the DMA transfer, consider the case of writing data to the address X of the guest physical memory # 0. Incidentally, to write the data in a predetermined memory area by the DMA transfer of "DMA Write". In addition, the memory address indicating the write destination of the data by the DMA transfer of "DMA address".

In this case, when the VM # 0 is set to the address X as a DMA address to the IO adapter, DMA write is performed to the address X of the host physical memory. Address X of the host physical memory for the address X of the guest physical memory # 0 is independent of the memory area, memory corruption is caused. When the memory corruption is caused, the panic occurred in the system, then the system is stopped.

Therefore, execution of the DMA write by VM # 0 is performed in the following procedure.
(1) VM # 0 in the IO adapter, to request the DMA write to the address X of the guest physical memory # 0.
(2) VMM 102 traps the request for DMA write VM # 0, it converts the address X of the guest physical memory # 0 to address W in the buffer area of ​​the host physical memory. Then, VMM 102 sets the translated address W in the DMA address setting register of the IO adapter.
(3) VM # 0 instructs the DMA start the IO adapter.
(4) IO adapter performs DMA write to the address W.
(5) When the DMA write is complete, IO adapter notifies the completion of the DMA write by the DMA completion interrupt.
(6) VMM 102 copies the data stored in the address W of the host physical memory address X of the guest physical memory # 0.
(7) VMM 102 notifies the completion of the DMA write to the VM # 0 by the DMA completion interrupt.
(8) VM # 0 extracts the data from the address X of the guest physical memory # 0.

One of the functions related to server virtualization is a technique that live migration (Live Migration). The A live migration, the VM running on one server, a technique for shifting the operation without stopping the operation to another server.

FIG. 3 is a diagram showing the outline of live migration.
Live migration, as shown in FIG. 3, the two servers # 0 and # 1, and server # 0 and # storage 320 1 shares, with the network 330 that the server # 0 and # 1 are connected, the it is possible to perform in comprising environment. Live migration is performed in the following procedure.
(1) VMM311 operating at the destination server # 1, is prepared VM312.
(2) in a state in which the movement source VM302 continues business, mobile source VMM301 transfers the memory contents transfer source VM302 is using the destination VM 310. This process is referred to as a "pre-copy".
(3) business of the moving source VM302 temporarily stopped, the moving source VMM301 transfers the memory contents transfer source VM302 is using the destination VM 310. This process is referred to as a "stop-and-copy".
(4) in accordance with an instruction from the destination VMM311, destination VM312 resume operations.

As described above, the memory copy of such pre-copy or stop-and-copy all VMM performs. The VMM is can execute memory copy, because the VMM manages the host physical memory.

VMM also interposed the DMA write not only write process from a CPU (Central Processing Unit) to the host physical memory, detects a change amount of the memory data of the migration source VM.

There is a technique that IOMMU (Input / Output Memory Management Unit) as IO virtualization technology. This IOMMU is a technology to increase the speed by reducing the overhead of memory access by VMM intervention as described above.

IOMMU is connected to the IO adapter and the host physical memory is a memory management unit for performing the conversion of the guest physical memory addresses and host physical memory addresses.
Implementing IOMMU, as shown in FIG. 4, it is possible to perform a direct DMA from the IO device to the VM's guest physical memory. Using this technique, when access to the guest physical memory by DMA, there is no need VMM mediated. Also, VMM host physical memory - not necessary to perform data copy between the guest physical memory.

In conjunction with the above techniques, it is known for the bridge for a multi-processor system comprising a dirty RAM mechanism in which a predetermined value is set when the memory area is written by the DMA access.

Also, eliminating the complexity of reconfiguration of the configuration of the time of the virtual machine movement, known for virtual machine control method for improving the availability of the system by making the movement of the virtual machine and the virtual machine control program, a copy or save there.

Further, in order to allow the migration of data between physical pages to receive an access by physical I / O adapters, known mechanism for temporarily stopping the DMA operation which has been selected in the physical I / O adapter.

At least one host processor, are known for the virtualization system of the host computer and a system resources including memory, which is divided into a user memory with lower privileges and system memory with the highest privileges.
JP 2002-518734 JP JP 2006-072591 JP JP 2007-287140 JP JP 2007-510198 JP

As described above, the use of IOMMU, VMM would not interposed during DMA access. In this case, VMM is, can not grasp the update of the guest physical memory by the DMA write, VMM is not able to perform memory copy correctly. Therefore, there is a problem that can not be realized live migration and IOMMU use.

This information processing apparatus has been made in view of the above problem, the problem to be its solution is to provide an information processing apparatus that can execute the live migration even when using a IOMMU it is.

In order to solve the above problem, the information processing apparatus comprises the following means.
Virtual Machine means for realizing, by managing the hardware resources, realizes one or more virtual machines.

Data transfer means converts the address of the first memory area allocated to the virtual machine, and the address of the second memory area is a real memory of the first memory area, to each other and. Then, the data transfer means performs direct data transfer to the first memory region from the input-output device allocated to the virtual machine that controls input and output of data with an external device.

Transferring data detecting means detects the data directly is data transferred to said first memory area allocated to the virtual machine from the input device.
Update information registration unit generates updating information on the first memory area to be changed by the data detected by said transfer data detecting means, for storing the update information in the update information storage unit.

Update information output means outputs the update information stored in the update information storage unit.
According to the information processing apparatus, a virtual machine, when a direct data transfer from the external device to the first memory area by using the data transfer means, the first memory change information registration unit, which is changed by the data transfer storing information about the area in the update information storage unit. The update information output means outputs the update information stored in the update information output means.

According to the information processing apparatus described above, it becomes possible to perform a live migration even when using a IOMMU.

Is a diagram showing an overview of server virtualization technology. Is a diagram showing an overview of the memory management by VMM. Is a diagram showing the outline of live migration. It is a diagram for explaining IOMMU. It is a diagram illustrating a configuration example of an information processing apparatus. It is a diagram illustrating the operation of the DMA process in the north bridge. Is a diagram illustrating the operation of the DMA process in the PCIe switch. It is a diagram showing a configuration example of a FIFO # 0. It is a diagram illustrating a configuration example of the header of the DMA packet. It is a flowchart of a process of registering dirty page information by the dirty page management unit. It is a flowchart illustrating the output processing of the dirty page information by the dirty page management unit. Is a diagram illustrating an outline of live migration according to this embodiment. Is a flowchart showing the outline of live migration according to this embodiment. Is a flowchart showing the specific processing of the pre-copy. It is a flowchart illustrating a specific process of the stop-and-copy.

Hereinafter, an example of the present embodiment will be described with reference to FIGS. 5 to 15.
(Information processing apparatus according to the present embodiment)
Figure 5 is a diagram showing a configuration example of an information processing apparatus 500.

The information processing apparatus 500 includes a CPU510 and 511 as an arithmetic processing unit, a memory 520 serving as a main memory, a north bridge 530 as a memory controller, a. The information processing apparatus 500 includes a IO adapters 540 and 541 and 542 of the output control device, a PCIe switch (PCI Express Switch) 550, a.

CPU510 and 511 is a processing unit for executing a program developed in the memory 520. CPU510 and 511, by executing a predetermined program, realizing the virtualization server. Also, CPU 510 and 511, by executing the like storage # 0 and # 1 reads a predetermined program to realize the live migration according to this embodiment.

It should be noted that, with technologies such as hardware resources and memory, such as management need to virtualization of the server is available prior art.
Memory 520 is a volatile memory for storing programs and data CPU510a and 510b is performed. For example, a RAM (Random Access Memory) is used as the memory 520. It is also possible to use a non-volatile memory as needed.

North bridge 530, a CPU510a and 510b, are connected to the memory 520 and the PCIe switch 550. North bridge 530, a CPU510a and 510b, a memory 520 and the PCIe switch 550, but to control the data transfer path to allow communication with each other.

The north bridge 530 includes a IOMMU531, the IO table storage unit 532, a.
IOMMU531 is a memory management unit for memory management, such as performing a conversion between an address of the guest physical memory address of the host physical memory. Below, the address of the guest physical memory referred to as a "guest physical address." In addition, the address of the host physical memory referred to as a "host physical address."

IO table storage unit 532 is a storage device for storing an IO table used when IOMMU531 performs conversion of the guest physical address and the host physical address. For example, cache memory is used as the IO table storage unit 532. The IO table, will be described with reference to FIG.

IO adapters 540 and 541 and 542 is an interface with an IO device connected to the information processing apparatus 500. DMA circuit for performing a DMA is provided in the IO adapter 540, 541 and 542.

And IO device, for example, storage # 0 for storing data shown in FIG. 5, an input-output device such as a network device to be connected to the # 1 and the network.
PCIe switch 550 is connected to the north bridge 530, IO adapters 540, 541 and 542.

PCIe switch 550 performs such switching control of the data transfer path connecting between the north bridge 530 and the IO adapter 540, 541 and 542. The information processing apparatus 500 uses a "PCI Express 2.0" is a serial transfer interface standard for data transfer path.

Also, PCIe switch 550 includes a dirty page management unit 551, a dirty page storing unit 552, a.
Dirty page management unit 551, the IO adapter 540, 541 or 542 in the memory 520, detects the packet as the data to be transferred by the DMA write. The dirty page management unit 551, added by the DMA write, stores information about the changed or updated, such as data in the dirty page storing unit 552 in units of pages.

Below, added by the DMA write, the data in units of pages that have been changed or updated, etc., referred to as a "dirty page". In addition, information about the dirty page, referred to as a "dirty page information".

Dirty page storing unit 552 is a storage device for storing dirty page information. For example, such as static RAM is used as a dirty page storage unit 552.
The information processing apparatus 500 are connected via the information processing apparatus 501 and the network to implement the live migration. The information processing apparatus 500 and the information processing apparatus 501 shares the storage # 0 and # 1.

The information processing apparatus 501 includes a CPU560 and 561, a memory 570, a north bridge 580, a IO adapters 590 and 591 and 592, the PCIe switch 600, the.

CPU560,561, memory 570, north bridge 580, IO adapter 590,591,592 and the PCIe switch 600, CPU510,511, a memory 520, a north bridge 530, IO adapter 540,541,542 and the PCIe switch 550, it is the same.

However, the north bridge 580, may not include the IOMMU531 and IO table storage unit 532. Similarly, the PCIe switch 600 may not include the dirty page managing unit 551 and dirty page storing unit 552.

The information processing apparatus 501 connected to the information processing apparatus 500, the general live migration may be a feasible shown in FIG.
Configuration shown in FIG. 5 is an example of an information processing apparatus 500 according to this embodiment. Therefore, it is not intended to limit the configuration of the information processing apparatus 500 to the configuration shown in FIG. For example, it is not intended to limit the number of number and IO adapters CPU, and the like arrangement of each unit constituting the information processing apparatus 500 to that shown in FIG.

The information processing apparatus 500 may comprise a medium driving device for driving a portable storage medium such as a CD or DVD. If the live migration according to this embodiment is stored in the portable storage medium such as a CD or DVD, CPU 510 and 511, by executing the portable storage medium via a medium drive device reads a predetermined program, to achieve live migration according to this embodiment.

Figure 6 is a diagram for explaining the operation of the DMA process in the north bridge 530.
DMA packet 610 and 611 is a packet as the data to be transferred from the IO adapter 540, 541 or 542 to a predetermined destination by the DMA processing.

IO table 620 shows the IO table stored in the IO table storage unit 532. IO table 620 is an address conversion table of the guest physical address and the host physical address. IO table 620 defines the host physical address corresponding to the address consisting of a guest physical address and the source ID.

IO table 620 is to cache some of the entries that are frequently used among the entries of the page table 630 to be described later (temporarily held).
Here, a source ID is an ID for identifying the transfer source unit of the packet (Identification Data).

Or less, and in the drawings, if necessary, the guest physical address "GPA (Guest Physical Address)", the host physical address "HPA (Host Physical Address)", the source ID referred to as "SID (Source ID).

Page table 630 is an address conversion table of the guest physical address and the host physical address. Page table 630, defines the host physical address corresponding to the guest physical address.

IOMMU531 detects a DMA packet 610, the header of the DMA packet 610 is detected, acquires the guest physical address and the source ID.
Then, IOMMU531 refers to the IO table 620. Then, IOMMU531 the address consisting of a guest physical address and the source ID obtained from the DMA packet 610, determines whether or not it is registered in the IO table 620.

If a guest physical address and the source ID consists of an address acquired from the DMA packet 610 has been registered, IOMMU531 acquires the host physical address corresponding to the address consisting of the guest physical address and the source ID.

Then, IOMMU531 is a guest physical address indicating the destination set in the header of the DMA packet 610 is changed to a host physical address obtained from the IO table 620.

On the other hand, when the address consisting of a guest physical address and the source ID obtained from the DMA packet 610 is not registered in the IO table 620, IOMMU531 refers to the page table 630 stored in the memory 520.

Then, IOMMU531 is the address of the page table 630, and acquires the host physical address registered in the guest physical address identical to the address obtained from the DMA packet 610.

Then, IOMMU531 is a guest physical address indicating the destination set in the header of the DMA packet 610 is changed to a host physical address obtained from the page table 630.

Address of the transfer destination as described above is DMA packet 611 converted from the guest physical address to a host physical address is outputted to the memory 520.
Figure 7 is a diagram for explaining the operation of the DMA process in the PCIe switch 550.

Dirty page management unit 551 includes a control I / F (Interface) unit 710, a packet detecting unit 720, a write pointer 730, the read pointer 740, a.

In order to facilitate understanding of the operation of the dirty page management unit 551, FIG. 7 describes a dirty page storing unit 552 into the dirty page management unit 551.

Dirty page storing unit 552, FIFO: of memory # 0 and # 1 to realize (First In First Out FIFO). Below, each of the memory # 0 and # 1 to implement the FIFO "FIFO # 0", referred to as a "FIFO # 1".

Control I / F unit 710 is an interface dirty page management unit 551. VMM102 acquires dirty page information stored via the control I / F unit 710 to the FIFO # 0 or # 1.

Control I / F unit 710 includes a status register 711, a data register 712, a control register 713, a.
Status register 711 is a register that can be read / written by software such as VMM 102. Status register 711 includes a status display bits as follows.

Overflow information bit # 0: it indicates that the FIFO # 0 has caused an overflow.
Overflow information bit # 1: indicates that FIFO # 1 has caused an overflow.

Valid data count # 0: FIFO in # 0 indicates a value obtained by dividing the size of the dirty page information a difference between the address indicated by the address and the read pointer 740 indicated by the write pointer 730. Dirty page information that is not reading still indicates there are any remaining much to the FIFO # 0.

Valid data count # 1: In FIFO # 1, shows a value obtained by dividing the difference in size of the dirty page information with the address indicated by the address and the read pointer indicated by the write pointer. Dirty page information that is not reading still indicates there are any remaining much to the FIFO # 1.

Data register 712 is a register read is possible from software such as VMM 102. A register for use the data stored in the FIFO # 0 or # 1 to read from VMM 102.

Data register 712 is dirty page information read from the FIFO # 0 or # 1 specified by the read select bit of the control register 713 is set. Dirty page management unit 551, and at the same time dirty page information stored in the data register 712 is read, the read pointer 740 is set to the address next dirty page information is stored.

Control register 713 is a register that can be read / written by software such as VMM 102. Control register 713 is provided with a control bit as follows.

Start bit: to start the registration of dirty page information to the FIFO # 0 or # 1.
Stop bit: to stop the registration of dirty page information to the FIFO # 0 or # 1.

Clear bit: the pointer of the FIFO # 0 or # 1 back to 0, the FIFO # 0 or # 1 to the empty state. Empty state and is a state in which there is no dirty page information registered in the FIFO.

Write select bit: to which of the two FIFO # 0 or # 1 to select whether to register the dirty page information.
Read select bit: to select a read or two FIFO # 0 or # dirty page information from either of 1.

Packet detecting unit 720, while the start bit of the control register 713 is set to "1", detects a DMA write packet 750 to be input to the PCIe switch 550. Then, the packet detecting unit 720, from the header of the DMA write packet 750 has been detected, obtains a guest physical address and the source ID. Further, the packet detecting unit 720, the data consisting of a guest physical address and a source ID acquired as a dirty page information is written to the FIFO # 0 or # 1 currently being selected. Simultaneously, the packet detecting unit 720, the write pointer 730, then set the address of an area for storing the dirty page information.

Write pointer 730 indicates the address of the dirty page information that has been written in the last to FIFO # 0 or # 1. In this embodiment, as shown in FIG. 7, respectively for FIFO # 0 and the FIFO # for 1 by the write pointer 730 is provided.

Read pointer 740 indicates the address of the dirty page information that has been read from the FIFO # 0 or # 1 to the last. In this embodiment, as shown in FIG. 7, includes a read pointer 740 respectively for FIFO # 0 and the FIFO # for 1.

In the case where FIFO # 0 is selected, the write pointer and the read pointer for the FIFO # 0 is stored in the write pointer 730 and read pointer 740.

Similarly, if the FIFO # 1 is selected, the write pointer and the read pointer for the FIFO # 1 is stored in the write pointer 730 and read pointer 740.

Figure 8 is a diagram showing a configuration example of a FIFO # 0. Incidentally, in FIG. 8 shows the FIFO # 0 only, the same configuration applies to the FIFO # 1.
FIFO # 0 includes a source ID indicating the source of the IO adapter DMA packet, a guest physical address [63:12] indicating a transfer destination of the DMA packet. For PCI Express, the source ID is a source of the bus number of the DMA packet, and the source of the function number of the DMA packet consists.

In this embodiment, the size of one page for example and 4KB. In this case, the lower 12 bits of the address data of 64 bits wide representing the address of the same page. Thus, in this embodiment, among the guest physical address, and registers only the FIFO # 0 data to bits 63-12.

If you want to use the data of the guest physical address to a 32-bit length, to register the address data of 64 bits in length, which complements the "0" in the bits 63-32 of the guest physical address to the FIFO # 0.

The source ID mentioned above, the guest physical address can be acquired from the header of the DMA packet.
Figure 9 shows a configuration example of the header of the DMA packet. In this embodiment, the use of the PCIe switch 550, the header of the DMA packet conforms to the standard "PCI Express 2.0".

Header 1101 of the DMA packet shown in (1) in FIG. 9 shows a configuration example of the header of the DMA packet when using the address data of 32 bits wide in the guest physical address. The header 1102 of the DMA packet shown in (2) of FIG. 9 shows a configuration example of the header of the DMA packet when using the address data of 64 bits wide in the guest physical address.

"R" is a reserved area. Always "0" is set.
"Fmt (Format)" is two-bit data width indicated presence or absence of data stored in the payload, the header length.

"Type" is data of a 5-bit width, which indicates the type of packet.
"TC (Transaction Class)" is a 3-bit data width indicating the priority of the packet.

"TD (TLP (Transaction Layer Packet) Digest)" is data of one bit wide indicating the presence or absence of ECRC is an error check code (Extended Cyclical Redundancy Check).

"EP (Error Poisoned)" is 1-bit data width indicated the possibility that the broken data stored in the payload.
"Attr (Attributes)" is a two-bit data width indicated supplemental information regarding the order and protocol of the packet.

"AT (Address Translation)" is a two-bit data width indicated supplemental information about address translation.
"Length" is the 10-bit data width indicating the data length of data stored in the payload.

"Bus Number" is 8-bit data width indicated the source bus number of the DMA packet.
"Function number" is data of 8-bit width indicating the transmission source of the function number of the DMA packet.

"Tag" is the data of 8-bit width indicating the management number of the DMA packet.
"Last DW BE" is data of four bits wide indicating a valid or invalid Last DW Byte.

"1st DW BE" is a 4-bit data width shown to enable or disable of 1st DW Byte.
"Address" is an address data of 30 bit or 62 bit wide.

Figure 10 is a flow chart showing registration processing of dirty page information by the dirty page management unit 551. Incidentally, FIFO mentioned in FIG. 10, of the FIFO # 0 or # 1, shows the set FIFO to write select bit of the control register 713.

Software such VMM102 is, setting the start bit of the control register 713 included in the dirty page management unit 551 to "1", the dirty page management unit 551 starts the process of registering dirty page information (Step S1000) .

In step S1001, the packet detecting unit 720 refers to the header of the DMA packet input to the PCIe switch 550 from the IO adapter, such as IO adapter 540, 541 or 542.

Then, the packet detecting unit 720 acquires the "Fmt" and "Type" from the header of the DMA packet.
Packet detecting unit 720 is transferred from the IO adapter memory 520, Fmt = 10 (2 decimal) or Fmt = 11 (2 decimal), and upon detecting a DMA write packet is Type = 00000 (2 decimal), step S1002 the process proceeds to (step S1001 YES).

In the case of Fmt = 10 (2 decimal), indicates that the DMA packet using the address data of 32 bits wide in the guest physical address. Also, if the Fmt = 11 (2 decimal), it indicates that the DMA packet using the address data of 64 bits wide in the guest physical address.

Moreover, Type = 00000 (2 binary) indicates that a DMA write packet.
Packet detecting unit 720, DMA packet input to the PCIe switch 550, it is determined not to be a DMA write packet, executes step S1001 again (step S1001 NO).

In step S1002, the packet detecting unit 720, the difference between the addresses address and the read pointer 740 write pointer 730 points pointed to, by whether equal to the value obtained by dividing the size of the dirty page information on the size of the FIFO, FIFO There determines whether Full.

If the difference between the addresses address and the read pointer 740 write pointer 730 points to points is 0, the packet detecting unit 720, FIFO determines the Full (step S1002 YES). In this case, the packet detecting unit 720 moves the process to step S1003.

In step S1003, the packet detecting unit 720, setting "1" in the overflow information bit of the status register 711, the flow goes to step S1008. Then, the dirty page management unit 551 finishes the process of registration in the dirty page information.

In step S1002, if not equal to the value difference between the address address and the read pointer 740 write pointer 730 points pointed to by dividing the size of the dirty page information on the size of the FIFO, the packet detecting unit 720, FIFO is not Full It is determined (step S1002 NO). In this case, the packet detecting unit 720 moves the process to step S1004.

In step S1004, the packet detecting unit 720 acquires the source ID and a guest physical address from the header of the DMA write packet.
In step S1005, the packet detecting unit 720 registers the address of the FIFO indicated by write pointer 730, the data consisting of a source ID and a guest physical address acquired in step S1004 as the dirty page information.

In step S1006, the packet detecting unit 720, only the area size for storing the dirty page information, and increments the address stored in the write pointer 730.

In step S1007, the packet detecting unit 720 refers to the control register 713 included in the control I / F unit 710. When the stop bit of the control register 713, "1" is set (step S1007 YES), the packet detecting unit 720 moves the process to step S1008. And dirty page management unit 551 finishes the process of registration in the dirty page information.

In step S1007, when the stop bit of the control register 713 is not "1", the packet detecting unit 720 moves the process to step S1001 (step S1007 NO).

Figure 11 is a flowchart illustrating the output processing of the dirty page information by the dirty page management unit 551. Incidentally, FIFO mentioned in FIG. 11, of the FIFO # 0 or # 1, indicating that the set FIFO to read select bit of the control register 713.

In step S1101, software such as VMM102 is, reading the dirty page information from the data register 712 provided in the dirty page management unit 551, the control I / F unit 710 moves the process to step S1102.

In step S1102, the control I / F unit 710, only the area size for storing the dirty page information, and increments the address stored in the read pointer 740.

In step S1103, the control I / F unit 710 acquires the dirty page information from the address of the FIFO indicated by the read pointer 740 is latched by the data register 712.

When the above process is completed, the control I / F unit 710 moves the process to step S1104. The control I / F unit 710 terminates the output processing of the dirty page information.
(Live migration according to this embodiment)
Figure 12 is a diagram for describing the outline of the live migration according to this embodiment.

The information processing system shown in FIG. 12 1200, server and # 0, the server # 0 and the server # 1 via the network communicatively connected to each other, the server # 0 and the server # storage 1 and share # 0 and # It includes 1, a.

Server # 0 is an information processing apparatus 500 shown in FIG. The server # 0 is an information processing apparatus 501 shown in FIG.
In the server # 0 to operate the VMM # 0. The VMM # 0, to implement the VM # 0 and VM # 1. On the other hand, in the server # 1 VMM # 1 operates. In addition, VM # 0 is proprietary storage # 0, VM # 1 is the exclusive storage # 1.

In the above state, explaining the VM # 0 to VMM # 0 is realized running on the server # 0, below when performing live migration to move on VMM # 1 running on the server # 1.

Figure 13 is a flowchart showing the outline of live migration according to this embodiment.
In step S1301, VMM # 0, to the VMM # 1 is the moving destination of the VM # 0, requests the securing of memory area to be allocated to the new VM. Below, the memory area to be allocated to the VM called "VM region".

On the other hand, if the VMM # 1 receives a request for VM area reservation, VMM # 1 is to ensure VM area in a predetermined area of ​​the memory provided in the server # 1. Then, the server # 1 notifies that the secure VM region has been completed to the server # 0.

Upon receiving the notification from the server # 1 to the effect that secure VM area has been completed, the server # 0, the flow goes to step S1302.
In step S1302, VMM # 0, at some point, it acquires the data stored in the area of ​​the host physical memory allocated to VM # 0 is a moving target. This, the data stored in the area of ​​the host physical memory allocated to the VM at some point (checkpoint time) called "snapshot".

In step S1303, VMM # 0, set the start bit of the control register 713 of the dirty page management unit 551 to "1", to start recording the dirty page information.

In step S1304, VMM # 0 is a snapshot taken at step S1302, a predetermined area of ​​the memory provided to the destination server # 1 VM # 0, the VM area secured in Step S1301, the memory make a copy.

In step S1305, VMM # 0 through the valid data count of the status register 711 of the control I / F unit 710 from the dirty page management unit 551, and acquires the remaining number of dirty page information. Then, VMM # 0 compares the predetermined threshold with the rest of the number of dirty pages information.

If the number of remaining dirty page information is larger than the threshold value (step S1305 YES), VMM # 0, the process proceeds to step S1306. Also, if the remaining number of dirty page information is equal to or less than the threshold (step S1305 NO), VMM # 0, the process proceeds to step S1307.

In step S1306, VMM # 0 via the data register 712 of the control I / F unit 710 from the dirty page management unit 551, all dirty page information registered so far in the dirty page storing unit 552 to get.

Then, VMM # 0 is, to convert the guest physical address of the acquired dirty page information to the host physical address.
Then, VMM # 0 from the memory included in the server # 0, and acquires the data stored in the converted host physical address. Then, VMM # 0 the acquired data, an area of ​​the memory provided to the destination server # 1 VM # 0, the VM area secured in step S1301, memory copy.

Running the memory copy, VMM # 0, the process proceeds to step S1305.
Processing of steps S1302 ~ S1306 explained above is a "pre-copy". Pre-copy, VM # 0 is performed in the ongoing business. Therefore, during the pre-copy also the VMM # 0, via IOMMU531, performs read / write processing for the storage apparatus # 0. Therefore, it is necessary to stop-and-copy of the following.

In step S1307, VMM # 0 stops operations VM # 0.
In step S1308, VMM # 0 performs the same processing as in step S1306.

Processing of steps S1307 ~ S1308 explained above is a "stop-and-copy".
In step S1309, VMM # 0 is the VMM # 1 operating on the destination server # 1 VM # 0, and notifies the completion of the memory copy.

In step S1310, when the VMM # 0 receives notification of completion of the memory copy, VMM # 1 starts the operations of the VM # 0 on VMM # 1. When the VM # 0 on the VMM # 1 is to resume business, VMM # 1, the process proceeds to step S1311. Then, VMM # 0 and # 1 ends the live migration.

Figure 14 is a flowchart showing the specific processing of the pre-copy.
In step S1401, VMM # 0 by setting "1" to clear bit of the control register 713 included in the control I / F unit 710 initializes the FIFO # 0 and # 1.

In addition, VMM # 0 is, by setting the write select bit of the control register 713 to "0", to set the FIFO to record the dirty page information to the FIFO # 0. Similarly, VMM # 0 is, by setting the read select bit of the control register 713 to "0", to set the FIFO to read the dirty page information to the FIFO # 0.

In step S1402, VMM # 0 by setting the start bit of the control register 713 included in the dirty page management unit 551 to "1", to start recording the dirty page information.

In step S1403, VMM # 0 performs a memory copy. In step S1403, memory copy processing described in steps S1302 ~ S1304 shown in FIG. 13 is performed.

In step S1404, VMM # 0, the process moves to a predetermined time wait state. After a certain length of time has elapsed, VMM # 0, the process proceeds to step S1405.
In step S1405, VMM # 0 by setting "0" or "1" to the write select bit of the control register 713 included in the control I / F unit 710, changes the FIFO for recording the dirty page information.

For example, if the FIFO currently being selected is FIFO # 0, VMM # 0 is changed, by setting "1" to write select bit of the control register 713, the FIFO for recording dirty page information in FIFO # 1 to.

Similarly, if FIFO currently being selected is FIFO # 1, VMM # 0 by setting "0" to the write select bit of the control register 713, the FIFO for recording dirty page information in FIFO # 0 change.

In step S1406, VMM # 0 reads the status register 711 included in the control I / F unit 710.
In step S1407, VMM # 0 determines whether overflow information bit of the FIFO currently being selected is set to "1".

If overflow information bit of the FIFO currently being selected is set to "1" (step S1407 YES), VMM # 0, the process proceeds to step S1408. In this case, VMM # 0 is again a live migration of a running interrupted or from the beginning.

In step S1407, if the overflow information bit of the FIFO currently being selected is set to "0" (step S1407 NO), VMM # 0, the process proceeds to step S1409.

In step S1409, VMM # 0 reads the data register 712 by the number set in the valid data count in the status register 711, acquires the dirty page information.

In step S1410, VMM # 0 among the dirty page information read in step S1409, to extract only the dirty page information source ID indicating the storage # 0.

Step S1410 or the dirty page information to be extracted in the process of which will be described later S1507 referred to as a "copy target dirty page information".
In step S1411, VMM # 0 will convert guest physical address of the copy target dirty page information, according to the page table 630, the host physical address.

In step S1412, VMM # 0 obtains the data stored in the host physical address of the copy target dirty page information, from the memory 520 included in the server # 0. Then, VMM # 0 the acquired data is transferred to the VMM # 1 is the moving destination of the VM # 0.

On the other hand, VMM # 1 receives the data from the VMM # 0, and stores the received data in the VM area reserved in the processing of step S1301 shown in FIG. 13.
In step S1413, VMM # 0 by setting "0" or "1" to the read select bit of the control register 713 included in the control I / F unit 710, changes the FIFO to read the dirty page information.

For example, if the FIFO of the currently selected of the FIFO # 0, VMM # 0 is, by setting "1" to the read select bit of the control register 713, to change the FIFO to read the dirty page information to the FIFO # 1 .

Similarly, if the FIFO of the currently selected of FIFO # 1, VMM # 0 is, by setting the "0" to read select bit of the control register 713, change the FIFO to read the dirty page information to the FIFO # 0 to.

In step S1414, VMM # 0 determines whether to satisfy the completion condition of the pre-copy. In the process of step S1414, the processing of step S1305 shown in FIG. 13 is performed.

If it is determined that the completion conditions of the pre-copy is satisfied (step S1414 YES), VMM # 0, the process proceeds to step S1415. In this case, VMM # 0 ends the pre-copy.

When it is determined not to satisfy the completion condition of the pre-copy (step S1414 NO), VMM # 0, the process proceeds to step S1404.
Figure 15 is a flowchart illustrating a specific process of stop-and-copy.

When pre-copy shown in FIG. 14 is completed, VMM # 0 starts the stop-and-copy process. The VMM # 0, and to stop the work of the VM # 0, the process proceeds to step S1501 (step S1500).

In step S1501, VMM # 0, the process moves to a predetermined time wait state. DMA write process is to wait of up to a complete stop. After a certain length of time has elapsed, VMM # 0, the process proceeds to step S1502.

In step S1502, VMM # 0 by setting "0" or "1" to the write select bit of the control register 713 included in the control I / F unit 710, changes the FIFO for recording the dirty page information.

For example, if the FIFO currently being selected is FIFO # 0, VMM # 0 is changed, by setting "1" to write select bit of the control register 713, the FIFO for recording dirty page information in FIFO # 1 to.

Similarly, if FIFO currently being selected is FIFO # 1, VMM # 0 by setting "0" to the write select bit of the control register 713, the FIFO for recording dirty page information in FIFO # 0 change.

In step S1503, VMM # 0 reads the status register 711 included in the control I / F unit 710. Then, VMM # 0 determines whether overflow information bit of the FIFO currently being selected is set to "1".

In step S1504, VMM # 0, when the overflow information bit of the FIFO currently being selected is set to "1" (step S1504 YES), VMM # 0, the process proceeds to step S1505. In this case, VMM # 0 is again a live migration interrupted or from the beginning.

In step S1504, if the overflow information bit of the FIFO currently being selected is set to "0" (step S1504 NO), VMM # 0, the process proceeds to step S1506.

In step S1506, VMM # 0 reads the data register 712 by the number set in the valid data count in the status register 711, acquires the dirty page information.

In step S1507, VMM # 0 among the dirty page information read in step S1506, the source ID of the dirty page information to extract copied dirty page information indicating a storage # 0.

In step S1508, VMM # 0 will convert guest physical address of the copy target dirty page information, according to the page table 630, the host physical address.

In step S1509, VMM # 0, from the valid data count bit of the status register 711 included in the control I / F unit 710, determines whether FIFO has data page information.

If valid data count in the status register 711 is "0" (step S1509 YES), VMM # 0 is, FIFO is determined that the empty, the flow goes to step S1510.

In step S1510, VMM # 0 obtains the data stored in the host physical address of the copy target dirty page information, from the memory 520 included in the server # 0. Then, VMM # 0 the acquired data is transferred to the VMM # 1 is the moving destination of the VM # 0.

On the other hand, VMM # 1 receives the data from the VMM # 0, and stores the received data in the VM area reserved in the processing of step S1301 shown in FIG. 13.
When the data transfer to the VMM # 1 is completed, VMM # 0, the process proceeds to step S1511. Then, VMM # 0 ends the stop-and-copy (step S1511).

On the other hand, in step S1509, if valid data count in the status register 711 is not "0" (step S1509 NO), VMM # 0 is, FIFO is determined not empty, the process proceeds to step S1512.

In step S1512, VMM # 0 by setting "0" or "1" to the read select bit of the control register 713 included in the control I / F unit 710, changes the FIFO to read the dirty page information.

For example, if the FIFO of the currently selected of the FIFO # 0, VMM # 0 is, by setting "1" to the read select bit of the control register 713, to change the FIFO to read the dirty page information to the FIFO # 1 .

Similarly, if the FIFO of the currently selected of FIFO # 1, VMM # 0 is, by setting the "0" to read select bit of the control register 713, change the FIFO to read the dirty page information to the FIFO # 0 to.

If you change the FIFO to read the dirty page information, VMM # 0, the process proceeds to step S1501.
As described above, the dirty page management unit 551, DMA packet transferred from the IO adapter 540, 541 and 542 in the memory 520 passes through the PCIe switch 550, detects the DMA packet by packet detector 720 .

When DMA packet detection is DMA write packet, the dirty page management unit 551 registers from the header of the DMA packet to get the guest physical memory and the source ID, the FIFO # 0 or # 1 as dirty page information to.

Also, the dirty page management unit 551, CPU 510, or 511, i.e., a control I / F unit 710 of the VMM to CPU 510 or 511 is implemented, it is registered in the FIFO # 0 or # 1 in response to a request from the VMM and outputs the dirty page information you are.

As a result, the VMM running on the information processing apparatus 500, the dirty page information, added by DMA write using IOMMU531, it is possible to obtain data on the memory 520 that have changed or updated, or the like.

As described above, added by DMA write, by which it is possible to obtain data on the memory 520 that have been modified or updated, such as, pre-copy and a stop-and-copy shown in FIGS. 13 to 15 it is possible. As a result, it is possible to execute the live migration even when using a IOMMU.

The information processing apparatus 500 includes, as dirty page storing unit 552, comprises two FIFO of the FIFO # 0 and # 1. Then, one of the FIFO may be written by the target reading the other FIFO, read and write operations for a single FIFO is possible to avoid conflict. As a result, it is possible to perform the registration processing of the dirty page information to the FIFO, and the read processing of dirty page information from the FIFO, the efficiently.

Claims (12)

  1. By managing the hardware resources, a virtual machine implementation means for implementing one or more virtual machines,
    The address of the first memory area allocated to the virtual machine, and the first second memory area address is a real memory of the memory area, by converting each other, incoming data with an external device and data transfer means for performing direct data transfer to the first memory region from the input-output device allocated to the virtual machine to control the output,
    And transfer data detection means for detecting the data directly is data transferred to said first memory area allocated to the virtual machine from the input device,
    Update information registration means for generating update information pertaining to said first memory area to be changed by the detected data, and stores the update information in the update information storage unit by said transfer data detecting means,
    Update information output means for outputting the update information stored in the update information storage means,
    The information processing apparatus comprising: a.
  2. Data detected by the transfer data detecting means according to an instruction from the virtual machine, the directly transfer data from the input-output device to said first memory area allocated to the virtual machine, written in the first memory area it is data,
    The information processing apparatus according to claim 1, characterized in that.
  3. The update information is information including the identification information identifying the input-output device that transferred the data, and the address of the first memory area which is the transfer destination of the data, and
    The information processing apparatus according to claim 1, characterized in that.
  4. The update information storage means comprises a second storage means the first storage means, and
    It is possible to store or read updated information independently of each other,
    The information processing apparatus according to claim 1, characterized in that.
  5. By managing the hardware resources, the steps for implementing one or more virtual machines,
    The address of the first memory area allocated to the virtual machine, and the first second memory area address is a real memory of the memory area, by converting each other, incoming data with an external device performing a direct data transfer to the first memory region from the input-output device allocated to the virtual machine to control the output,
    Detecting the data directly is data transferred to said first memory area allocated to the virtual machine from the input device,
    A step of generating an update information on the first memory area is modified by the detected data, and stores the update information in the update information storage means,
    And outputting the update information stored in the update information storage means,
    Virtualization method for an information processing apparatus comprising: a.
  6. By managing the hardware resources, a virtual machine implementation means for implementing one or more virtual machines,
    The address of the first memory area allocated to the virtual machine, and the first second memory area address is a real memory of the memory area, by converting each other, incoming data with an external device and data transfer means for performing direct data transfer to the first memory region from the input-output device allocated to the virtual machine to control the output,
    A memory area transfer means for transferring data to the destination to get stored in the first memory area allocated to the virtual machine to be moved,
    And transfer data detection means for detecting the data directly is data transferred to said first memory area allocated to the virtual machine from the input device,
    Update information registration means for generating update information pertaining to said first memory area to be changed by the detected data, and stores the update information in the update information storage unit by said transfer data detecting means,
    Update information acquiring means for acquiring update information from the update information storage means,
    Wherein based on the acquired update information by the updating information obtaining means, an update data changed by the detected data by said transfer data detecting means in the first memory area allocated to the virtual machine to be moved, said movement destination and update data transfer means for transferring,
    The information processing apparatus comprising: a.
  7. Data detected by the transfer data detecting means according to an instruction from the virtual machine, the directly transfer data from the input-output device to said first memory area allocated to the virtual machine, written in the first memory area it is data,
    The information processing apparatus according to claim 6, characterized in that.
  8. The update information is information including the identification information identifying the input-output device that transferred the data, and the address of the first memory area which is the transfer destination of the data, and
    The information processing apparatus according to claim 6, characterized in that.
  9. The update information storage means comprises a second storage means the first storage means, and
    It is possible to store or read updated information independently of each other,
    The information processing apparatus according to claim 6, characterized in that.
  10. The update data transfer means,
    Until the number of update information stored in the update information storage unit is below a predetermined value, the first update data transfer means for transferring the updated data to the destination,
    After stopping the virtual machine operation of the moving object, and the second update data transfer means for transferring the updated data to the destination,
    Equipped with a,
    The information processing apparatus according to claim 6, characterized in that.
  11. A virtual machine that implemented by the first information processing apparatus, the migration method of moving the second information processing apparatus connected to be capable of communicating with the first information processing apparatus,
    By managing the hardware resources, the steps for implementing one or more of the virtual machines,
    The address of the first memory area allocated to the virtual machine, and the first second memory area address is a real memory of the memory area, by converting each other, incoming data with an external device performing a direct data transfer to the first memory region from the input-output device allocated to the virtual machine to control the output,
    A step of acquiring the data stored in the first memory area allocated to the virtual machine to be moved by transfer to the second information processing apparatus,
    Detecting the data directly is data transferred to said first memory area allocated to the virtual machine from the input device,
    A step of generating an update information on the first memory area is modified by the detected data, and stores the update information in the update information storage means,
    Acquiring update information from the update information storage means,
    And transferring on the basis of the update information, the changed update data by data the detected in the first memory area allocated to the virtual machine to be moved, to the second information processing apparatus,
    Migration method characterized by comprising a.
  12. A virtual machine that implemented by the first information processing apparatus having a processing unit, in the migration program to move to the second information processing device communicably connected to the first information processing apparatus,
    By managing the hardware resources, a virtual machine implemented process for implementing one or more virtual machines,
    The address of the first memory area allocated to the virtual machine, and the first second memory area address is a real memory of the memory area, by converting each other, incoming data with an external device a data transfer processing for direct data transfer to the first memory region from the input-output device allocated to the virtual machine to control the output,
    A memory area transfer process for transferring to the first information processing apparatus the data stored in the first memory area allocated to the virtual machine to be moved to obtain,
    And transfer data detecting process for detecting the data directly is data transferred to said first memory area is allocated from the input device to the virtual machine,
    Generates update information relating to the first memory area to be changed by the data detected by said transfer data detection processing, the update information registration process of storing the update information in the update information storage means,
    Update information acquisition process for acquiring the update information from the update information storage means,
    Wherein based on the acquired update information by the update information obtaining process, the update data that has been changed by the detected data by said transfer data detection processing in the first memory area allocated to the virtual machine to be moved, the first update data transfer process of transferring the information processing apparatus,
    A program characterized by executing the arithmetic processing device.
PCT/JP2009/001464 2009-03-30 2009-03-30 Information processor WO2010116402A1 (en)

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WO2012063334A1 (en) * 2010-11-10 2012-05-18 株式会社日立製作所 Memory control device and i/o switch for assisting live migration of virtual machine
JP2012128807A (en) * 2010-12-17 2012-07-05 Fujitsu Ltd Information processing apparatus
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JP2002518734A (en) * 1998-06-15 2002-06-25 サン・マイクロシステムズ・インコーポレーテッド Tracking of the memory page change in the bridge for a multi-processor system
JP2008269600A (en) * 2007-04-16 2008-11-06 Internatl Business Mach Corp <Ibm> Method, device and program for controlling migration of logical partition
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Cited By (9)

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JP2011221945A (en) * 2010-04-14 2011-11-04 Hitachi Ltd Data transfer device, computer system and memory copy device
WO2012063334A1 (en) * 2010-11-10 2012-05-18 株式会社日立製作所 Memory control device and i/o switch for assisting live migration of virtual machine
JPWO2012063334A1 (en) * 2010-11-10 2014-05-12 株式会社日立製作所 Memory controller and i / o switch to support live migration of a virtual machine
JP2012128807A (en) * 2010-12-17 2012-07-05 Fujitsu Ltd Information processing apparatus
US8924624B2 (en) 2010-12-17 2014-12-30 Fujitsu Limited Information processing device
US8966480B2 (en) 2011-03-31 2015-02-24 Fujitsu Limited System for migrating a virtual machine between computers
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JP2014191752A (en) * 2013-03-28 2014-10-06 Fujitsu Ltd Migration processing program, migration method, and cloud system
JP2018500646A (en) * 2014-11-12 2018-01-11 インテル コーポレイション Live migration of virtual machines from the host computer using a graphics virtualization / to the host computer

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