WO2010116268A1 - Procédé et appareil pour coder et décoder une image et une vidéo - Google Patents

Procédé et appareil pour coder et décoder une image et une vidéo Download PDF

Info

Publication number
WO2010116268A1
WO2010116268A1 PCT/IB2010/050703 IB2010050703W WO2010116268A1 WO 2010116268 A1 WO2010116268 A1 WO 2010116268A1 IB 2010050703 W IB2010050703 W IB 2010050703W WO 2010116268 A1 WO2010116268 A1 WO 2010116268A1
Authority
WO
WIPO (PCT)
Prior art keywords
block
pixel
pixels
transform
pixel area
Prior art date
Application number
PCT/IB2010/050703
Other languages
English (en)
Inventor
Cixun Zhang
Kemal Ugur
Original Assignee
Nokia Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corporation filed Critical Nokia Corporation
Publication of WO2010116268A1 publication Critical patent/WO2010116268A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/146—Data rate or code amount at the encoder output
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/119—Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/12—Selection from among a plurality of transforms or standards, e.g. selection between discrete cosine transform [DCT] and sub-band transform or selection between H.263 and H.264
    • H04N19/122—Selection of transform size, e.g. 8x8 or 2x4x8 DCT; Selection of sub-band transforms of varying structure or type
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
    • H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding

Definitions

  • the present invention relates to apparatus for coding and decoding and specifically but not only for coding and decoding of image and video signals
  • a video codec comprises an encoder which transforms input video into a compressed representation suitable for storage and/or transmission and a decoder that can uncompress the compressed video representation back into a viewable form.
  • the encoder discards some information in the original video sequence in order to represent the video in a more compact form, for example at a lower bit rate.
  • Typical video codecs for example International Telephone Union - Technical Board (ITU-T) H.263 and H.264 coding standards, encode video information in two phases.
  • pixel values in a certain picture area or "block" are predicted.
  • These pixel values can be predicted, for example, by motion compensation mechanisms, which involve finding and indicating an area in one of the previously encoded video frames (or a later coded video frame) that corresponds closely to the block being coded.
  • pixel values can be predicted by spatial mechanisms which involve finding and indicating a spatial region relationship.
  • the second phase is one of coding the error between the predicted block of pixels and the original block of pixels. This is typically accomplished by transforming the difference in pixel values using a specified transform. This transform is typically a Discrete Cosine Transform (DCT) or a variant thereof. After transforming the difference, the transformed difference is quantized and entropy encoded.
  • DCT Discrete Cosine Transform
  • the encoder can control the balance between the accuracy of the pixel representation, (in other words, the quality of the picture) and the size of the resulting encoded video representation (in other words, the file size or transmission bit rate).
  • the decoder reconstructs the output video by applying a prediction mechanism similar to that used by the encoder in order to form a predicted representation of the pixel blocks (using the motion or spatial information created by the encoder and stored in the compressed representation of the image) and prediction error decoding (the inverse operation of the prediction error coding to recover the quantised prediction signal in the spatial domain).
  • the decoder After applying pixel prediction and error decoding processes the decoder combines the prediction and the prediction error signals (the pixel values) to form the output video frame.
  • the decoder may also apply additional filtering processes in order to improve the quality of the output video before passing it for display and/or storing as a prediction reference for the forthcoming frames in the video sequence.
  • the motion information is indicated by motion vectors associated with each motion compensated image block.
  • Each of these motion vectors represents the displacement of the image block in the picture to be coded (in the encoder) or decoded (at the decoder) and the prediction source block in one of the previously coded or decoded images (or pictures).
  • motion vectors are typically coded differentially with respect to block specific predicted motion vector.
  • the predicted motion vectors are created in a predefined way, for example by calculating the median of the encoded or decoded motion vectors of the adjacent blocks.
  • Typical video encoders utilise the Lagrangian cost function to find optimal coding modes, for example the desired macro block mode and associated motion vectors.
  • This type of cost function uses a weighting factor or ⁇ to tie together the exact or estimated image distortion due to lossy coding methods and the exact or estimated amount of information required to represent the pixel values in an image area. This may be represented by the equation:
  • C the Lagrangian cost to be minimised
  • D the image distortion (in other words the mean-squared error) with the mode and motion vectors currently considered
  • R the number of bits needed to represent the required data to reconstruct the image block in the decoder (including the amount of data to represent the candidate motion vectors).
  • alignment of the block size used for transform coding of the prediction error to the block size used for motion compensation occurs.
  • edges occur within a block, produce a sub-optimal coding efficiency.
  • the video coding method described used a transform where the location of the transform block within the macroblock and the transform size is not fixed but is variable.
  • This approach is called Spatially Varying Transform (SVT) and aimed to reduce the residual error and increase the coding efficiency of the image/video coder.
  • SVT Spatially Varying Transform
  • this method attempted to improve the coding efficiency it does it at the cost of increased encoder complexity as the encoder searches for the best position and/or size of the selected transform block among all candidate positions and sizes. This added encoded complexity is problematic for real time encoding on resource constrained devices.
  • the selected transform from the candidate set has to be signalled to the decoder. In the current examples the signalling bits used to code the candidate positions can become a significant overhead in low bit rate signalling situations.
  • This invention proceeds from the consideration that by circumscribing the number of candidate sizes and position from which the transform block may be selected from and furthermore using non-overlapping transform block partitions the encoder complexity issue and the signalling overhead issue may be addressed.
  • Embodiments of the present invention aim to address the above problem.
  • an apparatus comprising: a controller configured to select a first set of transform blocks from a second set of transform blocks dependent on a criteria, wherein each transform block is defined by a pixel area in a block of pixels; and a processor configured to transform a pixel area defined by at least one of the first set of transform blocks selected pixel area.
  • the first set of transform blocks from which the processor transforms a pixel area defined by one of the first set enables more efficient processing of the pixel area by filtering candidate transform blocks.
  • embodiments of the invention enable the coding process to be carried out on simpler and less powerful coders and/or enable the coding process for a specific quality of encoding to be carried out using fewer processing cycles.
  • the controller may be further configured to generate a transform indicator comprising at least one of: a first set indicator representing the first set of transform blocks; a second set indicator representing the second set of transform blocks; and a transform indicator representing the at least one of the first set of transform blocks applied.
  • At least one of the first set indicator and the second set indicator may comprise information on how the block of pixels is partitioned into transform blocks.
  • the transform indicator may comprise information identifying the at least one of the first set of transformed blocks applied in relation to the partitioned block of pixels.
  • the apparatus may be further configured to select the at least one of the first set of transform blocks dependent on a second criteria.
  • the criteria may comprise at least one of: apparatus processing capacity; apparatus storage capacity; bit-rate capacity; a previous slice bit value; picture/frame size; frame/slice interval periods; and block transform errors.
  • Each pixel area is preferably defined by a pixel area size and a pixel area position in the block of pixels.
  • the first set of transforms may comprise at least one group of contiguous regular sized areas.
  • an apparatus comprising: a controller configured to determine a set of pixel areas within a block of pixels; and a processor configured to select a pixel area from the set of pixel areas within the block of pixels dependent on a first part of a signal; and regenerate a first set of pixel values for the pixel area dependent on a second part of the signal.
  • the apparatus may further comprise a further processor configured to regenerate a second set of pixel values for remainder of the pixels within the block of pixels.
  • the apparatus may further comprise an adder configured to combine the first and second set of pixel values.
  • the controller may be further configured to select the set of pixel areas dependent on at least one of: a third part of the signal; and a characteristic of a previously decoded image/frame.
  • a method comprising: selecting a first set of transform blocks from a second set of transform blocks dependent on a criteria, wherein each transform block is defined by a pixel area in a block of pixels; and transforming a pixel area defined by at least one of the first set of transform blocks selected pixel area.
  • the method may further comprise generating a transform indicator comprising at least one of: a first set indicator representing the first set of transform blocks; a second set indicator representing the second set of transform blocks; and a transform indicator representing the at least one of the first set of transform blocks applied.
  • At least one of the first set indicator and the second set indicator may comprise information on how the block of pixels is partitioned into transform blocks.
  • the transform indicator may comprise information identifying the at least one of the first set of transformed blocks applied in relation to the partitioned block of pixels
  • the method may further comprise selecting the at least one of the first set of transform blocks dependent on a second criteria.
  • the criteria may comprise at least one of: apparatus processing capacity; apparatus storage capacity; bit-rate capacity; a previous slice bit value; picture/frame size; frame/slice interval periods; and block transform errors.
  • Each pixel area is preferably defined by a pixel area size and a pixel area position in the block of pixels.
  • the first set of transforms may comprise at least one group of contiguous regular sized areas.
  • a method comprising: determining a set of pixel areas within a block of pixels; selecting a pixel area from the set of pixel areas within the block of pixels from a set of pixel areas dependent on a first part of a signal; and regenerating a first set of pixel values for the pixel area dependent on a second part of the signal.
  • the method may further comprise regenerating a second set of pixel values for remainder of the pixels within the block of pixels.
  • the method may further comprise combining the first and second set of pixel values.
  • the method may further comprise selecting the set of pixel areas dependent on at least one of: a third part of the signal; and a characteristic of a previously decoded image/frame.
  • a computer-readable medium encoded with instructions that, when executed by a computer, perform: selecting a first set of transform blocks from a second set of transform blocks dependent on a criteria, wherein each transform block is defined by a pixel area in a block of pixels; and transforming a pixel area defined by at least one of the first set of transform blocks selected pixel area.
  • a computer-readable medium encoded with instructions that, when executed by a computer, perform: determining a set of pixel areas within a block of pixels; selecting a pixel area from the set of pixel areas within the block of pixels from a set of pixel areas dependent on a first part of a signal; and regenerating a first set of pixel values for the pixel area dependent on a second part of the signal.
  • the computer-readable medium encoded with instructions may when executed by a computer further perform regenerating a second set of pixel values for remainder of the pixels within the block of pixels.
  • the computer-readable medium encoded with instructions may when executed by a computer further perform combining the first and second set of pixel values.
  • an apparatus comprising: means for selecting a first set of transform blocks from a second set of transform blocks dependent on a criteria, wherein each transform block is defined by a pixel area in a block of pixels; and means for transforming a pixel area defined by at least one of the first set of transform blocks selected pixel area.
  • an apparatus comprising: means for determining a set of pixel areas within a block of pixels; means for selecting a pixel area from a set of pixel areas within a block of pixels dependent on a first part of a signal; and means for regenerating a first set of pixel values for the pixel area dependent on a second part of the signal.
  • the apparatus may further comprise means for regenerating a second set of pixel values for remainder of the pixels within the block of pixels.
  • the apparatus may further comprise means for combining the first and second set of pixel values.
  • An electronic device may comprise apparatus as described above.
  • a chipset may comprise apparatus as described above.
  • An encoder may comprise apparatus as described above.
  • a decoder may comprise apparatus as described above.
  • Figure 1 shows schematically an electronic device employing embodiments of the invention
  • Figure 2 shows schematically a user equipment suitable for employing embodiments of the invention
  • FIG. 3 further shows schematically electronic devices employing embodiments of the invention connected using wireless and wired network connections
  • Figure 4a shows schematically an embodiment of the invention as incorporated within an encoder
  • Figure 4b shows schematically a prediction error coder according to an embodiment of the invention as shown in Figure 4a;
  • Figure 4c shows schematically a prediction error decoder according to an embodiment of the invention as shown in Figure 4a;
  • Figure 5 shows a flow diagram showing the operation of an embodiment of the invention with respect to the residual encoder as shown in Figures 4a, 4b and 4c;
  • Figure 6 shows a schematic diagram of a decoder according to embodiments of the invention.
  • Figure 7 shows a flow diagram of showing the operation of an embodiment of the invention with respect to the decoder shown in figure 6;
  • Figures 8a, 8b and 8c show schematically a simplified representation of a spatially varying transform block sizes and offsets from the macro block origin according to embodiments of the invention;
  • Figure 9 shows a further simplified representation of non overlapping spatially varying transform block size and offsets from the macro block origin according to embodiments of the invention
  • Figures 10a and 10b show a third set of representations of non overlapping spatially varying transform block selection at offset from the macro block origin according to embodiments of the invention.
  • Figures 1 and 2 shows a schematic block diagram of an exemplary apparatus or electronic device 50, which may incorporate a codec according to an embodiment of the invention and a possible physical representation of the same apparatus.
  • the electronic device 50 may for example be a mobile terminal or user equipment of a wireless communication system. However, it would be appreciated that embodiments of the invention may be implemented within any electronic device or apparatus which may be configured to encode and decode, or encode, or decode video images.
  • the apparatus 50 may comprise a housing 30 for incorporating and protecting the device.
  • the apparatus 50 further may comprise a display 32 in the form of a liquid crystal display.
  • the display may be any suitable display technology suitable to display an image or video.
  • the apparatus 50 may further comprise a keypad 34.
  • any suitable data or user interface mechanism may be employed.
  • the user interface may be implemented as a virtual keyboard or data entry system as part of a touch-sensitive display.
  • the apparatus may comprise a microphone 36 or any suitable audio input which may be a digital or analogue signal input.
  • the apparatus 50 may further comprise an audio output device which in embodiments of the invention may be any one of: an earpiece 38, speaker, or an analogue audio or digital audio output connection.
  • the apparatus 50 may also comprise a battery 40 (or in other embodiments of the invention the device may be powered by any suitable mobile energy device such as solar cell, fuel cell or clockwork generator).
  • the apparatus may further comprise an infrared port 42 for short range line of sight communication to other devices.
  • the apparatus 50 may further comprise any suitable short range communication solution such as for example a Bluetooth wireless connection or a USB/firewire wired connection.
  • the apparatus 50 may comprise a controller 56 or processor for controlling the apparatus 50.
  • the controller 56 may be connected to memory 58 which in embodiments of the invention may store both data in the form of image and audio data and/or may also store instructions for implementation on the controller 56.
  • the controller 56 may further be connected to codec circuitry 54 suitable for carrying out coding and decoding of audio and/or video data or assisting in coding and decoding carried out by the controller 56.
  • the apparatus 50 may further comprise a card reader 48 and a smart card 46, for example a UICC and UICC reader for providing user information and being suitable for providing authentication information for authentication and authorization of the user at a network.
  • a card reader 48 and a smart card 46 for example a UICC and UICC reader for providing user information and being suitable for providing authentication information for authentication and authorization of the user at a network.
  • the apparatus 50 may comprise radio interface circuitry 52 connected to the controller and suitable for generating wireless communication signals for example for communication with a cellular communications network, a wireless communications system or a wireless local area network.
  • the apparatus 50 further may comprise an antenna 44 connected to the radio interface circuitry 52 for transmitting and receiving radio frequency signals generated at the radio interface circuitry 52.
  • the apparatus 50 comprises a camera capable of recording or detecting individual frames which are then passed to the codec 54 or controller for processing.
  • the apparatus may receive the video image data for processing from an adjacent device prior to transmission and/or storage.
  • the apparatus 50 may receive either wirelessly or by a wired connection the image for coding/decoding.
  • FIG 3 a system within which embodiments of the present invention can be utilised is shown.
  • the system 10 comprises multiple communication devices which can communicate through one or more networks.
  • the system 10 may comprise any combination of wired or wireless networks including, but not limited to a wireless cellular telephone network (such as code division multiple access (CDMA), global systems for mobile communications (GSM), universal mobile telecommunications system (UMTS), time divisional multiple access (TDMA), frequency division multiple access (FDMA)) ), a wireless local area network (WLAN) such as defined by any of the IEEE 802.x standards, a Bluetooth personal area network, an Ethernet local area network, a token ring local area network, a wide area network, and the Internet.
  • a wireless cellular telephone network such as code division multiple access (CDMA), global systems for mobile communications (GSM), universal mobile telecommunications system (UMTS), time divisional multiple access (TDMA), frequency division multiple access (FDMA)
  • WLAN wireless local area network
  • Bluetooth personal area network such as defined by any of the IEEE 802.x standards
  • Ethernet local area network such as Ethernet local area network, a token ring local area network, a wide area network, and the Internet.
  • token ring local area network such
  • the system 10 may include both wired and wireless communication devices or apparatus 50 suitable for implementing embodiments of the invention.
  • the system shown in Figure 3 shows a mobile telephone network 11 and a representation of the internet 28.
  • Connectivity to the internet 28 may include, but is not limited to, long range wireless connections, short range wireless connections, and various wired connections including, but not limited to, telephone lines, cable lines, power lines, and similar communication pathways.
  • the example communication devices shown in the system 10 may include, but are not limited to, an electronic device or apparatus 50, a combination personal digital assistant (PDA) and mobile telephone 14, a PDA 16, an integrated messaging device (IMD) 18, a desktop computer 20, a notebook computer 22.
  • the apparatus 50 may be stationary or mobile when carried by an individual who is moving.
  • the apparatus 50 may also be located in a mode of transport including, but not limited to, a car, a truck, a taxi, a bus, a train, a boat, an aeroplane, a bicycle, a motorcycle or any similar suitable mode of transport.
  • Some or further apparatus may send and receive calls and messages and communicate with service providers through a wireless connection 25 to a base station 24.
  • the base station 24 may be connected to a network server 26 that allows communication between the mobile telephone network 11 and the internet 28.
  • the system may include additional communication devices and communication devices of various types.
  • the communication devices may communicate using various transmission technologies including, but not limited to, code division multiple access (CDMA), global systems for mobile communications (GSM), universal mobile telecommunications system (UMTS), time divisional multiple access (TDMA), frequency division multiple access (FDMA) 1 transmission control protocol-internet protocol (TCP-IP), short messaging service (SMS), multimedia messaging service (MMS), email, instant messaging service (IMS), Bluetooth, IEEE 802.11 and any similar wireless communication technology.
  • CDMA code division multiple access
  • GSM global systems for mobile communications
  • UMTS universal mobile telecommunications system
  • TDMA time divisional multiple access
  • FDMA frequency division multiple access
  • TCP-IP transmission control protocol-internet protocol
  • SMS short messaging service
  • MMS multimedia messaging service
  • email instant messaging service
  • IMS instant messaging service
  • Bluetooth IEEE 802.11 and any similar wireless communication technology.
  • a communications device involves in implementing various embodiments of the present invention may communicate using various media including, but not limited to, radio, infrared, laser, cable connections, and any
  • FIG. 4a a block diagram of a video encoder suitable for carrying out embodiments of the invention is shown. Furthermore, with respect to Figure 5, the operation of the encoder exemplifying embodiments of the invention specifically with respect to the residual macro block encoding process is shown in detail.
  • Figure 4a shows the encoder as comprising a pixel predictor 302, prediction error coder 303 and prediction error decoder 304.
  • the pixel predictor 302 may receive the image from an image store 300 to be encoded at both the inter-predictor 306 (which determines the difference between the image and a reference frame which may be stored in a reference frame memory 318) and the intra-predictor 308 (which determines the image based only on the current frame or picture).
  • the output of both the inter-predictor and the intra- predictor are passed to the mode selector 310.
  • the mode selector 310 also receives a copy of the image 300.
  • the output of the mode selector 310 is the predicted representation of an image block 312 from either the intra-predictor 306 or intra-predictor 308 which is passed to a first summing device 321.
  • the first summing 321 device may subtract the pixel predictor 302 output from the image which may be stored in the image store 300 to produce a first prediction error signal 320 which is input to the prediction error encoder 303.
  • the pixel predictor 302 further receives from a preliminary reconstructor 339 the combination of the prediction representation of the image block 312 which may be the output of the pixel predictor 302 and the output 338 of the prediction error decoder 304.
  • the preliminary reconstructed image may be stored in a preliminary image store 314 and may be passed to the intra-predictor 308 and to a filter 316.
  • the filter 316 receiving the preliminary image representation may filter the preliminary image representation and output a final reconstructed image 340 which may be saved in a reference frame memory 318.
  • the reference frame memory 318 may be connected to the inter-predictor 306 to be used as the reference image against which the image from the image store 300 may be compared against in inter-prediction operations.
  • the operation of the pixel predictor 302 may be configured to carry out any known pixel prediction algorithm known in the art.
  • the image store 300, reference frame memory 318, and preliminary image store 314 are shown as separate structures in some embodiments of the invention the stores and memories are parts of a memory or store.
  • the encoder generates images in terms of 16x16 pixel macroblocks which go to form the full image or picture.
  • the pixel predictor 302 and the first summing device 321 output a series of 16x16 pixel macro-blocks, the pixel predictor 302 outputting 16x16 pixel predicted representation macro-blocks 312 and the first summing device 321 outputting 16x16 pixel prediction error macro- blocks 320 which may represent the difference between a first macro-block in the image against a similar macro-block in the reference image or picture (in the inter- prediction mode) or an image macro-block itself (in the intra-prediction mode). It would be appreciated that other size macro-blocks may be used.
  • the prediction error coder 303 may comprise a controller 355 which controls a block processor 357.
  • the block processor 357 may receive the selected 16x16 pixel residual (or prediction error) macroblock 320.
  • the output of the block processor 351 may be passed to the entropy encoder 330 and also to the prediction error decoder 304.
  • the entropy coder 330 may receive the output of the prediction error encoder and may perform a suitable entropy encoding/variable length encoding on the signal to provide error detection and correction capability. Any suitable entropy encoding algorithm may be employed.
  • the prediction error decoder 304 may receive the output from the prediction error coder 303 and perform the opposite processes of the prediction error coder 303 to produce a decoded prediction error signal 338 which may, when combined with the prediction representation of the image block 312 at the second summing device 339, produce the preliminary reconstructed image.
  • the prediction error decoder 304 may be considered to comprise a block processor 359 which extracts the block values, regenerates the macroblock and, filters the regenerated macroblock according to further decoded information and filter parameters.
  • the prediction error decoder 304 may also comprise a controller 361 for controlling the block processor 359.
  • the prediction error decoder 304 will be discussed in further detail later with reference to the prediction error decoder in the decoder as shown in Figure 6 and described with reference to figure 7.
  • a prediction error coder 303 according to an embodiment of the invention is shown in Figure 4b.
  • the operation and implementation of the prediction error coder 303 according to embodiments of the invention is shown in further detail with respect to Figure 5.
  • the prediction error coder 303 may therefore receive the prediction error macro- block 320, and output an encoded version of the prediction error macro-block to the entropy encoder 320.
  • the encoding process may be divided up into operations of the processing of the pixel values within a selected spatially variable transform window or residual area, the processing of the residual pixel values outside of the spatially variable transform area and a processing of the pixel values bordering the selected spatially variable transform window.
  • the controller 355 may select from a set of candidate residual areas a sub-set or lists of candidate residual areas dependent on some criteria.
  • the criteria may have a single discrete threshold such that when the threshold of the criteria is met the controller selects a first sub-set of candidate residual areas and if the threshold of the criteria is not met the controller 355 selects a second sub-set of the candidate residual areas.
  • the criteria may comprise several thresholds defining intervals wherein the controller 355 associates a sub-set of the candidate residual areas for each interval.
  • the criteria thresholds are fixed and predefined and as such only require the decoder to know of the same threshold values.
  • the criteria thresholds are variable and dependent at least partially on the previously coded images, frames or macro-blocks.
  • the criteria may be signalled to the decoder.
  • the sub-sets may be exclusive to each other, in other words no candidate residual area from one sub-set may be in a different sub-set. In some embodiments of the invention the sub-sets may be inclusive, in which case a candidate residual area in one of the sub-sets may be also in a different sub-set.
  • the candidate residual areas may in embodiments of the invention be defined by a pixel area and position or location within the macro-block.
  • an example 8x8 pixel residual block is shown. From the 16x16 macro block 701 , the 8x8 pixel residual block 703 is located within the macro-block by an offset from the origin of the macro block 701 by an X component, ⁇ X, 705 and a Y component, ⁇ Y, 707. Although in this example the origin of the macro-block is defined with respect to the top left corner of the macro- block it would be understood that the origin may be any suitable position within the macro-block (for example the bottom left of the macro-block).
  • FIG. 8b an example of a 16x4 pixel residual block is shown. From the 16x16 pixel macro block 701 origin the 16x4 pixel residual block 711 is offset by a Y component, ⁇ Y, 713.
  • FIG. 8c an example of a 4x16 pixel residual block is shown. From the 16x16 pixel macro block 701 origin the 4x16 pixel residual block 721 is offset by a X component, ⁇ X, 723.
  • the controller 355 may select a sub-set of candidate residual blocks which significantly reduces the number of candidate residual blocks by having a candidate set only of non-overlapping or contiguous residual blocks.
  • Figure 9 a non-overlapping 8x8 pixel residual block configuration is shown.
  • the 16x16 macro block 701 comprises four non- overlapping and contiguous 8x8 pixel residual blocks.
  • the first pixel residual block 801 is located at the macro block origin (in other words has an X and Y displacement of (0,0)), the second 8x8 pixel residual block 803 is located with a 0 Y-axis displacement but with a 8 pixel X-axis displacement, the third 8x8 pixel residual block 805 is shown with a 8 pixel Y-axis displacement and a 0 X-axis displacement and the fourth 8x8 SVT transform block 807 is shown with a 8 pixel X-axis and Y-axis displacement.
  • FIG. 10a With respect to Figure 10a, four 16x4 pixel non-overlapping and contiguous residual blocks are shown.
  • a first 16x4 pixel residual block 901 with a 0 pixel Y-axis offset or displacement there is a second 16x4 pixel residual block 903 with a 4 pixel Y-axis offset, a third 16x4 pixel residual block 905 with a 8 pixel Y-axis offset, and a fourth 16x4 pixel residual block 907 with a 12 pixel Y-axis offset.
  • the 16x16 macro block 701 has a first 4x16 pixel residual block 911 with a 0 pixel X-axis offset or displacement, a second 4x16 pixel residual block 913 with a 4 pixel X-axis displacement, a third 4x16 pixel residual block 915 with an 8 pixel X-axis displacement and a fourth 4x16 pixel residual block 917 with a 12 pixel X-axis displacement.
  • the number of candidates pixel residual blocks within the candidate set may be significantly reduced.
  • signalling bit overheads for transmitting the index of the selected residual block from the list of candidate blocks may be reduced as there are fewer initial candidate positions to select from.
  • the encoder may signal to the decoder how the macro-block is partitioned and the remaining syntax of the macro-block may not to be changed. This is because the positions of the transform blocks are not varying but fixed.
  • the controller 355 may in some embodiments of the invention select the sub-sets of candidate residual blocks from a 'global' or 'universal' set of candidate residual blocks. In such embodiments the controller 355 may thus select from the 'universal' set of possible candidate sub-sets or lists the list or sub-set of candidate pixel residual blocks to be used.
  • overlapping and non-overlapping pixel residual blocks may constitute a sub-set or list of pixel residual blocks.
  • the selection criteria used to select a set or sub-set of candidate residual blocks from the 'universal' set of candidate pixel residual blocks may be any suitable criteria.
  • the selection criteria may be at least one of: the processing power of the apparatus; the frame or slice period; the memory capacity of the apparatus; the full picture size; and the desired bitrate for the encoded video.
  • the candidate set selected may have a large number of potential candidates from which the spatially variable transform pixel residual block is selected from.
  • the large number of possible candidates to be tested provides a high quality video stream at the cost of the processing time to analyse each of the possible candidates and also the bits required to signal to the decoder which one of the candidates from the list the spatially variable transform pixel residual block is in order to successfully decode the signal.
  • the selected candidate set may be a small or short list of potential candidates from which the spatially variable transform pixel residual block is selected from. This thus may introduce possible image error but enable the processor to maintain a sufficient encoding frame rate.
  • the criteria used to select a set of pixel residual blocks from the complete set of candidate pixel residual blocks may be a bit rate / distortion trade off or optimisation. In other words to select a set which attempts to minimize the cost function
  • C D+ ⁇ R
  • C the Lagrangian cost to be minimised
  • ⁇ a weighting factor
  • D the image distortion (in other words the mean-squared error) with the mode and motion vectors currently considered
  • R the number of bits needed to represent the required data to reconstruct the image block in the decoder (including the amount of data to represent the candidate motion vectors).
  • the candidate selection may be explicitly coded into the indication of different block size transformation and location parameters in the bit stream and transmitted in the slice and picture header information.
  • the candidate set or list selection criteria used by the controller 355 may be dependent on previously encoded information.
  • the decoder may determine the criteria based on decoded previously encoded information the selection may not be explicitly signalled in some embodiments of the invention.
  • the controller 355 may be designed so that if the number of bits per pixel used in previous picture or slice is less than a threshold value then the controller 355 selects or set of pixel residual blocks as the 16x4 pixel or 4x16 pixel residual blocks for the current slice.
  • this set or list of pixel residual blocks there are a total 8 possible candidate pixel residual block positions.
  • the controller 355 and the entropy encoder 330 as described later may then signal which of the pixel residual blocks used using only three bits (where a fixed length code is used).
  • step 500 The selection of the set (or sub-sets) of candidate pixel residual blocks from the 'universal' set of pixel residual blocks is shown in figure 5 by step 500.
  • the spatially varying transform (SVT) block selector 371 receives the 16x16 pixel residual macro block prediction error from the first adder 321.
  • the controller 355 then controls the SVT block selector 371 to select one out of the selected set or list of possible candidate pixel residual block positions and sizes.
  • the controller 355 may initiate a loop control mechanism where the block selector 371 selects a residual block or residual area from the 16x16 pixel residual macro block.
  • the residual block selected from the 16x16 pixel residual macro block may be an 8x8, 16x4, or 4x16 or any size or position pixel residual block from the set selected in the operation described above.
  • the controller 355 may perform a parallel or semi-parallel operation where more than one of the candidate pixel residual blocks are operated on at a time.
  • the SVT block selector 371 outputs the pixel residual block to the transformer 373.
  • the selection of the block from the macro block is shown in Figure 5 by step 503.
  • the transformer 373 then transforms the residual transform block using any suitable transformation.
  • the discrete cosine transform (DCT) is used to exploit the correlation between the original image and the pixel predicted image as a frequency domain two- dimensional array.
  • DCT discrete cosine transform
  • other suitable space to frequency domain transform may be implemented by the transformer 373.
  • the output of the transformer 373 is input to the quantiser 375.
  • quantiser 375 performs a suitable quantisation on the pixel residual block. Any suitable quantisation scheme may be employed including but not exclusively vector quantisation. In other embodiments of the invention each frequency coefficient value (from the transformer) may be quantised independently.
  • the output of the quanitser 375 is passed to the error coder tester 381.
  • the operation of applying quantisation to the transformed pixel residual block is shown in Figure 5 by step 507.
  • the residual value generator 377 furthermore generates a reconstruction value for the residual pixels in the remainder of the 16x16 pixel residual macroblock not selected as the pixel residual block.
  • the reconstruction values for the residual pixels in the remaining part of the 16x16 pixel residual macroblock may in an embodiment of the invention be set to zero.
  • the residual pixel values in the part of the 16x16 residual macroblock which are not selected for transform may either be represented individually or jointly.
  • each one of the pixels in the remaining area may be represented by a fixed value where each value may be selected from the following set of values -1 (11 , 2bits) 0 (0, 1 bit), 1 (10, 2bits).
  • all the remaining pixel values may be represented as a single value selected from the above set of values.
  • the output of the residual value generator 377 is input to the error coder tester 381.
  • step 509 The generation of the reconstruction value for the remainder of 16x16 pixel residual macroblock operation is shown in Figure 5 by step 509.
  • the error coder tester 381 having received the output of the quantiser 375, the residual value generator 377 and the prediction error macroblock compares a reconstructed combination of the quantiser 375 and residual value generator 377 against the original macroblock.
  • the error coder tester 381 determines the mean square error (or some other error value).
  • step 511 The operation of testing the error between the transformed and the quantised pixel transformed block in combination with the reconstruction value for the remainder of 16x16 residual macroblock and the input 16x16 residual macroblock 801 is shown in Figure 5 by step 511.
  • the controller 355 may then determine whether or not all reconstruction value options in the selected set or list have been tested. This operation is shown in
  • step 513 If all reconstruction value options have not been tested, the operation passes back to the step 509 and a further reconstruction value option is generated and tested. If all reconstruction value options have been tested, the operation passes to the step of determining whether all pixel transformation block options have been tested.
  • the controller 355 further determines whether or not all pixel transformation block 81 1 options from the selected set have been tested. If at least one pixel transform block option remains to be operated on the operation passes back to step 503 where a further pixel transform block option is selected. Otherwise, the operation passes to the next step of selecting the lowest offset and reconstruction values with the lowest error.
  • the operation of checking whether or not all pixel transform block options have been selected is shown in Figure 5 by step 515.
  • the controller 355 may output the pixel residual block selection information 387 to the entropy encoder 330.
  • the selection of the pixel residual block and the passing of information on the selection of the pixel residual block is shown in figure 5 by step 517.
  • the error coder tester 381 may also pass the selected pixel residual block to the block filter 383.
  • the block filter 383 may then determine if internal filtering for the
  • the filtering may be deblocking filtering and may in embodiments of the invention be deblocking filtering similar to the filter used for the reconstructed frame.
  • the details of the filter may be further encoded and sent to the entropy encoder together with the filtered data as the prediction error coded data 385.
  • the operation of internal filtering is shown in figure 5 by step 519.
  • the filter 383 may in some embodiments of the invention perform an external 16x16 pixel residual macroblock filtering operation where the selected pixel residual block boundary coincides with the macroblock boundary.
  • the operation of external filtering is shown in figure 5 by step 521.
  • none, one of, or both of the internal and external filtering processes may be performed.
  • the operations of filter determination may be carried out during the testing of the cost function.
  • the cost of the filtering in terms of the processing and signalling information required to be transferred may also be used as a factor in the cost function determination and as such the configuration of the filtering of the macroblocks may be determined dependent on the cost function optimisation process.
  • apparatus comprising a controller configured to select a first set of transform blocks from a second set of transform blocks dependent on a criteria, wherein each transform block is defined by a pixel area in a block of pixels; and a processor configured to transform a pixel area defined by at least one of the first set of transform blocks selected pixel area.
  • a controller may be considered to be configured to select one of at least two sets of transform blocks dependent on the criteria, wherein each transform block defines by a pixel area in a block of pixels.
  • a processor configured to transform a pixel area defined by at least one of the set of transform blocks selected pixel area.
  • the entropy encoder 330 receives the prediction error coded data and the pixel residual block selection information and may encode this information in a suitable manner. The encoding of these values is shown in Figure 5 by step 523.
  • the 8x8 pixel block is encoded using spatial coding in other words is not transformed.
  • the reconstruction value of the remainder of the residual macroblock may be determined dependent on the quantisation step and signalled separately in the sequence or the picture header.
  • the coefficient of the spatially varying transform are coded using entropy coding methods such as variable length coding tables.
  • the prediction error decoder 304 is described in further detail with respect to the decoder shown in Figure 6 and described with reference to Figure 7 described below.
  • Figure 6 shows a block diagram for a video decoder suitable for employing embodiments of the invention.
  • the decoder shows an entropy decoder 600 which performs entropy decoding on the received signal.
  • the entropy decoder 600 thus performs the inverse operation to the entropy encoder 330 of the encoder described above.
  • the entropy decoder outputs the results of the entropy decoding to a prediction error decoder 304 and the pixel predictor 604.
  • the pixel predictor 604 receives the output of the entropy decoder.
  • the pixel predictor 604 comprises a predictor selector 614 which determines that either an intra-prediction or an inter-prediction operation is to be carried out.
  • the predictor selector 614 furthermore outputs a predicted representation of an image block 312 to a first combiner 613.
  • the predicted representation of the image block 312 is used in conjunction with the reconstructed prediction error signal 338 received from the prediction error decoder 304 to generate a preliminary image which may be stored in the preliminary image store 618.
  • the preliminary reconstructed image store 618 may output a preliminary reconstructed image which may be used in the predictor 614 or may be passed to a filter 620.
  • the filter 620 applies a filtering which outputs the final predicted signal 340.
  • the final predicted signal 340 may be stored in a reference frame memory 624.
  • the reference frame memory 620 further being connected to the predictor 614 for prediction operations.
  • the operation of the prediction error decoder 304 is similar to the encoder prediction error decoder 304 and will be described in further detail below.
  • the prediction error decoder has a block processor 359 and a controller 361.
  • the prediction error decoder 304 is further described with regards to Figure 4c and the operation of the decoder is described in further detail with respect to the flow diagram of Figure 7.
  • the prediction error decoder 304 receives both the predicted error coded data 385 and also the pixel residual block selection information 387 from the entropy decoder 600 (or from the prediction error coder 303 in the encoder device).
  • the block selection information decoder 602 may receive this information and select the 16x16 pixel macroblock to regenerate.
  • the selection of the 16x16 pixel residual macroblock to be regenerated is shown in step 701.
  • the block selection information decoder 602 furthermore may receive the information from the entropy decoder 600 and separate and decodes these values to select the encoded pixel residual block.
  • the decoding of this information from the pixel residual block selection information 387 is shown in Figure 7 by step 703.
  • the dequantiser 604 may dequantise the selected pixel residual block information from the prediction error coded data 385.
  • the output of the dequantiser 604 is output to the inverse transformer 606.
  • the dequantisation of the pixel transform block is shown in Figure 7 by step 705.
  • the inverse transformer 606 may perform an inverse transformation on the selected dequantised pixel residual block.
  • the inverse transformation carried out is dependent upon the transformation carried out within the encoder.
  • the output of the inverse transformer 606 is input to the combiner and filter 608.
  • step 707 The operation of performing the inverse transformation is shown in Figure 7 by step 707.
  • the reconstructor 610 furthermore decodes the reconstruction values and sets the remainder of the 16x16 pixel residual macroblock to a value dependent on the reconstruction value.
  • the output of the reconstructor 610 is input to the combiner and filter 608.
  • the decoding and reconstruction of the remainder of the 16x16 pixel residual macroblock is shown in Figure 7 by step 709.
  • the block combiner and filter 608 receives the combined data from the inverse transformer 606 and the reconstructor 610 and may combine the value to generate a reconstructed 16x16 pixel macroblock.
  • the reconstruction of the macroblock is shown in Figure 7 by step 711.
  • block combiner and filter 608 may also perform any internal or external edge filtering in a manner similar to that performed by the encoder.
  • the filtering of the internal/external edges is shown in Figure 7 by step 713.
  • the combiner and filter 608 thus output the reconstructed 16x16 pixel residual macroblock to be combined with the current reference image output by the intra- prediction operation or inter-prediction operation to create a preliminary reconstructed image 338 as described above.
  • step 715 The outputting of the reconstructed residual macroblock is shown in Figure 7 by step 715.
  • apparatus comprising: a controller configured to determine a set of pixel areas within a block of pixels; and a processor configured to select a pixel area from the set of pixel areas within the block of pixels dependent on a first part of a signal; and regenerate a first set of pixel values for the pixel area dependent on a second part of the signal
  • user equipment may comprise a video codec such as those described in embodiments of the invention above.
  • user equipment is intended to cover any suitable type of wireless user equipment, such as mobile telephones, portable data processing devices or portable web browsers.
  • PLMN public land mobile network
  • elements of a public land mobile network may also comprise video codecs as described above.
  • the various embodiments of the invention may be implemented in hardware or special purpose circuits, software, logic or any combination thereof.
  • some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto.
  • firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto.
  • While various aspects of the invention may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.
  • the embodiments of this invention may be implemented by computer software executable by a data processor of the mobile device, such as in the processor entity, or by hardware, or by a combination of software and hardware.
  • any blocks of the logic flow as in the Figures may represent program steps, or interconnected logic circuits, blocks and functions, or a combination of program steps and logic circuits, blocks and functions.
  • the software may be stored on such physical media as memory chips, or memory blocks implemented within the processor, magnetic media such as hard disk or floppy disks, and optical media such as for example DVD and the data variants thereof, CD.
  • the memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor-based memory devices, magnetic memory devices and systems, optical memory devices and systems, fixed memory and removable memory.
  • the data processors may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASIC), gate level circuits and processors based on multi-core processor architecture, as non-limiting examples.
  • Embodiments of the inventions may be practiced in various components such as integrated circuit modules.
  • the design of integrated circuits is by and large a highly automated process.
  • Complex and powerful software tools are available for converting a logic level design into a semiconductor circuit design ready to be etched and formed on a semiconductor substrate.

Abstract

L'invention concerne un appareil comprenant un processeur configuré pour sélectionner un premier ensemble de blocs de transformation à partir d'un second ensemble de blocs de transformation dépendant d'un critère, chaque bloc de transformation étant défini par une zone de pixel dans un bloc de pixels; et transformer une zone de pixel définie par au moins un bloc du premier ensemble de blocs de transformation de la zone de pixel sélectionnée.
PCT/IB2010/050703 2009-04-07 2010-02-17 Procédé et appareil pour coder et décoder une image et une vidéo WO2010116268A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0906058A GB0906058D0 (en) 2009-04-07 2009-04-07 An apparatus
GB0906058.3 2009-04-07

Publications (1)

Publication Number Publication Date
WO2010116268A1 true WO2010116268A1 (fr) 2010-10-14

Family

ID=40750282

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2010/050703 WO2010116268A1 (fr) 2009-04-07 2010-02-17 Procédé et appareil pour coder et décoder une image et une vidéo

Country Status (2)

Country Link
GB (1) GB0906058D0 (fr)
WO (1) WO2010116268A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2680584A1 (fr) * 2011-08-31 2014-01-01 Huawei Technologies Co., Ltd Procédé et module d'acquisition d'informations de localisation d'un bloc de transformée
WO2017039501A1 (fr) * 2015-09-01 2017-03-09 Telefonaktiebolaget Lm Ericsson (Publ) Perfectionnement spatial de blocs de transformée
WO2019076290A1 (fr) * 2017-10-16 2019-04-25 Huawei Technologies Co., Ltd. Transformées variant dans l'espace pour un codage vidéo
CN110719477A (zh) * 2018-07-11 2020-01-21 腾讯美国有限责任公司 视频编解码的方法、装置、计算机设备及计算机可读存储介质
US11006139B2 (en) 2017-10-16 2021-05-11 Huawei Technologies Co., Ltd. Encoding method and apparatus
US11252426B2 (en) 2018-05-31 2022-02-15 Huawei Technologies Co., Ltd. Spatially varying transform with adaptive transform type
US11388402B2 (en) 2018-02-23 2022-07-12 Huawei Technologies Co., Ltd. Position dependent spatial varying transform for video coding

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821119A (en) * 1988-05-04 1989-04-11 Bell Communications Research, Inc. Method and apparatus for low bit-rate interframe video coding
EP0811951A2 (fr) * 1996-06-07 1997-12-10 Lsi Logic Corporation Système et méthode d'estimation de mouvement dans le domaine DCT, à rendement amélioré
US20030156648A1 (en) * 2001-12-17 2003-08-21 Microsoft Corporation Sub-block transform coding of prediction residuals
US20080232705A1 (en) * 2007-03-23 2008-09-25 Samsung Electronics Co., Ltd. Method and apparatus for image encoding and image decoding
WO2008152573A2 (fr) * 2007-06-12 2008-12-18 Nokia Corporation Codage conjoint de multiples blocs de transformée avec un nombre réduit de coefficients

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4821119A (en) * 1988-05-04 1989-04-11 Bell Communications Research, Inc. Method and apparatus for low bit-rate interframe video coding
EP0811951A2 (fr) * 1996-06-07 1997-12-10 Lsi Logic Corporation Système et méthode d'estimation de mouvement dans le domaine DCT, à rendement amélioré
US20030156648A1 (en) * 2001-12-17 2003-08-21 Microsoft Corporation Sub-block transform coding of prediction residuals
US20080232705A1 (en) * 2007-03-23 2008-09-25 Samsung Electronics Co., Ltd. Method and apparatus for image encoding and image decoding
WO2008152573A2 (fr) * 2007-06-12 2008-12-18 Nokia Corporation Codage conjoint de multiples blocs de transformée avec un nombre réduit de coefficients

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
CIXUN ZHANG ET AL: "Video Coding Using Spatially Varying Transform", LECTURE NOTES IN COMPUTER SCIENCE; PROCEEDINGS OF THE 3RD PACIFIC RIM SYMPOSIUM ON ADVANCES IN IMAGE AND VIDEO TECHNOLOGY, vol. 5414, - 13 January 2009 (2009-01-13), pages 796 - 806, XP007907612 *

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2680584A1 (fr) * 2011-08-31 2014-01-01 Huawei Technologies Co., Ltd Procédé et module d'acquisition d'informations de localisation d'un bloc de transformée
EP2680584A4 (fr) * 2011-08-31 2014-05-21 Huawei Tech Co Ltd Procédé et module d'acquisition d'informations de localisation d'un bloc de transformée
US9401031B2 (en) 2011-08-31 2016-07-26 Huawei Technologies Co., Ltd. Method and module for acquiring position information of transform block
EP3142364A1 (fr) * 2011-08-31 2017-03-15 Huawei Technologies Co., Ltd. Procédé et module pour acquérir des informations de position de bloc de transformation
US9866847B2 (en) 2011-08-31 2018-01-09 Huawei Technologies Co., Ltd. Method and module for acquiring position information of transform block
WO2017039501A1 (fr) * 2015-09-01 2017-03-09 Telefonaktiebolaget Lm Ericsson (Publ) Perfectionnement spatial de blocs de transformée
US10080038B2 (en) 2015-09-01 2018-09-18 Telefonaktiebolaget Lm Ericsson (Publ) Spatial improvement of transform blocks
US11006139B2 (en) 2017-10-16 2021-05-11 Huawei Technologies Co., Ltd. Encoding method and apparatus
US11343523B2 (en) 2017-10-16 2022-05-24 Huawei Technologies Co., Ltd. Coding method and apparatus
CN111226441A (zh) * 2017-10-16 2020-06-02 华为技术有限公司 视频编码的空间变化变换
WO2019076290A1 (fr) * 2017-10-16 2019-04-25 Huawei Technologies Co., Ltd. Transformées variant dans l'espace pour un codage vidéo
CN111226441B (zh) * 2017-10-16 2021-10-15 华为技术有限公司 视频编码的空间变化变换方法及相关设备
US11956455B2 (en) 2017-10-16 2024-04-09 Huawei Technologies Co., Ltd. Coding method and apparatus
US11606571B2 (en) 2017-10-16 2023-03-14 Huawei Technologies Co., Ltd. Spatial varying transform for video coding
US11523129B2 (en) 2017-10-16 2022-12-06 Huawei Technologies Co., Ltd. Encoding method and apparatus
US11388402B2 (en) 2018-02-23 2022-07-12 Huawei Technologies Co., Ltd. Position dependent spatial varying transform for video coding
US11917152B2 (en) 2018-02-23 2024-02-27 Huawei Technologies Co., Ltd. Position dependent spatial varying transform for video coding
US11601663B2 (en) 2018-05-31 2023-03-07 Huawei Technologies Co., Ltd. Spatially varying transform with adaptive transform type
US11252426B2 (en) 2018-05-31 2022-02-15 Huawei Technologies Co., Ltd. Spatially varying transform with adaptive transform type
CN114900695A (zh) * 2018-07-11 2022-08-12 腾讯美国有限责任公司 视频编解码的方法、装置、计算机设备及计算机可读存储介质
CN110719477A (zh) * 2018-07-11 2020-01-21 腾讯美国有限责任公司 视频编解码的方法、装置、计算机设备及计算机可读存储介质
CN110719477B (zh) * 2018-07-11 2022-03-25 腾讯美国有限责任公司 视频编解码的方法、装置、计算机设备及计算机可读存储介质

Also Published As

Publication number Publication date
GB0906058D0 (en) 2009-05-20

Similar Documents

Publication Publication Date Title
US20210409756A1 (en) Method for video coding and an apparatus
US11368700B2 (en) Apparatus, a method and a computer program for video coding
US8724692B2 (en) Apparatus, a method and a computer program for video coding
KR101215682B1 (ko) 공간적으로 가변하는 변환을 이용하는 비디오 코딩 장치, 방법 및 컴퓨터 판독가능 저장 매체
US8848801B2 (en) Apparatus, a method and a computer program for video processing
US20130094776A1 (en) Method for coding and an apparatus
US20120243606A1 (en) Methods, apparatuses and computer programs for video coding
US9432699B2 (en) Methods, apparatuses and computer programs for video coding
WO2010116268A1 (fr) Procédé et appareil pour coder et décoder une image et une vidéo
WO2010051846A1 (fr) Algorithme de sélection de blocs rapide pour le codage vidéo utilisant une transformation variable dans l'espace

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10761251

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10761251

Country of ref document: EP

Kind code of ref document: A1