WO2010114278A2 - Flexible substrate, and solar cell using same - Google Patents
Flexible substrate, and solar cell using same Download PDFInfo
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- WO2010114278A2 WO2010114278A2 PCT/KR2010/001926 KR2010001926W WO2010114278A2 WO 2010114278 A2 WO2010114278 A2 WO 2010114278A2 KR 2010001926 W KR2010001926 W KR 2010001926W WO 2010114278 A2 WO2010114278 A2 WO 2010114278A2
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- substrate
- layer
- flexible substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 95
- 230000009975 flexible effect Effects 0.000 title claims abstract description 48
- 230000004888 barrier function Effects 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 230000008018 melting Effects 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 32
- 229910001374 Invar Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 4
- 239000000463 material Substances 0.000 abstract description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 21
- 238000006243 chemical reaction Methods 0.000 description 12
- 238000002425 crystallisation Methods 0.000 description 11
- 238000010438 heat treatment Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 230000008025 crystallization Effects 0.000 description 9
- 230000005693 optoelectronics Effects 0.000 description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001017 electron-beam sputter deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000000313 electron-beam-induced deposition Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
- H02S30/00—Structural details of PV modules other than those related to light conversion
- H02S30/20—Collapsible or foldable PV modules
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Definitions
- the present invention relates to a flexible substrate and a solar cell using the same. More specifically, the present invention relates to a flexible substrate and a solar cell using the same, which can prevent the substrate from being deformed in the heat treatment of the semiconductor layer formed on the substrate.
- Flexible substrate technology includes display devices such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), or photoelectric devices such as thin-film type solar cells. It is a core technology that improves the portability of the device and at the same time, various installation places thereof such as windows, automobiles, exterior walls of houses or buildings.
- LCDs liquid crystal displays
- OLEDs organic light emitting diodes
- photoelectric devices such as thin-film type solar cells.
- Such flexible substrates include plastic-based substrates and metal-based substrates, and a technique using a metal foil-type flexible substrate capable of simultaneously performing an electrode function with excellent heat resistance is generally used. have.
- such a high temperature crystallization process may cause unnecessary chemical reaction between the flexible substrate and the semiconductor layer (silicon layer), thereby degrading the characteristics of the solar cell or peeling the semiconductor layer from the flexible substrate.
- the present invention is to solve the above problems of the prior art, an object of the present invention is to provide a flexible substrate that can absorb the residual stress generated during the solar cell manufacturing process.
- Another object of the present invention is to provide a flexible substrate capable of preventing chemical reactions at the interface between the substrate and the semiconductor layer.
- Another object of the present invention is to provide a flexible substrate capable of preventing the thin film (for example, a semiconductor layer) formed on the flexible substrate from being peeled off.
- Another object of the present invention is to provide a solar cell having improved photoelectric conversion efficiency and increased reliability and lifetime.
- the flexible substrate includes a buffer layer to absorb stress to prevent the occurrence of warpage of the substrate.
- the flexible substrate includes a barrier layer to prevent diffusion between layers and to improve interface characteristics.
- the photoelectric conversion efficiency of the solar cell can be improved and life and reliability can be increased.
- FIG 1 and 2 are views showing a process for manufacturing a flexible substrate according to an embodiment of the present invention.
- FIGS. 4 and 5 are views illustrating a manufacturing process of a solar cell using a flexible substrate according to an embodiment of the present invention.
- FIG. 6 is a cross-sectional view of another type of solar cell using a flexible substrate according to an embodiment of the present invention.
- the object of the present invention is a substrate of a conductive material; A buffer layer formed on the substrate but having a lower melting point than the substrate; And it is achieved by a flexible substrate comprising a barrier layer formed on the buffer layer.
- the object of the present invention is a substrate of a conductive material; A buffer layer formed on the substrate but having a lower melting point than the substrate; A barrier layer formed on the buffer layer; A semiconductor layer formed on the barrier layer; And it is also achieved by a solar cell comprising an upper electrode formed on the semiconductor layer.
- the buffer layer may be Al.
- the barrier layer may be TiN.
- the barrier layer may have a stacked structure of Ti / TiN / Ti.
- the substrate may be a sus (SUS) or an invar.
- the semiconductor layer comprises a first polycrystalline semiconductor layer; A second polycrystalline semiconductor layer formed on the first polycrystalline semiconductor layer; And a third polycrystalline semiconductor layer formed on the second polycrystalline semiconductor layer.
- a flexible substrate is to be understood as a generic term for a substrate capable of forming an electronic device that can be driven by an electrical stimulus using a metal foil as a substrate.
- FIG 1 and 2 are views showing a process for manufacturing a flexible substrate according to an embodiment of the present invention.
- a substrate 100 having a flexible property is provided, and the material of the substrate 100 may be stainless steel or invar manufactured in the form of a metal foil. .
- a buffer layer 110 may be formed on the substrate 100 to absorb residual stresses generated during the subsequent high temperature heat treatment.
- the buffer layer 110 may be formed by electron beam evaporation or sputtering. It may be formed by using physical vapor deposition (PVD), such as (sputtering).
- the buffer layer 110 preferably uses a metal such as aluminum (Al) having a lower melting point than that of the substrate 100, which is melted during high temperature heat treatment (for example, when the amorphous silicon layer is crystallized). This is because a function of absorbing residual stress generated in the thin film layer (for example, the semiconductor layer) formed on the substrate 100 and the substrate 100 can be performed.
- a metal such as aluminum (Al) having a lower melting point than that of the substrate 100, which is melted during high temperature heat treatment (for example, when the amorphous silicon layer is crystallized).
- a barrier layer 120 may be further formed on the buffer layer 110.
- the barrier layer 120 may be a physical vapor deposition method such as electron beam deposition or sputtering, or a plasma chemical vapor deposition method (Plasma).
- Chemical Vapor Deposition (CVD) such as Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD) and Metal Organic Chemical Vapor Deposition (MOCVD) Can be formed.
- PECVD Enhanced Chemical Vapor Deposition
- LPCVD Low Pressure Chemical Vapor Deposition
- MOCVD Metal Organic Chemical Vapor Deposition
- the barrier layer 120 may be formed of titanium nitride (TiN) to effectively prevent diffusion between the substrate 100 and the semiconductor layer in a high temperature heat treatment process.
- TiN titanium nitride
- the multilayer structure includes TiN to improve the interfacial properties to improve the adhesion between the barrier layer 120 and the semiconductor layer to be formed thereon.
- the barrier layer 120 may use a titanium / titanium nitride / titanium (Ti / TiN / Ti) structure, but the present invention is not limited thereto.
- a predetermined semiconductor layer was formed on a conventional flexible substrate, and the state of the substrate was photographed after performing a crystallization process.
- an amorphous silicon layer was formed as a semiconductor layer on a stainless steel substrate 100 having a foil shape having a thickness of 200 ⁇ m. Subsequently, heat treatment was performed at a temperature of 650 ° C. to crystallize the amorphous silicon layer into a polycrystalline silicon layer, and then the state of the substrate 100 was observed.
- the buffer layer 110 and the barrier layer 120 are formed on the substrate 100, the predetermined semiconductor layer is formed thereon, and the crystallization process is performed, like the flexible substrate according to the exemplary embodiment of the present invention.
- a 40 nm thick Al buffer layer 110 was formed by sputtering on a 200 ⁇ m-thick foil-shaped stainless steel substrate 100.
- a barrier layer 120 having a stacked structure of Ti (100 nm) / TiN (300 nm) / Ti (40 nm) was formed on the Al buffer layer 110 by sputtering.
- an amorphous silicon layer was formed on the barrier layer 120 as a semiconductor layer.
- heat treatment was performed at a temperature of 650 ° C. to crystallize the amorphous silicon layer into a polycrystalline silicon layer, and then the state of the substrate was observed.
- the warpage phenomenon 10 and the reaction region 20 can be clearly identified with the naked eye (see FIG. 3A).
- the substrate 100 according to the experimental example it can be seen that neither the warpage phenomenon 10 nor the reaction region 20 exist (see FIG. 3B).
- the flexible substrate 100 has a function of preventing the bending of the substrate 100 by suppressing the occurrence of residual stress during high temperature heat treatment by providing the buffer layer 110.
- the barrier layer 120 is provided, a function of suppressing diffusion between the substrate 100 and the semiconductor layer during the high temperature heat treatment and improving the interface characteristics may be performed.
- FIGS. 4 and 5 are cross-sectional views of a solar cell using a flexible substrate according to an embodiment of the present invention.
- three amorphous silicon layers 210, 220, and 230 are examples of semiconductor layers.
- the first amorphous silicon layer 210 is formed on the barrier layer 120, and then the second amorphous silicon layer 220 is formed on the first amorphous silicon layer 210, followed by the second amorphous silicon layer 210.
- the third amorphous silicon layer 230 may be formed on the silicon layer 220.
- the first to third amorphous silicon layers 210, 220, and 230 may be formed using chemical vapor deposition such as PECVD or LPCVD.
- a process of crystallizing the first, second, and third amorphous silicon layers 210, 220, and 230 may be performed. That is, the first amorphous silicon layer 210 is the first polycrystalline silicon layer 211, the second amorphous silicon layer 220 is the second polycrystalline silicon layer 221, and the third amorphous silicon layer 230 is formed of the first amorphous silicon layer 210. Each of the three polycrystalline silicon layers 231 is crystallized. As a result, the photoelectric device 200 including the first, second, and third polycrystalline silicon layers 211, 221, and 231 is formed on the barrier layer 120.
- the photovoltaic device 200 is a structure in which a polycrystalline silicon layer is stacked and a pin diode in which p-type, i-type, and n-type polycrystalline silicon layers are stacked in order to generate power using photovoltaic power generated by receiving light. Can be.
- the i type means intrinsic without impurities.
- Crystallization methods of the first, second, and third amorphous silicon layers 210, 220, and 230 may include Solid Phase Crystallization (SPC), Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), And MILC (Metal Induced Lateral Crystallization). Since the crystallization method of the amorphous silicon is a known technique, a detailed description thereof will be omitted herein.
- SPC Solid Phase Crystallization
- ELA Excimer Laser Annealing
- SLS Sequential Lateral Solidification
- MIC Metal Induced Crystallization
- MILC Metal Induced Lateral Crystallization
- the first, second, and third amorphous silicon layers 210, 220, and 230 are all formed, and the layers are simultaneously crystallized, but the present invention is not limited thereto.
- the crystallization process may be performed separately for each amorphous silicon layer, and the two amorphous silicon layers may simultaneously undergo a crystallization process and the other amorphous silicon layer may be separately crystallized.
- the first polycrystalline silicon layer 211, the second polycrystalline silicon layer 221, and the third polycrystalline silicon layer 231 may further perform a defect removal process to further improve the properties of the polycrystalline silicon.
- the polycrystalline silicon layer may be subjected to high temperature heat treatment or hydrogen plasma treatment to remove defects (eg, impurities and dangling bonds) present in the polycrystalline silicon layer.
- an upper electrode 400 of a transparent conductive material is formed on the third polycrystalline silicon layer 231.
- the material of the upper electrode 400 may be any one of indium tin oxide (ITO), ZnO, BZO (ZnO: B), IZO (ZnO: In), AZO (ZnO: Al), and FTO (SnO 2 : F). Preferred but not necessarily limited thereto.
- the method of forming the upper electrode 400 may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.
- the lower electrode becomes the flexible substrate 100 itself. Therefore, when the solar cell module is manufactured using the solar cell of FIG. 5 as a unit cell as described above, the flexible substrate 100 of the solar cell and the upper electrode of the solar cell adjacent to the solar cell are not shown. Can be electrically connected.
- the optoelectronic device 200 is formed on the flexible substrate 100 on which the buffer layer 110 and the barrier layer 120 are formed as described above, the curvature of the substrate, the peeling of the semiconductor layer, and the chemical reaction between the substrate and the semiconductor layer may be suppressed. It can improve the photoelectric conversion efficiency of solar cells and can also expect the effect of increasing the reliability and lifespan.
- FIG. 6 is a cross-sectional view of another type of solar cell using a flexible substrate according to an embodiment of the present invention.
- another optoelectronic device 300 may be further formed on the optoelectronic device 200 described above.
- the optoelectronic device 300 has a structure in which an amorphous semiconductor layer is stacked, for example, three layers.
- the amorphous silicon layers 310, 320, and 330 may be formed.
- the first amorphous silicon layer 310 is formed on the photoelectric device 200 positioned below, and the second amorphous silicon layer 320 is formed on the first amorphous silicon layer 310. Subsequently, a third amorphous silicon layer 330 is formed on the second amorphous silicon layer 320 to form a photoelectric device 300 having a pin diode structure such as the photoelectric device 300.
- the first, second, and third amorphous silicon layers 310, 320, and 330 may be formed using chemical vapor deposition such as PECVD or LPCVD.
- an upper electrode 400 of a transparent conductive material is formed on the third amorphous semiconductor layer 330.
- the material and manufacturing method of the upper electrode 400 are the same as described with reference to FIG. 5.
- connection layer of a transparent conductive material may be further formed between the third polycrystalline silicon layer 231 and the first amorphous silicon layer 310.
- the connection layer may be any one of ITO, AZO (ZnO: Al), GZO (ZnO: Ga), BZO (ZnO: B), and FTO (SnO 2 : F), which may transmit light.
- the formation method of the connection layer may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.
- connection layer allows ohmic contact between the third polycrystalline silicon layer 231 and the first amorphous silicon layer 310, and as a result, better photoelectric conversion efficiency of the solar cell can be expected.
- a tandem solar cell including the optoelectronic device 200 made of a polycrystalline silicon layer and the optoelectronic device 300 made of an amorphous silicon layer may be obtained.
- the photoelectric device 200 is made of a polycrystalline silicon layer, the photoelectric conversion efficiency is good for the long wavelength light, and the photoelectric device 300 is made of the amorphous silicon layer, and thus the photoelectric conversion efficiency is good for the short wavelength light. Do. Therefore, the tandem structured solar cell according to the present invention can absorb light in various wavelength bands, thereby improving photoelectric conversion efficiency.
- the optoelectronic devices 200 and 300 are stacked as an example.
- the optoelectronic devices may be stacked in double or more as necessary.
- the optoelectronic devices 200 and 300 may use n-i-p type, p-n type, n-p type or the like instead of p-i-n type.
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Abstract
Disclosed are a flexible substrate, and a solar cell using same. The flexible substrate and the solar cell using same according to the present invention comprise: a substrate (100) made of a conductive material; a buffer layer (110) formed on the substrate (100), and made of a material having a melting point lower than that of the substrate (100); and a barrier layer (120) formed on the buffer layer (110).
Description
본 발명은 플렉서블 기판 및 이를 이용한 태양전지에 관한 것이다. 보다 상세하게는 기판 상에 형성되는 반도체층을 열처리하는 공정에서 기판이 변형되는 것을 방지할 수 있는 플렉서블 기판과 이를 이용한 태양전지에 관한 것이다.The present invention relates to a flexible substrate and a solar cell using the same. More specifically, the present invention relates to a flexible substrate and a solar cell using the same, which can prevent the substrate from being deformed in the heat treatment of the semiconductor layer formed on the substrate.
플렉서블(flexible) 기판 관련 기술은 액정 표시 장치(Liquid Crystal Display: LCD)나 유기 발광 다이오드(Organic Light Emitting Diode: OLED)와 같은 표시장치, 또는 박막형 태양전지(Thin-Film Type Solar Cell)와 같은 광전소자의 휴대성을 향상시킴과 동시에 이들의 설치 장소를 윈도우, 자동차, 주택이나 건물의 외벽 등과 같이 다양하게 할 수 하는 핵심 기술이다.Flexible substrate technology includes display devices such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), or photoelectric devices such as thin-film type solar cells. It is a core technology that improves the portability of the device and at the same time, various installation places thereof such as windows, automobiles, exterior walls of houses or buildings.
이러한 플렉서블(flexible) 기판으로는 플라스틱 계열의 기판과 금속 계열의 기판이 있는데, 내열성이 우수하며 전극의 기능을 동시에 수행할 수 있는 금속 포일(foil) 형태의 플렉서블 기판을 이용하는 기술이 일반적으로 활용되고 있다.Such flexible substrates include plastic-based substrates and metal-based substrates, and a technique using a metal foil-type flexible substrate capable of simultaneously performing an electrode function with excellent heat resistance is generally used. have.
그러나, 이와 같은 플렉서블(flexible) 기판을 다결정 실리콘 태양전지에 이용하는 경우 플렉서블 기판이 변형되는 문제점이 있었다. 즉, 플렉서블 기판 상에서 비정질 실리콘층(a-si)을 다결정 실리콘층(p-si)으로 결정화시키는 과정에서 통상적으로 요구되는 최대 550℃ 내지 650℃ 정도의 결정화 온도를 포함하는 열처리 공정 사이클에 의하여 발생되는 잔류 응력(residual stress) 때문에 플렉서블 기판의 휨 현상이 나타나는 문제점이 있었다.However, when such a flexible substrate is used in a polycrystalline silicon solar cell, there is a problem in that the flexible substrate is deformed. That is, it is generated by a heat treatment process cycle including a crystallization temperature of about 550 ° C. to 650 ° C., which is typically required in the process of crystallizing the amorphous silicon layer (a-si) to the polycrystalline silicon layer (p-si) on the flexible substrate. There was a problem in that the bending phenomenon of the flexible substrate appeared due to residual stress.
또한, 이러한 고온의 결정화 공정은 플렉서블 기판과 반도체층(실리콘층) 사이에서 불필요한 화학적 반응을 초래하여 태양전지의 특성을 저하시키거나 플렉서블 기판에서 반도체층이 박리되는 문제점도 있었다.In addition, such a high temperature crystallization process may cause unnecessary chemical reaction between the flexible substrate and the semiconductor layer (silicon layer), thereby degrading the characteristics of the solar cell or peeling the semiconductor layer from the flexible substrate.
본 발명은 상기와 같은 종래 기술의 제반 문제점을 해결하기 위한 것으로, 태양전지 제조 공정시 발생하는 잔류 응력을 흡수할 수 있는 플렉서블 기판을 제공하는 것을 목적으로 한다.The present invention is to solve the above problems of the prior art, an object of the present invention is to provide a flexible substrate that can absorb the residual stress generated during the solar cell manufacturing process.
또한, 본 발명은 기판과 반도체층 사이의 계면에서 화학적 반응을 방지할 수 있는 플렉서블 기판을 제공하는 것을 다른 목적으로 한다.Another object of the present invention is to provide a flexible substrate capable of preventing chemical reactions at the interface between the substrate and the semiconductor layer.
또한, 본 발명은 플렉서블 기판 상에 형성되는 박막(예를 들면, 반도체층)이 박리되는 것을 방지할 수 있는 플렉서블 기판을 제공하는 것을 또 다른 목적으로 한다.Another object of the present invention is to provide a flexible substrate capable of preventing the thin film (for example, a semiconductor layer) formed on the flexible substrate from being peeled off.
또한, 광전 변환 효율성이 향상되고 신뢰성과 수명이 증대된 태양전지를 제공하는 것을 또 다른 목적으로 한다.In addition, another object of the present invention is to provide a solar cell having improved photoelectric conversion efficiency and increased reliability and lifetime.
본 발명에 의하면, 플렉서블 기판은 버퍼층을 구비함으로써 응력을 흡수하여 기판의 휨 발생을 방지할 수 있다.According to the present invention, the flexible substrate includes a buffer layer to absorb stress to prevent the occurrence of warpage of the substrate.
또한, 본 발명에 의하면, 플렉서블 기판은 배리어층을 구비함으로써 층간의 확산을 방지하고 계면 특성을 향상시킬 수 있다.In addition, according to the present invention, the flexible substrate includes a barrier layer to prevent diffusion between layers and to improve interface characteristics.
또한, 본 발명에 의하면, 플렉서블 기판 상의 박막이 박리되는 것을 방지하여 양호한 계면 특성을 얻을 수 있다.In addition, according to the present invention, it is possible to prevent the thin film on the flexible substrate from being peeled off and obtain good interfacial characteristics.
또한, 본 발명에 의하면, 상술된 플렉서블 기판 상에 태양전지를 구현함으로써 태양전지의 광전 변환 효율이 향상되고 수명 및 신뢰성이 증대될 수 있다.In addition, according to the present invention, by implementing the solar cell on the above-described flexible substrate, the photoelectric conversion efficiency of the solar cell can be improved and life and reliability can be increased.
도 1 및 도 2는 본 발명의 일 실시예에 의한 플렉서블 기판을 제조 공정을 나타내는 도면이다.1 and 2 are views showing a process for manufacturing a flexible substrate according to an embodiment of the present invention.
도 3은 본 발명의 비교예 및 실험예에 의한 기판의 상태를 촬영한 사진이다.3 is a photograph of the state of the substrate according to the comparative example and the experimental example of the present invention.
도 4 및 도 5는 본 발명의 일 실시예에 의한 플렉서블 기판을 이용한 태양전지의 제조 공정을 나타내는 도면이다.4 and 5 are views illustrating a manufacturing process of a solar cell using a flexible substrate according to an embodiment of the present invention.
도 6은 본 발명의 일 실시예에 의한 플렉서블 기판을 이용한 다른 형태의 태양전지의 단면도이다.6 is a cross-sectional view of another type of solar cell using a flexible substrate according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100: 기판100: substrate
110: 버퍼층110: buffer layer
120: 배리어층120: barrier layer
200, 300: 광전소자200, 300: photoelectric device
400: 상부전극400: upper electrode
본 발명의 상기 목적은 전도성 재질의 기판; 상기 기판 상에 형성되되 상기 기판 보다 용융점이 낮은 재질의 버퍼층; 및 상기 버퍼층 상에 형성되는 배리어층을 포함하는 것을 특징으로 하는 플렉서블 기판에 의해 달성된다.The object of the present invention is a substrate of a conductive material; A buffer layer formed on the substrate but having a lower melting point than the substrate; And it is achieved by a flexible substrate comprising a barrier layer formed on the buffer layer.
또한, 본 발명의 상기 목적은 전도성 재질의 기판; 상기 기판 상에 형성되되 상기 기판 보다 용융점이 낮은 재질의 버퍼층; 상기 버퍼층 상에 형성되는 배리어층; 상기 배리어층 상에 형성되는 반도체층; 및 상기 반도체층 상에 형성되는 상부전극을 포함하는 것을 특징으로 하는 태양전지에 의해서도 달성된다.In addition, the object of the present invention is a substrate of a conductive material; A buffer layer formed on the substrate but having a lower melting point than the substrate; A barrier layer formed on the buffer layer; A semiconductor layer formed on the barrier layer; And it is also achieved by a solar cell comprising an upper electrode formed on the semiconductor layer.
이때, 상기 버퍼층은 Al일 수 있다.In this case, the buffer layer may be Al.
상기 배리어층은 TiN일 수 있다.The barrier layer may be TiN.
상기 배리어층은 Ti/TiN/Ti의 적층 구조일 수 있다.The barrier layer may have a stacked structure of Ti / TiN / Ti.
상기 기판은 서스(SUS) 또는 인바(Invar)일 수 있다.The substrate may be a sus (SUS) or an invar.
상기 반도체층은 제1 다결정 반도체층; 상기 제1 다결정 반도체층 상에 형성되는 제2 다결정 반도체층; 및 상기 제2 다결정 반도체층 상에 형성되는 제3 다결정 반도체층을 포함할 수 있다.The semiconductor layer comprises a first polycrystalline semiconductor layer; A second polycrystalline semiconductor layer formed on the first polycrystalline semiconductor layer; And a third polycrystalline semiconductor layer formed on the second polycrystalline semiconductor layer.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용 효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
플렉서블 기판Flexible board
본 명세서에 있어서, 플렉서블 기판이란 금속 포일(metal foil)을 기판으로 사용하여 전기적 자극으로 구동이 가능한 전자소자를 형성할 수 있는 기판을 총칭하는 포괄적인 의미로 이해되어야 한다.In the present specification, a flexible substrate is to be understood as a generic term for a substrate capable of forming an electronic device that can be driven by an electrical stimulus using a metal foil as a substrate.
이하의 상세한 설명에서는 편의를 위해 일 예로, 플렉서블 기판 상에 박막형 태양전지를 형성하는 기술을 중심으로 설명하지만, 본 발명이 이에 한정되는 것은 아니다.In the following detailed description, for convenience, a description will be given based on a technique of forming a thin film solar cell on a flexible substrate, but the present invention is not limited thereto.
도 1 및 도 2는 본 발명의 일 실시예에 의한 플렉서블 기판을 제조 공정을 나타내는 도면이다.1 and 2 are views showing a process for manufacturing a flexible substrate according to an embodiment of the present invention.
먼저, 도 1을 참조하면, 플렉서블 특성을 가지는 기판(100)을 제공하는데 이러한 기판(100)의 재질은 금속 포일(foil) 형태로 제조되는 스테인레스 스틸(stainless steel) 또는 인바(Invar)일 수 있다.First, referring to FIG. 1, a substrate 100 having a flexible property is provided, and the material of the substrate 100 may be stainless steel or invar manufactured in the form of a metal foil. .
이어서, 기판(100) 상에 이후의 고온의 열처리 과정에서 발생하는 잔류 응력을 흡수할 수 있는 버퍼층(110)을 형성할 수 있는데, 이러한 버퍼층(110)은 전자빔 증착법(E-beam evaporation)이나 스퍼터링(sputtering)과 같은 물리기상 증착법(Physical Vapor Deposition: PVD)을 이용하여 형성할 수 있다.Subsequently, a buffer layer 110 may be formed on the substrate 100 to absorb residual stresses generated during the subsequent high temperature heat treatment. The buffer layer 110 may be formed by electron beam evaporation or sputtering. It may be formed by using physical vapor deposition (PVD), such as (sputtering).
이때, 버퍼층(110)은 기판(100) 보다 용융점이 낮은 알루미늄(Al)과 같은 금속을 사용하는 것이 바람직한데, 이는 고온의 열처리시(예를 들면, 비정질 실리콘층의 결정화시) 용융되어 기판(100)과 기판(100) 상에 형성되는 다른 박막층(예를 들면, 반도체층)에서 발생되는 잔류 응력을 흡수하는 기능을 수행할 수 있기 때문이다.In this case, the buffer layer 110 preferably uses a metal such as aluminum (Al) having a lower melting point than that of the substrate 100, which is melted during high temperature heat treatment (for example, when the amorphous silicon layer is crystallized). This is because a function of absorbing residual stress generated in the thin film layer (for example, the semiconductor layer) formed on the substrate 100 and the substrate 100 can be performed.
다음으로, 도 2를 참조하면, 버퍼층(110) 상에는 배리어층(120)을 더 형성할 수 있는데, 이러한 배리어층(120)은 전자빔 증착법이나 스퍼터링과 같은 물리기상 증착법, 또는 플라즈마 화학기상 증착법(Plasma Enhanced Chemical Vapor Deposition: PECVD), 저압 화학기상 증착법(Low Pressure Chemical Vapor Deposition: LPCVD), 유기금속 화학기상 증착법(Metal Organic Chemical Vapor Deposition: MOCVD)과 같은 화학기상 증착법(Chemical Vapor Deposition: CVD)을 이용하여 형성할 수 있다.Next, referring to FIG. 2, a barrier layer 120 may be further formed on the buffer layer 110. The barrier layer 120 may be a physical vapor deposition method such as electron beam deposition or sputtering, or a plasma chemical vapor deposition method (Plasma). Chemical Vapor Deposition (CVD) such as Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD) and Metal Organic Chemical Vapor Deposition (MOCVD) Can be formed.
이때, 배리어층(120)은 고온의 열처리 과정에서 기판(100)과 반도체층 간의 확산을 효율적으로 방지를 위하여 질화티타늄(TiN)으로 형성할 수 있다. 이 경우, 계면 특성을 개선시켜서 배리어층(120)과 이후 그 위에 형성될 반도체층간의 접착력을 향상시키기 위하여 TiN을 포함하는 다층 구조인 것이 바람직하다. 일 예로, 배리어층(120)은 티타늄/질화티타늄/티타늄(Ti/TiN/Ti) 구조를 사용할 수 있으나 본 발명이 이에 한정되는 것은 아니다.In this case, the barrier layer 120 may be formed of titanium nitride (TiN) to effectively prevent diffusion between the substrate 100 and the semiconductor layer in a high temperature heat treatment process. In this case, it is preferable that the multilayer structure includes TiN to improve the interfacial properties to improve the adhesion between the barrier layer 120 and the semiconductor layer to be formed thereon. For example, the barrier layer 120 may use a titanium / titanium nitride / titanium (Ti / TiN / Ti) structure, but the present invention is not limited thereto.
이러한 본 발명의 플렉서블 기판의 보다 상세한 이해를 돕기 위해 아래와 같은 비교예 및 실험예를 제시한다. 다만, 하기의 실험예는 본 발명의 이해를 돕기 위한 것일 뿐이며 본 발명이 하기의 실험예에 의해 한정되는 것이 아님을 밝혀둔다.In order to help more detailed understanding of the flexible substrate of the present invention, the following Comparative Examples and Experimental Examples are presented. However, the following experimental examples are only for helping the understanding of the present invention, and the present invention is not limited to the following experimental examples.
[비교예][Comparative Example]
이하의 비교예에서는 종래의 플렉서블 기판 상에 소정의 반도체층을 형성하고, 결정화 공정을 수행한 후 기판의 상태를 촬영하였다.In the following comparative example, a predetermined semiconductor layer was formed on a conventional flexible substrate, and the state of the substrate was photographed after performing a crystallization process.
먼저, 200 ㎛ 두께의 포일 형태의 스테인레스 스틸 기판(100) 상에 반도체층으로 비정질 실리콘층을 형성하였다. 이어서, 650℃의 온도에서 열처리를 수행하여 비정질 실리콘층을 다결정 실리콘층으로 결정화한 후에 기판(100)의 상태를 관찰하였다.First, an amorphous silicon layer was formed as a semiconductor layer on a stainless steel substrate 100 having a foil shape having a thickness of 200 μm. Subsequently, heat treatment was performed at a temperature of 650 ° C. to crystallize the amorphous silicon layer into a polycrystalline silicon layer, and then the state of the substrate 100 was observed.
[실험예]Experimental Example
이하의 실험예에서는 본 발명의 일 실시예에서 의한 플렉서블 기판과 같이 기판(100) 상에 버퍼층(110) 및 배리어층(120)을 형성하고, 그 위에 소정의 반도체층을 형성하고, 결정화 공정을 수행한 후 기판(100)의 상태를 촬영하였다. 먼저, 200 ㎛ 두께의 포일 형태의 스테인레스 스틸 기판(100) 상에 스퍼터링으로 40 nm 두께의 Al 버퍼층(110)을 형성하였다. 이어서, Al 버퍼층(110) 상에 스퍼터링으로 Ti(100 nm)/TiN(300 nm)/Ti(40 nm)의 적층 구조로 이루어진 배리어층(120)을 형성하였다. 이어서, 배리어층(120) 상에 반도체층으로 비정질 실리콘층을 형성하였다. 이어서, 650℃의 온도에서 열처리를 수행하여 비정질 실리콘층을 다결정 실리콘층으로 결정화한 후에 기판의 상태를 관찰하였다.In the following experimental example, the buffer layer 110 and the barrier layer 120 are formed on the substrate 100, the predetermined semiconductor layer is formed thereon, and the crystallization process is performed, like the flexible substrate according to the exemplary embodiment of the present invention. After performing the state of the substrate 100 was taken. First, a 40 nm thick Al buffer layer 110 was formed by sputtering on a 200 μm-thick foil-shaped stainless steel substrate 100. Subsequently, a barrier layer 120 having a stacked structure of Ti (100 nm) / TiN (300 nm) / Ti (40 nm) was formed on the Al buffer layer 110 by sputtering. Subsequently, an amorphous silicon layer was formed on the barrier layer 120 as a semiconductor layer. Subsequently, heat treatment was performed at a temperature of 650 ° C. to crystallize the amorphous silicon layer into a polycrystalline silicon layer, and then the state of the substrate was observed.
이상의 실험예와 비교예에 의한 기판의 상태는 도 3을 참조한 이하의 설명에서 명확해질 것이다.The state of the substrate according to the above experimental example and comparative example will be apparent in the following description with reference to FIG. 3.
도 3은 본 발명의 비교예 및 실험예에 의한 기판의 상태를 촬영한 사진이다.3 is a photograph of the state of the substrate according to the comparative example and the experimental example of the present invention.
도 3을 참조하면, 비교예에 의한 기판(100)에서는 휨 현상(10)과 반응 영역(20)을 명확하게 육안으로 확인할 수 있다(도 3의 (A) 참조). 반면에, 실험예에 의한 기판(100)에서는 휨 현상(10)과 반응 영역(20)이 모두 존재하지 않음을 확인할 수 있다(도 3의 (B) 참조).Referring to FIG. 3, in the substrate 100 according to the comparative example, the warpage phenomenon 10 and the reaction region 20 can be clearly identified with the naked eye (see FIG. 3A). On the other hand, in the substrate 100 according to the experimental example, it can be seen that neither the warpage phenomenon 10 nor the reaction region 20 exist (see FIG. 3B).
따라서, 종래의 플렉서블 기판과 대비할 때, 본 발명의 일 실시예에 의한 플렉서블 기판(100)은 버퍼층(110)을 구비함으로써 고온 열처리시 잔류 응력의 발생을 억제하여 기판(100)의 휨을 방지하는 기능을 수행할 수 있으며, 아울러 배리어층(120)을 구비함으로써 고온 열처리시 기판(100)과 반도체층 사이의 확산을 억제하고 계면 특성을 개선하는 기능을 수행할 수 있다.Therefore, as compared with the conventional flexible substrate, the flexible substrate 100 according to an embodiment of the present invention has a function of preventing the bending of the substrate 100 by suppressing the occurrence of residual stress during high temperature heat treatment by providing the buffer layer 110. In addition, since the barrier layer 120 is provided, a function of suppressing diffusion between the substrate 100 and the semiconductor layer during the high temperature heat treatment and improving the interface characteristics may be performed.
플렉서블 기판을 이용한 태양전지Solar Cell Using Flexible Substrate
도 4 및 도 5는 본 발명의 일 실시예에 의한 플렉서블 기판을 이용한 태양전지의 단면도이다.4 and 5 are cross-sectional views of a solar cell using a flexible substrate according to an embodiment of the present invention.
먼저 도 4를 참조하면, 본 발명의 일 실시예에 의한 플렉서블 기판(100)의 버퍼층(110) 및 배리어층(120) 상에는 반도체층 중 일 예로, 3층의 비정질 실리콘층(210, 220, 230)이 적층되어 형성될 수 있다. 보다 상세하게 설명하면, 배리어층(120) 상에는 제1 비정질 실리콘층(210)을 형성하고, 이어서 제1 비정질 실리콘층(210) 상에는 제2 비정질 실리콘층(220)을 형성하고, 이어서 제2 비정질 실리콘층(220) 상에는 제3 비정질 실리콘층(230)을 형성할 수 있다. 이때, 제1 내지 제3 비정질 실리콘층(210, 220, 230)의 형성 방법으로는 PECVD 또는 LPCVD와 같은 화학기상 증착법을 이용하여 형성할 수 있다.First, referring to FIG. 4, on the buffer layer 110 and the barrier layer 120 of the flexible substrate 100 according to an embodiment of the present invention, three amorphous silicon layers 210, 220, and 230 are examples of semiconductor layers. ) May be stacked and formed. In more detail, the first amorphous silicon layer 210 is formed on the barrier layer 120, and then the second amorphous silicon layer 220 is formed on the first amorphous silicon layer 210, followed by the second amorphous silicon layer 210. The third amorphous silicon layer 230 may be formed on the silicon layer 220. In this case, the first to third amorphous silicon layers 210, 220, and 230 may be formed using chemical vapor deposition such as PECVD or LPCVD.
다음으로, 도 5를 참조하면, 제1, 제2, 제3 비정질 실리콘층(210, 220, 230)을 열처리하여 결정화하는 과정을 수행할 수 있다. 즉, 제1 비정질 실리콘층(210)은 제1 다결정 실리콘층(211)으로, 제2 비정질 실리콘층(220)은 제2 다결정 실리콘층(221)으로, 제3 비정질 실리콘층(230)은 제3 다결정 실리콘층(231)으로 각각 결정화한다. 결국, 배리어층(120) 상에는 제1, 제2, 제3 다결정 실리콘층(211, 221, 231)으로 구성되는 광전소자(200)가 형성된다.Next, referring to FIG. 5, a process of crystallizing the first, second, and third amorphous silicon layers 210, 220, and 230 may be performed. That is, the first amorphous silicon layer 210 is the first polycrystalline silicon layer 211, the second amorphous silicon layer 220 is the second polycrystalline silicon layer 221, and the third amorphous silicon layer 230 is formed of the first amorphous silicon layer 210. Each of the three polycrystalline silicon layers 231 is crystallized. As a result, the photoelectric device 200 including the first, second, and third polycrystalline silicon layers 211, 221, and 231 is formed on the barrier layer 120.
이러한 광전소자(200)는 다결정 실리콘층이 적층된 구조로 광이 수광되어 발생되는 광기전력으로 전력을 생산할 수 있는 p 형, i 형, n 형의 다결정 실리콘층이 순서대로 적층된 p-i-n 다이오드의 구조일 수 있다.The photovoltaic device 200 is a structure in which a polycrystalline silicon layer is stacked and a pin diode in which p-type, i-type, and n-type polycrystalline silicon layers are stacked in order to generate power using photovoltaic power generated by receiving light. Can be.
여기서, i 형은 불순물이 도핑되지 않은 진성(intrinsic)을 의미한다. 또한, n 형 또는 p 형 도핑은 비정질 실리콘층 형성시에 불순물을 인시츄(in situ) 방식으로 도핑하는 것이 바람직하다. P 형 도핑시 불순물로서는 보론(B)을 n 형 도핑시 불순물로서는 인(P) 또는 비소(As)를 사용하는 것이 일반적이나, 이에 한정되는 것은 아니며 공지된 기술을 제한 없이 사용할 수 있다.Here, the i type means intrinsic without impurities. In addition, in the n-type or p-type doping, it is preferable to dope the impurities in situ when forming the amorphous silicon layer. It is common to use boron (B) as an impurity in P-type doping and phosphorus (P) or arsenic (As) as an impurity in n-type doping, but it is not limited to this, and well-known techniques can be used without limitation.
제1, 제2, 제3 비정질 실리콘층(210, 220, 230)의 결정화 방법은 SPC(Solid Phase Crystallization), ELA(Excimer Laser Annealing), SLS(Sequential Lateral Solidification), MIC(Metal Induced Crystallization), 및 MILC(Metal Induced Lateral Crystallization) 중 어느 하나의 방법을 사용할 수 있다. 상기의 비정질 실리콘의 결정화 방법은 공지의 기술이므로 이에 대한 상세한 설명은 본 명세서에서는 생략하기로 한다.Crystallization methods of the first, second, and third amorphous silicon layers 210, 220, and 230 may include Solid Phase Crystallization (SPC), Excimer Laser Annealing (ELA), Sequential Lateral Solidification (SLS), Metal Induced Crystallization (MIC), And MILC (Metal Induced Lateral Crystallization). Since the crystallization method of the amorphous silicon is a known technique, a detailed description thereof will be omitted herein.
한편, 상기에서는 제1, 제2, 제3 비정질 실리콘층(210, 220, 230)을 모두 형성한 후에 이들 층을 동시에 결정화시키는 것으로 설명하고 있으나 반드시 이에 한정되는 것은 아니다. 예를 들어, 하나의 비정질 실리콘층 마다 결정화 공정을 별도로 진행할 수 있으며, 또한 두 개의 비정질 실리콘층은 동시에 결정화 공정을 진행하고 나머지 하나의 비정질 실리콘층은 별도로 결정화 공정을 진행할 수도 있다.In the above description, the first, second, and third amorphous silicon layers 210, 220, and 230 are all formed, and the layers are simultaneously crystallized, but the present invention is not limited thereto. For example, the crystallization process may be performed separately for each amorphous silicon layer, and the two amorphous silicon layers may simultaneously undergo a crystallization process and the other amorphous silicon layer may be separately crystallized.
또한, 도시되지는 않았지만 제1 다결정 실리콘층(211), 제2 다결정 실리콘층(221), 제3 다결정 실리콘층(231)은 다결정 실리콘의 성질을 보다 향상시키기 위하여 결함 제거 공정을 추가로 진행할 수 있다. 본 발명에서는 다결정 실리콘층을 고온 열처리하거나 수소 플라즈마 처리하여 다결정 실리콘층 내에 존재하는 결함(예를 들어, 불순물 및 댕글링 본드 등)을 제거할 수 있다.Although not shown, the first polycrystalline silicon layer 211, the second polycrystalline silicon layer 221, and the third polycrystalline silicon layer 231 may further perform a defect removal process to further improve the properties of the polycrystalline silicon. have. In the present invention, the polycrystalline silicon layer may be subjected to high temperature heat treatment or hydrogen plasma treatment to remove defects (eg, impurities and dangling bonds) present in the polycrystalline silicon layer.
이어서, 제3 다결정 실리콘층(231) 상에는 투명 전도성 재질의 상부전극(400)을 형성한다. 상부전극(400)의 소재는 ITO(Indium Tin Oxide), ZnO, BZO(ZnO:B), IZO(ZnO:In), AZO(ZnO:Al), FTO(SnO2:F) 중 어느 하나인 것이 바람직하나 반드시 이에 한정되는 것은 아니다. 상부전극(400)의 형성 방법으로는 스퍼터링과 같은 물리기상 증착법 및 LPCVD, PECVD, MOCVD와 같은 화학기상 증착법 등을 포함할 수 있다.Subsequently, an upper electrode 400 of a transparent conductive material is formed on the third polycrystalline silicon layer 231. The material of the upper electrode 400 may be any one of indium tin oxide (ITO), ZnO, BZO (ZnO: B), IZO (ZnO: In), AZO (ZnO: Al), and FTO (SnO 2 : F). Preferred but not necessarily limited thereto. The method of forming the upper electrode 400 may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.
한편, 본 실시예에 따른 태양전지에서 하부전극은 플렉서블 기판(100) 자체가 된다. 따라서, 상술한 바와 같은 도 5의 태양전지를 단위셀로 하여 태양전지 모듈을 제조하는 경우에는 상기 태양전지의 플렉서블 기판(100)과 상기 태양전지와 이웃하는 태양전지의 상부전극(미도시)이 전기적으로 연결될 수 있다.On the other hand, in the solar cell according to the present embodiment, the lower electrode becomes the flexible substrate 100 itself. Therefore, when the solar cell module is manufactured using the solar cell of FIG. 5 as a unit cell as described above, the flexible substrate 100 of the solar cell and the upper electrode of the solar cell adjacent to the solar cell are not shown. Can be electrically connected.
상기와 같이 버퍼층(110)과 배리어층(120)이 형성된 플렉서블 기판(100) 상에 광전소자(200)를 형성하면, 기판의 휨, 반도체층의 박리 및 기판과 반도체층간의 화학 반응을 억제할 수 있어 태양전지의 광전 변환 효율성을 향상시킬 수 있으며 신뢰성과 수명을 증대시키는 효과도 기대할 수 있다.When the optoelectronic device 200 is formed on the flexible substrate 100 on which the buffer layer 110 and the barrier layer 120 are formed as described above, the curvature of the substrate, the peeling of the semiconductor layer, and the chemical reaction between the substrate and the semiconductor layer may be suppressed. It can improve the photoelectric conversion efficiency of solar cells and can also expect the effect of increasing the reliability and lifespan.
도 6은 본 발명의 일 실시예에 의한 플렉서블 기판을 이용한 다른 형태의 태양전지의 단면도이다.6 is a cross-sectional view of another type of solar cell using a flexible substrate according to an embodiment of the present invention.
도 6을 참조하면, 이상에서 설명된 광전소자(200) 상에 다른 광전소자(300)가 더 형성될 수 있는데, 이러한 광전소자(300)는 비정질 반도체층이 적층된 구조로, 일 예로 3층의 비정질 실리콘층(310, 320, 330)이 형성될 수 있다.Referring to FIG. 6, another optoelectronic device 300 may be further formed on the optoelectronic device 200 described above. The optoelectronic device 300 has a structure in which an amorphous semiconductor layer is stacked, for example, three layers. The amorphous silicon layers 310, 320, and 330 may be formed.
보다 상세하게 설명하면, 하부에 위치하는 광전소자(200) 상에는 제1 비정질 실리콘층(310)을 형성하고, 이어서 제1 비정질 실리콘층(310) 상에는 제2 비정질 실리콘층(320)을 형성하고, 이어서 제2 비정질 실리콘층(320) 상에는 제3 비정질 실리콘층(330)을 형성하여 광전소자(300)와 같은 p-i-n 다이오드의 구조의 광전소자(300)가 구성된다. 이때, 제1, 제2, 제3 비정질 실리콘층(310, 320, 330)의 형성 방법으로는 PECVD 또는 LPCVD와 같은 화학기상 증착법을 이용하여 형성할 수 있다.In more detail, the first amorphous silicon layer 310 is formed on the photoelectric device 200 positioned below, and the second amorphous silicon layer 320 is formed on the first amorphous silicon layer 310. Subsequently, a third amorphous silicon layer 330 is formed on the second amorphous silicon layer 320 to form a photoelectric device 300 having a pin diode structure such as the photoelectric device 300. In this case, the first, second, and third amorphous silicon layers 310, 320, and 330 may be formed using chemical vapor deposition such as PECVD or LPCVD.
이어서, 제3 비정질 반도체층(330) 상에는 투명 전도성 재질의 상부전극(400)을 형성한다. 상부전극(400)의 소재 및 제조 방법은 도 5에서 설명한 바와 동일하다.Subsequently, an upper electrode 400 of a transparent conductive material is formed on the third amorphous semiconductor layer 330. The material and manufacturing method of the upper electrode 400 are the same as described with reference to FIG. 5.
한편, 도시되어 있지 않지만, 제3 다결정 실리콘층(231)과 제1 비정질 실리콘층(310) 사이에는 투명 전도성 재질의 연결층이 추가로 형성될 수 있다. 이때, 연결층은 광을 투과시킬 수 있는 ITO, AZO(ZnO:Al), GZO(ZnO:Ga), BZO(ZnO:B), FTO(SnO2:F) 중 어느 하나일 수 있다. 연결층의 형성 방법으로는 스퍼터링과 같은 물리기상 증착법 및 LPCVD, PECVD, MOCVD와 같은 화학기상 증착법 등을 포함할 수 있다.Although not shown, a connection layer of a transparent conductive material may be further formed between the third polycrystalline silicon layer 231 and the first amorphous silicon layer 310. In this case, the connection layer may be any one of ITO, AZO (ZnO: Al), GZO (ZnO: Ga), BZO (ZnO: B), and FTO (SnO 2 : F), which may transmit light. The formation method of the connection layer may include a physical vapor deposition method such as sputtering and a chemical vapor deposition method such as LPCVD, PECVD, and MOCVD.
이러한 연결층은 제3 다결정 실리콘층(231)과 제1 비정질 실리콘층(310)간에 오믹 컨택(ohmic contact)이 이루어지게 하여서 그 결과 태양전지의 보다 양호한 광전 변환 효율을 기대할 수 있게 된다.Such a connection layer allows ohmic contact between the third polycrystalline silicon layer 231 and the first amorphous silicon layer 310, and as a result, better photoelectric conversion efficiency of the solar cell can be expected.
이로써, 다결정 실리콘층으로 이루어진 광전소자(200)와 비정질 실리콘층으로 이루어진 광전소자(300)로 구성되는 탠덤 구조의 태양전지를 얻을 수 있다. 이때, 광전소자(200)는 다결정 실리콘층으로 이루어지기 때문에 장파장대 광에 대하여 광전 변환 효율이 양호하고, 광전소자(300)는 비정질 실리콘층으로 이루어지기 때문에 단파장대 광에 대하여 광전 변환 효율이 양호하다. 따라서, 본 발명에 따른 탠덤 구조의 태양전지는 다양한 파장대의 광을 흡수할 수 있어서 광전 변환 효율성을 향상시킬 수 있다.As a result, a tandem solar cell including the optoelectronic device 200 made of a polycrystalline silicon layer and the optoelectronic device 300 made of an amorphous silicon layer may be obtained. In this case, since the photoelectric device 200 is made of a polycrystalline silicon layer, the photoelectric conversion efficiency is good for the long wavelength light, and the photoelectric device 300 is made of the amorphous silicon layer, and thus the photoelectric conversion efficiency is good for the short wavelength light. Do. Therefore, the tandem structured solar cell according to the present invention can absorb light in various wavelength bands, thereby improving photoelectric conversion efficiency.
이상의 상세한 설명에서는 광전소자(200, 300)로 적층된 탠덤(tandem) 구조를 일 예로 설명하였지만 필요에 따라 광전소자를 이중 이상으로 적층시킬 수도 있다. 또한, 광전소자(200, 300)는 p-i-n 형이 아닌 n-i-p 형, p-n 형, n-p 형 등을 사용할 수도 있다.In the above detailed description, a tandem structure in which the optoelectronic devices 200 and 300 are stacked has been described as an example. Alternatively, the optoelectronic devices may be stacked in double or more as necessary. In addition, the optoelectronic devices 200 and 300 may use n-i-p type, p-n type, n-p type or the like instead of p-i-n type.
본 발명은 상술한 바와 같이 바람직한 실시예를 들어 도시하고 설명하였으나, 상기 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변형과 변경이 가능하다. 그러한 변형예 및 변경예는 본 발명과 첨부된 특허청구범위의 범위 내에 속하는 것으로 보아야 한다.Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above embodiments and various modifications made by those skilled in the art without departing from the spirit of the present invention. Modifications and variations are possible. Such modifications and variations are intended to fall within the scope of the invention and the appended claims.
Claims (10)
- 전도성 재질의 기판;A substrate made of a conductive material;상기 기판 상에 형성되되 상기 기판 보다 용융점이 낮은 재질의 버퍼층; 및A buffer layer formed on the substrate but having a lower melting point than the substrate; And상기 버퍼층 상에 형성되는 배리어층A barrier layer formed on the buffer layer을 포함하는 것을 특징으로 하는 플렉서블 기판.Flexible substrate comprising a.
- 제1항에 있어서,The method of claim 1,상기 버퍼층은 Al인 것을 특징으로 하는 플렉서블 기판.The buffer layer is Al, characterized in that the flexible substrate.
- 제1항에 있어서,The method of claim 1,상기 배리어층은 TiN인 것을 특징으로 하는 플렉서블 기판.The barrier layer is a flexible substrate, characterized in that the TiN.
- 제3항에 있어서,The method of claim 3,상기 배리어층은 Ti/TiN/Ti의 적층 구조인 것을 특징으로 하는 플렉서블 기판.The barrier layer is a flexible substrate, characterized in that the laminated structure of Ti / TiN / Ti.
- 제1항에 있어서,The method of claim 1,상기 기판은 서스(SUS) 또는 인바(Invar)인 것을 특징으로 하는 플렉서블 기판.The substrate is a flexible substrate, characterized in that the sus (SUS) or Invar (Invar).
- 전도성 재질의 기판;A substrate made of a conductive material;상기 기판 상에 형성되되 상기 기판 보다 용융점이 낮은 재질의 버퍼층;A buffer layer formed on the substrate but having a lower melting point than the substrate;상기 버퍼층 상에 형성되는 배리어층;A barrier layer formed on the buffer layer;상기 배리어층 상에 형성되는 반도체층; 및A semiconductor layer formed on the barrier layer; And상기 반도체층 상에 형성되는 상부전극An upper electrode formed on the semiconductor layer을 포함하는 것을 특징으로 하는 태양전지.Solar cell comprising a.
- 제6항에 있어서,The method of claim 6,상기 버퍼층은 Al인 것을 특징으로 하는 태양전지.The buffer layer is a solar cell, characterized in that Al.
- 제6항에 있어서,The method of claim 6,상기 배리어층은 TiN인 것을 특징으로 하는 태양전지.The barrier layer is a solar cell, characterized in that TiN.
- 제8항에 있어서,The method of claim 8,상기 배리어층은 Ti/TiN/Ti의 적층 구조인 것을 특징으로 하는 태양전지.The barrier layer is a solar cell, characterized in that the laminated structure of Ti / TiN / Ti.
- 제6항에 있어서,The method of claim 6,상기 반도체층은 제1 다결정 반도체층;The semiconductor layer comprises a first polycrystalline semiconductor layer;상기 제1 다결정 반도체층 상에 형성되는 제2 다결정 반도체층; 및A second polycrystalline semiconductor layer formed on the first polycrystalline semiconductor layer; And상기 제2 다결정 반도체층 상에 형성되는 제3 다결정 반도체층을 포함하는 것을 특징으로 하는 태양전지.And a third polycrystalline semiconductor layer formed on the second polycrystalline semiconductor layer.
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KR100599357B1 (en) * | 2005-01-12 | 2006-07-12 | 한국과학기술연구원 | Method for fabricating semiconductor device having quantum dot structure |
US20090078313A1 (en) * | 2007-09-18 | 2009-03-26 | Basol Bulent M | Substrate preparation for thin film solar cell manufacturing |
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KR100599357B1 (en) * | 2005-01-12 | 2006-07-12 | 한국과학기술연구원 | Method for fabricating semiconductor device having quantum dot structure |
US20090078313A1 (en) * | 2007-09-18 | 2009-03-26 | Basol Bulent M | Substrate preparation for thin film solar cell manufacturing |
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Title |
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WEN-FA WU ET AL.: 'Novel multilayered Ti/TiN Diffusion Barrier for A1 metallization' JOURNAL OF ELECTRONIC MATERIALS vol. 34, no. 8, August 2005, pages 1 - 7 * |
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