WO2010097831A1 - I2c monitor sequential read data storage device - Google Patents

I2c monitor sequential read data storage device Download PDF

Info

Publication number
WO2010097831A1
WO2010097831A1 PCT/JP2009/000809 JP2009000809W WO2010097831A1 WO 2010097831 A1 WO2010097831 A1 WO 2010097831A1 JP 2009000809 W JP2009000809 W JP 2009000809W WO 2010097831 A1 WO2010097831 A1 WO 2010097831A1
Authority
WO
WIPO (PCT)
Prior art keywords
read data
data storage
storage device
address
sequential read
Prior art date
Application number
PCT/JP2009/000809
Other languages
French (fr)
Japanese (ja)
Inventor
福富聡
Original Assignee
富士通テレコムネットワークス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通テレコムネットワークス株式会社 filed Critical 富士通テレコムネットワークス株式会社
Priority to JP2011501345A priority Critical patent/JP5298185B2/en
Priority to PCT/JP2009/000809 priority patent/WO2010097831A1/en
Publication of WO2010097831A1 publication Critical patent/WO2010097831A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/349—Performance evaluation by tracing or monitoring for interfaces, buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3471—Address tracing

Definitions

  • the present invention relates to an I2C monitoring sequential read data storage device that can support a plurality of reading methods.
  • a transmission device that monitors and controls using an I2C interface such as an optical module or LSI is composed of a plurality of units, and each unit is an EEPROM in which physical inventory information (hereinafter referred to as PI information) of each unit is stored. Is provided.
  • the transmission apparatus reads PI information from the EEPROM of each unit via the I2C interface.
  • the transmission device When the unit is mounted on the transmission device, the transmission device reads and controls the PI information stored in advance in the EEPROM of the unit via the I2C interface, and acquires the PI information.
  • the PI information is information unique to the unit such as wavelength information handled by the transponder.
  • the transmission apparatus reads the PI information of the replaced unit through the I2C interface.
  • the I2C monitoring sequential read data storage device connected to the I2C interface acquires and stores necessary I2C communication data (typically PI information) between the transmission device and the unit.
  • the PI information and the like stored in the I2C monitoring sequential read data storage device is used when required by other units.
  • the read method using the I2C interface between them is a sequential read method with a relatively short read time, a random read method specifying address information, or a sequential random read method. Etc. are used.
  • Communication processing means that realizes a read method with a short transmission time in addition to a read method that specifies address information in order to shorten the time required for initial setting of the system and to provide flexibility of the communication processing means, For example, it is disclosed in Patent Document 1 below.
  • the I2C monitoring sequential read data storage device only supports a single I2C read method, for example, if the read method using the I2C interface between the transmission device and the unit is different, the communication data cannot be read, It becomes impossible to acquire desired information held in the EEPROM or the like in the unit.
  • an I2C monitoring sequential read data storage device capable of high versatility can be expected with respect to various read methods using an I2C interface between the master circuit side and the slave circuit side.
  • the present invention has been made in view of the above-described problems. I2C monitoring sequential read data storage that can cope with various read methods using an I2C interface between a master circuit side and a slave circuit side with high versatility. An object is to provide an apparatus.
  • An I2C monitoring sequential read data storage device is an I2C monitoring sequential read data storage device that acquires communication data via an I2C interface between a master circuit and a slave circuit, and counts the address equivalent number of the slave circuit.
  • an address counter is provided and a byte address specifying a predetermined area of the slave circuit is acquired, the acquired byte address is set as an initial value of the address counter.
  • the I2C monitoring sequential read data storage device preferably includes a byte address register for temporarily storing the acquired byte address, and when the slave circuit returns a normal signal for reception of the byte address, the byte address register The byte address temporarily stored in may be used as the initial value of the address counter.
  • the I2C monitoring sequential read data storage device more preferably stores the acquired communication data when the slave circuit that has received the device address or byte address specifying the slave circuit returns an abnormal signal. It does not have to be.
  • the I2C monitoring sequential read data storage device preferably further includes an acknowledge register for temporarily storing a reply signal of a slave circuit that has received a device address or byte address for specifying the slave circuit, and a counter value of the address counter. And a decoder unit that outputs timing for storing communication data acquired by decoding the data, and when the return signal input from the ACK register is an abnormal signal, the decoder does not store the acquired communication data The unit may not output the timing for storing the communication data.
  • the I2C monitoring sequential read data storage device is more preferably initialized even when the slave circuit receiving the device address or the byte address specifying the slave circuit returns an abnormal signal. Good.
  • the I2C monitoring sequential read data storage device preferably further detects a termination signal for ending the communication between the master circuit and the slave circuit, and detects the N2 detection that initializes the I2C monitoring sequential read data storage device.
  • the Nac detection unit may initialize the I2C monitoring sequential read data storage device when the return signal input from the acknack register is an abnormal signal.
  • a plurality of slave circuits are connected via an I2C interface, and the I2C monitoring sequential read data storage device specifies a slave circuit that is an information acquisition target.
  • An expected device address value may be set in advance, and communication data of the slave circuit corresponding to the expected device address value may be stored.
  • the I2C monitoring sequential read data storage device is more preferably an I2C monitoring sequential read data storage device, wherein an expected value storage unit that stores in advance a device address expected value that specifies a slave circuit that is an information acquisition target; A device address expected value stored in the expected value storage unit and a device address expected value comparing unit that compares the acquired device address, and the device address expected value comparing unit includes the device address expected value and the acquired device address. May be output from the initialization signal of the I2C monitoring sequential read data storage device.
  • the I2C monitoring sequential read data storage device preferably initializes the address counter only when the I2C monitoring sequential read data storage device is turned on so that the address counter matches the address count of the slave circuit. May be used.
  • the restart is transmitted from the master circuit to the slave circuit even when the address counter acquires the start signal transmitted from the master circuit to the slave circuit. Even if the signal is acquired, it may not be initialized in either case.
  • the slave circuit is preferably an EEPROM, and the I2C monitoring sequential read data storage device is stored in a predetermined area of the EEPROM read by the master circuit via the I2C interface.
  • a storage unit that acquires and stores the processed data may be provided.
  • the read method of the I2C interface may be any one or more of a random read method, a sequential read method, and a sequential random read method. .
  • the circuit on the side that controls I2C is a master circuit, and the circuit that is controlled by I2C is a slave circuit.
  • the slave circuit is typically a memory such as an EEPROM.
  • the master circuit and slave circuit connected by the I2C interface may require data written in the slave circuit in a unit other than the master circuit.
  • the I2C monitoring read data storage device retrieves read data (also referred to as read data) when the master circuit performs read control on the slave circuit via the I2C interface. Accordingly, each embodiment will be described after the I2C reading method such as the sequential read method is described in detail.
  • FIG. 1 is a conceptual diagram illustrating the configuration of a communication device 100 between a master circuit and a slave circuit.
  • the slave circuit 120 and the master circuit 110 are connected via an I2C interface 140.
  • the I2C interface 140 includes a serial data (appropriately referred to as SDA or sda) connection line 140a and a serial clock (appropriately also referred to as SCL or scl) connection line 140b, which are connected so as to enable bidirectional communication.
  • SDA or sda serial data (appropriately referred to as SDA or sda) connection line 140a and a serial clock (appropriately also referred to as SCL or scl) connection line 140b, which are connected so as to enable bidirectional communication.
  • SDA or sda serial data (appropriately referred to as SDA or sda) connection line 140a
  • SCL or scl) connection line 140b which are connected so as to enable bidirectional communication.
  • the I2C monitoring sequential read data storage device 130 is connected to the serial data connection line 140a and the serial clock connection line 140b so that the communication data of the serial data connection line 140a and the serial clock connection line 140b are respectively branched and input. Is done.
  • the serial data connection line 140a typically transmits various information such as PI information read from the slave circuit 120 as communication data.
  • the serial clock connection line 140b typically transmits a clock signal for synchronization between the slave circuit 120 and the master circuit 110.
  • the I2C monitoring sequential read data storage device 130 transmits communication data between the slave circuit 120 and the master circuit 110 as necessary by the above-described connection configuration. You can get it.
  • the slave circuit 100 is an EEPROM in which PI information is stored in advance
  • the master circuit 110 reads and controls the PI information of the EEPROM
  • the I2C monitoring sequential read data storage device 130 passes through the I2C interface.
  • the read PI information can be acquired and stored.
  • the I2C monitoring sequential read data storage device 130 can read all data such as all PI information in the slave circuit 120 collectively in a relatively short time by one read control by reading by the sequential read method. It is.
  • a read circuit corresponding to the sequential read method tends to be frequently used because the circuit scale can be made relatively simple and small and can be made inexpensive.
  • the master circuit 110 and the I2C monitoring sequential read data storage device 130 are described as being provided in the communication unit 150, but the arrangement position of the I2C monitoring sequential read data storage device 130 is limited to this. Is not to be done.
  • the slave circuit 120 and the I2C monitoring sequential read data storage device 130 may be configured in the same unit so that the unit in which the slave circuit 120 is disposed has the function.
  • FIG. 2 is a diagram illustrating an outline of the configuration of the I2C monitoring sequential read data storage device 130 (1) that supports only the sequential read method.
  • the I2C monitoring sequential read data storage device 130 (1) detects that the communication start signal between the master circuit 110 and the slave circuit 120 is input from the serial data connection line 140a.
  • the unit 210 is provided. Further, the I2C monitoring sequential read data storage device 130 (1) confirms that a communication end signal (also referred to as “nack“ Nack ”) between the master circuit 110 and the slave circuit 120 is input from the serial data connection line 140a.
  • a nack (also referred to as “Nack”) detection unit 220 for detection is provided.
  • the set reset unit 230 When the start detection unit 210 detects the start signal, the set reset unit 230 outputs an “enable” signal to the bit counter 240, and the bit counter 240 initialized by the “enable” signal starts counting up. Further, the set / reset unit 230 disables the bit counter 240 when the Nack detection unit 220 detects a communication end signal.
  • the next “Start” the entire I2C monitoring sequential data storage device 130 is initialized.
  • the counter values of various counters provided in the I2C monitoring sequential read data storage device 130 (1) are typically reset to zero.
  • the bit counter 250 When the bit counter 240 counts 9 bits from 0 to 8 bits, the byte counter 250 counts up one byte at a time from the initial value zero. Typically, 8 bits out of a total of 9 bits counted by the bit counter 240 are read data or the like, and 1 bit out of a total of 9 bits counted by the bit counter 240 is a master circuit for receiving read data.
  • the byte counter 250 is reset to zero by a communication start “Start” or a communication restart “Re Start”.
  • the first decoder 260 detects the timing of “read bit” that the master circuit 110 instructs the slave circuit 120 to read from the count value of the byte counter 250 and the like.
  • the second decoder unit 270 receives the data read from the slave circuit 120 (also referred to as “read data”) based on the counter value of the byte counter 250, and the master circuit 110 sends an acknowledgment signal to the slave circuit 120. Detect the notification timing.
  • the third decoder unit 2a0 detects the timing at which the read data is stored in the storage unit 2b from the counter value of the address counter 290.
  • the address counter 290 counts up the number corresponding to the address of the slave circuit 120.
  • the serial / parallel converter 280 performs parallel conversion on communication data (typically data read from the EEPROM) input from the serial data connection line 140a.
  • the storage unit 2b stores the data converted in parallel by the serial / parallel conversion unit 280 at the timing detected by the third decoder unit 2a0.
  • the storage unit 2b typically stores “read data0”, “read data1”,..., “Read datatan”, which are sequentially acquired every 8 bits, sequentially in register 2b0, register 2b1, and register 2bn (n Is an arbitrary natural number, typically 255), and is stored by the trigger input from the third decoder unit 2a0.
  • the clock signal is input to the bit counter 240, the byte counter 250, the serial / parallel converter 280, and the address counter 290 from the serial clock connection line 140b. That is, the I2C monitoring sequential read data storage device 130 (1) performs operation processing in synchronization with the master circuit 110 and the slave circuit 120.
  • FIG. 3 is a timing chart conceptual diagram showing an outline of operation processing of the I2C monitoring sequential read data storage device 130 (1).
  • FIG. 3 illustrates a chart when the memory capacity of the slave circuit 120 is 256 bytes.
  • the set reset unit 230 when the start detection unit 210 detects a communication start signal, the set reset unit 230 outputs an “enable” signal.
  • the bit counter 240 is reset to zero by the “enable” signal and starts counting up. Also, “read data0” input from the serial data connection line 140a is stored in the register 2b0 at a timing instructed by the third decoder unit 2a0.
  • the address counter 290 starts counting up sequentially.
  • the address counter 290 sequentially counts up to 255 bytes so as to be delayed by 1 byte with respect to the count value of the byte counter 250 thereafter. That is, when the count value of the address counter 290 is 1, “read data1” is stored in the register 2b1 at a timing instructed by the third decoder unit 2a0.
  • the count value of the address counter 290 is 255, “read data 255” is stored in the register 2b255 at the timing indicated by the third decoder unit 2a0.
  • the Nack detection unit 220 detects a Nack signal instructing the end of communication
  • the “enable” output of the set reset unit 230 is stopped and the count up of the bit counter 240 is stopped.
  • the count-up of the bit counter 240 is stopped, the operation process of the I2C monitoring sequential read data storage device 130 (1) is stopped.
  • FIG. 4 is a conceptual diagram illustrating three types of I2C communication methods.
  • FIG. 4A is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 for the random read method.
  • FIG. 4B is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 in the sequential read method.
  • FIG. 4C is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 in the sequential random read method.
  • the master circuit 110 transmits a communication start signal “Start” and “Device add + Write” in which a write signal is added to a device address that identifies the slave circuit 120. Is done.
  • the slave circuit 120 When the slave circuit 120 correctly receives “Device add + Write”, it returns “Ack” to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Write”, it returns “Nack” to the master circuit 110.
  • the case where “Device add + Write” is not correctly received includes, for example, the case where there is no slave circuit 120 corresponding to the instructed device address.
  • Nack detection unit 220 since “Nack” returned from the slave circuit 120 is different from the communication end signal, the Nack detection unit 220 does not detect it, and the operation and processing of the I2C monitoring sequential read data storage device 130 (1) are not detected. None ends.
  • the master circuit 110 transmits a byte address “Byte add” designating a specific area of the slave circuit 120.
  • the byte address is typically an address where information to be read from the EEPROM is stored.
  • the slave circuit 120 When the slave circuit 120 correctly receives “Byte add”, it returns Ack to the master circuit 110. If the slave circuit 120 does not correctly receive “Byte add”, it returns Nack to the master circuit 110.
  • the case where “Byte add” is not correctly received includes, for example, the case where there is no memory area corresponding to the designated byte address.
  • the communication restart signal “Re Start” and “Device add + Read” obtained by adding a read signal to the device address that identifies the slave circuit 120 are transmitted from the master circuit 110.
  • the slave circuit 120 When the slave circuit 120 correctly receives “Device add + Read”, the slave circuit 120 returns Ack to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Read”, it returns Nack to the master circuit 110. In addition, the slave circuit 120 transmits “Read data” obtained by reading the information stored in the designated byte address to the master circuit 110.
  • the master circuit 110 transmits “Nack” instructing the end of communication to the slave circuit 120, and the communication between the master circuit 110 and the slave circuit 120 is completed.
  • the master circuit 110 For each piece of information to be read, information for specifying the slave circuit 120 in which the information to be read is stored (corresponding to “Device add”) and information for specifying the storage location (“Byte”). add ”) is instructed by the master circuit 110.
  • the master circuit 110 can read desired information in an arbitrary order.
  • the above is an outline of the random read type I2C communication.
  • the slave circuit 120 When the slave circuit 120 correctly receives “Device add + Read”, it returns “Ack” to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Read”, it returns “Nack” to the master circuit 110.
  • the case where “Device add + Read” is not correctly received includes, for example, the case where there is no slave circuit 120 corresponding to the instructed device address.
  • the master circuit 110 does not need to transmit a byte address “Byte add” that designates a specific area of the slave circuit 120.
  • the master circuit 110 typically reads all the information stored in the EEPROM sequentially from the first address.
  • the designated slave circuit 120 transmits “Read data” obtained by reading the stored information to the master circuit 110. If the master circuit 110 correctly receives “Read data”, it returns “Ack” to the slave circuit 120. Thereafter, the slave circuit 120 sequentially transmits “Read data” obtained by sequentially reading stored information to the master circuit 110. Also, the master circuit 110 returns “Ack” to the slave circuit 120 every time it correctly receives “Read data”.
  • the master circuit 110 transmits “Nack” instructing the end of communication to the slave circuit 120, and the communication between the master circuit 110 and the slave circuit 120 is completed.
  • the sequential read method it is not necessary for the master circuit 110 to instruct information specifying the storage location (corresponding to “Byte add”) for each piece of information to be read. Thereby, the master circuit 110 can read desired information relatively quickly.
  • the above is an outline of the sequential read type I2C communication.
  • the front part is a random read method and the rear part is a sequential read method. That is, since the reading method is a continuous connection of both, detailed description is avoided here in order to avoid duplication of explanation.
  • the sequential read method sequentially reads from a specific area corresponding to the byte address read last when the random read method is completed.
  • FIG. 5 is a conceptual diagram illustrating the configuration of the I2C monitoring sequential read data storage device 130 (2) according to the first embodiment.
  • the I2C monitoring sequential read data storage device 130 (2) loads the byte address “Byte add” designating a specific area of the slave circuit 120 as an initial value of the address counter 290 (2). Thereby, it is possible to cope with any of the I2C reading methods of the sequential read method, the random read method, and the sequential random read method.
  • FIG. 5 the same parts as those already described in FIG. 2 are denoted by the same reference numerals, and the description is avoided here to avoid duplication of explanation, and the I2C monitoring sequential read data storage device The structure etc. which differ from 130 (1) are demonstrated.
  • the I2C monitoring sequential read data storage device 130 (2) includes a byte address decoder unit 510 that detects the timing at which a byte address is transmitted from the master circuit 110.
  • the I2C monitoring sequential read data storage device 130 (2) includes a byte address ack decoder unit 520 that detects timing at which “Ack” for byte address reception is transmitted from the slave circuit 120.
  • the byte address decoder unit 510 and the byte address ACK decoder unit 520 receive the count values of the bit counter 240 (2) and the byte counter 250 (2), respectively, and the bit counter 240 (2) and the byte counter 250 (2 ) And the respective timings are detected based on the count values.
  • the I2C monitoring sequential read data storage device 130 (2) includes a byte address register 530 that temporarily stores a byte address “Byte add” transmitted from the master circuit 110.
  • the byte address register 530 acquires and stores the byte address “Byte add” converted in parallel by the serial / parallel conversion unit 280 (2) at the timing detected by the byte address decoder unit 510.
  • the address counter 290 (2) loads (also referred to as acquisition) the byte address “Byte add” stored in the byte address register 530 as an initial value at the timing detected by the byte address ack decoder unit 520. After that, the address counter 290 (2) starts counting up sequentially from the loaded byte address “Byte add” when the second decoder unit 270 (2) detects the “Ack” signal timing after “read data”. To do.
  • the I2C monitoring sequential read data storage device 130 (2) has the configuration of the I2C monitoring sequential read data storage device 130 (1), and therefore can support a sequential method.
  • FIG. 6 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (2) in the case of the random method.
  • FIG. 6 shows an example in which the byte address “Byte add” instructed from the master circuit 110 is “7”.
  • the start detection unit 210 (2) detects the communication start signal “Start” from the master circuit 110
  • the set reset unit 230 (2) outputs an “enable” signal to the bit counter 240 (2).
  • the bit counter 240 (2) is initialized by the “enable” signal and starts counting up.
  • FIG. 7 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (2) in the case of the sequential random system.
  • FIG. 7 shows an example in which the byte address “Byte add” reads the equivalent of 10 bytes from “7”.
  • the start detection unit 210 (2) detects the communication start signal “Start” from the master circuit 110
  • the set / reset unit 230 (2) outputs an “enable” signal to the bit counter 240 (2).
  • the bit counter 240 (2) is initialized to zero by the “enable” signal, and starts counting up at the rising edge of the clock “scl”.
  • the byte counter 250 (2) is reset to zero by the communication start “Start” or the communication restart “Re Start”.
  • the address counter 290 (2) to which “enable” is input starts counting up sequentially from the initial values 7 to 16 already loaded.
  • the I2C monitoring sequential read data storage device 130 (2) sequentially acquires “read data8”, “read data9”,..., “Read data16” sequentially in the register 2b8.
  • Registers 2b9,... are stored in the register 2b16 by a trigger input from the third decoder unit 2a0 (2).
  • the address counter 290 counts up the number corresponding to the address of the slave circuit 120.
  • the Nack detection unit 220 (2) detects “Nack” instructing the end of communication transmitted from the master circuit 110 to the slave circuit 120, the operation and processing of the I2C monitoring sequential read data storage device 130 (2) Ends.
  • the I2C monitoring sequential read data storage device 130 (3) monitors the responses “Ack” and “Nack” from the slave circuit 120 after receiving the device address “Device add” or the byte address “Byte add”. To do.
  • the I2C monitoring sequential read data storage device 130 (3) stores only the read data “Read data” with high reliability, so that the reliability of the stored “Read data” can be improved. it can.
  • FIG. 8 and 14 are conceptual diagrams illustrating the configuration of the I2C monitoring sequential read data storage device 130 (3). If the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the I2C monitoring sequential read data storage device 130 (3) illustrated in FIG. 8 reads “Read” read from the slave circuit 120. This is a configuration example in which “data” is not stored.
  • the I2C monitoring sequential read data storage device 130 (3) includes an ack register 810 that temporarily stores “Ack” or “Nack” after receiving the byte address “Byte add”.
  • the ACK register 810 receives the trigger from the byte address ACK decoder unit 520 (2) that detects the timing at which “Ack” or “Nack” is transmitted from the slave circuit 120 in response to the byte address reception.
  • the “Ack” or “Nack” converted in parallel in (3) is temporarily stored.
  • the acknack register 810 masks the trigger output of the third decoder unit 2a0 (3) if the temporarily stored information is “Nack”.
  • the storage unit 2b (3) does not store “Read data” because the timing for storing the acquired “Read data” is not given.
  • the I2C monitoring sequential read data storage device 130 (3) is replaced with a byte address ack decoder unit 520 (2) that detects the timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120.
  • a device address ack decoder unit that detects the timing at which “Ack” or “Nack” for device address reception is transmitted from the slave circuit 120 together with the byte address ack decoder unit 520 (2) may be provided.
  • the I2C monitoring sequential read data storage device 130 (6) shown in FIG. 14 returns a response from the slave circuit 120 after receiving the device address “Device add” or from the slave circuit 120 after receiving the byte address “Byte add”. If at least one of the replies is “Nack”, the “Read data” read from the slave circuit 120 is not stored. Thereby, the I2C monitoring sequential read data storage device 130 (6) can hold storage data with higher reliability.
  • the I2C monitoring sequential read data storage device 130 (6) replaces the byte address ack decoder unit 520 (2) included in the I2C monitoring sequential read data storage device 130 (3), and a byte address device address ack decoder unit 520 (5). Is provided.
  • the byte address device address ack decoder unit 520 (5) has a timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120 and “Ack” or “Nack” for device address reception is the slave circuit 120. And the timing transmitted from.
  • the ACKNACK register 810 is “Ack” or “Nack” converted in parallel by the serial / parallel converter 280 (3) in response to a trigger input from the byte address device address ACK decoder 520 (5) that has detected the above timing. Is temporarily stored.
  • the ACKNACK register 810 masks the trigger output of the third decoder unit 2a0 (3) if the temporarily stored information is “Nack”.
  • the storage unit 2b (3) does not store “Read data” because the timing for storing the acquired “Read data” is not given.
  • FIG. 9 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (6) when the byte address is “7” in the random read method.
  • the I2C monitoring sequential read data storage device 130 (6) if the reply after receiving “Device add + Write” obtained by adding a write signal to the device address specifying the slave circuit 120 is “Nack”.
  • the acknowledge register 810 masks the third decoder unit 2a0 (3).
  • the storage unit 2b (3) is not given a timing to store the read “Read data7”, so that “Read data7” is stored in the register 2b7 ( It will not be stored in 3).
  • the I2C monitoring sequential read data storage device 130 (6) if the reply after receiving “Device add + Read” obtained by adding a read signal to the device address specifying the slave circuit 120 is “Nack”, the acknowledge register 810. Masks the third decoder section 2a0 (3). That is, “Device add” in the second embodiment is included in both cases of “Device add + Read” and “Device add + Write”.
  • the I2C monitoring sequential read data storage device 130 (4) described in the third embodiment is the same as the I2C monitoring sequential read data storage device 130 (3), 130 (6) described in the second embodiment.
  • the ACKNACK register 810 (2) replaces the Nack detection unit 220 (4) with the entire I2C monitoring sequential read data storage device 130 (4). End the operation and control.
  • the Nack detection unit 220 (4) performs the same reset operation as when the communication end signal “Nack” is detected. 4), and the I2C communication monitoring operation ends.
  • the I2C monitoring sequential read data storage device 130 (4) stops acquiring “Read data” in a situation where there may be an abnormality in the monitored I2C communication, so that data with low reliability is acquired. It is preferable because it is neither stored nor stored. In other words, for example, PI information stored in the I2C monitoring sequential read data storage device 130 (4) is only extremely reliable information.
  • FIG. 10 and 15 are block diagrams conceptually illustrating a configuration example of the I2C monitoring sequential read data storage device 130 (4). If the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the I2C monitoring sequential read data storage device 130 (3) shown in FIG. This is a configuration example waiting for “Start”.
  • the I2C monitoring sequential read data storage device 130 (4) includes an ACK register 810 (2) that temporarily stores “Ack” or “Nack” after receiving the byte address “Byte add”.
  • the ACKNACK register 810 (2) receives serial or parallel data in response to a trigger input from the byte address ACK decoder unit 520 (3) that detects the timing at which “Ack” or “Nack” is transmitted from the slave circuit 120 in response to byte address reception.
  • the “Ack” or “Nack” converted in parallel by the conversion unit 280 (4) is temporarily stored.
  • the acknowledge register 810 (2) outputs a signal to the Nack detection unit 220 (4).
  • the Nack detector 220 (4) causes the set / reset unit 230 (4) to output an initialization signal.
  • the bit counter 240 (4) to which the initialization signal of the set / reset unit 230 (4) is input stops counting up.
  • the I2C monitoring sequential read data storage device 130 (4) is replaced with a byte address ack decoder unit 520 (3) that detects the timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120.
  • a device address ack decoder unit that detects the timing at which “Ack” or “Nack” for device address reception is transmitted from the slave circuit 120 may be provided together with the byte address ack decoder unit 520 (3).
  • the I2C monitoring sequential read data storage device 130 (7) shown in FIG. 15 returns a response from the slave circuit 120 after receiving the device address “Device add” or from the slave circuit 120 after receiving the byte address “Byte add”. If at least one of the replies is “Nack”, the I2C monitoring operation is stopped and the communication start signal “Start” is waited. As a result, the I2C monitoring sequential read data storage device 130 (7) can hold storage data with higher reliability.
  • the I2C monitoring sequential read data storage device 130 (7) replaces the byte address ack decoder unit 520 (3) provided in the I2C monitoring sequential read data storage device 130 (4), and a byte address device address ack decoder unit 520 (6). Is provided.
  • the byte address device address ack decoder unit 520 (6) has a timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120, and “Ack” or “Nack” for device address reception is the slave circuit 120. And the timing transmitted from.
  • the ACK register 810 (2) receives “Ack” or “Ack” converted in parallel by the serial / parallel converter 280 (4) in response to a trigger input from the byte address device address ACK decoder 520 (6) that has detected the timing described above. “Nack” is temporarily stored.
  • the I2C monitoring sequential read data storage device 130 (7) ends the I2C monitoring operation and waits for “Start”.
  • FIG. 11 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (7) when the byte address is “7” in the random read method.
  • the I2C monitoring sequential read data storage device 130 (7) if the reply after receiving the device address “Device add” for specifying the slave circuit 120 is “Nack”, the acknowledge register 810 ( 2) causes the set reset unit 230 (4) to output the same output as when the Nack detection unit 220 (4) detects the communication end signal “Nack”.
  • the Nack detection unit 220 (4) stops the output of the “enable” signal to the set / reset unit 230 (4) to stop the count up of the bit counter 240 (4).
  • the I2C monitoring sequential read data storage device 130 (7) performs the I2C monitoring control operation if the reply after receiving “Device add + Read” obtained by adding a read signal to the device address specifying the slave circuit 120 is “Nack”. To stop. That is, “Device add” in the third embodiment is included in both cases of “Device add + Read” and “Device add + Write”.
  • the I2C monitoring sequential read data storage device 130 (5) includes a slave circuit 120 that is an information acquisition target when a plurality of slave circuits 120 are I2C connected to a single master circuit 110.
  • the expected value to be identified is compared with the acquired device address “Device add”.
  • the I2C monitoring sequential read data storage device 130 (5) becomes an information acquisition target only when the expected value that identifies the slave circuit 120 that is the information acquisition target matches the acquired device address “Device add”. PI information of a specific slave circuit 120 is acquired.
  • the I2C monitoring sequential read data storage device 130 (5) can acquire PI information and the like of the desired slave circuit 120 even when there are a plurality of slave circuits 120 in the connected I2C interface 140. It becomes possible.
  • FIG. 12 is a diagram conceptually illustrating a configuration outline of the I2C monitoring sequential read data storage device 130 (5).
  • the same parts as those already described in the above-described embodiment are denoted by the corresponding reference numerals, and detailed description is avoided here in order to avoid duplication of explanation.
  • the I2C monitoring sequential read data storage device 130 (5) includes a device address decoder unit 1210 that detects the timing at which the device address “Device add” is transmitted from the master circuit 110.
  • the device address decoder unit 1210 detects the timing at which the device address “Device add” is transmitted from the master circuit 110 based on the counter values of the bit counter 240 (5) and the byte counter 250 (5).
  • the I2C monitoring sequential read data storage device 130 (5) is a device address register that temporarily stores the device address “Device add” input from the serial data connection line 140a using the timing detected by the device address decoder unit 1210 as a trigger. 1220.
  • the device address “Device add” temporarily stored in the device address register 1220 is data converted into parallel by the serial / parallel conversion unit 280 (5).
  • the I2C monitoring sequential read data storage device 130 (5) includes a device address expected value comparison unit that compares the device address “Device add” temporarily stored in the device address register 1220 with a preset expected value. 1230.
  • the device address expected value comparison unit 1230 includes an expected value storage unit 1231 that stores a device address “Device add” corresponding to a specific slave circuit 120 that is an information acquisition target as an expected value.
  • the expected value stored in the expected value storage unit 1231 may be set in advance by an operator or the like.
  • the device address expected value comparison unit 1230 compares the device address “Device add” with the expected value, and if they match, the I2C monitoring sequential read data storage device 130 (5) continues the processing and reads “Read data”. ”And memorize.
  • the device address expected value comparison unit 1230 compares the device address “Device add” with the expected value and does not match, the device address expected value comparison unit 1230 sends a mismatch signal to the Nack detection unit 220 (5). Output.
  • the Nack detection unit 220 (5) receives the I2C monitoring sequential read data storage device 130 (5) in the same manner as when the communication end signal “Nack” is detected. To stop the monitoring operation.
  • the Nack detection unit 220 (5) receiving the mismatch signal causes the set reset unit 230 (5) to output an initialization signal.
  • the bit counter 240 (5) to which the initialization signal of the set / reset unit 230 (5) is input stops counting up.
  • the initialization signal of the set / reset unit 230 (5) typically corresponds to a process of lowering the “enable” flag for the bit counter 240 (5).
  • FIG. 13 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (5).
  • FIG. 13 shows an example in which the byte address “Byte add” is “7”.
  • the expected value storage unit 1230 stores in advance an expected value “A0h” corresponding to the device address of the slave circuit 120 that is the information acquisition target.
  • the device address “Device add” acquired by the I2C monitoring sequential read data storage device 130 (5) from the serial data connection line 140a is “C0h”, and a trigger from the device address decoder unit 1210 causes the device address register 1220 to store “ “C0h” is temporarily stored.
  • the device address expected value comparison unit 1230 compares “C0h” stored in the device address register 1220 with the expected value “A0h” stored in the expected value storage unit 1230 in advance.
  • the device address expected value comparison unit 1230 outputs a mismatch signal to the Nack detection unit 220 (5) because the comparison result does not match.
  • the Nack detection unit 220 (5) sends a trigger to reset the set reset unit 230 (5), and the set reset unit 230 (5) lowers the “enable” flag output to the bit counter 240 (5).
  • the bit counter 240 (5) stops counting up and enters a communication start “Start” waiting state. In this case, the I2C monitoring sequential read data storage device 130 (5) does not operate until the next communication start signal “Start” is acquired.
  • the I2C monitoring sequential read data storage device 130 (5) can extract normal read data even when a plurality of slave circuits 120 are connected.
  • the I2C monitoring sequential read data storage device 130 (8) described in the fifth embodiment has the same configuration as the configuration of the I2C monitoring sequential read data storage device 130 (2) illustrated in FIG. 5 described in the first embodiment. Become.
  • the address counter 290 (2) is reset to zero only when the I2C monitoring sequential read data storage device 130 (8) is powered on (powered on).
  • the I2C monitoring sequential read data storage device 130 Since the address counter 290 (2) is not reset except when the power is turned on, the I2C monitoring sequential read data storage device 130 (8) always holds the counter value of the address counter 290 (2) during the I2C monitoring operation. The value coincides with the byte address “Byte add” of the slave circuit 120.
  • the I2C monitoring sequential read data storage device 130 always holds the same read address as that of the slave circuit 120 and acquires normal read data even when accessed alternately by various read methods. Can remember.
  • the I2C monitoring sequential read data storage device 130 (8) is typically suitable when a read process is performed by the sequential read method after the random read method. After the communication between the master circuit 110 and the slave circuit 120 by the random method is completed, the last read byte address by the random method is held on the slave circuit 120 side. The slave circuit 120 only initializes the read address to zero when the power is turned on, and the last read address remains as long as the power is turned on.
  • the I2C monitoring sequential read data storage device 130 (8) is not initialized by the communication end signal “Nack” at the time when reading by the random method is completed, and the address counter 290 (2) is based on the random method Holds the read address at the end of the read.
  • the read address held by the slave circuit 120 matches the read address held by the I2C monitoring sequential read data storage device 130 (8), and both hold even if the sequential method is subsequently shifted. It is possible to sequentially read from the address.
  • the address counter 290 (2) is randomly set. The counter value becomes zero without holding the read address at the time when reading by the method is completed.
  • the read address held by the slave circuit 120 is the last address at the time when the random read is completed. That is, if the state is shifted to the sequential read method in this state, the initial value of the read address is different between the I2C monitoring sequential read data storage device 130 (8) and the slave circuit 120, so the I2C monitoring sequential read data storage device. 130 (8) cannot acquire accurate information.
  • the I2C monitoring sequential read data storage device 130 (8) described in the fifth embodiment includes a power-on reset of the address counter 290 (2) or a unit in which the I2C monitoring sequential read data storage device 130 (8) is incorporated. Since it is only at reset (however, the read target slave circuit 120 is not reset by resetting the unit), so even if I2C communication of various methods is continued, the desired information is obtained accurately. It is preferable because it can be stored.
  • the configurations of the I2C monitoring sequential read data storage device 130 (1) to the I2C monitoring sequential read data storage device 130 (8) illustrated in the first to fifth embodiments will be described in each embodiment.
  • the configuration is not limited, and the configuration can be changed as appropriate within the obvious range.
  • the operations and processes of the I2C monitoring sequential read data storage device 130 (1) to the I2C monitoring sequential read data storage device 130 (8) illustrated in the first to fifth embodiments are respectively performed. It is not limited to the description in the form, and its operation and processing can be changed as appropriate within the obvious range.
  • the present invention can be used for an apparatus for monitoring communication data between a master circuit and a slave circuit that communicate via an I2C interface.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Information Transfer Systems (AREA)

Abstract

Provided is an I2C monitor sequential read data storage device capable of dealing with various read schemes in highly versatile manner. The I2C monitor sequential read data storage device acquires communication data through an I2C interface between a master circuit and a slave circuit and is equipped with an address counter for counting the number of addresse equivalents of the slave circuit. When acquiring a byte address for specifying a predetermined region of the slave circuit, the I2C monitor sequential read data storage device sets the acquired byte address as an initial value of the address counter.

Description

Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置I2C monitoring sequential read data storage device
　本発明は、複数の読み出し方式に対応可能なＩ２Ｃ監視シーケンシャルリードデータ記憶装置に関する。 The present invention relates to an I2C monitoring sequential read data storage device that can support a plurality of reading methods.
　光モジュールやＬＳＩなどＩ２Ｃインターフェースを用いて監視したり制御する伝送装置は複数のユニットで構成されており、各ユニットは各ユニットのフィジカルインベントリ情報（以下、適宜ＰＩ情報と称する）が格納されたＥＥＰＲＯＭを備える。伝送装置は、各ユニットのＥＥＰＲＯＭからＩ２Ｃインターフェースを介してＰＩ情報を読み出す。 A transmission device that monitors and controls using an I2C interface such as an optical module or LSI is composed of a plurality of units, and each unit is an EEPROM in which physical inventory information (hereinafter referred to as PI information) of each unit is stored. Is provided. The transmission apparatus reads PI information from the EEPROM of each unit via the I2C interface.
　ユニットが伝送装置に実装された場合に、伝送装置はＩ２Ｃインターフェースを介してユニットのＥＥＰＲＯＭに予め格納されているＰＩ情報を読み出し制御して、ＰＩ情報を取得する。ＰＩ情報は、例えばユニットがトランスポンダである場合には、そのトランスポンダが担当する波長情報等ユニット固有の情報等である。 When the unit is mounted on the transmission device, the transmission device reads and controls the PI information stored in advance in the EEPROM of the unit via the I2C interface, and acquires the PI information. For example, when the unit is a transponder, the PI information is information unique to the unit such as wavelength information handled by the transponder.
　また、ユニットをバージョンアップするために差し替えた場合には、差し替えられたユニットのＰＩ情報を伝送装置がＩ２Ｃインターフェースにより読み出す。この際、Ｉ２Ｃインターフェースに接続されたＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、伝送装置とユニットとの間の必要なＩ２Ｃ通信データ（典型的にはＰＩ情報）を取得して記憶する。Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置に記憶されたＰＩ情報等は、他のユニット等で必要となった場合に利用される。 In addition, when the unit is replaced to upgrade the version, the transmission apparatus reads the PI information of the replaced unit through the I2C interface. At this time, the I2C monitoring sequential read data storage device connected to the I2C interface acquires and stores necessary I2C communication data (typically PI information) between the transmission device and the unit. The PI information and the like stored in the I2C monitoring sequential read data storage device is used when required by other units.
　また、伝送装置をマスタ側としてユニットのＥＥＰＲＯＭをスレーブ側とすれば、その間のＩ２Ｃインターフェースによる読み出し方式は、読み出し時間が比較的短いシーケンシャルリード方式や番地情報を指定したランダムリード方式やシーケンシャルランダムリード方式等が用いられる。 If the transmission device is the master side and the unit's EEPROM is the slave side, the read method using the I2C interface between them is a sequential read method with a relatively short read time, a random read method specifying address information, or a sequential random read method. Etc. are used.
　システムの初期設定などに要する時間の短縮を可能とし、通信処理手段の柔軟性を持たせるために、番地情報を指定したリード方式に加えて伝送時間の短いリード方式も実現する通信処理手段が、例えば下記特許文献１に開示されている。 Communication processing means that realizes a read method with a short transmission time in addition to a read method that specifies address information in order to shorten the time required for initial setting of the system and to provide flexibility of the communication processing means, For example, it is disclosed in Patent Document 1 below.
特開平８－３１６９７３号公報JP-A-8-316973
　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置が、単一のＩ２Ｃ読み出し方式にしか対応していなければ、例えば伝送装置とユニットとの間のＩ２Ｃインターフェースによる読み出し方式が異なる場合には通信データの読み出しができず、ユニット内のＥＥＰＲＯＭ等が有する所望の情報を取得できなくなる。 If the I2C monitoring sequential read data storage device only supports a single I2C read method, for example, if the read method using the I2C interface between the transmission device and the unit is different, the communication data cannot be read, It becomes impossible to acquire desired information held in the EEPROM or the like in the unit.
　そこで、マスタ回路側とスレーブ回路側との間のＩ２Ｃインターフェースによる様々な読み出し方式に対して、汎用性高く対応できるＩ２Ｃ監視シーケンシャルリードデータ記憶装置が期待される。 Therefore, an I2C monitoring sequential read data storage device capable of high versatility can be expected with respect to various read methods using an I2C interface between the master circuit side and the slave circuit side.
　本発明は、上述の問題点に鑑み為されたものであり、マスタ回路側とスレーブ回路側との間のＩ２Ｃインターフェースによる様々な読み出し方式に対して、汎用性高く対応できるＩ２Ｃ監視シーケンシャルリードデータ記憶装置を提供することを目的とする。 The present invention has been made in view of the above-described problems. I2C monitoring sequential read data storage that can cope with various read methods using an I2C interface between a master circuit side and a slave circuit side with high versatility. An object is to provide an apparatus.
　本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、マスタ回路とスレーブ回路とのＩ２Ｃインターフェースを介した通信データを取得するＩ２Ｃ監視シーケンシャルリードデータ記憶装置であって、スレーブ回路のアドレス相当数をカウントするアドレスカウンタを備え、スレーブ回路の所定領域を指定するバイトアドレスを取得した場合に、取得したバイトアドレスを、アドレスカウンタの初期値とする。 An I2C monitoring sequential read data storage device according to the present invention is an I2C monitoring sequential read data storage device that acquires communication data via an I2C interface between a master circuit and a slave circuit, and counts the address equivalent number of the slave circuit. When an address counter is provided and a byte address specifying a predetermined area of the slave circuit is acquired, the acquired byte address is set as an initial value of the address counter.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、好ましくは取得したバイトアドレスを一時記憶するバイトアドレスレジスタを備え、スレーブ回路がバイトアドレスの受信に対する正常信号を返信した場合に、バイトアドレスレジスタに一時記憶したバイトアドレスを、アドレスカウンタの初期値としてもよい。 The I2C monitoring sequential read data storage device according to the present invention preferably includes a byte address register for temporarily storing the acquired byte address, and when the slave circuit returns a normal signal for reception of the byte address, the byte address register The byte address temporarily stored in may be used as the initial value of the address counter.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはスレーブ回路を特定するデバイスアドレスまたはバイトアドレスを受信したスレーブ回路が、異常信号を返信した場合に、取得した通信データを記憶しなくてもよい。 The I2C monitoring sequential read data storage device according to the present invention more preferably stores the acquired communication data when the slave circuit that has received the device address or byte address specifying the slave circuit returns an abnormal signal. It does not have to be.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはスレーブ回路を特定するデバイスアドレスまたはバイトアドレスを受信したスレーブ回路の返信信号を一時記憶するアックナックレジスタと、アドレスカウンタのカウンタ値をデコードして取得した通信データを記憶するタイミングを出力するデコーダ部と、を備え、アックナックレジスタから入力された返信信号が異常信号である場合に、取得した通信データを記憶しないように、デコーダ部は、通信データを記憶するタイミングを出力しなくてもよい。 The I2C monitoring sequential read data storage device according to the present invention preferably further includes an acknowledge register for temporarily storing a reply signal of a slave circuit that has received a device address or byte address for specifying the slave circuit, and a counter value of the address counter. And a decoder unit that outputs timing for storing communication data acquired by decoding the data, and when the return signal input from the ACK register is an abnormal signal, the decoder does not store the acquired communication data The unit may not output the timing for storing the communication data.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはスレーブ回路を特定するデバイスアドレスの受信またはバイトアドレスを受信したスレーブ回路が、異常信号を返信した場合に、初期化されてもよい。 Further, the I2C monitoring sequential read data storage device according to the present invention is more preferably initialized even when the slave circuit receiving the device address or the byte address specifying the slave circuit returns an abnormal signal. Good.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはマスタ回路とスレーブ回路との間の通信を終了する終了信号を検出すると、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置を初期化するナック検出部を備え、ナック検出部は、アックナックレジスタから入力された返信信号が異常信号である場合に、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置を初期化してもよい。 Further, the I2C monitoring sequential read data storage device according to the present invention preferably further detects a termination signal for ending the communication between the master circuit and the slave circuit, and detects the N2 detection that initializes the I2C monitoring sequential read data storage device. The Nac detection unit may initialize the I2C monitoring sequential read data storage device when the return signal input from the acknack register is an abnormal signal.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくは複数のスレーブ回路がＩ２Ｃインターフェースを介して接続され、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置は、情報取得対象となるスレーブ回路を特定するデバイスアドレス期待値を予め設定され、デバイスアドレス期待値に対応するスレーブ回路の通信データを記憶してもよい。 In the I2C monitoring sequential read data storage device according to the present invention, more preferably, a plurality of slave circuits are connected via an I2C interface, and the I2C monitoring sequential read data storage device specifies a slave circuit that is an information acquisition target. An expected device address value may be set in advance, and communication data of the slave circuit corresponding to the expected device address value may be stored.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、情報取得対象となるスレーブ回路を特定するデバイスアドレス期待値を予め記憶する期待値記憶部と、期待値記憶部が記憶するデバイスアドレス期待値と、取得したデバイスアドレスと、を比較するデバイスアドレス期待値比較部とを備え、デバイスアドレス期待値比較部は、デバイスアドレス期待値と取得したデバイスアドレスとが異なる場合に、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の初期化信号を出力してもよい。 Further, the I2C monitoring sequential read data storage device according to the present invention is more preferably an I2C monitoring sequential read data storage device, wherein an expected value storage unit that stores in advance a device address expected value that specifies a slave circuit that is an information acquisition target; A device address expected value stored in the expected value storage unit and a device address expected value comparing unit that compares the acquired device address, and the device address expected value comparing unit includes the device address expected value and the acquired device address. May be output from the initialization signal of the I2C monitoring sequential read data storage device.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはアドレスカウンタとスレーブ回路のアドレスカウントとは合致するように、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の電源投入時のみにアドレスカウンタを初期化してもよい。 The I2C monitoring sequential read data storage device according to the present invention preferably initializes the address counter only when the I2C monitoring sequential read data storage device is turned on so that the address counter matches the address count of the slave circuit. May be used.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはアドレスカウンタが、マスタ回路からスレーブ回路に送信されるスタート信号を取得した場合も、マスタ回路からスレーブ回路に送信されるリスタート信号を取得した場合も、いずれの場合にも初期化されなくてもよい。 Further, in the I2C monitoring sequential read data storage device according to the present invention, it is more preferable that the restart is transmitted from the master circuit to the slave circuit even when the address counter acquires the start signal transmitted from the master circuit to the slave circuit. Even if the signal is acquired, it may not be initialized in either case.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはスレーブ回路がＥＥＰＲＯＭであり、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置は、マスタ回路がＩ２Ｃインターフェースを介して読み出したＥＥＰＲＯＭの所定領域に記憶されたデータを取得して記憶する記憶部を備えてもよい。 In the I2C monitoring sequential read data storage device according to the present invention, the slave circuit is preferably an EEPROM, and the I2C monitoring sequential read data storage device is stored in a predetermined area of the EEPROM read by the master circuit via the I2C interface. A storage unit that acquires and stores the processed data may be provided.
　また、本発明にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置は、さらに好ましくはＩ２Ｃインターフェースの読み出し方式が、ランダムリード方式またはシーケンシャルリード方式またはシーケンシャルランダムリード方式のいずれか一つ以上の方式であってもよい。 In the I2C monitoring sequential read data storage device according to the present invention, more preferably, the read method of the I2C interface may be any one or more of a random read method, a sequential read method, and a sequential random read method. .
　様々な読み出し方式に対して、汎用性高く対応できるＩ２Ｃ監視シーケンシャルリードデータ記憶装置を提供できる。 It is possible to provide an I2C monitoring sequential read data storage device that can handle various read methods with high versatility.
マスタ回路－スレーブ回路間通信装置の構成を例示する概念図である。It is a conceptual diagram which illustrates the structure of the communication apparatus between a master circuit and a slave circuit. シーケンシャルリード方式に対応したＩ２Ｃ監視シーケンシャルリードデータ記憶装置の構成概要を例示する図である。It is a figure which illustrates the structure outline | summary of the I2C monitoring sequential read data storage device corresponding to a sequential read system. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の動作処理の概要を示すタイミングチャート概念図である。It is a timing chart conceptual diagram which shows the outline | summary of the operation processing of an I2C monitoring sequential read data storage device. ３種類のＩ２Ｃ通信方式について説明する概念図である。It is a conceptual diagram explaining three types of I2C communication systems. 第一の実施形態にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置の構成を説明する概念図である。It is a conceptual diagram explaining the structure of the I2C monitoring sequential read data storage device concerning 1st embodiment. シーケンシャルランダム方式である場合のＩ２Ｃ監視シーケンシャルリードデータ記憶装置の動作と処理との概要を説明するチャート図である。It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device in the case of a sequential random system. シーケンシャルランダム方式である場合のＩ２Ｃ監視シーケンシャルリードデータ記憶装置の動作と処理との概要を説明するチャート図である。It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device in the case of a sequential random system. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の構成を例示する概念図である。It is a conceptual diagram which illustrates the structure of an I2C monitoring sequential read data storage device. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の動作及び処理の概要を説明するチャート図である。It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の構成例を概念的に説明するブロック図である。It is a block diagram which illustrates notionally the structural example of an I2C monitoring sequential read data storage device. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の動作及び処理の概要を説明するチャート図である。It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の構成概要を概念的に説明する図である。It is a figure which illustrates notionally the structure outline | summary of an I2C monitoring sequential read data storage device. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の動作と処理との概要を説明するチャート図である。It is a chart figure explaining the outline | summary of operation | movement and a process of an I2C monitoring sequential read data storage device. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の構成を例示する概念図である。It is a conceptual diagram which illustrates the structure of an I2C monitoring sequential read data storage device. Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の構成を例示する概念図である。It is a conceptual diagram which illustrates the structure of an I2C monitoring sequential read data storage device.
符号の説明Explanation of symbols
　１００・・マスタ回路－スレーブ回路間通信装置、１１０・・マスタ回路、１２０・・スレーブ回路、１３０・・Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置、１４０・・Ｉ２Ｃインターフェース、１５０・・通信ユニット。 100..Master circuit-slave circuit communication device 110..Master circuit 120..Slave circuit 130..I2C monitoring sequential read data storage device 140..I2C interface 150..Communication unit.
　Ｉ２Ｃを制御する側の回路をマスタ回路とし、Ｉ２Ｃにより制御される側の回路をスレーブ回路とする。スレーブ回路は、典型的にはＥＥＰＲＯＭ等のメモリである。Ｉ２Ｃインターフェースにより接続されたマスタ回路とスレーブ回路とは、スレーブ回路に書き込まれているデータを、マスタ回路以外のユニット内で必要とされる場合がある。 The circuit on the side that controls I2C is a master circuit, and the circuit that is controlled by I2C is a slave circuit. The slave circuit is typically a memory such as an EEPROM. The master circuit and slave circuit connected by the I2C interface may require data written in the slave circuit in a unit other than the master circuit.
　このような場合には、既存のマスタ回路とスレーブ回路とに影響を及ぼすことなく、Ｉ２Ｃインターフェースを監視して必要なデータを取得することが好ましい。Ｉ２Ｃ監視リードデータ記憶装置は、マスタ回路がスレーブ回路に対してＩ２Ｃインターフェースを介して読み出し制御をする際に、読み出されたデータ（リードデータとも称する）を取り出す。そこで、以下シーケンシャルリード方式等のＩ２Ｃ読み出し方式について詳細に説明した上で、各実施形態について説明をすることとする。 In such a case, it is preferable to monitor the I2C interface and acquire necessary data without affecting the existing master circuit and slave circuit. The I2C monitoring read data storage device retrieves read data (also referred to as read data) when the master circuit performs read control on the slave circuit via the I2C interface. Accordingly, each embodiment will be described after the I2C reading method such as the sequential read method is described in detail.
　図１は、マスタ回路－スレーブ回路間通信装置１００の構成を例示する概念図である。図１に示すように、スレーブ回路１２０とマスタ回路１１０との間は、Ｉ２Ｃインターフェース１４０を介して接続される。また、Ｉ２Ｃインターフェース１４０は、シリアルデータ（適宜ＳＤＡまたはｓｄａとも称する）接続線１４０ａと、シリアルクロック（適宜ＳＣＬまたはｓｃｌとも称する）接続線１４０ｂとがあり、各々双方向通信が可能なように接続される。 FIG. 1 is a conceptual diagram illustrating the configuration of a communication device 100 between a master circuit and a slave circuit. As shown in FIG. 1, the slave circuit 120 and the master circuit 110 are connected via an I2C interface 140. The I2C interface 140 includes a serial data (appropriately referred to as SDA or sda) connection line 140a and a serial clock (appropriately also referred to as SCL or scl) connection line 140b, which are connected so as to enable bidirectional communication. The
　また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０は、シリアルデータ接続線１４０ａとシリアルクロック接続線１４０ｂとの通信データを各々分岐入力されるように、シリアルデータ接続線１４０ａとシリアルクロック接続線１４０ｂとに接続される。シリアルデータ接続線１４０ａは、典型的にはスレーブ回路１２０から読み出されたＰＩ情報等の各種情報を通信データとして伝送する。また、シリアルクロック接続線１４０ｂは、典型的にはスレーブ回路１２０とマスタ回路１１０との間で同期させるためのクロック信号を伝送する。 Further, the I2C monitoring sequential read data storage device 130 is connected to the serial data connection line 140a and the serial clock connection line 140b so that the communication data of the serial data connection line 140a and the serial clock connection line 140b are respectively branched and input. Is done. The serial data connection line 140a typically transmits various information such as PI information read from the slave circuit 120 as communication data. The serial clock connection line 140b typically transmits a clock signal for synchronization between the slave circuit 120 and the master circuit 110.
　図１に示すマスタ回路－スレーブ回路間通信装置１００においては、上述した接続構成により、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０が、スレーブ回路１２０とマスタ回路１１０との間の通信データを必要に応じて取得できる。 In the master circuit-slave circuit communication device 100 shown in FIG. 1, the I2C monitoring sequential read data storage device 130 transmits communication data between the slave circuit 120 and the master circuit 110 as necessary by the above-described connection configuration. You can get it.
　典型的には、スレーブ回路１００が予めＰＩ情報を格納されたＥＥＰＲＯＭであれば、マスタ回路１１０がＥＥＰＲＯＭのＰＩ情報を読み出し制御する際に、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０が、Ｉ２Ｃインターフェースを経由する読み出されたＰＩ情報を取得し記憶することができる。 Typically, if the slave circuit 100 is an EEPROM in which PI information is stored in advance, when the master circuit 110 reads and controls the PI information of the EEPROM, the I2C monitoring sequential read data storage device 130 passes through the I2C interface. The read PI information can be acquired and stored.
　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０は、シーケンシャルリード方式で読み出すことで、スレーブ回路１２０内の全てのＰＩ情報等の全データを一回の読み出し制御により一括して比較的短時間で読み出すことが可能である。シーケンシャルリード方式に対応する読み出し回路は、回路規模を比較的シンプルかつ小さくすることが可能であり、安価にできるので多用される傾向にある。 The I2C monitoring sequential read data storage device 130 can read all data such as all PI information in the slave circuit 120 collectively in a relatively short time by one read control by reading by the sequential read method. It is. A read circuit corresponding to the sequential read method tends to be frequently used because the circuit scale can be made relatively simple and small and can be made inexpensive.
　なお、図１においては、マスタ回路１１０とＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０とが、通信ユニット１５０内に備えられる構成として記載したが、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０の配置位置はこれに限定されるものではない。例えば、スレーブ回路１２０が配置されたユニットがその機能を有するように、スレーブ回路１２０とＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０とを同一ユニットに構成してもよい。 In FIG. 1, the master circuit 110 and the I2C monitoring sequential read data storage device 130 are described as being provided in the communication unit 150, but the arrangement position of the I2C monitoring sequential read data storage device 130 is limited to this. Is not to be done. For example, the slave circuit 120 and the I2C monitoring sequential read data storage device 130 may be configured in the same unit so that the unit in which the slave circuit 120 is disposed has the function.
　ここで、シーケンシャルリード方式に対応したＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）の構成概要について説明する。図２は、シーケンシャルリード方式のみに対応したＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）の構成概要を例示する図である。 Here, an outline of the configuration of the I2C monitoring sequential read data storage device 130 (1) corresponding to the sequential read method will be described. FIG. 2 is a diagram illustrating an outline of the configuration of the I2C monitoring sequential read data storage device 130 (1) that supports only the sequential read method.
　図２に示すようにＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）は、マスタ回路１１０とスレーブ回路１２０との間の通信スタート信号が、シリアルデータ接続線１４０ａから入力されたことを検出するスタート検出部２１０を備える。また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）は、マスタ回路１１０とスレーブ回路１２０との間の通信終了信号（ナック「Ｎａｃｋ」とも称する）が、シリアルデータ接続線１４０ａから入力されたことを検出するナック（「Ｎａｃｋ」とも称する）検出部２２０を備える。 As shown in FIG. 2, the I2C monitoring sequential read data storage device 130 (1) detects that the communication start signal between the master circuit 110 and the slave circuit 120 is input from the serial data connection line 140a. The unit 210 is provided. Further, the I2C monitoring sequential read data storage device 130 (1) confirms that a communication end signal (also referred to as “nack“ Nack ”) between the master circuit 110 and the slave circuit 120 is input from the serial data connection line 140a. A nack (also referred to as “Nack”) detection unit 220 for detection is provided.
　セットリセット部２３０は、スタート検出部２１０がスタート信号を検出すると、「ｅｎａｂｌｅ」信号をビットカウンタ２４０に出力し、「ｅｎａｂｌｅ」信号により初期化されたビットカウンタ２４０がカウントアップを開始する。また、セットリセット部２３０は、Ｎａｃｋ検出部２２０が通信終了信号を検出すると、ビットカウンタ２４０をディスエーブルとする。次の「Ｓｔａｒｔ」検出時に、Ｉ２Ｃ監視シーケンシャルデータ記憶装置１３０全体を初期化する。Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）全体を初期化すると、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）が備える各種カウンタのカウンタ値は典型的にはゼロにリセットされることとなる。 When the start detection unit 210 detects the start signal, the set reset unit 230 outputs an “enable” signal to the bit counter 240, and the bit counter 240 initialized by the “enable” signal starts counting up. Further, the set / reset unit 230 disables the bit counter 240 when the Nack detection unit 220 detects a communication end signal. When the next “Start” is detected, the entire I2C monitoring sequential data storage device 130 is initialized. When the entire I2C monitoring sequential read data storage device 130 (1) is initialized, the counter values of various counters provided in the I2C monitoring sequential read data storage device 130 (1) are typically reset to zero.
　ビットカウンタ２４０が０乃至８ビットの計９ビットをカウントすると、バイトカウンタ２５０が初期値ゼロから１バイトずつカウントアップする。典型的には、ビットカウンタ２４０がカウントする計９ビットのうち８ビット相当分が読み出しデータ等であり、ビットカウンタ２４０がカウントする計９ビットのうち１ビット相当分が読み出しデータの受信に対するマスタ回路１１０からの返信であるアック（「Ａｃｋ」とも称する）信号またはナック信号となる。なお、バイトカウンタ２５０は、通信スタート「Ｓｔａｒｔ」または通信再スタート「Ｒｅ　Ｓｔａｒｔ」により、ゼロにリセットされる。 When the bit counter 240 counts 9 bits from 0 to 8 bits, the byte counter 250 counts up one byte at a time from the initial value zero. Typically, 8 bits out of a total of 9 bits counted by the bit counter 240 are read data or the like, and 1 bit out of a total of 9 bits counted by the bit counter 240 is a master circuit for receiving read data. An ACK (also referred to as “Ack”) signal or a NACK signal, which is a reply from 110. The byte counter 250 is reset to zero by a communication start “Start” or a communication restart “Re Start”.
　また、第一デコーダ部２６０は、バイトカウンタ２５０のカウンタ値等から、マスタ回路１１０がスレーブ回路１２０へ読み出し指示する「ｒｅａｄ　ｂｉｔ」のタイミングを検知する。 Also, the first decoder 260 detects the timing of “read bit” that the master circuit 110 instructs the slave circuit 120 to read from the count value of the byte counter 250 and the like.
　第二デコーダ部２７０は、バイトカウンタ２５０のカウンタ値等に基づいて、スレーブ回路１２０から読み出されたデータ（「ｒｅａｄ　ｄａｔａ」とも称する）を受信したマスタ回路１１０が、スレーブ回路１２０にアック信号を通知するタイミングを検知する。 The second decoder unit 270 receives the data read from the slave circuit 120 (also referred to as “read data”) based on the counter value of the byte counter 250, and the master circuit 110 sends an acknowledgment signal to the slave circuit 120. Detect the notification timing.
　第二デコーダ部２７０が、「ｒｅａｄ　ｄａｔａ」後のアック信号のタイミングを検知すると「ｅｎａｂｌｅ」信号がアドレスカウンタ２９０へと出力されて、アドレスカウンタ２９０がカウントアップを開始する。第三デコーダ部２ａ０は、アドレスカウンタ２９０のカウンタ値から、読み出されたデータを記憶部２ｂに記憶させるタイミングを検知する。なお、アドレスカウンタ２９０は、スレーブ回路１２０のアドレス相当数をカウントアップする。 When the second decoder section 270 detects the timing of the ACK signal after “read data”, an “enable” signal is output to the address counter 290, and the address counter 290 starts counting up. The third decoder unit 2a0 detects the timing at which the read data is stored in the storage unit 2b from the counter value of the address counter 290. The address counter 290 counts up the number corresponding to the address of the slave circuit 120.
　シリアル／パラレル変換部２８０は、シリアルデータ接続線１４０ａから入力された通信データ（典型的にはＥＥＰＲＯＭから読み出されたデータ）をパラレル変換する。また、記憶部２ｂは、シリアル／パラレル変換部２８０によりパラレル変換されたデータを、第三デコーダ部２ａ０が検知したタイミングで記憶する。 The serial / parallel converter 280 performs parallel conversion on communication data (typically data read from the EEPROM) input from the serial data connection line 140a. The storage unit 2b stores the data converted in parallel by the serial / parallel conversion unit 280 at the timing detected by the third decoder unit 2a0.
　記憶部２ｂは、典型的には８ビット毎に順次取得される「ｒｅａｄ　ｄａｔａ０」、「ｒｅａｄ　ｄａｔａ１」、・・、「ｒｅａｄ　ｄａｔａｎ」をそれぞれ、順次レジスタ２ｂ０、レジスタ２ｂ１、・・レジスタ２ｂｎ（ｎは任意の自然数であり、典型的には２５５である）に、第三デコーダ部２ａ０からのトリガ入力により記憶する。 The storage unit 2b typically stores “read data0”, “read data1”,..., “Read datatan”, which are sequentially acquired every 8 bits, sequentially in register 2b0, register 2b1, and register 2bn (n Is an arbitrary natural number, typically 255), and is stored by the trigger input from the third decoder unit 2a0.
　ビットカウンタ２４０とバイトカウンタ２５０とシリアル／パラレル変換部２８０とアドレスカウンタ２９０とには、各々シリアルクロック接続線１４０ｂからクロック信号が入力される。すなわち、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）は、マスタ回路１１０とスレーブ回路１２０とに同期して動作処理する。 The clock signal is input to the bit counter 240, the byte counter 250, the serial / parallel converter 280, and the address counter 290 from the serial clock connection line 140b. That is, the I2C monitoring sequential read data storage device 130 (1) performs operation processing in synchronization with the master circuit 110 and the slave circuit 120.
　図３は、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）の動作処理の概要を示すタイミングチャート概念図である。図３においては、スレーブ回路１２０のメモリ容量が２５６バイトである場合のチャートを例示したものである。 FIG. 3 is a timing chart conceptual diagram showing an outline of operation processing of the I2C monitoring sequential read data storage device 130 (1). FIG. 3 illustrates a chart when the memory capacity of the slave circuit 120 is 256 bytes.
　図３において、スタート検出部２１０が通信スタート信号を検出すると、セットリセット部２３０が「ｅｎａｂｌｅ」信号を出力する。ビットカウンタ２４０は、「ｅｎａｂｌｅ」信号によりゼロにリセットされてカウントアップを開始する。また、シリアルデータ接続線１４０ａから入力された「ｒｅａｄ　ｄａｔａ０」は、第三デコーダ部２ａ０が指示するタイミングでレジスタ２ｂ０に記憶される。 In FIG. 3, when the start detection unit 210 detects a communication start signal, the set reset unit 230 outputs an “enable” signal. The bit counter 240 is reset to zero by the “enable” signal and starts counting up. Also, “read data0” input from the serial data connection line 140a is stored in the register 2b0 at a timing instructed by the third decoder unit 2a0.
　一方、第二デコーダ部２７０が、「ｒｅａｄ　ｄａｔａ０」の後のＡｃｋ信号タイミングを検出すると、アドレスカウンタ２９０が順次カウントアップを開始する。なお、シーケンシャル方式においては、アドレスカウンタ２９０は、その後バイトカウンタ２５０のカウント値に対して１バイト遅れるように２５５バイトまで順次カウントアップする。すなわち、アドレスカウンタ２９０のカウント値が１の場合には、「ｒｅａｄ　ｄａｔａ１」がレジスタ２ｂ１に、第三デコーダ部２ａ０が指示するタイミングで格納される。また、アドレスカウンタ２９０のカウント値が２５５の場合には、「ｒｅａｄ　ｄａｔａ２５５」がレジスタ２ｂ２５５に、第三デコーダ部２ａ０が指示するタイミングで格納される。 On the other hand, when the second decoder unit 270 detects the Ack signal timing after “read data0”, the address counter 290 starts counting up sequentially. In the sequential method, the address counter 290 sequentially counts up to 255 bytes so as to be delayed by 1 byte with respect to the count value of the byte counter 250 thereafter. That is, when the count value of the address counter 290 is 1, “read data1” is stored in the register 2b1 at a timing instructed by the third decoder unit 2a0. When the count value of the address counter 290 is 255, “read data 255” is stored in the register 2b255 at the timing indicated by the third decoder unit 2a0.
　また、Ｎａｃｋ検出部２２０が通信終了を指示するＮａｃｋ信号を検出すると、セットリセット部２３０の「ｅｎａｂｌｅ」出力が停止されて、ビットカウンタ２４０のカウントアップが停止する。ビットカウンタ２４０のカウントアップが停止すると、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）の動作処理が停止する。 Further, when the Nack detection unit 220 detects a Nack signal instructing the end of communication, the “enable” output of the set reset unit 230 is stopped and the count up of the bit counter 240 is stopped. When the count-up of the bit counter 240 is stopped, the operation process of the I2C monitoring sequential read data storage device 130 (1) is stopped.
　図４は、３種類のＩ２Ｃ通信方式について説明する概念図である。図４（ａ）はランダムリード方式についてマスタ回路１１０とスレーブ回路１２０との間のＩ２Ｃ通信を説明する概念図である。また、図４（ｂ）はシーケンシャルリード方式についてマスタ回路１１０とスレーブ回路１２０との間のＩ２Ｃ通信を説明する概念図である。また、図４（ｃ）はシーケンシャルランダムリード方式についてマスタ回路１１０とスレーブ回路１２０との間のＩ２Ｃ通信を説明する概念図である。 FIG. 4 is a conceptual diagram illustrating three types of I2C communication methods. FIG. 4A is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 for the random read method. FIG. 4B is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 in the sequential read method. FIG. 4C is a conceptual diagram illustrating I2C communication between the master circuit 110 and the slave circuit 120 in the sequential random read method.
　図４（ａ）に示すように、ランダムリード方式においては、マスタ回路１１０から通信スタート信号「Ｓｔａｒｔ」と、スレーブ回路１２０を特定するデバイスアドレスに書き込み信号を加えた「Ｄｅｖｉｃｅ　ａｄｄ＋Ｗｒｉｔｅ」と、が送信される。 As shown in FIG. 4A, in the random read method, the master circuit 110 transmits a communication start signal “Start” and “Device add + Write” in which a write signal is added to a device address that identifies the slave circuit 120. Is done.
　スレーブ回路１２０は、「Ｄｅｖｉｃｅ　ａｄｄ＋Ｗｒｉｔｅ」を正しく受信すると、マスタ回路１１０に「Ａｃｋ」を返信する。また、スレーブ回路１２０は、「Ｄｅｖｉｃｅ　ａｄｄ＋Ｗｒｉｔｅ」を正しく受信しなければ、マスタ回路１１０に「Ｎａｃｋ」を返信する。「Ｄｅｖｉｃｅ　ａｄｄ＋Ｗｒｉｔｅ」を正しく受信しない場合とは、例えば指示されたデバイスアドレスに該当するスレーブ回路１２０が存在しない場合等がある。 When the slave circuit 120 correctly receives “Device add + Write”, it returns “Ack” to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Write”, it returns “Nack” to the master circuit 110. The case where “Device add + Write” is not correctly received includes, for example, the case where there is no slave circuit 120 corresponding to the instructed device address.
　なお、ここでスレーブ回路１２０から返信される「Ｎａｃｋ」は通信終了信号とは異なるので、Ｎａｃｋ検出部２２０が検出することはなく、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）の動作と処理とが終了することはない。 Here, since “Nack” returned from the slave circuit 120 is different from the communication end signal, the Nack detection unit 220 does not detect it, and the operation and processing of the I2C monitoring sequential read data storage device 130 (1) are not detected. Never ends.
　次に、マスタ回路１１０が、スレーブ回路１２０の特定領域を指定するバイトアドレス「Ｂｙｔｅ　ａｄｄ」を送信する。バイトアドレスは、典型的にはＥＥＰＲＯＭの読み出し対象情報が格納されているアドレスとなる。 Next, the master circuit 110 transmits a byte address “Byte add” designating a specific area of the slave circuit 120. The byte address is typically an address where information to be read from the EEPROM is stored.
　スレーブ回路１２０は、「Ｂｙｔｅ　ａｄｄ」を正しく受信すると、マスタ回路１１０にＡｃｋを返信する。また、スレーブ回路１２０は、「Ｂｙｔｅ　ａｄｄ」を正しく受信しなければ、マスタ回路１１０にＮａｃｋを返信する。「Ｂｙｔｅ　ａｄｄ」を正しく受信しない場合とは、例えば指示されたバイトアドレスに該当するメモリ領域が存在しない場合等がある。 When the slave circuit 120 correctly receives “Byte add”, it returns Ack to the master circuit 110. If the slave circuit 120 does not correctly receive “Byte add”, it returns Nack to the master circuit 110. The case where “Byte add” is not correctly received includes, for example, the case where there is no memory area corresponding to the designated byte address.
　次に、マスタ回路１１０から通信再スタート信号「Ｒｅ　Ｓｔａｒｔ」と、スレーブ回路１２０を特定するデバイスアドレスに読み出し信号を加えた「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」と、が送信される。 Next, the communication restart signal “Re Start” and “Device add + Read” obtained by adding a read signal to the device address that identifies the slave circuit 120 are transmitted from the master circuit 110.
　スレーブ回路１２０は、「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」を正しく受信すると、マスタ回路１１０にＡｃｋを返信する。また、スレーブ回路１２０は、「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」を正しく受信しなければ、マスタ回路１１０にＮａｃｋを返信する。また、スレーブ回路１２０は、指定されたバイトアドレスに格納されている情報を読み出した「Ｒｅａｄ　ｄａｔａ」をマスタ回路１１０に送信する。 When the slave circuit 120 correctly receives “Device add + Read”, the slave circuit 120 returns Ack to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Read”, it returns Nack to the master circuit 110. In addition, the slave circuit 120 transmits “Read data” obtained by reading the information stored in the designated byte address to the master circuit 110.
　最後に、マスタ回路１１０は、通信終了を指示する「Ｎａｃｋ」をスレーブ回路１２０に送信してマスタ回路１１０とスレーブ回路１２０との通信が終了する。ランダムリード方式においては、読み出し対象となる情報ごとに、読み出し対象となる情報が格納されているスレーブ回路１２０を特定する情報（「Ｄｅｖｉｃｅ　ａｄｄ」に対応）と、格納場所を特定する情報（「Ｂｙｔｅ　ａｄｄ」）とをマスタ回路１１０が指示することとなる。これにより、マスタ回路１１０は、所望の情報を任意の順序で読み出すことができる。以上が、ランダムリード方式のＩ２Ｃ通信の概要説明となる。 Finally, the master circuit 110 transmits “Nack” instructing the end of communication to the slave circuit 120, and the communication between the master circuit 110 and the slave circuit 120 is completed. In the random read method, for each piece of information to be read, information for specifying the slave circuit 120 in which the information to be read is stored (corresponding to “Device add”) and information for specifying the storage location (“Byte”). add ") is instructed by the master circuit 110. Thereby, the master circuit 110 can read desired information in an arbitrary order. The above is an outline of the random read type I2C communication.
　また、図４（ｂ）に示すように、シーケンシャルリード方式においては、マスタ回路１１０から通信スタート信号「Ｓｔａｒｔ」と、スレーブ回路１２０を特定するデバイスアドレスに読み出し信号を加えた「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」と、が送信される。 Also, as shown in FIG. 4B, in the sequential read method, the communication start signal “Start” from the master circuit 110 and “Device add + Read” obtained by adding a read signal to the device address specifying the slave circuit 120; Is sent.
　スレーブ回路１２０は、「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」を正しく受信すると、マスタ回路１１０に「Ａｃｋ」を返信する。また、スレーブ回路１２０は、「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」を正しく受信しなければ、マスタ回路１１０に「Ｎａｃｋ」を返信する。「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」を正しく受信しない場合とは、例えば指示されたデバイスアドレスに該当するスレーブ回路１２０が存在しない場合等がある。 When the slave circuit 120 correctly receives “Device add + Read”, it returns “Ack” to the master circuit 110. If the slave circuit 120 does not correctly receive “Device add + Read”, it returns “Nack” to the master circuit 110. The case where “Device add + Read” is not correctly received includes, for example, the case where there is no slave circuit 120 corresponding to the instructed device address.
　シーケンシャルリード方式においては、マスタ回路１１０が、スレーブ回路１２０の特定領域を指定するバイトアドレス「Ｂｙｔｅ　ａｄｄ」を送信する必要はない。マスタ回路１１０は、典型的にはＥＥＰＲＯＭに格納されている情報を、最初のアドレスから順次全て読み出すこととなる。 In the sequential read method, the master circuit 110 does not need to transmit a byte address “Byte add” that designates a specific area of the slave circuit 120. The master circuit 110 typically reads all the information stored in the EEPROM sequentially from the first address.
　指定されたスレーブ回路１２０は、格納されている情報を読み出した「Ｒｅａｄ　ｄａｔａ」をマスタ回路１１０に送信する。マスタ回路１１０は、「Ｒｅａｄ　ｄａｔａ」を正しく受信すれば、スレーブ回路１２０に「Ａｃｋ」を返信する。その後、スレーブ回路１２０は、格納されている情報を順次読み出した「Ｒｅａｄ　ｄａｔａ」をマスタ回路１１０に順次送信する。また、マスタ回路１１０は、「Ｒｅａｄ　ｄａｔａ」を正しく受信する毎に、スレーブ回路１２０に「Ａｃｋ」を返信する。 The designated slave circuit 120 transmits “Read data” obtained by reading the stored information to the master circuit 110. If the master circuit 110 correctly receives “Read data”, it returns “Ack” to the slave circuit 120. Thereafter, the slave circuit 120 sequentially transmits “Read data” obtained by sequentially reading stored information to the master circuit 110. Also, the master circuit 110 returns “Ack” to the slave circuit 120 every time it correctly receives “Read data”.
　最後に、マスタ回路１１０は、通信終了を指示する「Ｎａｃｋ」をスレーブ回路１２０に送信してマスタ回路１１０とスレーブ回路１２０との通信が終了する。シーケンシャルリード方式においては、読み出し対象となる情報ごとに、格納場所を特定する情報（「Ｂｙｔｅ　ａｄｄ」に対応）とをマスタ回路１１０が指示する必要がない。これにより、マスタ回路１１０は、所望の情報を比較的迅速に読み出すことができる。以上が、シーケンシャルリード方式のＩ２Ｃ通信の概要説明となる。 Finally, the master circuit 110 transmits “Nack” instructing the end of communication to the slave circuit 120, and the communication between the master circuit 110 and the slave circuit 120 is completed. In the sequential read method, it is not necessary for the master circuit 110 to instruct information specifying the storage location (corresponding to “Byte add”) for each piece of information to be read. Thereby, the master circuit 110 can read desired information relatively quickly. The above is an outline of the sequential read type I2C communication.
　また、図４（ｃ）に示すように、シーケンシャルランダムリード方式においては、前段部がランダムリード方式であり後段部がシーケンシャルリード方式である。すなわち、両者を連続的に繋げた読み出し方式となるので、説明の重複を避けるためにここでは詳述を避ける。 Further, as shown in FIG. 4C, in the sequential random read method, the front part is a random read method and the rear part is a sequential read method. That is, since the reading method is a continuous connection of both, detailed description is avoided here in order to avoid duplication of explanation.
　シーケンシャルランダムリード方式においては、ランダムリード方式が終了した時点での最後に読み出されたバイトアドレスに対応する特定領域から、シーケンシャルリード方式により順次読み出されることとなる。 In the sequential random read method, the sequential read method sequentially reads from a specific area corresponding to the byte address read last when the random read method is completed.
　（第一の実施形態）
　図５は、第一の実施形態にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）の構成を説明する概念図である。Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）は、スレーブ回路１２０の特定領域を指定するバイトアドレス「Ｂｙｔｅ　ａｄｄ」を、アドレスカウンタ２９０（２）の初期値としてロードする。これにより、シーケンシャルリード方式とランダムリード方式とシーケンシャルランダムリード方式とのいずれのＩ２Ｃ読み出し方式に対しても対応可能である。 (First embodiment)
FIG. 5 is a conceptual diagram illustrating the configuration of the I2C monitoring sequential read data storage device 130 (2) according to the first embodiment. The I2C monitoring sequential read data storage device 130 (2) loads the byte address “Byte add” designating a specific area of the slave circuit 120 as an initial value of the address counter 290 (2). Thereby, it is possible to cope with any of the I2C reading methods of the sequential read method, the random read method, and the sequential random read method.
　なお、図５においては、図２において既に説明した構成と同一の部位には対応する符号を付して、説明の重複を避けるためにここでは説明を避けることとし、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）と相違する構成等について説明する。 In FIG. 5, the same parts as those already described in FIG. 2 are denoted by the same reference numerals, and the description is avoided here to avoid duplication of explanation, and the I2C monitoring sequential read data storage device The structure etc. which differ from 130 (1) are demonstrated.
　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）は、マスタ回路１１０からバイトアドレスが送信されるタイミングを検出するバイトアドレスデコーダ部５１０を備える。また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）は、スレーブ回路１２０から、バイトアドレス受信に対する「Ａｃｋ」が送信されるタイミングを検出するバイトアドレスアックデコーダ部５２０を備える。 The I2C monitoring sequential read data storage device 130 (2) includes a byte address decoder unit 510 that detects the timing at which a byte address is transmitted from the master circuit 110. In addition, the I2C monitoring sequential read data storage device 130 (2) includes a byte address ack decoder unit 520 that detects timing at which “Ack” for byte address reception is transmitted from the slave circuit 120.
　バイトアドレスデコーダ部５１０とバイトアドレスアックデコーダ部５２０とは、各々ビットカウンタ２４０（２）とバイトカウンタ２５０（２）とのカウント値が共に入力され、ビットカウンタ２４０（２）とバイトカウンタ２５０（２）とのカウント値に基づいて各々タイミングを検出する。 The byte address decoder unit 510 and the byte address ACK decoder unit 520 receive the count values of the bit counter 240 (2) and the byte counter 250 (2), respectively, and the bit counter 240 (2) and the byte counter 250 (2 ) And the respective timings are detected based on the count values.
　また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）は、マスタ回路１１０から送信されるバイトアドレス「Ｂｙｔｅ　ａｄｄ」を、一時記憶するバイトアドレスレジスタ５３０を備える。バイトアドレスレジスタ５３０は、シリアル／パラレル変換部２８０（２）でパラレル変換されたバイトアドレス「Ｂｙｔｅ　ａｄｄ」を、バイトアドレスデコーダ部５１０が検出したタイミングで取得して記憶する。 The I2C monitoring sequential read data storage device 130 (2) includes a byte address register 530 that temporarily stores a byte address “Byte add” transmitted from the master circuit 110. The byte address register 530 acquires and stores the byte address “Byte add” converted in parallel by the serial / parallel conversion unit 280 (2) at the timing detected by the byte address decoder unit 510.
　アドレスカウンタ２９０（２）は、バイトアドレスレジスタ５３０が記憶するバイトアドレス「Ｂｙｔｅ　ａｄｄ」を、バイトアドレスアックデコーダ部５２０が検出したタイミングで初期値としてロード（取得ともいう）する。その後、アドレスカウンタ２９０（２）は、第二デコーダ部２７０（２）が、「ｒｅａｄ　ｄａｔａ」の後の「Ａｃｋ」信号タイミングを検出すると、ロードしたバイトアドレス「Ｂｙｔｅ　ａｄｄ」から順次カウントアップを開始する。 The address counter 290 (2) loads (also referred to as acquisition) the byte address “Byte add” stored in the byte address register 530 as an initial value at the timing detected by the byte address ack decoder unit 520. After that, the address counter 290 (2) starts counting up sequentially from the loaded byte address “Byte add” when the second decoder unit 270 (2) detects the “Ack” signal timing after “read data”. To do.
　なお、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）は、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）の構成を備えているので、シーケンシャル方式に対応可能である。 Note that the I2C monitoring sequential read data storage device 130 (2) has the configuration of the I2C monitoring sequential read data storage device 130 (1), and therefore can support a sequential method.
　図６は、ランダム方式である場合のＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）の動作と処理との概要を説明するチャート図である。また、図６は、マスタ回路１１０から指示されたバイトアドレス「Ｂｙｔｅ　ａｄｄ」が、「７」である場合の例である。 FIG. 6 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (2) in the case of the random method. FIG. 6 shows an example in which the byte address “Byte add” instructed from the master circuit 110 is “7”.
　図６において、スタート検出部２１０（２）が、マスタ回路１１０からの通信スタート信号「Ｓｔａｒｔ」を検出すると、セットリセット部２３０（２）が「ｅｎａｂｌｅ」信号をビットカウンタ２４０（２）に出力し、「ｅｎａｂｌｅ」信号によりビットカウンタ２４０（２）が初期化されてカウントアップを開始する。 In FIG. 6, when the start detection unit 210 (2) detects the communication start signal “Start” from the master circuit 110, the set reset unit 230 (2) outputs an “enable” signal to the bit counter 240 (2). , The bit counter 240 (2) is initialized by the “enable” signal and starts counting up.
　また、バイトアドレス受信に対する「Ａｃｋ」がスレーブ回路１２０から送信されるタイミングをバイトアドレスアックデコーダ部５２０が検出すると、バイトアドレスレジスタ５３０に一時記憶されたバイトアドレス「Ｂｙｔｅ　ａｄｄ＝７」は、アドレスカウンタ２９０（２）に初期値としてロードされる。 When the byte address ack decoder 520 detects the timing at which “Ack” for byte address reception is transmitted from the slave circuit 120, the byte address “Byte add = 7” temporarily stored in the byte address register 530 is stored in the address counter. 290 (2) is loaded as an initial value.
　また、スレーブ回路１２０のバイトアドレス「Ｂｙｔｅ　ａｄｄ＝７」から読み出された読み出しデータ「Ｒｅａｄ　ｄａｔａ」は、シリアル／パラレル変換部２８０（２）でパラレル変換された後に、第三デコーダ部２ａ０（２）がアドレスカウンタ２９０（２）のカウンタ値から読み出されたデータを記憶部２ｂ（２）に記憶させるタイミングを検知すると、バイトアドレス「Ｂｙｔｅ　ａｄｄ＝７」に対応するレジスタ２ｂ７（２）に記憶される。 The read data “Read data” read from the byte address “Byte add = 7” of the slave circuit 120 is parallel-converted by the serial / parallel converter 280 (2), and then the third decoder 2a0 (2 ) Detects the timing at which the data read from the counter value of the address counter 290 (2) is stored in the storage unit 2b (2), the data is stored in the register 2b7 (2) corresponding to the byte address “Byte add = 7”. Is done.
　また図７は、シーケンシャルランダム方式である場合のＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）の動作と処理との概要を説明するチャート図である。図７においては、バイトアドレス「Ｂｙｔｅ　ａｄｄ」が、「７」から１０バイト相当分を読み出す例を示す。 FIG. 7 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (2) in the case of the sequential random system. FIG. 7 shows an example in which the byte address “Byte add” reads the equivalent of 10 bytes from “7”.
　図７において、スタート検出部２１０（２）が、マスタ回路１１０からの通信スタート信号「Ｓｔａｒｔ」を検出すると、セットリセット部２３０（２）が「ｅｎａｂｌｅ」信号をビットカウンタ２４０（２）に出力し、「ｅｎａｂｌｅ」信号によりビットカウンタ２４０（２）がゼロに初期化されて、クロック「ｓｃｌ」の立ち上がりでカウントアップを開始する。なお、バイトカウンタ２５０（２）は、通信スタート「Ｓｔａｒｔ」または通信再スタート「Ｒｅ　Ｓｔａｒｔ」により、ゼロにリセットされる。 In FIG. 7, when the start detection unit 210 (2) detects the communication start signal “Start” from the master circuit 110, the set / reset unit 230 (2) outputs an “enable” signal to the bit counter 240 (2). , The bit counter 240 (2) is initialized to zero by the “enable” signal, and starts counting up at the rising edge of the clock “scl”. The byte counter 250 (2) is reset to zero by the communication start “Start” or the communication restart “Re Start”.
　また、バイトアドレス受信に対する「Ａｃｋ」がスレーブ回路１２０から送信されるタイミングをバイトアドレスアックデコーダ部５２０が検出すると、バイトアドレスレジスタ５３０に一時記憶されたバイトアドレス「Ｂｙｔｅ　ａｄｄ＝７」は、アドレスカウンタ２９０（２）に初期値「７」としてロードされる。 When the byte address ack decoder 520 detects the timing at which “Ack” for byte address reception is transmitted from the slave circuit 120, the byte address “Byte add = 7” temporarily stored in the byte address register 530 is stored in the address counter. 290 (2) is loaded as an initial value “7”.
　また、スレーブ回路１２０のバイトアドレス「Ｂｙｔｅ　ａｄｄ＝７」から読み出された読み出しデータ「Ｒｅａｄ　ｄａｔａ」は、シリアル／パラレル変換部２８０（２）でパラレル変換された後に、第三デコーダ部２ａ０（２）がアドレスカウンタ２９０（２）のカウンタ値から読み出されたデータを記憶部２ｂ（２）に記憶させるタイミングを検知すると、バイトアドレス「Ｂｙｔｅ　ａｄｄ＝７」に対応するレジスタ２ｂ７（２）に記憶される。ここまでが、シーケンシャルランダム方式におけるランダム方式に対応するチャートである。これ以降、シーケンシャルランダム方式におけるシーケンシャル方式に対応するチャートとなる。 The read data “Read data” read from the byte address “Byte add = 7” of the slave circuit 120 is parallel-converted by the serial / parallel converter 280 (2), and then the third decoder 2a0 (2 ) Detects the timing at which the data read from the counter value of the address counter 290 (2) is stored in the storage unit 2b (2), the data is stored in the register 2b7 (2) corresponding to the byte address “Byte add = 7”. Is done. This is the chart corresponding to the random method in the sequential random method. Thereafter, the chart corresponds to the sequential method in the sequential random method.
　第二デコーダ部２７０（２）がバイトアドレス「Ｂｙｔｅ　ａｄｄ＝７」から読み出された「ｒｅａｄ　ｄａｔａ」の後の「Ａｃｋ」信号タイミングを検出すると、第二デコーダ部２７０（２）がアドレスカウンタ２９０（２）に「ｅｎａｂｌｅ」を出力する。「ｅｎａｂｌｅ」を入力されたアドレスカウンタ２９０（２）は、既にロードされている初期値７から１６まで順次カウントアップを開始する。 When the second decoder unit 270 (2) detects the “Ack” signal timing after “read data” read from the byte address “Byte add = 7”, the second decoder unit 270 (2) detects the address counter 290. “Enable” is output to (2). The address counter 290 (2) to which “enable” is input starts counting up sequentially from the initial values 7 to 16 already loaded.
　以降、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）は、シーケンシャル方式で説明したように、順次取得される「ｒｅａｄ　ｄａｔａ８」、「ｒｅａｄ　ｄａｔａ９」、・・、「ｒｅａｄ　ｄａｔａ１６」をそれぞれ、順次レジスタ２ｂ８、レジスタ２ｂ９、・・レジスタ２ｂ１６に、第三デコーダ部２ａ０（２）からのトリガ入力により記憶する。なお、アドレスカウンタ２９０は、スレーブ回路１２０のアドレス相当数をカウントアップする。 Thereafter, as described in the sequential method, the I2C monitoring sequential read data storage device 130 (2) sequentially acquires “read data8”, “read data9”,..., “Read data16” sequentially in the register 2b8. , Registers 2b9,... Are stored in the register 2b16 by a trigger input from the third decoder unit 2a0 (2). The address counter 290 counts up the number corresponding to the address of the slave circuit 120.
　そして、Ｎａｃｋ検出部２２０（２）が、マスタ回路１１０からスレーブ回路１２０へ送信された通信終了を指示する「Ｎａｃｋ」を検出すると、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）の動作と処理とが終了する。 When the Nack detection unit 220 (2) detects “Nack” instructing the end of communication transmitted from the master circuit 110 to the slave circuit 120, the operation and processing of the I2C monitoring sequential read data storage device 130 (2) Ends.
　（第二の実施形態）
　第二の実施形態にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）は、デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」またはバイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信「Ａｃｋ」「Ｎａｃｋ」を監視する。 (Second embodiment)
The I2C monitoring sequential read data storage device 130 (3) according to the second embodiment monitors the responses “Ack” and “Nack” from the slave circuit 120 after receiving the device address “Device add” or the byte address “Byte add”. To do.
　そして、デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、またはバイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、のいずれか一方が「Ｎａｃｋ」であれば、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）は、スレーブ回路１２０から読み出された「Ｒｅａｄ　ｄａｔａ」を記憶しない。 If either one of the reply from the slave circuit 120 after receiving the device address “Device add” or the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the I2C monitoring sequential The read data storage device 130 (3) does not store “Read data” read from the slave circuit 120.
　デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、またはバイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、のいずれか一方が「Ｎａｃｋ」であれば、デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、またはバイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、の少なくともいずれか一方が正常に受信されていないと考えられるので、当該バイトアドレス「Ｂｙｔｅ　ａｄｄ」から読み出された読み出しデータ「Ｒｅａｄ　ｄａｔａ」の信頼度は低下すると考えられる。 If either the reply from the slave circuit 120 after receiving the device address “Device add” or the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the device address “Device add” is received. "At least one of the reply from the slave circuit 120 after reception or the reply from the slave circuit 120 after reception of the byte address" Byte add "is not normally received. The reliability of the read data “Read data” read from “add” is considered to decrease.
　これにより、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）は、信頼性の高い読み出しデータ「Ｒｅａｄ　ｄａｔａ」のみを記憶することになるので、記憶された「Ｒｅａｄ　ｄａｔａ」の信頼性を向上させることができる。 As a result, the I2C monitoring sequential read data storage device 130 (3) stores only the read data “Read data” with high reliability, so that the reliability of the stored “Read data” can be improved. it can.
　図８と図１４とは、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）の構成を例示する概念図である。図８に示すＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）は、バイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信が「Ｎａｃｋ」であれば、スレーブ回路１２０から読み出された「Ｒｅａｄ　ｄａｔａ」を記憶しない構成例である。 8 and 14 are conceptual diagrams illustrating the configuration of the I2C monitoring sequential read data storage device 130 (3). If the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the I2C monitoring sequential read data storage device 130 (3) illustrated in FIG. 8 reads “Read” read from the slave circuit 120. This is a configuration example in which “data” is not stored.
　図８においては、既に説明したＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）と同一の構成部位については対応する符号を付して、説明の重複を避けるためにここでは詳述を避けることとする。 In FIG. 8, the same components as those of the already described I2C monitoring sequential read data storage device 130 (2) are denoted by corresponding reference numerals, and detailed description is avoided here in order to avoid duplication of explanation. .
　図８に示すように、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）は、バイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後の「Ａｃｋ」または「Ｎａｃｋ」を一時記憶するアックナックレジスタ８１０を備える。 As shown in FIG. 8, the I2C monitoring sequential read data storage device 130 (3) includes an ack register 810 that temporarily stores “Ack” or “Nack” after receiving the byte address “Byte add”.
　アックナックレジスタ８１０は、バイトアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングを検出するバイトアドレスアックデコーダ部５２０（２）からのトリガ入力により、シリアル／パラレル変換部２８０（３）でパラレル変換された「Ａｃｋ」または「Ｎａｃｋ」を、一時記憶する。 The ACK register 810 receives the trigger from the byte address ACK decoder unit 520 (2) that detects the timing at which “Ack” or “Nack” is transmitted from the slave circuit 120 in response to the byte address reception. The “Ack” or “Nack” converted in parallel in (3) is temporarily stored.
　また、アックナックレジスタ８１０は、一時記憶した情報が「Ｎａｃｋ」であれば、第三デコーダ部２ａ０（３）のトリガ出力をマスクする。第三デコーダ部２ａ０（３）のトリガ出力がマスクされると、取得された「Ｒｅａｄ　ｄａｔａ」を記憶するタイミングが与えられないので、記憶部２ｂ（３）は「Ｒｅａｄ　ｄａｔａ」を記憶しない。 Further, the acknack register 810 masks the trigger output of the third decoder unit 2a0 (3) if the temporarily stored information is “Nack”. When the trigger output of the third decoder unit 2a0 (3) is masked, the storage unit 2b (3) does not store “Read data” because the timing for storing the acquired “Read data” is not given.
　なお、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）は、バイトアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングを検出するバイトアドレスアックデコーダ部５２０（２）に替えて、またはバイトアドレスアックデコーダ部５２０（２）と共にデバイスアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングを検出するデバイスアドレスアックデコーダ部を備えてもよい。 The I2C monitoring sequential read data storage device 130 (3) is replaced with a byte address ack decoder unit 520 (2) that detects the timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120. Alternatively, a device address ack decoder unit that detects the timing at which “Ack” or “Nack” for device address reception is transmitted from the slave circuit 120 together with the byte address ack decoder unit 520 (2) may be provided.
　また、図１４に示すＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（６）は、デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、またはバイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、の少なくともいずれか一方が「Ｎａｃｋ」であれば、スレーブ回路１２０から読み出された「Ｒｅａｄ　ｄａｔａ」を記憶しない構成例である。これにより、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（６）は、さらに信頼性の高い記憶データを保持することができる。 Also, the I2C monitoring sequential read data storage device 130 (6) shown in FIG. 14 returns a response from the slave circuit 120 after receiving the device address “Device add” or from the slave circuit 120 after receiving the byte address “Byte add”. If at least one of the replies is “Nack”, the “Read data” read from the slave circuit 120 is not stored. Thereby, the I2C monitoring sequential read data storage device 130 (6) can hold storage data with higher reliability.
　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（６）は、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）が備えるバイトアドレスアックデコーダ部５２０（２）に替えて、バイトアドレスデバイスアドレスアックデコーダ部５２０（５）を備える。 The I2C monitoring sequential read data storage device 130 (6) replaces the byte address ack decoder unit 520 (2) included in the I2C monitoring sequential read data storage device 130 (3), and a byte address device address ack decoder unit 520 (5). Is provided.
　バイトアドレスデバイスアドレスアックデコーダ部５２０（５）は、バイトアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングと、デバイスアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングと、を検出する。 The byte address device address ack decoder unit 520 (5) has a timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120 and “Ack” or “Nack” for device address reception is the slave circuit 120. And the timing transmitted from.
　アックナックレジスタ８１０は、上述のタイミングを検出したバイトアドレスデバイスアドレスアックデコーダ部５２０（５）からのトリガ入力により、シリアル／パラレル変換部２８０（３）でパラレル変換された「Ａｃｋ」または「Ｎａｃｋ」を、一時記憶する。 The ACKNACK register 810 is “Ack” or “Nack” converted in parallel by the serial / parallel converter 280 (3) in response to a trigger input from the byte address device address ACK decoder 520 (5) that has detected the above timing. Is temporarily stored.
　また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（６）において、アックナックレジスタ８１０は、一時記憶した情報が「Ｎａｃｋ」であれば、第三デコーダ部２ａ０（３）のトリガ出力をマスクする。第三デコーダ部２ａ０（３）のトリガ出力がマスクされると、取得された「Ｒｅａｄ　ｄａｔａ」を記憶するタイミングが与えられないので、記憶部２ｂ（３）は「Ｒｅａｄ　ｄａｔａ」を記憶しない。 In the I2C monitoring sequential read data storage device 130 (6), the ACKNACK register 810 masks the trigger output of the third decoder unit 2a0 (3) if the temporarily stored information is “Nack”. When the trigger output of the third decoder unit 2a0 (3) is masked, the storage unit 2b (3) does not store “Read data” because the timing for storing the acquired “Read data” is not given.
　図９は、ランダムリード方式でバイトアドレスが「７」である場合のＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（６）の動作及び処理の概要を説明するチャート図である。図９に示すように、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（６）は、スレーブ回路１２０を特定するデバイスアドレスに書き込み信号を加えた「Ｄｅｖｉｃｅ　ａｄｄ＋Ｗｒｉｔｅ」の受信後の返信が「Ｎａｃｋ」であれば、アックナックレジスタ８１０が第三デコーダ部２ａ０（３）をマスクする。 FIG. 9 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (6) when the byte address is “7” in the random read method. As shown in FIG. 9, the I2C monitoring sequential read data storage device 130 (6), if the reply after receiving “Device add + Write” obtained by adding a write signal to the device address specifying the slave circuit 120 is “Nack”. The acknowledge register 810 masks the third decoder unit 2a0 (3).
　アックナックレジスタ８１０が第三デコーダ部２ａ０（３）をマスクすると、記憶部２ｂ（３）は読み出された「Ｒｅａｄ　ｄａｔａ７」を記憶するタイミングが与えられないので、「Ｒｅａｄ　ｄａｔａ７」はレジスタ２ｂ７（３）に記憶されないこととなる。 When the acknowledge register 810 masks the third decoder unit 2a0 (3), the storage unit 2b (3) is not given a timing to store the read “Read data7”, so that “Read data7” is stored in the register 2b7 ( It will not be stored in 3).
　なお、図９におけるＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（６）のその余の動作と処理とは、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）の動作と処理と、として図６で既に説明しているので、説明の重複を避けるためにここでは詳述をしないこととする。 The remaining operations and processing of the I2C monitoring sequential read data storage device 130 (6) in FIG. 9 are already described in FIG. 6 as operations and processing of the I2C monitoring sequential read data storage device 130 (2). Therefore, in order to avoid duplication of explanation, it will not be described in detail here.
　また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（６）は、スレーブ回路１２０を特定するデバイスアドレスに読み出し信号を加えた「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」の受信後の返信が「Ｎａｃｋ」であれば、アックナックレジスタ８１０が第三デコーダ部２ａ０（３）をマスクする。すなわち、第二の実施形態における「Ｄｅｖｉｃｅ　ａｄｄ」は、「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」である場合も「Ｄｅｖｉｃｅ　ａｄｄ＋Ｗｒｉｔｅ」である場合もいずれの場合においても含まれるものとする。 Further, the I2C monitoring sequential read data storage device 130 (6), if the reply after receiving “Device add + Read” obtained by adding a read signal to the device address specifying the slave circuit 120 is “Nack”, the acknowledge register 810. Masks the third decoder section 2a0 (3). That is, “Device add” in the second embodiment is included in both cases of “Device add + Read” and “Device add + Write”.
　（第三の実施形態）
　第三の実施形態で説明するＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）は、第二の実施形態で説明したＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３），１３０（６）等において、アックナックレジスタ８１０（２）が第三デコーダ部２ａ０（４）をマスクすることに替えて、アックナックレジスタ８１０（２）がＮａｃｋ検出部２２０（４）にＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）全体の動作と制御とを終了させる。 (Third embodiment)
The I2C monitoring sequential read data storage device 130 (4) described in the third embodiment is the same as the I2C monitoring sequential read data storage device 130 (3), 130 (6) described in the second embodiment. Instead of the register 810 (2) masking the third decoder unit 2a0 (4), the ACKNACK register 810 (2) replaces the Nack detection unit 220 (4) with the entire I2C monitoring sequential read data storage device 130 (4). End the operation and control.
　すなわち、アックナックレジスタ８１０（２）が「Ｎａｃｋ」を一時記憶した場合には、Ｎａｃｋ検出部２２０（４）は、通信終了信号「Ｎａｃｋ」を検出した場合と同じリセット動作をセットリセット部２３０（４）に指示し、Ｉ２Ｃ通信監視動作が終了する。 That is, when the Nack register 810 (2) temporarily stores “Nack”, the Nack detection unit 220 (4) performs the same reset operation as when the communication end signal “Nack” is detected. 4), and the I2C communication monitoring operation ends.
　これにより、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）は、監視するＩ２Ｃ通信に異常があるかもしれない状況においては、「Ｒｅａｄ　ｄａｔａ」の取得自体を停止するので、信頼性の低いデータは取得もされず記憶もされないので好ましい。換言すれば、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）に記憶される例えばＰＩ情報等は、極めて信頼性の高い情報のみとなる。 As a result, the I2C monitoring sequential read data storage device 130 (4) stops acquiring “Read data” in a situation where there may be an abnormality in the monitored I2C communication, so that data with low reliability is acquired. It is preferable because it is neither stored nor stored. In other words, for example, PI information stored in the I2C monitoring sequential read data storage device 130 (4) is only extremely reliable information.
　デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、またはバイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、のいずれか一方が「Ｎａｃｋ」であれば、デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、またはバイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、の少なくともいずれか一方が正常に受信されていないと考えられるところ、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）は、信頼性の高い読み出しデータ「Ｒｅａｄ　ｄａｔａ」のみを記憶することになるので、記憶された「Ｒｅａｄ　ｄａｔａ」の信頼性を向上させることができる。 If either the reply from the slave circuit 120 after receiving the device address “Device add” or the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the device address “Device add” is received. "At least one of the reply from the slave circuit 120 after reception or the reply from the slave circuit 120 after reception of the byte address" Byte add "is considered not to be normally received. I2C monitoring sequential read data Since the storage device 130 (4) stores only the read data “Read data” with high reliability, it is possible to improve the reliability of the stored “Read data”.
　図１０と図１５とは、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）の構成例を概念的に説明するブロック図である。図１０に示すＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）は、バイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信が「Ｎａｃｋ」であれば、Ｉ２Ｃ監視動作を停止して通信スタート信号「Ｓｔａｒｔ」待ちとなる構成例である。 10 and 15 are block diagrams conceptually illustrating a configuration example of the I2C monitoring sequential read data storage device 130 (4). If the reply from the slave circuit 120 after receiving the byte address “Byte add” is “Nack”, the I2C monitoring sequential read data storage device 130 (3) shown in FIG. This is a configuration example waiting for “Start”.
　図１０においては、既に説明したＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（３）と同一の構成部位については対応する符号を付して、説明の重複を避けるためにここでは詳述を避けることとする。 In FIG. 10, the same components as those of the already described I2C monitoring sequential read data storage device 130 (3) are denoted by the corresponding reference numerals, and detailed description is avoided here to avoid duplication of explanation. .
　図１０に示すように、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）は、バイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後の「Ａｃｋ」または「Ｎａｃｋ」を一時記憶するアックナックレジスタ８１０（２）を備える。 As shown in FIG. 10, the I2C monitoring sequential read data storage device 130 (4) includes an ACK register 810 (2) that temporarily stores “Ack” or “Nack” after receiving the byte address “Byte add”.
　アックナックレジスタ８１０（２）は、バイトアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングを検出するバイトアドレスアックデコーダ部５２０（３）からのトリガ入力により、シリアル／パラレル変換部２８０（４）でパラレル変換された「Ａｃｋ」または「Ｎａｃｋ」を、一時記憶する。 The ACKNACK register 810 (2) receives serial or parallel data in response to a trigger input from the byte address ACK decoder unit 520 (3) that detects the timing at which “Ack” or “Nack” is transmitted from the slave circuit 120 in response to byte address reception. The “Ack” or “Nack” converted in parallel by the conversion unit 280 (4) is temporarily stored.
　また、アックナックレジスタ８１０（２）は、一時記憶した情報が「Ｎａｃｋ」であれば、Ｎａｃｋ検出部２２０（４）に信号出力する。信号出力を受けたＮａｃｋ検出部２２０（４）は、セットリセット部２３０（４）に初期化信号を出力させる。セットリセット部２３０（４）の初期化信号を入力されたビットカウンタ２４０（４）は、カウントアップを停止する。 Further, if the temporarily stored information is “Nack”, the acknowledge register 810 (2) outputs a signal to the Nack detection unit 220 (4). Receiving the signal output, the Nack detector 220 (4) causes the set / reset unit 230 (4) to output an initialization signal. The bit counter 240 (4) to which the initialization signal of the set / reset unit 230 (4) is input stops counting up.
　なお、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）は、バイトアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングを検出するバイトアドレスアックデコーダ部５２０（３）に替えて、またはバイトアドレスアックデコーダ部５２０（３）と共にデバイスアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングを検出するデバイスアドレスアックデコーダ部を備えてもよい。 Note that the I2C monitoring sequential read data storage device 130 (4) is replaced with a byte address ack decoder unit 520 (3) that detects the timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120. Alternatively, a device address ack decoder unit that detects the timing at which “Ack” or “Nack” for device address reception is transmitted from the slave circuit 120 may be provided together with the byte address ack decoder unit 520 (3).
　また、図１５に示すＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（７）は、デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、またはバイトアドレス「Ｂｙｔｅ　ａｄｄ」受信後のスレーブ回路１２０からの返信、の少なくともいずれか一方が「Ｎａｃｋ」であれば、Ｉ２Ｃ監視動作を停止して通信スタート信号「Ｓｔａｒｔ」待ちとなる構成例である。これにより、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（７）は、さらに信頼性の高い記憶データを保持することができる。 Further, the I2C monitoring sequential read data storage device 130 (7) shown in FIG. 15 returns a response from the slave circuit 120 after receiving the device address “Device add” or from the slave circuit 120 after receiving the byte address “Byte add”. If at least one of the replies is “Nack”, the I2C monitoring operation is stopped and the communication start signal “Start” is waited. As a result, the I2C monitoring sequential read data storage device 130 (7) can hold storage data with higher reliability.
　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（７）は、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（４）が備えるバイトアドレスアックデコーダ部５２０（３）に替えて、バイトアドレスデバイスアドレスアックデコーダ部５２０（６）を備える。 The I2C monitoring sequential read data storage device 130 (7) replaces the byte address ack decoder unit 520 (3) provided in the I2C monitoring sequential read data storage device 130 (4), and a byte address device address ack decoder unit 520 (6). Is provided.
　バイトアドレスデバイスアドレスアックデコーダ部５２０（６）は、バイトアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングと、デバイスアドレス受信に対する「Ａｃｋ」または「Ｎａｃｋ」がスレーブ回路１２０から送信されるタイミングと、を検出する。 The byte address device address ack decoder unit 520 (6) has a timing at which “Ack” or “Nack” for byte address reception is transmitted from the slave circuit 120, and “Ack” or “Nack” for device address reception is the slave circuit 120. And the timing transmitted from.
　アックナックレジスタ８１０（２）は、上述のタイミングを検出したバイトアドレスデバイスアドレスアックデコーダ部５２０（６）からのトリガ入力により、シリアル／パラレル変換部２８０（４）でパラレル変換された「Ａｃｋ」または「Ｎａｃｋ」を、一時記憶する。 The ACK register 810 (2) receives “Ack” or “Ack” converted in parallel by the serial / parallel converter 280 (4) in response to a trigger input from the byte address device address ACK decoder 520 (6) that has detected the timing described above. “Nack” is temporarily stored.
　また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（７）は、アックナックレジスタ８１０（２）が一時記憶した情報が「Ｎａｃｋ」であれば、Ｉ２Ｃ監視動作を終了して「Ｓｔａｒｔ」待ちとなる。 Also, if the information temporarily stored in the acknack register 810 (2) is “Nack”, the I2C monitoring sequential read data storage device 130 (7) ends the I2C monitoring operation and waits for “Start”.
　図１１は、ランダムリード方式でバイトアドレスが「７」である場合のＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（７）の動作及び処理の概要を説明するチャート図である。図１１に示すように、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（７）は、スレーブ回路１２０を特定するデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」の受信後の返信が「Ｎａｃｋ」であれば、アックナックレジスタ８１０（２）がＮａｃｋ検出部２２０（４）に通信終了信号「Ｎａｃｋ」を検出した場合と同様の出力をセットリセット部２３０（４）にさせる。 FIG. 11 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (7) when the byte address is “7” in the random read method. As shown in FIG. 11, the I2C monitoring sequential read data storage device 130 (7), if the reply after receiving the device address “Device add” for specifying the slave circuit 120 is “Nack”, the acknowledge register 810 ( 2) causes the set reset unit 230 (4) to output the same output as when the Nack detection unit 220 (4) detects the communication end signal “Nack”.
　すなわち、Ｎａｃｋ検出部２２０（４）はセットリセット部２３０（４）に「ｅｎａｂｌｅ」信号の出力を停止させてビットカウンタ２４０（４）のカウントアップを停止させる。 That is, the Nack detection unit 220 (4) stops the output of the “enable” signal to the set / reset unit 230 (4) to stop the count up of the bit counter 240 (4).
　なお、図１１におけるＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（７）のその余の動作と処理とは、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）の動作と処理と、として図６で既に説明しているので、説明の重複を避けるためにここでは詳述をしないこととする。 The remaining operations and processing of the I2C monitoring sequential read data storage device 130 (7) in FIG. 11 are already described in FIG. 6 as operations and processing of the I2C monitoring sequential read data storage device 130 (2). Therefore, in order to avoid duplication of explanation, it will not be described in detail here.
　また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（７）は、スレーブ回路１２０を特定するデバイスアドレスに読み出し信号を加えた「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」の受信後の返信が「Ｎａｃｋ」であれば、Ｉ２Ｃ監視制御動作を停止する。すなわち、第三の実施形態における「Ｄｅｖｉｃｅ　ａｄｄ」は、「Ｄｅｖｉｃｅ　ａｄｄ＋Ｒｅａｄ」である場合も「Ｄｅｖｉｃｅ　ａｄｄ＋Ｗｒｉｔｅ」である場合もいずれの場合においても含まれるものとする。 Further, the I2C monitoring sequential read data storage device 130 (7) performs the I2C monitoring control operation if the reply after receiving “Device add + Read” obtained by adding a read signal to the device address specifying the slave circuit 120 is “Nack”. To stop. That is, “Device add” in the third embodiment is included in both cases of “Device add + Read” and “Device add + Write”.
　（第四の実施形態）
　第四の実施形態にかかるＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、単一のマスタ回路１１０に複数のスレーブ回路１２０がＩ２Ｃ接続されている場合に、情報取得対象となるスレーブ回路１２０を特定する期待値と、取得したデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」とを比較する。 (Fourth embodiment)
The I2C monitoring sequential read data storage device 130 (5) according to the fourth embodiment includes a slave circuit 120 that is an information acquisition target when a plurality of slave circuits 120 are I2C connected to a single master circuit 110. The expected value to be identified is compared with the acquired device address “Device add”.
　そして、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、情報取得対象となるスレーブ回路１２０を特定する期待値と、取得したデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」とが一致した場合のみ、情報取得対象となる特定のスレーブ回路１２０のＰＩ情報等を取得する。 The I2C monitoring sequential read data storage device 130 (5) becomes an information acquisition target only when the expected value that identifies the slave circuit 120 that is the information acquisition target matches the acquired device address “Device add”. PI information of a specific slave circuit 120 is acquired.
　これにより、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、接続されているＩ２Ｃインターフェース１４０に複数のスレーブ回路１２０が存在する場合においても、所望のスレーブ回路１２０のＰＩ情報等を取得することが可能となる。 As a result, the I2C monitoring sequential read data storage device 130 (5) can acquire PI information and the like of the desired slave circuit 120 even when there are a plurality of slave circuits 120 in the connected I2C interface 140. It becomes possible.
　図１２は、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）の構成概要を概念的に説明する図である。図１２においては、上述した実施形態で既に説明した構成部位と同一の部位には対応する符号を付して、説明の重複を避けるためにここでは詳述を避けることとする。 FIG. 12 is a diagram conceptually illustrating a configuration outline of the I2C monitoring sequential read data storage device 130 (5). In FIG. 12, the same parts as those already described in the above-described embodiment are denoted by the corresponding reference numerals, and detailed description is avoided here in order to avoid duplication of explanation.
　図１２に示すように、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」がマスタ回路１１０から送信されるタイミングを検出するデバイスアドレスデコーダ部１２１０を備える。デバイスアドレスデコーダ部１２１０は、ビットカウンタ２４０（５）とバイトカウンタ２５０（５）とのカウンタ値に基づいて、デバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」がマスタ回路１１０から送信されるタイミングを検出する。 As shown in FIG. 12, the I2C monitoring sequential read data storage device 130 (5) includes a device address decoder unit 1210 that detects the timing at which the device address “Device add” is transmitted from the master circuit 110. The device address decoder unit 1210 detects the timing at which the device address “Device add” is transmitted from the master circuit 110 based on the counter values of the bit counter 240 (5) and the byte counter 250 (5).
　また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、デバイスアドレスデコーダ部１２１０が検出したタイミングをトリガとして、シリアルデータ接続線１４０ａから入力されたデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」を一時記憶するデバイスアドレスレジスタ１２２０を備える。デバイスアドレスレジスタ１２２０が一時記憶するデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」は、シリアル／パラレル変換部２８０（５）がパラレルに変換したデータである。 The I2C monitoring sequential read data storage device 130 (5) is a device address register that temporarily stores the device address “Device add” input from the serial data connection line 140a using the timing detected by the device address decoder unit 1210 as a trigger. 1220. The device address “Device add” temporarily stored in the device address register 1220 is data converted into parallel by the serial / parallel conversion unit 280 (5).
　また、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、デバイスアドレスレジスタ１２２０に一時記憶されたデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」と、予め設定されている期待値と、を比較するデバイスアドレス期待値比較部１２３０を備える。 Further, the I2C monitoring sequential read data storage device 130 (5) includes a device address expected value comparison unit that compares the device address “Device add” temporarily stored in the device address register 1220 with a preset expected value. 1230.
　デバイスアドレス期待値比較部１２３０は、情報取得対象である特定のスレーブ回路１２０に対応するデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」を期待値として記憶する期待値記憶部１２３１を備える。期待値記憶部１２３１が記憶する期待値は、オペレータ等により予め設定されていてもよい。 The device address expected value comparison unit 1230 includes an expected value storage unit 1231 that stores a device address “Device add” corresponding to a specific slave circuit 120 that is an information acquisition target as an expected value. The expected value stored in the expected value storage unit 1231 may be set in advance by an operator or the like.
　デバイスアドレス期待値比較部１２３０がデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」と期待値とを比較した結果、一致する場合には、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、処理を継続して「Ｒｅａｄ　ｄａｔａ」の取得と記憶とをする。 If the device address expected value comparison unit 1230 compares the device address “Device add” with the expected value, and if they match, the I2C monitoring sequential read data storage device 130 (5) continues the processing and reads “Read data”. ”And memorize.
　また、デバイスアドレス期待値比較部１２３０がデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」と期待値とを比較した結果、一致しない場合には、デバイスアドレス期待値比較部１２３０は、Ｎａｃｋ検出部２２０（５）に不一致信号出力する。Ｎａｃｋ検出部２２０（５）は、デバイスアドレス期待値比較部１２３０から不一致信号を入力されると、通信終了信号「Ｎａｃｋ」を検出した場合と同様に、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）の監視動作を停止させる処理をする。 If the device address expected value comparison unit 1230 compares the device address “Device add” with the expected value and does not match, the device address expected value comparison unit 1230 sends a mismatch signal to the Nack detection unit 220 (5). Output. When a mismatch signal is input from the device address expected value comparison unit 1230, the Nack detection unit 220 (5) receives the I2C monitoring sequential read data storage device 130 (5) in the same manner as when the communication end signal “Nack” is detected. To stop the monitoring operation.
　図１２において、不一致信号を受けたＮａｃｋ検出部２２０（５）は、セットリセット部２３０（５）に初期化信号を出力させる。セットリセット部２３０（５）の初期化信号を入力されたビットカウンタ２４０（５）は、カウントアップを停止する。なお、セットリセット部２３０（５）の初期化信号とは、典型的にはビットカウンタ２４０（５）に対する「ｅｎａｂｌｅ」フラグを下げる処理に対応する。 In FIG. 12, the Nack detection unit 220 (5) receiving the mismatch signal causes the set reset unit 230 (5) to output an initialization signal. The bit counter 240 (5) to which the initialization signal of the set / reset unit 230 (5) is input stops counting up. The initialization signal of the set / reset unit 230 (5) typically corresponds to a process of lowering the “enable” flag for the bit counter 240 (5).
　図１３は、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）の動作と処理との概要を説明するチャート図である。図１３においては、バイトアドレス「Ｂｙｔｅ　ａｄｄ」が、「７」である場合の例を示している。 FIG. 13 is a chart for explaining the outline of the operation and processing of the I2C monitoring sequential read data storage device 130 (5). FIG. 13 shows an example in which the byte address “Byte add” is “7”.
　図１３に示すように、期待値記憶部１２３０は、予め情報取得対象となるスレーブ回路１２０のデバイスアドレスに対応する期待値「Ａ０ｈ」を記憶している。Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）が、シリアルデータ接続線１４０ａから取得したデバイスアドレス「Ｄｅｖｉｃｅ　ａｄｄ」は「Ｃ０ｈ」であり、デバイスアドレスデコーダ部１２１０からのトリガにより、デバイスアドレスレジスタ１２２０に「Ｃ０ｈ」が一時記憶される。 As shown in FIG. 13, the expected value storage unit 1230 stores in advance an expected value “A0h” corresponding to the device address of the slave circuit 120 that is the information acquisition target. The device address “Device add” acquired by the I2C monitoring sequential read data storage device 130 (5) from the serial data connection line 140a is “C0h”, and a trigger from the device address decoder unit 1210 causes the device address register 1220 to store “ “C0h” is temporarily stored.
　また、デバイスアドレス期待値比較部１２３０は、デバイスアドレスレジスタ１２２０に記憶された「Ｃ０ｈ」と、期待値記憶部１２３０が予め記憶する期待値「Ａ０ｈ」と、比較する。デバイスアドレス期待値比較部１２３０は、比較結果が不一致であるので不一致信号をＮａｃｋ検出部２２０（５）に出力する。 Also, the device address expected value comparison unit 1230 compares “C0h” stored in the device address register 1220 with the expected value “A0h” stored in the expected value storage unit 1230 in advance. The device address expected value comparison unit 1230 outputs a mismatch signal to the Nack detection unit 220 (5) because the comparison result does not match.
　Ｎａｃｋ検出部２２０（５）は、セットリセット部２３０（５）のリセットにトリガを送出し、セットリセット部２３０（５）は、ビットカウンタ２４０（５）へ出力する「ｅｎａｂｌｅ」フラグを下げる。これにより、ビットカウンタ２４０（５）は、カウントアップを停止して通信スタート「Ｓｔａｒｔ」待ち状態となる。この場合には、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、次の通信スタート信号「Ｓｔａｒｔ」が取得されるまで動作しない。 The Nack detection unit 220 (5) sends a trigger to reset the set reset unit 230 (5), and the set reset unit 230 (5) lowers the “enable” flag output to the bit counter 240 (5). As a result, the bit counter 240 (5) stops counting up and enters a communication start “Start” waiting state. In this case, the I2C monitoring sequential read data storage device 130 (5) does not operate until the next communication start signal “Start” is acquired.
　これにより、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（５）は、複数のスレーブ回路１２０が接続されている場合においても、正常な読み出しデータを取り出すことが可能となる。 Thus, the I2C monitoring sequential read data storage device 130 (5) can extract normal read data even when a plurality of slave circuits 120 are connected.
　（第五の実施形態）
　第五の実施形態で説明するＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）は、第一の実施形態で説明した図５に示すＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（２）の構成と同じ構成となる。 (Fifth embodiment)
The I2C monitoring sequential read data storage device 130 (8) described in the fifth embodiment has the same configuration as the configuration of the I2C monitoring sequential read data storage device 130 (2) illustrated in FIG. 5 described in the first embodiment. Become.
　但し、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）は、アドレスカウンタ２９０（２）がゼロにリセットされるのは、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）の電源投入（パワーオン）時のみとする。 However, in the I2C monitoring sequential read data storage device 130 (8), the address counter 290 (2) is reset to zero only when the I2C monitoring sequential read data storage device 130 (8) is powered on (powered on). And
　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）は、アドレスカウンタ２９０（２）が電源投入時を除いてリセットされないので、Ｉ２Ｃ監視動作中は常にアドレスカウンタ２９０（２）のカウンタ値が保持されて、スレーブ回路１２０のバイトアドレス「Ｂｙｔｅ　ａｄｄ」と一致した値となる。 Since the address counter 290 (2) is not reset except when the power is turned on, the I2C monitoring sequential read data storage device 130 (8) always holds the counter value of the address counter 290 (2) during the I2C monitoring operation. The value coincides with the byte address “Byte add” of the slave circuit 120.
　このため、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）は、様々な読み出し方式で交互にアクセスされた場合においても、常にスレーブ回路１２０と同一の読み出しアドレスを保持し、正常な読み出しデータを取得して記憶できる。 Therefore, the I2C monitoring sequential read data storage device 130 (8) always holds the same read address as that of the slave circuit 120 and acquires normal read data even when accessed alternately by various read methods. Can remember.
　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）は、典型的にはランダムリード方式の後にシーケンシャルリード方式で読み出し処理があった場合に好適である。ランダム方式によるマスタ回路１１０とスレーブ回路１２０との通信終了後は、スレーブ回路１２０側にランダム方式による最後の読み出しバイトアドレスが保持される。スレーブ回路１２０は、その電源投入時に読み出しアドレスがゼロに初期化されるのみで、電源が投入されている限り最後の読み出しアドレスが残留する。 The I2C monitoring sequential read data storage device 130 (8) is typically suitable when a read process is performed by the sequential read method after the random read method. After the communication between the master circuit 110 and the slave circuit 120 by the random method is completed, the last read byte address by the random method is held on the slave circuit 120 side. The slave circuit 120 only initializes the read address to zero when the power is turned on, and the last read address remains as long as the power is turned on.
　一方、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）は、ランダム方式による読み出しが終了した時点の通信終了信号「Ｎａｃｋ」により、初期化されることはなく、アドレスカウンタ２９０（２）がランダム方式による読み出しが終了した時点の読み出しアドレスを保持する。 On the other hand, the I2C monitoring sequential read data storage device 130 (8) is not initialized by the communication end signal “Nack” at the time when reading by the random method is completed, and the address counter 290 (2) is based on the random method Holds the read address at the end of the read.
　これにより、スレーブ回路１２０が保持する読み出しアドレスと、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）が保持する読み出しアドレスとが、合致することとなり、その後シーケンシャル方式に移行した場合でも、双方が保持するアドレスから順次読み出し処理できることとなる。 As a result, the read address held by the slave circuit 120 matches the read address held by the I2C monitoring sequential read data storage device 130 (8), and both hold even if the sequential method is subsequently shifted. It is possible to sequentially read from the address.
　ここで仮に、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）が、ランダム方式による読み出しが終了した時点の通信終了信号「Ｎａｃｋ」により、初期化されるとすれば、アドレスカウンタ２９０（２）がランダム方式による読み出しが終了した時点の読み出しアドレスを保持せずにカウンタ値がゼロとなる。この場合に、スレーブ回路１２０が保持する読み出しアドレスは、ランダム方式による読み出しが終了した時点の最後のアドレスである。すなわち、この状態でシーケンシャルリード方式に移行すれば、読み出しアドレスの初期値が、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）とスレーブ回路１２０とで異なることとなるので、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）は、正確な情報を取得できないこととなる。 Here, if the I2C monitoring sequential read data storage device 130 (8) is initialized by the communication end signal “Nack” at the time when reading by the random method is completed, the address counter 290 (2) is randomly set. The counter value becomes zero without holding the read address at the time when reading by the method is completed. In this case, the read address held by the slave circuit 120 is the last address at the time when the random read is completed. That is, if the state is shifted to the sequential read method in this state, the initial value of the read address is different between the I2C monitoring sequential read data storage device 130 (8) and the slave circuit 120, so the I2C monitoring sequential read data storage device. 130 (8) cannot acquire accurate information.
　第五の実施形態で説明したＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）は、アドレスカウンタ２９０（２）をパワーオンリセット、またはＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）が組み込まれたユニットのリセット時のみ（但し、ユニットのリセットにより読み出し対象スレーブ回路１２０はリセットされないものとする）とするので、様々な方式のＩ２Ｃ通信が継続してされた場合においても、正確に所望の情報を取得して記憶できるので好ましい。 The I2C monitoring sequential read data storage device 130 (8) described in the fifth embodiment includes a power-on reset of the address counter 290 (2) or a unit in which the I2C monitoring sequential read data storage device 130 (8) is incorporated. Since it is only at reset (however, the read target slave circuit 120 is not reset by resetting the unit), so even if I2C communication of various methods is continued, the desired information is obtained accurately. It is preferable because it can be stored.
　第一の実施形態乃至第五の実施形態で例示したＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）乃至Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）の構成は、各々、各実施形態での説明に限定されるものではなく、自明な範囲で適宜その構成を変更することができる。 The configurations of the I2C monitoring sequential read data storage device 130 (1) to the I2C monitoring sequential read data storage device 130 (8) illustrated in the first to fifth embodiments will be described in each embodiment. The configuration is not limited, and the configuration can be changed as appropriate within the obvious range.
　また、第一の実施形態乃至第五の実施形態で例示したＩ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（１）乃至Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置１３０（８）の動作と処理とは、各々、各実施形態での説明に限定されるものではなく、自明な範囲で適宜その動作と処理とを変更することができる。 The operations and processes of the I2C monitoring sequential read data storage device 130 (1) to the I2C monitoring sequential read data storage device 130 (8) illustrated in the first to fifth embodiments are respectively performed. It is not limited to the description in the form, and its operation and processing can be changed as appropriate within the obvious range.
　この発明は、Ｉ２Ｃインターフェースを介して通信するマスタ回路とスレーブ回路との通信データを監視する装置等に利用できる。 The present invention can be used for an apparatus for monitoring communication data between a master circuit and a slave circuit that communicate via an I2C interface.

Claims (12)

  1. 　マスタ回路とスレーブ回路とのＩ２Ｃインターフェースを介した通信データを取得するＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記スレーブ回路のアドレス相当数をカウントするアドレスカウンタを備え、
    　前記スレーブ回路の所定領域を指定するバイトアドレスを取得した場合に、取得した前記バイトアドレスを、前記アドレスカウンタの初期値とする
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     In an I2C monitoring sequential read data storage device for acquiring communication data between a master circuit and a slave circuit via an I2C interface,
    An address counter for counting the number of addresses corresponding to the slave circuit;
    An I2C monitoring sequential read data storage device characterized in that, when a byte address specifying a predetermined area of the slave circuit is acquired, the acquired byte address is used as an initial value of the address counter.
  2. 　請求項１に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　取得した前記バイトアドレスを一時記憶するバイトアドレスレジスタを備え、
    　前記スレーブ回路が前記バイトアドレスの受信に対する正常信号を返信した場合に、前記バイトアドレスレジスタに一時記憶した前記バイトアドレスを、前記アドレスカウンタの初期値とする
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     The I2C monitoring sequential read data storage device according to claim 1,
    A byte address register for temporarily storing the acquired byte address;
    When the slave circuit returns a normal signal for reception of the byte address, the byte address temporarily stored in the byte address register is used as an initial value of the address counter. I2C monitoring sequential read data storage apparatus.
  3. 　請求項１または請求項２に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記スレーブ回路を特定するデバイスアドレスまたは前記バイトアドレスを受信した前記スレーブ回路が、異常信号を返信した場合に、
    　取得した前記通信データを記憶しない
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     In the I2C monitoring sequential read data storage device according to claim 1 or 2,
    When the slave circuit that has received the device address or the byte address specifying the slave circuit has returned an abnormal signal,
    An I2C monitoring sequential read data storage device characterized by not storing the acquired communication data.
  4. 　請求項１乃至請求項３のいずれか一項に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記スレーブ回路を特定するデバイスアドレスまたは前記バイトアドレスを受信した前記スレーブ回路の返信信号を一時記憶するアックナックレジスタと、前記アドレスカウンタのカウンタ値をデコードして前記取得した通信データを記憶するタイミングを出力するデコーダ部と、を備え、
    　前記アックナックレジスタから入力された前記返信信号が異常信号である場合に、前記取得した通信データを記憶しないように、前記デコーダ部は、前記通信データを記憶するタイミングを出力しない
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     The I2C monitoring sequential read data storage device according to any one of claims 1 to 3,
    An acknowledge register that temporarily stores a reply signal of the slave circuit that has received the device address or the byte address that specifies the slave circuit, and a timing for storing the acquired communication data by decoding the counter value of the address counter An output decoder unit,
    The decoder unit does not output a timing for storing the communication data so as not to store the acquired communication data when the reply signal input from the acknack register is an abnormal signal. I2C monitoring sequential read data storage device.
  5. 　請求項３または請求項４に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記スレーブ回路を特定する前記デバイスアドレスの受信または前記バイトアドレスを受信した前記スレーブ回路が、前記異常信号を返信した場合に、
    　初期化される
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     In the I2C monitoring sequential read data storage device according to claim 3 or 4,
    When the slave circuit that has received the device address or the byte address specifying the slave circuit has returned the abnormal signal,
    An I2C monitoring sequential read data storage device characterized by being initialized.
  6. 　請求項４に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記マスタ回路と前記スレーブ回路との間の通信を終了する終了信号を検出すると、前記Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置を初期化するナック検出部を備え、
    　前記ナック検出部は、前記アックナックレジスタから入力された前記返信信号が異常信号である場合に、前記Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置を初期化する
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     The I2C monitoring sequential read data storage device according to claim 4,
    A detection unit that initializes the I2C monitoring sequential read data storage device when an end signal for ending communication between the master circuit and the slave circuit is detected;
    The I2C monitoring sequential read data storage device, wherein the Nack detection unit initializes the I2C monitoring sequential read data storage device when the reply signal input from the acknack register is an abnormal signal.
  7. 　請求項１または請求項２に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　複数の前記スレーブ回路が前記Ｉ２Ｃインターフェースを介して接続され、
    　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置は、情報取得対象となる前記スレーブ回路を特定するデバイスアドレス期待値を予め設定され、前記デバイスアドレス期待値に対応する前記スレーブ回路の通信データを記憶する
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     In the I2C monitoring sequential read data storage device according to claim 1 or 2,
    A plurality of the slave circuits are connected via the I2C interface;
    An I2C monitoring sequential read data storage device is characterized in that a device address expected value for specifying the slave circuit to be acquired information is preset, and communication data of the slave circuit corresponding to the device address expected value is stored. I2C monitoring sequential read data storage device.
  8. 　請求項７に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置は、情報取得対象となる前記スレーブ回路を特定するデバイスアドレス期待値を予め記憶する期待値記憶部と、
    　前記期待値記憶部が記憶する前記デバイスアドレス期待値と、取得した前記デバイスアドレスと、を比較するデバイスアドレス期待値比較部と、を備え、
    　前記デバイスアドレス期待値比較部は、前記デバイスアドレス期待値と取得した前記デバイスアドレスとが異なる場合に、Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の初期化信号を出力する
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     The I2C monitoring sequential read data storage device according to claim 7,
    An I2C monitoring sequential read data storage device includes an expected value storage unit that stores in advance a device address expected value that identifies the slave circuit that is an information acquisition target;
    A device address expected value comparison unit that compares the expected device address value stored in the expected value storage unit with the acquired device address; and
    The device address expected value comparison unit outputs an initialization signal of the I2C monitoring sequential read data storage device when the device address expected value and the acquired device address are different from each other. Storage device.
  9. 　請求項１または請求項２に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記アドレスカウンタと前記スレーブ回路のアドレスカウントとは合致するように、前記Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置の電源投入時のみに前記アドレスカウンタを初期化する
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     In the I2C monitoring sequential read data storage device according to claim 1 or 2,
    The I2C monitoring sequential read data storage device, wherein the address counter is initialized only when the I2C monitoring sequential read data storage device is powered on so that the address counter matches the address count of the slave circuit. .
  10. 　請求項９に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記アドレスカウンタは、前記マスタ回路から前記スレーブ回路に送信されるスタート信号を取得した場合も、前記マスタ回路から前記スレーブ回路に送信されるリスタート信号を取得した場合も、いずれの場合にも初期化されない
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     The I2C monitoring sequential read data storage device according to claim 9,
    The address counter is initial in both cases when a start signal transmitted from the master circuit to the slave circuit is acquired and when a restart signal transmitted from the master circuit to the slave circuit is acquired. An I2C monitoring sequential read data storage device, characterized in that:
  11. 　請求項１乃至請求項１０のいずれか一項に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記スレーブ回路はＥＥＰＲＯＭであり、
    　前記Ｉ２Ｃ監視シーケンシャルリードデータ記憶装置は、前記マスタ回路が前記Ｉ２Ｃインターフェースを介して読み出した前記ＥＥＰＲＯＭの前記所定領域に記憶されたデータを取得して記憶する記憶部を備える
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     The I2C monitoring sequential read data storage device according to any one of claims 1 to 10,
    The slave circuit is an EEPROM;
    The I2C monitoring sequential read data storage device includes a storage unit that acquires and stores data stored in the predetermined area of the EEPROM read by the master circuit via the I2C interface. Sequential read data storage device.
  12. 　請求項１乃至請求項１１のいずれか一項に記載のＩ２Ｃ監視シーケンシャルリードデータ記憶装置において、
    　前記Ｉ２Ｃインターフェースの読み出し方式は、ランダムリード方式またはシーケンシャルリード方式またはシーケンシャルランダムリード方式のいずれか一つ以上の方式である
    　ことを特徴とするＩ２Ｃ監視シーケンシャルリードデータ記憶装置。     The I2C monitoring sequential read data storage device according to any one of claims 1 to 11,
    The I2C monitoring sequential read data storage device is characterized in that the read method of the I2C interface is at least one of a random read method, a sequential read method, and a sequential random read method.
PCT/JP2009/000809 2009-02-24 2009-02-24 I2c monitor sequential read data storage device WO2010097831A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011501345A JP5298185B2 (en) 2009-02-24 2009-02-24 I2C monitoring sequential read data storage device
PCT/JP2009/000809 WO2010097831A1 (en) 2009-02-24 2009-02-24 I2c monitor sequential read data storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2009/000809 WO2010097831A1 (en) 2009-02-24 2009-02-24 I2c monitor sequential read data storage device

Publications (1)

Publication Number Publication Date
WO2010097831A1 true WO2010097831A1 (en) 2010-09-02

Family

ID=42665062

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/000809 WO2010097831A1 (en) 2009-02-24 2009-02-24 I2c monitor sequential read data storage device

Country Status (2)

Country Link
JP (1) JP5298185B2 (en)
WO (1) WO2010097831A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014153822A (en) * 2013-02-06 2014-08-25 Rohm Co Ltd Semiconductor device, communication system, camera shake correction controller, imaging apparatus, and electronic apparatus
JP5680212B2 (en) * 2011-09-27 2015-03-04 三菱電機株式会社 Slave device, master device and communication method
CN115658409A (en) * 2022-11-11 2023-01-31 苏州浪潮智能科技有限公司 Abnormity detection method, device, host equipment, system and storage medium
US11687485B2 (en) 2020-07-29 2023-06-27 Astec International Limited Systems and methods for monitoring serial communication between devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109213718B (en) * 2018-11-12 2024-01-26 上海艾为电子技术股份有限公司 I2C communication device and I2C communication equipment

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316973A (en) * 1995-05-23 1996-11-29 Hitachi Ltd Communication processing means
JP2000231539A (en) * 1999-02-12 2000-08-22 Ricoh Co Ltd Data transfer system and data transfer method
JP2002175269A (en) * 2000-09-29 2002-06-21 Lucent Technol Inc Extended bridge device for i2c bus and method
JP2005006306A (en) * 2003-06-12 2005-01-06 Hewlett-Packard Development Co Lp Inter-integrated circuit router error management system and method
JP2005004745A (en) * 2003-06-12 2005-01-06 Hewlett-Packard Development Co Lp Bus router between integrated circuits
JP2005250681A (en) * 2004-03-02 2005-09-15 Sanyo Electric Co Ltd Data transfer memory and module

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7430259B2 (en) * 2004-04-19 2008-09-30 Intersil Americas Inc. Two-wire chip-to-chip interface
JP5160100B2 (en) * 2007-02-08 2013-03-13 シャープ株式会社 Data communication malfunction prevention device, electronic apparatus, data communication malfunction prevention device control method, data communication malfunction prevention device control program, and recording medium recording the program

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08316973A (en) * 1995-05-23 1996-11-29 Hitachi Ltd Communication processing means
JP2000231539A (en) * 1999-02-12 2000-08-22 Ricoh Co Ltd Data transfer system and data transfer method
JP2002175269A (en) * 2000-09-29 2002-06-21 Lucent Technol Inc Extended bridge device for i2c bus and method
JP2005006306A (en) * 2003-06-12 2005-01-06 Hewlett-Packard Development Co Lp Inter-integrated circuit router error management system and method
JP2005004745A (en) * 2003-06-12 2005-01-06 Hewlett-Packard Development Co Lp Bus router between integrated circuits
JP2005250681A (en) * 2004-03-02 2005-09-15 Sanyo Electric Co Ltd Data transfer memory and module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5680212B2 (en) * 2011-09-27 2015-03-04 三菱電機株式会社 Slave device, master device and communication method
JP2014153822A (en) * 2013-02-06 2014-08-25 Rohm Co Ltd Semiconductor device, communication system, camera shake correction controller, imaging apparatus, and electronic apparatus
US11687485B2 (en) 2020-07-29 2023-06-27 Astec International Limited Systems and methods for monitoring serial communication between devices
CN115658409A (en) * 2022-11-11 2023-01-31 苏州浪潮智能科技有限公司 Abnormity detection method, device, host equipment, system and storage medium

Also Published As

Publication number Publication date
JPWO2010097831A1 (en) 2012-08-30
JP5298185B2 (en) 2013-09-25

Similar Documents

Publication Publication Date Title
JP5298185B2 (en) I2C monitoring sequential read data storage device
EP3537307A1 (en) Method for handling i2c bus deadlock, electronic device, and communication system
US7685325B2 (en) Synchronous bus controller system
CN107357595B (en) Bus-based multi-driver firmware online updating system
US8364872B2 (en) Slave and communicating method between a master and the same
CN110580235B (en) SAS expander communication method and device
US20150019919A1 (en) Storage control device and control device for detecting abnormality of signal line
US10721022B2 (en) Communication apparatus, communication method, program, and communication system
WO2012046634A1 (en) Electronic device and serial data communication method
US9934117B2 (en) Apparatus and method for fault detection to ensure device independence on a bus
US20150237145A1 (en) Information processing system and method
KR20150110860A (en) Apparatus and method for firmware updating of vehicle
US8151176B2 (en) CPU instruction RAM parity error procedure
US20230199306A1 (en) Communication device and communication system
CN101488825A (en) Error detection method and system for data transmission
US11853736B2 (en) Module, information processing device equipped with same, and method for updating program data to update program data in module
KR102174456B1 (en) Apparatus for synchronizing in serial communication interface and method thereof
CN109075902A (en) Communication device, communication means, program and communication system
US11012195B2 (en) Method, sensor, and controller for transmitting a data packet from a sensor to a controller
US20080162959A1 (en) Power source control circuit, power source control device, power source control system, and information processing device
JP5544099B2 (en) Controller communication method and controller communication device
CN108541307B (en) Programmable controller and synchronization control method
KR20160043378A (en) Apparatus and method for updating vehicle device having multiple modules
JP5801330B2 (en) Device status monitoring method
US8291143B1 (en) Single line communication

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09840687

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2011501345

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09840687

Country of ref document: EP

Kind code of ref document: A1