WO2010092641A1 - Program debugging device and emulator system - Google Patents

Abstract

On the basis of a result of comparison between a processing progress at the time of actual program execution and an event defining an arbitrary condition during program execution by a CPU, an event controller determines whether or not a partial progress has been established in the processing progress.  A trace controller provisionally records the partial progress that is determined as having been established, in a trace memory.  On the basis of the determination as to whether or not the period of the partial progress at a certain time point during the actual execution of the program is the longest the among periods of the prior partial progress group, a trace log record settlement controller selects whether or not the provisionally recorded partial progress should be recorded as a definite record.

Description

Program debugging device and emulator system

The present invention relates to a program debug apparatus having a trace function and an event function, and more particularly to a program debug apparatus effective for debugging a product program using multiple interrupts and the like.

This application is hereby incorporated herein by reference in its entirety, including Japanese Patent Application No. 2009-030689 filed on February 13, 2009, including the specification, drawings, and claims.

In recent years, emulators and on-board debuggers, which are program debugging devices, are widely used in development environments for embedded programs. In the embedded program, high-quality software is desired at the same time as the software becomes larger and more complex with higher functionality. In particular, in car navigation and mobile phone software, multiple interrupts are frequently used to realize high functions, and the functions of CPU (Central Processing Unit) are utilized to the maximum extent. Therefore, in the CPU design, it is necessary to appropriately set the interrupt processing time and the memory access exclusivity.

In a CPU design that requires such settings, the design work becomes more complicated as software becomes larger and more complex, and problems such as memory access exclusivity and interrupt processing time are more likely to occur. Therefore, CPU design often falls into a situation where the design contents must be analyzed using a program debugging device. The program debugging apparatus has a trace function and an event function, and the design contents are traced by the CPU using these functions, and as a result, the trace log (record of processing executed by the program) obtained by the CPU is analyzed. .

FIG. 20 is a block diagram showing a configuration of a conventional program debugging apparatus. The program debugging apparatus includes a CPU 1, an event controller 2, a trace controller 3, and a trace memory 11.

CPU1 executes the program. The event controller 2 monitors the state of processing performed by the CPU 1 during execution of the program, determines whether the monitored state is equivalent to the state set as an event, and determines the determination result as the event establishment state. To the trace controller 3. Based on the trace log acquired from the CPU 1 and the event establishment state acquired from the trace controller 3, the trace controller 3 is equivalent to the state established in advance as the start event and the end event and the event establishment state. It is determined whether or not. Further, the trace controller 3 creates the trace recording execution information 3a based on the determination result. When there is an instruction to record the trace log, the trace controller 3 records the held trace log in the trace memory 11 and then analyzes the log.

The program debug device sets a start event and an end event at a place where it can be assumed that a problem occurs in software as described above, and then in a period from the start event to the end event (hereinafter abbreviated as a trace log period). Acquire the trace log and analyze the acquired trace log. By repeating the above processing, a place where a problem finally occurs is specified.

In general, the longer the processing time is in the trace log period, the greater the effect of the problem that occurs on the software. Therefore, in the trace log period in which the processing time is the longest (hereinafter referred to as the longest trace log period), the influence of the problem occurring there is the maximum. From this, it is considered effective to reduce the time required to solve the problem by specifying the longest trace log period and analyzing the longest trace log period. A method for specifying the longest trace log period is proposed in Patent Document 1. A method for recording a trace log is proposed in Patent Document 2.

Japanese Patent Laid-Open No. 3-92940 Japanese Patent Laid-Open No. 5-241878

According to Patent Document 2, the trace logs in each period can be accumulated and recorded, but the trace log in the specified longest trace log period cannot be selectively recorded after the longest trace log period is specified. .

In the longest trace log period,
・ Multiple interrupts occur,
・ An unexpected interrupt occurs.
・ The amount of processing increases abnormally.
・ Multiple tasks have write access to variables,
As a result, it is assumed that the problem of exclusivity occurs and the task processing time becomes abnormally long. Therefore, the longest trace log period is estimated based on such an assumption. Therefore, if the interrupt is not entered, the processing time is shortened and the above-mentioned inconvenience often does not occur. Then, the trace log period that should be the longest trace log period is specified as the longest trace log period. It becomes impossible.

This will be described with reference to the program debugging apparatus shown in FIG. 21 to which the time measurement function shown in FIG. 20 is added. The event controller 2 also outputs the event establishment state to the time measuring device 7. The time measuring device 7 determines whether or not the state set in advance as the start event and the end event is equivalent to the event establishment state. The time measuring device 7 measures the time of the event establishment state determined to be equivalent to the state set in advance in the determination. Here, the time measurement is to measure the time length of the trace log period in which the processing state of the start / end event is equivalent to one arbitrary event in the event establishment state. Hereinafter, the time length measured in this way is simply referred to as the time length.

After performing the above time measurement, the time measuring device 7 records the measured time length. When recording, the time measuring device 7 compares the time length of the trace log period measured this time with the time length of the trace log period already stored, and the time length of the trace log period measured this time is the recorded trace log period. Only when the time length is longer than the time length, the time length is updated. When the time length is shorter, the time length is not updated. By performing such a record update operation, the time measuring device 7 maintains the longest time length while constantly updating it.

While the trace controller 3 accumulates the trace log, the time measuring device 7 performs time length measurement and update processing of the longest time length. The conventional program debugging apparatus repeats such an operation. The time measuring device 7 operates independently of the trace controller 3.

When analyzing problems on systems that are used for a long time or software with low reproducibility, the CPU 1 is executed for a long time and the trace log is accumulated. However, in that case, the accumulated trace log becomes enormous, and the analysis of the trace log itself becomes difficult, and the processing takes a lot of time. Furthermore, since the capacity of the trace memory 11 is limited, if the trace log becomes enormous, the area for recording the trace log is rolled over and the trace log is overwritten, so that the trace log cannot be analyzed. There is also.

For these reasons, it is practically impossible to analyze the trace log and identify the length of time when analysis takes longer than expected due to multiple interrupts or unexpected interrupts. is there.

For example, when the data unit of the trace log is 20 bytes and the average number of trace log data in the period (trace log period) from the start to the end of the trace is 5,000, The data size of the trace log in the trace log period is 100,000 bytes. If the setting cycle of the trace log period is 10 times per second and the capacity of the trace memory 11 is 1,000,000 bytes, the amount of trace log that can be recorded is only about 1 second, which is insufficient. I must say.

The main object of the present invention is to narrow down the trace log effectively in the recording of the trace log, thereby quickly and easily identifying a problem with low reproducibility and difficult to analyze.

Considering that the cause of the above-described conventional problem is that the trace log period to be traced is not narrowed down to the longest trace log period, the present invention has the following configuration.

(1) A program debugging apparatus according to the present invention comprises:
A CPU for executing the program;
After holding an event defining an arbitrary state at the time of execution of the program by the CPU, the process progress at the time of actual program execution by the CPU is compared with the event, and in the process progress based on the comparison result An event controller that determines whether or not a partial progress that defines the start and end of the event is established; and
A trace memory for recording the partial progress;
A trace controller for temporarily recording the partial progress determined to be established by the event controller in the trace memory;
Whether the period from the start of the partial progress to the end at the temporary point at the time of actual program execution is the longest among the groups of the partial progress groups established before that including the temporary point A trace log recording confirmation controller for selecting whether to record the partial progress temporarily recorded in the trace memory at the temporary point based on the determination of
Is provided.

In this configuration, the event controller is
-Holds an event that defines an arbitrary state when the program is executed by the CPU.
-Compare the process progress (trace log) and event during the actual program execution by the CPU,
-It is determined whether or not the partial progress in which the start and end are defined by the event in the processing progress is established based on the comparison result,
Perform the operation.

The trace controller
-Temporarily record the partial progress determined to be established by the event controller in the trace memory.
Perform the operation.

Trace log record confirmation controller
・ Whether the period from the start of the partial progress at the temporary point at the time of actual program execution to the end is the longest among the groups of partial progress groups established before that including the temporary point to decide,
-Select whether to record the partial progress temporarily recorded in the trace memory at a temporary point based on the judgment result,
Perform the operation.

By discarding unnecessary partial processes in this way, the number of partial processes remaining in the trace memory can be reduced. In addition, "the period from the start of the partial progress at the temporary point at the time of actual program execution to the end is the longest among the groups of the partial progress groups established before that including the temporary point" Is actually “longer than last time” and does not mean just one. The partial progress left in the trace memory is the partial progress related to events that are relatively long in duration and likely to contain more serious software problems. Therefore, by analyzing the partial progress that has been narrowed down and stored in the trace memory in this way, it is possible to quickly and easily identify the location of the final problem. In addition, narrowing down the partial progress of recording is also effective in avoiding an excessive increase in the capacity of the trace memory.

(2) In the program debugging apparatus of (1) described above,
The trace log record confirmation controller comprises a trace memory address manager;
The trace memory address manager sets a recording address (latest) that defines a memory position in the trace memory that stores the partial progress established at the temporary point, and the part established at a time before the temporary point. Set the recording address (previous) that defines the memory location in the trace memory that stores the progress,
When the trace memory address manager determines that the period is the longest in the group of periods, the trace memory address manager updates the recording address (latest) while determining that the period is not the longest in the group of periods. Then, the recording address (previous) is set to the recording address (latest).
There is a mode.

If the above period (in other words, the length of time required for the temporary recording) in the partial progress is the longest in the period group, the recording address (latest) is updated. Then, the next partial progress is recorded, the updated recording address (latest), and not the recording address (previous) which is the address at which temporary recording was performed one time before. For this reason, overwriting is not performed on the address where temporary recording was performed once before, and as a result, the partial progress recording at the address where temporary recording was performed once was confirmed as the main recording. It becomes. On the other hand, if it is determined that the period is not the longest in the period group, the recording address (previous) is set as the recording address (latest). Then, the next partial progress is recorded as a recording address (previous) where the temporary recording was performed once before, as a result of the recording address where the temporary recording was performed once before. Overwritten for (previous). As a result, the partial progress record at the address where the temporary recording was performed once is discarded, and a trace log relating to the current temporary recording is recorded instead.

(3) In the program debugging apparatus of (2) described above,
When the trace memory address manager determines that the period is the longest in the group of periods, the trace memory address manager copies the updated recording address (latest) to the recording address (previous), and the period is the period. If it is determined that it is not the longest in the group, the recording address (previous) is copied to the recording address (latest).
There is a mode.

Control to shift from temporary recording to actual recording or discarding is realized by copying the updated recording address (latest) to the recording address (previous) or copying the recording address (previous) to the recording address (latest). Therefore, the control from the temporary recording to the main recording or discarding can be easily realized with a simple configuration. If the updated recording address (latest) is copied to the recording address (previous), the recording address (previous) becomes the recording destination address of the partial passage temporarily recorded immediately before this. The fact that such an address is stored at the recording address (previous) corresponds to the temporary recording being promoted to the main recording. On the other hand, if the recording address (previous) is copied to the recording address (latest), the recording address updated after temporary recording (latest) will be restored, and overwriting of the next trace log to that address will be allowed. become. As a result, the previous temporary record is discarded.

(4) In the program debugging device of (2) described above,
An update timing controller;
The update timing controller determines the setting timing of the recording address (latest) by the trace memory address manager and the recording address (based on the determination whether the period is the longest in the group of periods. Control the timing of the previous)
There is a mode.

The update timing controller judges whether or not the period required for temporary recording of partial progress is the longest up to the present, and gives the judgment result to the trace memory address manager. The update timing controller is exclusively used for timing management. It can be configured to manage

(5) The program debug device of (2) described above includes
The trace log record confirmation controller further holds the record address (previous) as a trace start address.
There is a mode.

This uses the trace start address in addition to the record address (latest) and record address (previous). Since each recording address (latest) is held as a trace start address, a record address (latest) related to the actual recording is always set as the trace start address. The period related to this recording is the longest among the recorded period groups.

When the partial progress recording is completed, a plurality of partial progresses having the longest period are recorded in the trace memory. When reading the partial progress from the trace memory at the time of analysis, if the trace start address is accessed and read, the partial progress having the longest period (the longest partial progress in the longest) is read out from the recorded partial progress group. It will be. It can be estimated that the partial course having the longest period in the partial course group is likely to be a result of the program part including the most serious software problem. In this way, by analyzing after narrowing down the partial progress, it is possible to further quickly and easily identify the problem occurrence location.

(6) The program debugging device of (5) described above includes
When the trace log recording confirmation controller determines that the period is the longest in the group of the periods, it sets the recording address (previous) as the trace start address and then updates the updated recording address (latest ) Is copied to the recording address (previous), and if the period is determined not to be the longest in the group of periods, the recording address (previous) is copied to the recording address (latest).
There is a mode.

This is to adjust the address by copying to realize the program debugging device of (5) above.

(7) In the program debugging device of (4) described above,
A time measuring device,
The time measuring device generates longest time update information indicating a determination result of whether or not the period is the longest in the group of the periods;
The update timing controller controls the setting timing of the recording address (latest) and the setting timing of the recording address (previous) by the trace memory address manager based on the longest time update information. . If comprised in this way, it will become possible to comprise in the state which isolate | separated the time measuring device from the update timing controller. In the case of this configuration, by adding a time measuring device, it becomes easy to apply and deploy the present invention to a conventional program debugging apparatus having a trace function.

(8) The program debugging device (4) described above includes
There is a mode in which the update timing controller determines whether or not the period is the longest in the group of periods based on time information attached to the partial progress.

When the period is the longest in the group of the periods, the trace memory address manager updates the recording address (latest), thereby determining the temporary recording of the partial progress in the trace memory as the main recording. On the other hand, when the period is not the longest in the group of periods, the temporary recording of the trace log is discarded by setting the recording address (previous) as the recording address (latest). Then, the update timing controller controls the timing of the trace memory address manager based on the determination result of whether or not the period is the longest in the group of the periods. In this aspect, the longest determination of the period in the update timing controller is performed using time information attached to the partial progress. Calculate the time length of the period from the time information when the partial progress temporary recording starts and the time information when it ends, generate trace information based on the calculated time length of the period, and further generate the trace information Based on the timing of the trace memory address manager. According to this configuration, the present invention can be realized even in a program debug device that does not include the time measuring device in the configuration of (7) described above.

(9) In the program debugging device of (4) described above,
The update timing controller determines whether the period is the longest in the group of periods based on the partial progress and the event.
There is a mode.

In this mode, two elements of partial progress and event are used in the longest judgment of the period by the update timing controller. The update timing controller compares the event information set as the partial progress provisional recording start event with the processing progress, and compares the time information when the event matches the processing progress with the event information set as the partial progress provisional recording end event. Then, the time length of the period is calculated from the time information when they match. Further, the update timing controller generates event trace information indicating the calculated time length, and controls the timing of the trace memory address manager based on the event trace information. According to this aspect, the present invention can be realized even in a program debugging apparatus that does not include a time measuring device.

(10) The program debug device of (4) described above includes
An update timing mask controller;
The update timing mask controller controls the validity / invalidity of the control operation of the setting timing of the recording address (latest) by the update timing controller.
There is a mode.

If it is possible to predict in advance a partial process that causes a problem in software to some extent, it is reasonable to narrow the temporary record of the partial process to one that is predicted to cause a problem. Partial progress that is not predicted to cause a problem may be excluded from provisional recording. For example, the partial period immediately after the program execution tends to be the longest. However, in the partial progress determined to be the longest period immediately after the execution of the program, there are many cases where there is no problem in the program component that caused the partial progress. Therefore, although it is determined that the period is the longest, the partial progress that is considered to be unlikely to have a defect in the program component that caused the partial progress may be discarded. In this way, with respect to a partial process that is known in advance to be unlikely to be defective in the program component that caused the partial process, the recording address (latest) that the update timing controller performs for the partial process The update control is set to invalid by the update timing mask controller. By doing so, it is possible to discard the temporary recording of partial progress that is known in advance that the program component that caused the partial progress is unlikely to be defective. On the other hand, for partial progress that is known in advance that there is no low possibility that the program component that caused the partial progress is defective, the recording address (latest) that the update timing controller performs for the partial progress Set the update control to valid. By implementing the above control, the temporary recording in the trace memory is limited to the main recording, limited to the partial processing that is known in advance that the possibility that the program component that caused the partial processing is defective is not low. It becomes possible to confirm. As a result, the collection of partial progress related to the problem occurrence location is made efficient.

(11) In the program debugging device of (4) described above,
An external trigger output device
The update timing controller outputs address update information indicating update / non-update of the recording address (latest),
The external trigger output unit generates and outputs an external trigger composed of an arbitrary waveform signal based on the address update information.
There is a mode.

When analyzing problems that occur in the program, you can solve the problem by not only analyzing the collected partial progress, but also acquiring waveforms such as the location of the problem or the output status at the time of the problem, and analyzing that waveform together. Can be effectively advanced. The recording address (latest) is updated when the longest period is updated. At this time, the external trigger output unit outputs an arbitrary waveform signal used for problem solving as an external trigger. For example, a waveform such as an output state of an actuator or the like in the user target system is acquired by an oscilloscope or the like and output as an external trigger.

(12) The program debugging device (4) described above includes
A break controller,
The update timing controller outputs address update information indicating update / non-update of the recording address (latest),
The break controller stops the operation of the CPU based on the address update information;
There is a mode.

Update / non-update of the recording address (latest), that is, if the CPU is stopped when the longest value of the period is updated, the state and processing of the variable at the time of occurrence of the problem immediately using the partial progress acquired at that time It is possible to debug the state of the problem, and it is possible to speed up problem solving.

(13) The emulator system of the present invention
A host IF circuit that exchanges debugging information with the host computer;
The program debug according to claim 1, wherein debugging is performed by controlling a user target system based on an instruction of the host computer via the host IF circuit, and transmitting the debug result to the host computer via the host IF circuit. Equipment,
Is provided. The emulator system of the present invention can efficiently debug a problem on a program or a peripheral device.

According to the present invention, the partial progress in which the event establishment state is valid is temporarily recorded in the trace memory, and then only the partial progress in which the period is the longest is recorded, so that it is effective in recording the partial progress. As a result, it is possible to quickly and easily identify software problems that are difficult to analyze with low reproducibility.

FIG. 1 is a block diagram showing a configuration of a program debugging apparatus according to Embodiment 1 of the present invention. FIG. 2 is a flowchart showing the trace log temporary recording operation in the program debugging apparatus according to the first embodiment of the present invention. FIG. 3 is a flowchart of the address operation of the trace memory in the program debugging apparatus according to the first embodiment of the present invention. FIG. 4A is an explanatory diagram of a first transition of the length of the trace log period according to the first embodiment of the present invention. FIG. 4B is an explanatory diagram showing a second transition of the length of the trace log period according to the first embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of the program debugging apparatus according to the second embodiment of the present invention. FIG. 6 is a flowchart of the operation of the recording destination address in the program debugging apparatus according to the second embodiment of the present invention. FIG. 7 is a block diagram showing the configuration of the program debug apparatus according to the third embodiment of the present invention. FIG. 8 is a block diagram showing the configuration of the program debugging apparatus according to the fourth embodiment of the present invention. FIG. 9 is a diagram showing an example of a trace log accompanying time information according to Embodiment 4 of the present invention. FIG. 10 is a flowchart for determining the trace log period according to the fourth embodiment of the present invention. FIG. 11 is a block diagram showing a configuration of a program debugging apparatus according to Embodiment 5 of the present invention. FIG. 12 is a flowchart for determining the trace log period according to the fifth embodiment of the present invention. FIG. 13 is a block diagram showing the configuration of the program debugging apparatus according to the sixth embodiment of the present invention. FIG. 14 is a flowchart of trace memory address operations according to the sixth embodiment of the present invention. FIG. 15 is a block diagram showing a configuration of a program debugging apparatus according to the seventh embodiment of the present invention. FIG. 16 is a flowchart of the trace memory address operation in the seventh embodiment of the present invention. FIG. 17 is a block diagram showing a configuration of a program debugging apparatus according to the eighth embodiment of the present invention. FIG. 18 is a flowchart of the address operation of the trace memory according to the eighth embodiment of the present invention. FIG. 19 is a block diagram showing the configuration of an emulator system and its peripherals according to the present invention. FIG. 20 is a block diagram showing a configuration of a program debugging apparatus using a conventional trace function and event function. FIG. 21 is a block diagram showing a configuration of a program debugging apparatus to which a time measuring function of the prior art is added.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a program debugging apparatus according to Embodiment 1 of the present invention. The program debugging apparatus includes a CPU 1, an event controller 2, a trace controller 3, a trace log record confirmation controller 4, and a trace memory 11. The present embodiment is characterized in that it has the configuration of the conventional example shown in FIG. 20 and further includes a trace log recording confirmation controller 4.

The CPU 1 is configured by hardware or software and executes a program (specifically, a program code). The event controller 2 manages two or more events. An event defines an arbitrary state during program execution. More specifically, the event defines the start and end of an arbitrary partial progress included in the processing progress when the CPU 1 executes the program. An address when the CPU 1 executes a program, an address when reading or writing various data, and the like are defined by events. The event controller 2 registers and manages a plurality of events. After that, the event controller 2 compares the process progress when the CPU 1 actually executes the program with the managed event, and each part of the process progress specifies an arbitrary event (start / end of a predetermined partial progress). Is determined for each managed event, and the result of the determination is output as an event establishment state. The event establishment state is information indicating validity / invalidity. Here, “valid” indicates that one state included in the process progress is equivalent to one arbitrary event, and “invalid” indicates that it is not equivalent.

Trace memory 11 records a trace log. The trace log is a record of all or part of the processing progress of execution of the program by the CPU 1, and indicates the partial progress in the present invention. Typical examples of the trace log include an address at which the CPU 1 executes a program, an address at which various data are read or written, and the like. The contents of the trace log vary depending on the program debug device.

When the event establishment state output from the event controller 2 indicates that the event controller 2 is valid, the trace controller 3 starts a process of temporarily recording the trace log, which is an operation record of the CPU 1, in the trace memory 11, and subsequently another event is established. When the status indicates valid, the temporary recording process is terminated.

The trace log record confirmation controller 4
The trace log temporarily recorded in the trace memory 11 (hereinafter referred to as “trace log (latest)”) is confirmed as a trace log (hereinafter referred to as “trace log (record)”) that is continuously recorded without being discarded. To
・ Determine that the above trace log (latest) is to be discarded without being a trace log (record).
Switching control is performed.

Switching control by the trace log record confirmation controller 4 is performed as follows. The trace log recording confirmation controller 4 records a trace log period T indicating the time required for temporary recording of the trace log. Specifically, the trace log period T is a state equivalent to any other event managed by the event controller 2 after a state equivalent to any one event managed by the event controller 2 occurs. Refers to the period of time that occurs. In other words, the trace log period T is a period from the start of partial progress to the end. Hereinafter, the trace log period T calculated by the trace log recording confirmation controller 4 in accordance with the calculation of the trace log (latest) by the trace controller 3 is referred to as a trace log period (latest) T2. The trace log recording confirmation controller 4 temporarily records the longest trace log period (latest) T2 at that time, and then records it. Hereinafter, the longest recorded trace log period (latest) T2 is referred to as a trace log period (record) T1.

When the trace controller 3 newly calculates a trace log (latest) and temporarily records it in the trace memory 11, the trace log recording confirmation controller 4 sets a trace log period (latest) T2 corresponding to the trace log (latest). After the calculation, the trace log period (latest) T2 is compared with the already recorded trace log period (record) T1. In this comparison result, the trace log record confirmation controller 4 determines whether the trace log period (latest) T2 is longer than the trace log period (record) T1 (in other words, whether the trace log period (latest) T2 is the longest). Whether or not: T2> T1) is determined. Based on the determination result, the trace log record confirmation controller 4 determines whether or not to confirm the trace log (latest) in the trace memory 11 as the trace log (record).

The trace log record confirmation controller 4 includes a trace memory address manager 5 and an update timing controller 6. The trace memory address manager 5 manages the recording address (latest) A and the recording address (previous) B, and the trace memory address manager 5 is composed of a register, for example. The recording address (latest) A is address information for specifying a recording area on the trace memory 11. This address information is set to temporarily record the trace log (latest). Each time the temporary recording of the trace log (latest) is completed on the trace memory 11, the recording address (latest) A is updated by a process such as increment for the next temporary recording. The recording address (previous) B indicates a memory position on the trace memory 11 in which the trace log in which the main recording is confirmed is stored. The recording address (previous) B is equal to the recording address (latest) A before the update (that is, the old) of the trace log in which the main recording is confirmed after the temporary recording. In actual processing, every time the recording address (latest) A is updated, the recording address (latest) A before updating is recorded as the recording address (previous) B.

When the trace log period (latest) T2 calculated by the trace controller 3 is the longest at the present time (when T2 is longer than T1: T2> T1), the trace memory address manager 5 next traces in the trace memory 11. The recording address (latest) A indicating the memory location where the log is temporarily recorded is updated. The address update is performed by, for example, increment processing.

On the other hand, when the trace log period (latest) T2 is not the longest at the present time (when T2 is equal to or shorter than T1: T2 ≦ T1), the trace memory address manager 5 updates the record address (latest) as A. The current value is continuously set without performing.

After adjusting the recording address (latest) A described above, the trace memory address manager 5 adjusts the recording address (previous) B. That is, when the trace log period (latest) T2 is the longest at the present time (T2> T1), the trace memory address manager 5 updates the record address (latest) A and then updates the updated record address (latest). ) A is copied to the recording address (previous) B. By simultaneously updating the recording address (latest) A and copying the recording address (previous) B with the updated recording address (latest) A, the temporary recording of the trace log that has just been temporarily completed is Finalize as final record.

On the other hand, when the trace log period (latest) T2 is not the longest at the present time (T2 ≦ T1), the trace memory address manager 5 copies the recording address (latest) A to the recording address (previous) B. As a result, it is allowed that the trace log measured next time is overwritten at the memory location of the trace memory 11 where the trace log that has just been temporarily recorded is recorded, and as a result, the temporary recording is completed. The destruction of the temporary record of the last trace log is confirmed.

The update timing controller 6 determines whether or not the trace log period (latest) T2 is the longest at the present time (T2> T1), and controls the timing at which the determination result is given to the trace memory address manager 5. . This is used when the copy timing of the recording addresses A and B is controlled. There are various methods for managing time in the update timing controller 6, and details will be described in other embodiments.

FIG. 2 is a flowchart showing the operation of temporarily recording the trace log of the program debugging apparatus according to the first embodiment. First, the CPU 1 executes a program (specifically, a program code) (step S01). Next, the trace controller 3 acquires a trace log that is a record of the processing contents when the CPU 1 executes the program (step S02). Next, the trace controller 3 acquires the event establishment state from the event controller 2 (step S03). Here, when a state constituting a part of the processing in the program execution processing by the CPU 1 becomes equivalent to an event registered and managed in advance by the event controller 2, the event establishment state becomes valid, and becomes invalid when becoming non-equivalent. .

Next, the trace controller 3 determines whether or not to temporarily record the trace log based on the acquired event establishment state (step S04). If the event establishment state indicates valid, it is determined that temporary recording of the trace log is to be executed, and an execution instruction is generated. On the other hand, in the case of indicating invalidity, it is determined that the temporary recording of the trace log is not executed, and a non-execution instruction is generated.

Next, the trace controller 3 determines the instruction content related to the temporary recording of the trace log created in step AS04 (step S05). When determining that the temporary recording execution instruction has been created, the trace controller 3 traces the trace log to the memory location of the trace memory 11 defined by the recording address (latest) A recorded in the trace memory address manager 5. Is temporarily recorded, and the recording address (latest) A recorded in the trace memory address manager 5 is updated with address information indicating another memory position where the trace log is temporarily recorded next (step S06). Update is performed by increment or the like. On the other hand, when determining that a non-execution instruction has been created, the trace controller 3 does not temporarily record a trace log (step S07). The update process of the recording address (latest) A is performed in order to write the next trace log to another memory location on the trace memory 11 after writing the trace log to the trace memory 11.

FIG. 3 is a flowchart showing an operation for manipulating the address of the trace memory 11 of the program debugging apparatus of the first embodiment. First, when one arbitrary event is established (that is, when it is determined that one traced processing state is equivalent to a registered event), temporary recording of the trace log is started. In addition, when another arbitrary event is established (ie, it is determined that another traced processing state is equivalent to another registered event), the temporary recording of the trace log is terminated. The

In the temporary recording of the trace log executed in this way, the trace memory address manager 5 determines whether or not the trace log period (latest) T2 is the longest at the present time. Subsequent processing branches based on this determination (steps S10 and S20).

If it is determined in step S20 that the trace log period (latest) T2 is the longest at the present time, the update timing controller 6 outputs the updated recording address (latest) A to the trace memory address manager 5 ( Step S30). This process is recorded by the updated recording address (latest) A (indicating the memory position on the trace memory 11 where the trace log of the current measurement in which the trace log period (latest) T2 is determined to be the longest) is recorded. This is performed so that the address (previous) B is copied. By this copy recording, the recording address (latest) A determined to be recorded is registered as the recording address (previous) B.

On the other hand, if it is determined in step S20 that the trace log period (latest) T2 is not the longest at the present time, the update timing controller 6 causes the recording address (latest) A to be copied by the recording address (previous) B. Then, the recording address (previous) B is output to the trace memory address manager 5 (step S40). This copying allows the trace log to be overwritten, and the temporary recording of the trace log that has just been completed is discarded.

That is, as shown in FIG. 2, in an arbitrary trace log period T, the trace log (latest) is recorded at the memory position of the trace memory 11 specified by the recording address (latest) A. In addition, as shown in FIG. 3, only when the trace log period (latest) T2 is the longest at the present time, the recording address (latest) A is updated and the updated recording address (latest) A is recorded. It is copied to the address (previous) B and the main record of the trace log is finalized.

On the other hand, if it is determined that the trace log period T is not the longest at the present time, the recording address (latest) A is copied with the recording address (previous) B, contrary to the above. Will return. As a result, the trace log (latest) shifts to a state where it is discarded.

In the above processing, the actual recording of the trace log is performed only when the trace log period (latest) T2 is the longest at the present time. However, the number of trace logs (records) is not limited to one. The longest value of the trace log period (latest) T2 becomes longer and updated as the measurement time elapses, as is apparent from the measurement form. Accordingly, every time the longest value of the trace log period (latest) T2 is updated in the measurement result, the longest value of the trace log period (latest) T2 is detected. In addition, each time the maximum value is determined, the trace log (latest) at that time is regarded as a trace log (record). As a result, a plurality of trace logs (records) are recorded in the trace memory 11. Therefore, the trace log period (recording) T1 becomes longer as the recording time is later. This is shown in FIG.

4A shows the transition of the trace log period (latest) T2, and FIG. 4B shows the transition of the trace log period (record) T1 held in the trace memory 11. The trace log marked with ○ is selected and remains in the trace memory 11, and the trace log marked with × is discarded.

Now, as an example of the operation, with the recording of the trace log L0 at the previous time, the address [0100] is updated and set as the recording address (latest) A, and further, the recording is recorded with the update setting of the recording address (latest) A It is assumed that the address [0100] is also copied to the address (previous) B. In this state, it is assumed that the trace log L1 is currently recorded at the memory location of the trace memory 11 designated by the recording address (latest) A [0100]. In this state, the recording address (latest) A is updated (incremented) from address [0100] to address [0200].

As the above process proceeds, the candidate of the recording address (latest) at which the trace log L2 to be measured next is to be temporarily recorded is
-Updated recording address (latest) A1 [0200],
Recording address before update (latest) A2 [0100] (= recording address (previous) B),
It becomes two. Which of the recording address after update (latest) A1 [0200] and the recording address before update (latest) A2 [0100] is set as the next recording address (latest) A depends on the trace log period (latest) ) Determined based on the longest judgment in T2. That is, when it is determined that the trace log period (latest) T2 is the longest at the present time (T2> T1), the updated recording address (latest) A1 [0200] is set as the recording address (latest) A. When it is determined that the recording address is not the longest (T2 ≦ T1), the recording address (latest) A2 (= recording address (previous) B [0100]) before the update is set as the recording address (latest) A.

When the updated recording address (latest) A1 is set as the recording address (latest) A, the updated recording address (latest) A1 is also copied to the recording address (previous) B. As a result, the actual record of the trace log (latest) recorded at the memory location of the trace memory 11 defined by the recording address (latest) A2 before updating (= recording address (previous) B [0100]) is confirmed and overwritten. Is no longer allowed. Thereby, in the trace log (latest) recorded in the memory location of the trace memory 11 defined by the recording address (previous) B, the main record is recorded as the trace log having the longest trace log period (latest) T2 at the present time. Is confirmed. On the other hand, when the recording address (latest) A2 before update is set as the recording address (latest) A, overwriting is permitted at the memory location of the trace memory 11 defined by the recording address (latest) A2 before update. become. As a result, the trace log (latest) recorded at the memory location of the trace memory 11 defined by the recording address (latest) A2 before update (= recording address (previous) B [0100]) is discarded.

Hereinafter, the processing described above will be described in more detail.

(Processing of a-1)
It is determined that the trace log period (latest) T2 of the trace log L1 described above is the longest or equivalent to the present time, and the updated recording address (latest) A1 [0200] is set as the recording address (latest) A. When set, the next trace log L2 is recorded at the memory location of the trace memory 11 defined by the address [0200] which is the newly set recording address (latest) A. As a result, the trace log L1 and the trace log L2 are recorded in the trace memory 11. However, regarding the trace log L2, it is not determined whether or not the trace log period (latest) T2 is the longest at the present time. Therefore, the recorded trace log L2 is merely a trace log (latest) and not a definitive trace log (record). However, since the trace log (latest) is recorded, the recording address (latest) A is incremented and updated from address [0200] to address [0300].

(Process b-1)
On the other hand, when it is determined that the trace log period (latest) T2 is not the longest at the present time for the trace log L1 described above and the recording address (previous) B [0100] is set as the recording address (latest) A, the following The trace log L2 is recorded in the memory location of the trace memory 11 defined by the address [0100] which is the recording address (latest) A. Thus, at the memory location of the trace memory 11 defined by the address [0100], the trace log L1 recorded so far is overwritten and recorded by the trace log L2. That is, the trace log L1 previously recorded as the trace log (latest) is eventually discarded. Since the trace log (latest) is recorded, the recording address (latest) A is incremented and changed from address [0100] to address [0200].

(Process a-2)
Following the processing of a-1, if the trace log period (latest) T2 is the longest at the present time in the trace log L2, the address [0200] obtained by incrementing the address [0200] is determined as the recording address (latest) A Is done. In such a state, the address [0200] positioned before the increment [0300] determined as the recording address (latest) A cannot be the recording address (latest) A. Therefore, the main record of the trace log L2 recorded at the memory location of the trace memory 11 defined by the address [0200] which is the recording address (latest) A is confirmed. As a result, the trace logs having the longest trace log period (latest) T2 at the present time are the trace log L1 and the trace log L2.

(Process b-2)
Following the process of b-1, if the trace log period (latest) T2 is the longest at the present time in the trace log L2, the address [0200] incremented and updated as the recording address (latest) A is the recording address (latest). Confirmed as A. In such a state, the address [0100] positioned before the increment [0200] determined as the recording address (latest) A cannot be the recording address (latest) A. Therefore, the main record of the trace log L2 recorded at the memory location of the trace memory 11 defined by the address [0100] which is the recording address (latest) A is confirmed. Further, the trace log whose race log period (latest) T2 is the longest or equivalent to the current time is the trace log L2.

As described above, when the instruction to temporarily record the trace log is activated, the trace log is always recorded in the trace memory 11 once. However, it is not a main recording but a temporary recording. The determination as to whether or not the trace log (latest) temporarily recorded in this way is the trace log (record) is to determine whether or not the next measured trace log period (latest) T2 is the longest. It is entrusted. Further, the process of changing the trace log (latest) to the trace log (record) and the process of discarding the trace log (latest) are performed through the adjustment process of the recording address (latest) A. That is, the recording address (latest) A having the longest or equivalent trace log period (latest) T2 at the current time is set as the updated recording address (latest) A (address incremented with temporary recording), and The updated recording address (latest) A is copied to the recording address (previous) B in order to determine the temporary recording as the main recording. When the trace log period (latest) T2 is not the longest at the present time, the updated recording address (previous) B is copied to the recording address (latest) A. This is the technical point of the present embodiment.

By using the program debug device of the present embodiment, every time an arbitrary event is established and the trace log period (latest) T2 indicating the length of time until any one event is established is the longest, Trace log can be recorded. As a result, unnecessary trace logs can be discarded.

In the present embodiment, the trace log having the longest trace log period T at the present time is selectively recorded in the trace memory from among a plurality of temporarily recorded trace log groups, and the other trace log groups are discarded. Even in a state where the capacity of the trace memory 11 is limited, it is possible to selectively record a trace log that is likely to cause a problem in software. As a result, it is an extremely effective measure for quickly and easily finding and solving problems. In addition, since the trace log records are narrowed down, it is possible to avoid an excessive increase in the capacity of the trace memory 11.

(Embodiment 2)
The program debug apparatus according to the second embodiment of the present invention uses 1 trace log having the longest trace log period T (the longest in the longest trace log group) among a plurality of trace logs recorded in the trace memory 11. And a configuration for recording a trace start address for this purpose.

FIG. 5 is a block diagram showing the configuration of the program debugging apparatus according to the second embodiment. In FIG. 5, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components. The configuration specific to the present embodiment is as follows. The trace memory address manager 5 further holds a trace start address C. The trace start address C is held in order to back up and hold the recording address (previous) B among the addresses defining the memory position of the trace memory 11.

The timing at which the recording address (previous) B is backed up to the trace start address C is the timing at which the trace log period T is the longest at the present time. The update timing controller 6 further has a function of controlling the timing for copying the recording address (previous) B to the trace start address C. Other configurations are the same as those in the first embodiment, and thus description thereof is omitted.

FIG. 6 is a flowchart showing the operation of manipulating the address of the trace memory 11 of the program debugging apparatus according to the second embodiment, which corresponds to the flowchart of FIG. 3 according to the first embodiment with step S21 added. The flowchart of FIG. 2 in the first embodiment is followed in the present embodiment.

In step S21, the update timing controller 6 outputs the recording address (previous) B to the trace memory address manager 5 so as to copy it to the trace start address C. When the recording address (latest) A is copied to the recording address (previous) B, the recording address (previous) B changes, but the previous recording address (previous) B is copied to the trace start address C. Back up. Thereby, the trace start address C when the trace log is temporarily recorded is held.

Now, the trace log L1 is recorded at the recording address (latest) A [0100], and the recording address (latest) A is updated to the address [0200] according to this trace log recording, and the recording address (previous) B is Suppose that the address [0100] is repeated. In this state, if the trace log period T of the trace log L1 is the longest at the present time, the recording address (latest) A [0200] is copied to the recording address (previous) B. At this time, as a pre-processing for copying, the recording address (previous) B [0100] before copying is copied to the trace start address C. The address (address [0100] in this example) copied to the trace start address C indicates the storage address of the trace log L1 in which the trace log period T is the longest at the present time. After the recording address (previous) B [0100] before copying is copied to the trace start address C, the updated recording address (latest) A [0200] is copied to the recording address (previous) B. The recording address (previous) B is the address [0200].

Next, the trace log L2 is recorded at the recording address (latest) A [0200], and the recording address (latest) A is updated to the address [0300] accordingly. If the trace log period (latest) T2 of the trace log L2 is the longest at the present time, the recording address (previous) B [0200] is copied to the trace start address C. As a result, the trace start address C is the address [0200]. It becomes. This indicates that the address specifying the memory location where the trace log L2 having the longest trace log period T is stored is the address [0200] at the current time. Next, the updated recording address (latest) A [0300] is copied to the recording address (previous) B. As a result, the recording address (previous) B becomes address 0300.

As is apparent from the above, according to the present embodiment, the recording destination address of one trace log finally confirmed and recorded among the entire trace log group decided from temporary recording to actual recording is the trace start address C. Will be held. As a result, it is possible to specify the recording destination address of the longest trace log period T in the entire trace log group recorded in the trace memory 11 (the longest in the longest trace log group). it can. As a result, it is possible to quickly find and solve the problem part.

A configuration in which n trace start addresses C, C1, C2,. At the first time when the trace log period T is the longest so far, the address of the main recording at that time is recorded in the trace start address C1. At the second time when the trace log period T is the longest so far, the address at the trace start address C1 of the first main record is copied to the trace start address C2, and the current main record address is copied to the trace start address C1. Copy to. Similarly, at the third time when the trace log period T is the longest so far, the address at the trace start address C2 of the first main record is copied to the trace start address C3, and the trace of the second main record is performed. The address at the start address C1 is copied to the trace start address C2, and the current main recording address is copied to the trace start address C1.

When such processing is repeated, the recording addresses of the n trace logs can be specified sequentially from the longest to the next long as the trace log having a long trace log period T. Therefore, even when the problem cannot be analyzed with only one trace log of the longest one, it is possible to quickly find and solve the problem part by analyzing the nth trace log. It is also possible to have a configuration in which a plurality of trace memories 11 are provided and addresses are assigned to the respective trace memories 11.

(Embodiment 3)
The program debugging apparatus according to the third embodiment of the present invention is provided with a time measuring device for generating time information to be handled by the update timing controller 6 outside.

FIG. 7 is a block diagram showing the configuration of the program debugging apparatus according to the third embodiment. In FIG. 7, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components. In the present embodiment, a time measuring device 7 is added. The time measuring device 7 is supplied with the event establishment state output from the event controller 2. The time measuring device 7 measures each trace log period (latest) T2, and then, among the measured trace log period (latest) T2, the trace log period (latest) T2 that is the longest at the present time is determined as the trace log period. (Recording) Extracted as T1. Further, the time measuring device 7 determines whether or not the longest trace log period has been updated from the extraction result of the trace log period (record) T1, and further updates the determination result as the longest trace log period update information. Output to the timing controller 6. The update timing controller 6 that receives the longest trace log period update information, based on the received longest trace log period update information, records address (latest) A and record address (previous) B held by the trace memory address manager 5. Control the timing of the mutual copying process. That is, the update timing controller 6 determines whether or not the trace log period (record) T1 is the longest at the current time based on the longest time update information in step S20 of the flowchart of FIG. Other configurations and operations are the same as those in the first embodiment, and thus description thereof is omitted. The basic operation of the program debugging apparatus according to the present embodiment follows the flowcharts of FIGS. 2 and 3 in the case of the first embodiment. The update timing controller 6 can also be realized by a configuration including a time measurement function. The update timing controller 6 can also be realized by a configuration including the event controller 2. The update timing controller 6 can also be realized by a configuration including a time measurement function and the event controller 2.

According to the present embodiment, the program debugging apparatus equipped with the tracing function of the prior art of FIG. 21 corresponds to the addition of the time measurement function, and the conventional program debugging apparatus in terms of resource reuse and the like Easy application deployment

(Embodiment 4)
The program debugging apparatus according to the fourth embodiment of the present invention is configured to perform update timing control based on time information attached to the trace log.

FIG. 8 is a block diagram showing a configuration of the program debugging apparatus according to the fourth embodiment. In FIG. 8, the same reference numerals as those in FIG. 1 in the first embodiment indicate the same components. In the present embodiment, the update timing controller 6 is supplied with a trace log including time information from the CPU 1 and an event establishment state from the event controller 2. The update timing controller 6 determines whether or not the trace log period (record) T1 that is the longest at the present time has been updated based on the supplied event establishment state and the time information of the trace log. Some trace information is supplied to the trace memory address manager 5. The trace memory address manager 5 controls the execution timing of the copying process performed between the recording address (latest) A and the recording address (previous) B based on the supplied trace information. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

FIG. 9 is an example of a trace log accompanied with time information, and individual time information is attached to each trace log. The time information attached to each trace log includes start time information and end time information, respectively. The basic operation of the program debugging apparatus according to the present embodiment follows the flowcharts of FIGS. 2 and 3 in the case of the first embodiment. However, the operation in step S10 in FIG. 3 is changed to the flowchart in FIG.

FIG. 10 is a flow chart for determining whether or not the trace log period (record) T1 is the longest at the present time using the time information of the trace log.

First, the update timing controller 6 notified from the event controller 2 that the temporary recording of the trace log has been started acquires the trace log recording disclosure time information (step S51). Next, the update timing controller 6 notified from the event controller 2 that the temporary recording of the trace log has been completed acquires the recording end time information of the trace log (step S52). Next, the update timing controller 6 calculates a trace log period (latest) T2 from the recording start time information and the recording end time information (step S53). Next, the update timing controller 6 compares the trace log period (latest) T2 calculated this time with the previously calculated trace log period (record) T1, and the trace log period (latest) T2 is the longest at the present time. Whether or not (step S54). Next, when the update timing controller 6 determines that the trace log period T is the longest at the present time, the update timing controller 6 stores the trace log period (latest) T2 at that time as the trace log period (record) T1.

The trace log period (latest) T2 calculated and stored as described above is the trace information (step S55). As described above, in the present embodiment, in step S20 of the flowchart of FIG. 3, it is specifically determined whether or not the trace log period (latest) T2 is the longest at the present time, in the process of step S54 of FIG. Is realized.

Note that even when the time information is not attached to the trace log, it is possible to determine whether or not the trace log period (latest) T2 is the longest at the present time. That is, the update timing controller 6 calculates the trace log period (latest) T2 by detecting the trace log recording start time in the trace memory 11 and further detecting the trace log recording end time. Then, it is determined whether or not the trace log period (latest) T2 calculated in this way is the longest at the present time.

According to the present embodiment, the present invention can be realized even in a program debugging apparatus that does not include the time measuring device 7.

(Embodiment 5)
The program debugging apparatus according to the fifth embodiment of the present invention is configured to perform update timing control based on a trace log and an event.

FIG. 11 is a block diagram showing the configuration of the program debugging apparatus according to the fifth embodiment. In FIG. 11, the same reference numerals as those in FIG. 1 in the first embodiment indicate the same components. In the present embodiment, the update timing controller 6 is supplied with the trace log from the CPU 1 and the event managed by the event controller 2 from the event controller 2. The update timing controller 6 generates event trace information based on the trace log and the event. The event trace information is information indicating whether or not the longest value of the trace log period (latest) T2 has been updated. The update timing controller 6 supplies event trace information to the trace memory address manager 5. The trace memory address manager 5 controls the execution timing of the copying process performed between the recording address (latest) A and the recording address (previous) B based on the supplied event trace information.

Other configurations are the same as those in the first embodiment, and thus description thereof is omitted. The basic operation of the program debugging apparatus of the present embodiment follows the flowcharts of FIGS. 2 and 3 in the first embodiment. However, the operation in step S10 in FIG. 3 is changed to the flowchart in FIG.

FIG. 12 is a flowchart for determining whether or not the trace log period T is the longest at the present time using the trace log and the event. First, compare the supplied trace log with any one event registered in advance as the start event in the trace log period, and record the trace log when the trace log at that time matches the start event. It is determined that the trace log period to be started has started, and time information indicating the event disclosure time is acquired (step S61).

Next, the supplied trace log is compared with any other event registered in advance as an end event in the trace log period, and if the trace log at that time matches the end event, the trace log period Time information indicating the event end time is acquired (step S62).

Next, a trace log period (latest) T2 is calculated based on the event start time information acquired in step S61 and the event end time information acquired in step S62 (step S63).

Next, the calculated trace log period (latest) T2 and the recorded trace log period (previous) T1 are compared to determine whether the trace log period (latest) T2 is the longest at the present time ( Step S64).

Next, the trace log period (latest) T2 determined to be the longest is stored as the trace log period (record) T1 (step S65).

As described above, the processing of steps S10 and S20 (determination of whether the trace log period (latest) T2 is the longest at the present time) in the flowchart of FIG. 3 is performed by the flowchart of FIG. 12 (steps S61 to S65). It can be carried out. Even when the time information is not attached to the trace log, it is possible to determine whether or not the trace log period (latest) T2 is the longest at the present time. That is, the update timing controller 6 calculates the trace log period (latest) T2 by detecting the trace log recording start time in the trace memory 11 and further detecting the trace log recording end time. Then, it is determined whether or not the trace log period (latest) T2 calculated in this way is the longest at the present time.

According to the present embodiment, the present invention can be realized even in a program debugging apparatus that does not include the time measuring device 7.

(Embodiment 6)
The program debugging apparatus according to the sixth embodiment of the present invention includes an update timing mask controller that validates / invalidates the function of the update timing controller 6.

FIG. 13 is a block diagram showing the configuration of the program debugging apparatus according to the sixth embodiment. In FIG. 13, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components. In the present embodiment, an update timing mask controller 8 for setting validity / invalidity for the update control of the recording address (latest) A performed by the update timing controller 6 is added.

When the update timing mask controller 8 determines that the update of the recording address (latest) A is valid, the function of the update timing controller 6 is validated. Conversely, when the update timing controller 6 determines invalid, the function of the update timing controller 6 is invalid. It becomes. Such valid / invalid setting in the update control of the recording address (latest) A is performed by a user operation. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

FIG. 14 is a flowchart showing the operation of manipulating the address of the trace memory 11 in the program debugging apparatus of the sixth embodiment. Step S20 in the flowchart of FIG. 3 in the case of the first embodiment is replaced with step S22. The flowchart of FIG. 2 in the case of the first embodiment follows the present embodiment.

First, when one arbitrary event is established (that is, when it is determined that one traced arbitrary state is equivalent to the registered event), temporary recording of the trace log is started. Furthermore, when another arbitrary event is established (that is, when it is determined that another traced optional state is equivalent to another registered event), the temporary recording of the trace log is terminated. The

In the temporary recording of the trace log executed in this way, the trace memory address manager 5 determines whether the trace log period (latest) T2 is the longest at the present time and the update control of the recording address (latest) A is effective. Determine whether or not. Subsequent processing branches based on this determination (steps S10 and S22).

In step S20, when it is determined that the trace log period (latest) T2 is the longest at the present time and the update control of the recording address (latest) A is valid, the update timing controller 6 determines that the updated recording address ( The latest A is output to the trace memory address manager 5 (step S30). In this process, the updated recording address (latest) A (indicating the memory position on the trace memory 11 in which the trace log of the current measurement in which the trace log period (latest) T2 is determined to be the longest) is recorded is recorded. It is executed so as to be copied to the address (previous) B. As a result of this copying, the recording address (latest) A that is determined to be recorded is registered as the recording address (previous) B.

On the other hand, if it is determined in step S20 that the trace log period (latest) T2 is not the longest at the present time or the update control of the recording address (latest) A is invalid, the update timing controller 6 determines the recording address (previous). The recording address (previous) B is output to the trace memory address manager 5 so that B is copied to the recording address (latest) A (step S40). By this copying, the address is returned and overwriting of the trace log is permitted, so that the temporary recording of the trace log that has just been completed is discarded.

Thus, the operation when the update control of the recording address (latest) A is validated is the same as the flowchart of FIG. On the other hand, when the update control of the recording address (latest) A is invalidated, the recording log (previous) B is always copied to the recording address (latest) A, thereby allowing the trace log to be overwritten. As a result, the temporary recording of the trace log that has just been completed is discarded.

* Immediately after the program is executed, the longest value of the trace log period (latest) T2 is easily updated even if no problem occurs in the program. Therefore, the trace log for which the trace log period (latest) T2 is determined to be the longest value at this time is discarded. According to the present embodiment, when the pattern that reproduces the problem on the software can be specified to some extent, before the pattern to be reproduced appears, by enabling the update control of the recording address (latest) A, Necessary trace logs can be selectively acquired. This makes it possible to quickly find and solve problem areas.

(Embodiment 7)
The program debug apparatus according to the seventh embodiment of the present invention provides an external trigger output that outputs a waveform indicating a state in which the trace log period (latest) T2 is the longest in order to quickly find and solve a problem part in software. Equipped with a bowl.

FIG. 15 is a block diagram showing the configuration of the program debugging apparatus according to the seventh embodiment. In FIG. 15, the same reference numerals as those in FIG. 1 of the first embodiment indicate the same components. The present embodiment further includes an external trigger output unit 9, and the update timing controller 6 further has a function of outputting the update / non-update of the recording address (latest) A to the external trigger output unit 9 as address update information. There is a special feature. The external trigger output unit 9 outputs address update information to the outside with an arbitrary waveform. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

FIG. 16 is a flowchart showing the operation of manipulating the address of the trace memory 11 in the program debugging apparatus of the seventh embodiment. Step S30 in the flowchart of FIG. 3 in the first embodiment is replaced with step S31 of FIG. 16, and step S32 is further added. The flowchart of FIG. 2 in the case of the first embodiment follows the present embodiment.

First, when one arbitrary event is established (that is, when it is determined that one traced arbitrary state is equivalent to the registered event), temporary recording of the trace log is started. Furthermore, when another arbitrary event is established (that is, when it is determined that another traced optional state is equivalent to another registered event), the temporary recording of the trace log is terminated. The

In the temporary recording of the trace log executed in this way, the trace memory address manager 5 determines whether or not the trace log period (latest) T2 is the longest at the present time. Subsequent processing branches based on this determination (steps S10 and S20).

If it is determined in step S20 that the trace log period (latest) T2 is the longest at the present time, the update timing controller 6 outputs the updated recording address (latest) A to the trace memory address manager 5 ( Step S31). This process is recorded by the updated recording address (latest) A (indicating the memory position on the trace memory 11 where the trace log of the current measurement in which the trace log period (latest) T2 is determined to be the longest) is recorded. This is performed so that the address (previous) B is copied. By this copy recording, the recording address (latest) A determined to be recorded is registered as the recording address (previous) B. Next, the external trigger output unit 9 outputs a predetermined waveform corresponding to the address update information (step S32). The operation of the external trigger output device 9 is the point of this embodiment.

On the other hand, if it is determined in step S20 that the trace log period (latest) T2 is not the longest at the present time, the update timing controller 6 causes the recording address (latest) A to be copied by the recording address (previous) B. Then, the recording address (previous) B is output to the trace memory address manager 5 (step S40). By this copying, the address is returned and overwriting of the trace log is permitted, so that the temporary recording of the trace log that has just been completed is discarded.

According to the present embodiment, when the longest value of the trace log period (latest) T2 is updated, the external trigger output device 9 acquires any output waveform (for example, acquired by an oscilloscope) indicating update / non-update of the longest value. Waveform indicating the output state of the actuator, etc.). As a result, the change in the output waveform that occurs when a problem occurs and the trace log are faced and analyzed, so that the problem part can be quickly discovered and solved.

(Embodiment 8)
The program debugging apparatus according to the eighth embodiment of the present invention has a break control for stopping the CPU 1 when the longest value of the trace log period (latest) T2 is updated in order to quickly find and solve a problem part in software. Equipped with a bowl.

FIG. 17 is a block diagram showing the configuration of the program debugging apparatus according to the eighth embodiment. In FIG. 17, the same reference numerals as those in FIG. 1 of the first embodiment denote the same components. The present embodiment is characterized in that it further includes a break controller 10. The update timing controller 6 further includes a function capable of outputting address update information indicating update / non-update of the recording address (latest) A. The break controller 10 is configured to stop the CPU 1 based on the address update information and the state of the CPU 1. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

FIG. 18 is a flowchart showing an operation for manipulating the address of the trace memory 11 in the program debugging apparatus of the eighth embodiment. Step S30 in the flowchart of FIG. 3 in the first embodiment is replaced with step S33 of FIG. 18, and step S34 is further added. The flowchart of FIG. 2 in the case of the first embodiment follows the present embodiment.

First, when one arbitrary event is established (that is, when it is determined that one traced arbitrary state is equivalent to the registered event), temporary recording of the trace log is started. Furthermore, when another arbitrary event is established (that is, when it is determined that another traced optional state is equivalent to another registered event), the temporary recording of the trace log is terminated. The

In the temporary recording of the trace log executed in this way, the trace memory address manager 5 determines whether or not the trace log period (latest) T2 is the longest at the present time. Subsequent processing branches based on this determination (steps S10 and S20).

If it is determined in step S20 that the trace log period (latest) T2 is the longest at the present time, the update timing controller 6 outputs the updated recording address (latest) A to the trace memory address manager 5 ( Step S30). This process is recorded by the updated recording address (latest) A (indicating the memory position on the trace memory 11 where the trace log of the current measurement in which the trace log period (latest) T2 is determined to be the longest) is recorded. This is performed so that the address (previous) B is copied. By this copy recording, the recording address (latest) A determined to be recorded is registered as the recording address (previous) B. Next, the break controller 10 stops the CPU 1 (step S34). The operation of the break controller 10 is the point of this embodiment.

On the other hand, when the trace log period T is not the longest up to now, the update timing controller 6 outputs to the trace memory address manager 5 so as to copy the updated previous recording address B to the current recording address A (step S40). ). By this copying, the address is returned to allow overwriting, and the temporary recording of the trace log that has just been completed is discarded.

On the other hand, if it is determined in step S20 that the trace log period (latest) T2 is not the longest at the present time, the update timing controller 6 causes the recording address (latest) A to be copied by the recording address (previous) B. Then, the recording address (previous) B is output to the trace memory address manager 5 (step S40). By this copying, the address is returned and the overwriting of the trace log is allowed, so that the temporary recording of the trace log that has just been completed is discarded.

According to this embodiment, when the longest value of the trace log period (latest) T2 is updated, the CPU 1 is stopped. As a result, the program can be debugged using the trace log when the longest value of the period (latest) T2 is updated, and the problem location can be obtained by debugging the variable status and the processing status when the problem occurs. Can be quickly discovered and resolved.

(Embodiment 9)
The ninth embodiment of the present invention relates to an emulator system. FIG. 19 is a block diagram showing the configuration of the emulator system 20 and its periphery according to the present invention.

The emulator system 20 includes a host IF circuit 21, an emulation function 22, an emulation ROM / RAM 23, a microcomputer peripheral circuit 24, and the program debug device X according to any one of the first to eighth embodiments described above. The emulator system 20 is connected to a personal computer host and a user target system 40.

The host IF circuit 21 can receive a debug command from the personal computer / host 30 and transmit the debugging state and result to the personal computer / host 30. What is sent includes a trace log.

The program debug device X operates in response to a debug command from the personal computer host 30. The program debug device X includes a CPU 1. The CPU 1 performs emulation using the resources of the emulation function 22, the emulation ROM / RAM 23, and the microcomputer peripheral circuit 24. The program debugging apparatus X performs debugging by controlling the user target system 40 by the microcomputer peripheral circuit 24 during the emulation operation.

The details of the debugging operation by the program debugging device X will be described below. That is, while the emulator system 20 is debugging the user target system 40, the trace log (latest) at the time when the longest value of the trace log period (latest) T2 is updated is acquired as the trace log (record). Then, the obtained trace log (record) is analyzed by the personal computer / host 30 to quickly find and solve the problem part.

The program debugging apparatus of the present invention can effectively narrow down the trace logs related to events that are likely to contain software problems, and record them in the trace memory. This is useful to quickly and easily identify difficult problems.

1 CPU
2 Event controller 3 Trace controller 4 Trace log record confirmation controller 5 Trace memory address manager 6 Update timing controller 7 Time measuring device 8 Update timing mask controller 9 External trigger output device 10 Break controller 11 Trace memory 20 Emulator System 21 Host IF circuit 22 Emulation function 23 Emulation ROM / RAM
24 Microcomputer peripheral circuit 30 PC / host 40 User target system A Current recording address B Previous recording address C Trace start address X Program debug device

Claims (13)

1. A CPU for executing the program;
   After holding an event defining an arbitrary state at the time of execution of the program by the CPU, the process progress at the time of actual program execution by the CPU is compared with the event, and in the process progress based on the comparison result An event controller that determines whether or not a partial progress that defines the start and end of the event is established; and
   A trace memory for recording the partial progress;
   A trace controller for temporarily recording the partial progress determined to be established by the event controller in the trace memory;
   Whether the period from the start of the partial progress to the end at the temporary point at the time of actual program execution is the longest among the groups of the partial progress groups established before that including the temporary point A trace log recording confirmation controller for selecting whether to record the partial progress temporarily recorded in the trace memory at the temporary point based on the determination of
   A program debugging apparatus comprising:
2. The trace log record confirmation controller comprises a trace memory address manager;
   The trace memory address manager sets a recording address (latest) that defines a memory position in the trace memory that stores the partial progress established at the temporary point, and the part established at a time before the temporary point. Set the recording address (previous) that defines the memory location in the trace memory that stores the progress,
   When the trace memory address manager determines that the period is the longest in the group of periods, the trace memory address manager updates the recording address (latest) while determining that the period is not the longest in the group of periods. Then, the recording address (previous) is set to the recording address (latest).
   The program debugging apparatus according to claim 1.
3. When the trace memory address manager determines that the period is the longest in the group of periods, the trace memory address manager copies the updated recording address (latest) to the recording address (previous), and the period is the period. If it is determined that it is not the longest in the group, the recording address (previous) is copied to the recording address (latest).
   The program debugging apparatus according to claim 2.
4. An update timing controller;
   The update timing controller determines the setting timing of the recording address (latest) by the trace memory address manager and the recording address (based on the determination whether the period is the longest in the group of periods. Control the timing of the previous)
   The program debugging apparatus according to claim 2.
5. The trace log record confirmation controller further holds the record address (previous) as a trace start address.
   The program debugging apparatus according to claim 2.
6. When the trace log recording confirmation controller determines that the period is the longest in the group of the periods, it sets the recording address (previous) as the trace start address and then updates the updated recording address (latest ) Is copied to the recording address (previous), and if the period is determined not to be the longest in the group of periods, the recording address (previous) is copied to the recording address (latest).
   The program debug device according to claim 5.
7. A time measuring device,
   The time measuring device generates longest time update information indicating a determination result of whether or not the period is the longest in the group of the periods;
   The update timing controller controls the setting timing of the recording address (latest) and the setting timing of the recording address (previous) by the trace memory address manager based on the longest time update information.
   The program debugging apparatus according to claim 4.
8. The update timing controller determines whether or not the period is the longest in the group of periods based on time information attached to the partial progress.
   The program debugging apparatus according to claim 4.
9. The update timing controller determines whether the period is the longest in the group of periods based on the partial progress and the event.
   The program debugging apparatus according to claim 4.
10. An update timing mask controller;
    The update timing mask controller controls the validity / invalidity of the control operation of the setting timing of the recording address (latest) by the update timing controller.
    The program debugging apparatus according to claim 4.
11. An external trigger output device
    The update timing controller outputs address update information indicating update / non-update of the recording address (latest),
    The external trigger output unit generates and outputs an external trigger composed of an arbitrary waveform signal based on the address update information.
    The program debugging apparatus according to claim 4.
12. A break controller,
    The update timing controller outputs address update information indicating update / non-update of the recording address (latest),
    The break controller stops the operation of the CPU based on the address update information;
    The program debugging apparatus according to claim 4.
13. A host IF circuit that exchanges debugging information with the host computer;
    2. The program debugging according to claim 1, wherein debugging is performed by controlling a user target system based on an instruction of the host computer via the host IF circuit, and transmitting the debugging result to the host computer via the host IF circuit. Equipment,
    Comprising
    Emulator system.

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