WO2010085657A2 - Memory device power managers and methods - Google Patents
Memory device power managers and methods Download PDFInfo
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- WO2010085657A2 WO2010085657A2 PCT/US2010/021820 US2010021820W WO2010085657A2 WO 2010085657 A2 WO2010085657 A2 WO 2010085657A2 US 2010021820 W US2010021820 W US 2010021820W WO 2010085657 A2 WO2010085657 A2 WO 2010085657A2
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- WIPO (PCT)
- Prior art keywords
- memory
- stack
- power state
- memory device
- vault
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3225—Monitoring of peripheral devices of memory devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- Microprocessor technology has evolved at a faster rate than that of semiconductor memory technology.
- a mis-match in performance often exists between the modern host processor and the semiconductor memory subsystem to which the processor is mated to receive instructions and data. For example, it is estimated that some high-end servers idle three out of four clock cycles waiting for responses to memory requests.
- JEDEC Joint Electron Device Engineering Council
- FIG. 1 shows a block diagram of a memory system according to an embodiment of the invention.
- FIG. 2 shows a cut-away conceptual view of a stacked-die 3D memory with a logic die according to an embodiment of the invention.
- FIG. 3 shows a block diagram of a memory vault controller and associated modules according to an embodiment of the invention.
- FIG. 4A shows a method of operating a memory device according to an embodiment of the invention.
- FIG. 4B shows another method of operating a memory device according to an embodiment of the invention.
- FIG. 5 shows a block diagram of an information handling system according to an embodiment of the invention.
- FIG. 1 includes a block diagram of a memory device 100 according to various example embodiments of the current invention.
- the memory device 100 operates to substantially concurrently transfer a plurality of outbound and/or inbound streams of commands, addresses, and/or data between one or more originating devices and/or destination devices (e.g., one or more processors) and a set of stacked-array memory "vaults" 110.
- one or more originating devices and/or destination devices e.g., one or more processors
- a set of stacked-array memory "vaults" 110 e.g., one or more processors
- Multi-die memory array embodiments aggregate control logic that is normally located on each individual memory array die in previous designs. Subsections of a stacked group of dies, referred to in the present disclosure as memory vaults are shown as example vault 110 in Figure 1 and as example vault 230 in Figure 2. The memory vaults shown in the illustrated examples share common control logic. The memory vault architecture strategically partitions memory control logic to increase energy efficiency while providing a finer granularity of powered-on memory banks. Embodiments shown also enable a standardized host processor to memory system interface. The standardized interface may reduce re-design cycle times as memory technology evolves.
- FIG. 2 is a cut-away conceptual view of a stacked-die 3D memory array 200 stacked with a logic die 202 to form a memory device 100 according to various example embodiments.
- the memory device 100 incorporates one or more stacks of memory arrays 203 resulting in the stacked-die 3D memory array 200.
- Multiple memory arrays e.g., the memory array 203 are fabricated onto each of a plurality of dies (e.g., the die 204). The memory array dies are then stacked to form the stacked-die 3D memory array 200.
- Each die of the stack is divided into multiple "tiles" (e.g., the tiles 205 A, 205B, and 205C associated with the stacked die 204).
- Each tile e.g., the tile 205C
- the memory arrays 203 are not limited to any particular memory technology and may include dynamic random-access memory (DRAM), static random access memory (SRAM), flash memory, etc.
- DRAM dynamic random-access memory
- SRAM static random access memory
- flash memory etc.
- a stacked set of memory array tiles 208 may include a single tile from each of the stacked dies (e.g., the tiles 212B, 212C and 212D, with the base tile hidden from view in FIG. 1). Power, address, and/or data and similar common signals may traverse the stacked set of tiles 208 in the "Z" dimension 220 on conductive paths (e.g., the conductive path 224) such as "through- wafer interconnects" (TWIs). It is noted that a TWI need not necessarily pass entirely through a particular wafer or die.
- the stacked-die 3D memory array 200 in one configuration is partitioned into a set of memory "vaults" (e.g., the memory vault 230).
- Each memory vault includes a stacked set of tiles (e.g., the set of tiles 208), one tile from each of a plurality of stacked dies, together with a set of TWIs to electrically interconnect the set of tiles 208.
- Each tile of the vault includes one or more memory arrays (e.g., the memory array 240).
- partitions into individual vaults 230 are described, the 3D memory array 200 can be partitioned in a number of other ways also. Other example partitions include partitioning by dies, tiles, etc.
- a set of memory vaults 102 is illustrated in FIG. 1 in context within the memory device 100.
- the memory device 100 also includes a plurality 104 of memory vault controllers (MVCs) (e.g., the MVC 106). Each MVC is communicatively coupled to a corresponding memory vault (e.g., the memory vault 110 of the set 102) in a one-to-one relationship. Each MVC is thus capable of communicating with a corresponding memory vault independently from communications between other MVCs and their respective memory vaults.
- the memory device 100 also includes a plurality of configurable serialized communication link interfaces (SCLIs) 112.
- SCLIs serialized communication link interfaces
- the SCLIs 112 are divided into an outbound group of SCLIs 113 and an inbound group of SCLIs 115, where "outbound" and “inbound” directions are defined from the perspective of the processor(s) 114.
- Each SCLI of the plurality of SCLIs 112 is capable of concurrent operation with the other SCLIs.
- the SCLIs 112 communicatively couple the plurality of MVCs 104 to one or more host processor(s) 114.
- the memory device 100 presents a multi-link, high- throughput interface to the host processor(s) 114.
- the memory device 100 may also include a switch 116.
- the switch 116 may comprise a matrix switch which might also be referred to as a cross connect switch.
- the switch 116 is communicatively coupled to the plurality of SCLIs 112 and to the plurality of MVCs 104.
- the switch 116 is capable of cross-connecting each SCLI to a selected MVC.
- the host processor(s) 114 may thus access the plurality of memory vaults 102 across the plurality of SCLIs 112 in a substantially simultaneous fashion.
- This architecture can provide high processor-to-memory bandwidth for modern processor technologies, including multi-core technologies.
- the memory device 100 may also include a memory fabric control register 117 coupled to the switch 116.
- the memory fabric control register 117 accepts memory fabric configuration parameters from a configuration source and configures one or more components of the memory device 100 to operate according to a selectable mode.
- the switch 116 and each of the plurality of memory vaults 102 and the plurality of MVCs 104 may normally be configured to operate independently of each other in response to separate memory requests. Such a configuration can enhance memory system bandwidth as a result of the parallelism between the SCLIs 112 and the memory vaults 102.
- the memory device 100 may be reconfigured via the memory fabric control register 117 to cause a subset of two or more of the plurality of memory vaults 102 and a corresponding subset of MVCs to operate synchronously in response to a single request.
- the latter configuration may be used to access a data word that is wider than the width of a data word associated with a single vault. Such a word is herein referred to as a wide data word. This technique may decrease latency.
- Other configurations may be enabled by loading a selected bit pattern into the memory fabric control register 117.
- the outbound SCLIs 113 may include a plurality of outbound differential pair serial paths (DPSPs) 128.
- the DPSPs 128 are communicatively coupled to the host processor(s) 114 and may collectively transport an outbound packet.
- the outbound SCLI 113 may also include a deserializer 130 coupled to the plurality of outbound DPSPs 128.
- the outbound SCLI may also include a demultiplexer 138 communicatively coupled to the deserializer 130.
- the configuration of DSPSs, deserializers, and demultiplexers facilitates efficient transfer of data packets or sub-packets. Similar to the outbound SLCIs, in one embodiment, the inbound SCLIs and a similar configuration of DSPSs, serializers, and multiplexers facilitate efficient transfer of data packets or sub-packets.
- FIG. 3 is a block diagram of an MVC (e.g., the MVC 106) and associated modules according to various example embodiments.
- the MVC 106 may include a programmable vault control logic (PVCL) component 310.
- the PVCL 310 interfaces the MVC 106 to the corresponding memory vault (e.g., the memory vault 110).
- the PVCL 310 generates one or more control signals and/or timing signals associated with the corresponding memory vault 110.
- the PVCL 310 may be configured to adapt the MVC 106 to a memory vault 110 of a selected configuration or a selected technology.
- the memory device 100 may initially be configured using currently- available DDR2 DRAMs.
- the memory device 100 may subsequently be adapted to accommodate DDR3 -based memory vault technology by reconfiguring the PVCL 310 to include DDR3 bank control and timing logic.
- the MVC 106 includes a memory sequencer 314 communicatively coupled to the PVCL 310.
- the memory sequencer 314 performs a memory technology dependent set of operations based upon the technology used to implement the associated memory vault 110.
- the memory sequencer 314 may, for example, perform command decode operations, memory address multiplexing operations, memory address demultiplexing operations, memory refresh operations, memory vault training operations, and/or memory vault prefetch operations associated with the corresponding memory vault 110.
- the memory sequencer 314 may comprise a DRAM sequencer.
- memory refresh operations may originate in a separate refresh controller (not shown).
- the memory sequencer 314 may be configured to adapt the memory device 100 to a memory vault 110 of a selected configuration or technology.
- the memory sequencer 314 may be configured to operate synchronously with other memory sequencers associated with the memory device 100. Such a configuration may be used to deliver a wide data word from multiple memory vaults to a cache line (not shown) associated with the host processor(s) 114 in response to a single cache line request.
- the MVC 106 may also include a write buffer 316.
- the write buffer 316 may be coupled to the PVCL 310 to buffer data arriving at the MVC 106 from the host processor(s) 114.
- the MVC 106 may further include a read buffer 317.
- the read buffer 317 may be coupled to the PVCL 310 to buffer data arriving at the MVC 106 from the corresponding memory vault 110.
- the MVC 106 may also include an out-of-order request queue 318.
- the out-of-order request queue 318 establishes an ordered sequence of read and/or write operations to the plurality of memory banks included in the memory vault 110. The ordered sequence is chosen to avoid sequential operations to any single memory bank in order to reduce bank conflicts and to decrease read-to- write turnaround time.
- the MVC 106 may also include a memory map logic (MML) component 324.
- the MML 324 manages a number of operations such as TWI repair operations using TWI repair logic 328, or other repair operations.
- the MML 324 tracks multiple error data for multiple portions of the 3D memory array 200. A number of different portions can be tracked using the MML 324.
- error data is tracked for each die 204. Other examples include tracking error data for each tile 205, each array 203, etc.
- Figure 3 shows an embodiment including a memory map 315.
- the memory map 315 interacts with the MML 324, keeps track of various memory portions of the 3D memory array 200, and stores characteristics such as error data that is specific to a particular tracked portion.
- Examples include tracking one or more characteristics for individual dies 204, vaults 230, tiles 205, or other groupings of a number of memory cells of the 3D memory array 200.
- error data is discussed as a characteristic that is tracked and used by the memory device 100, the invention is not so limited.
- Other characteristics specific to each memory portion are also tracked in various embodiments. Other characteristics may include, but are not limited to temperature, activity level, power down state, and refresh rate.
- Various characteristic data stored in the memory map 315 can be used in selected embodiments to manage different memory portions of the 3D memory array 200 individually.
- an activity tracker 326 is included to monitor individual levels of activity of multiple memory portions of the 3D memory array 200. Data from the activity tracker 326 is used in one example to change an individual power state of individual memory portions of the 3D memory array 200 such as vaults, dies, tiles, etc.. By reducing a power state of portions not being used, or not being highly utilized, a power efficiency of the memory device 100 is increased.
- each separate activity tracker 326 is used to track an associated vault 230.
- each activity tracker 326 is further used to track portions of each associated vault 230 such as individual tiles 212, etc.
- Figures 1-3 illustrate an embodiment with a plurality of activity trackers 326, other embodiments include different numbers of activity trackers such as a single activity tracker located on the logic chip 202. Having one activity tracker 326 in each MVC 106 facilitates easy monitoring and power regulation of the vault level of granularity.
- Figure 4A illustrates an example method of operation using an activity tracker such as tracker 326.
- individual memory portions are controlled within a stack of memory arrays using a locally attached logic controller such as the MVC 106 shown in Figures 1-3.
- a locally attached logic controller such as the MVC 106 shown in Figures 1-3.
- examples of memory portions include vaults, dies, tiles etc.
- Operation 420 recites monitoring an activity level of each of the number of different memory portions.
- an entire 3D memory array 200 is controlled and monitored, although the invention is not so limited. In other examples, only a portion of a 3D memory array 200 is monitored and operated to regulate power in just the monitored portion.
- a power state of one or more of the portions is changed to correspond to the level of activity of each portion.
- a level of activity is tracked for a length of time, and compared to a threshold length of time. If the threshold is exceeded, then the power state of the portion is changed.
- activity level includes monitoring complete inactivity. If a portion is inactive for a length of time exceeding the threshold, then the power state of the portion is changed.
- Monitoring and managing power levels using an activity tracker 326 or other local logic within the logic chip 202 allows the memory device 100 to provide power efficiency independent of the processor 114. A number of levels of power states are possible using the discussed configurations.
- the simplest power levels include power to a memory portion such as a memory vault 230 being fully on, or fully off. In one embodiment, a number of intermediary power levels are also included. In one example, a portion such as a memory vault 230 is powered on, but without any refresh signals being sent to that portion. In one example, a refresh rate is increased or reduced depending on a level of activity of the memory portion. In one example, other support circuitry such as data links between the memory portion and the processor are powered down or up based on a level of activity of the memory portion. Data link examples include the SCLIs 112 shown in Figure 1, and discussed above. In addition to the individual component examples listed above, combinations of components can be powered up or down in selected embodiments.
- FIG. 4B illustrates a method where in operation 440, a packet command is received from a host processor such as processor 114 to change a power state of a memory vault of a stack of memory arrays such as vault 230. In operation 450, the packet command is implemented using a logic controller that is locally attached to the stack of memory arrays.
- a locally attached logic controller includes MVC 106.
- any of the above examples of power state options can be controlled by a packet command sent to the MVC 106.
- One specific example includes changing a refresh rate of a vault 230 upon receipt of a packet command to an MVC 106 as a result of changing activity within the vault 230.
- Another example of a packet command includes powering a selected MVC 106 on or off.
- Another example of a packet command includes powering a selected SCLI on or off.
- Selected system embodiments include a memory device such as device 100, coupled to multiple processors such as a multi-core processor.
- a portion of the memory device 100 is directly associated with a corresponding processor or processor core.
- the corresponding portion of the memory device 100 is also powered down. For instance a vault 230 is powered down when an associated processor or processor core is powered down. Likewise when a processor or processor core is powered to a higher level, the associated vault or other memory portion is powered to a higher state.
- an activity tracker such as tracker 326 from Figure 3 monitors an associated processor or processor core, and local logic on logic die 202 powers the memory portion up or down.
- a packet command is sent from the processor or processor core as it changes processor power state.
- the local logic on the logic die 202 then responds and changes a power state of the portion of the memory device accordingly.
- the apparatus and systems of various embodiments may be useful in applications other than a high-density, multi-link, high-throughput semiconductor memory subsystem. Thus, various embodiments of the invention are not so limited.
- the illustrations of the memory device 100 are intended to provide a general understanding of the structure of various embodiments. They are not intended to serve as a complete description of all the elements and features of apparatus and systems that can use the structures described herein.
- systems are described in the present disclosure that include 3D memory devices and processors.
- Examples of such systems include, but are not limited to televisions, cellular telephones, personal data assistants (PDAs), personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.
- PDAs personal data assistants
- personal computers e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.
- workstations e.g., radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.
- MP3 Motion Picture Experts Group, Audio Layer 3
- information handling system 500 comprises a data processing system that includes a system bus 502 to couple the various components of the system.
- System bus 502 provides communications links among the various components of the information handling system 500 and may be implemented as a single bus, as a combination of busses, or in any other suitable manner.
- Chip assembly 504 is coupled to the system bus 502.
- Chip assembly 504 may include any circuit or operably compatible combination of circuits.
- chip assembly 504 includes a processor 508 or multiple processors that can be of any type.
- processor means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit.
- DSP digital signal processor
- processor includes multiple processors or multiple processor cores.
- a memory device 506 is included in the chip assembly 504.
- a memory device such as a DRAM is one example of such a memory device 506.
- One example of a DRAM device includes a stacked memory chip 3D memory device with an integrated logic chip as described in embodiments above.
- Memory 506 can also include non-volatile memory such as flash memory.
- Information handling system 500 may also include an external memory
- 511 which in turn can include one or more memory elements suitable to the particular application, such as one or more hard drives 512, and/or one or more drives that handle removable media 513 such as flash memory drives, compact disks (CDs), digital video disks (DVDs), and the like.
- Information handling system 500 may also include a display device 509 such as a monitor, additional peripheral components 510, such as speakers, etc. and a keyboard and/or controller 514, which can include a mouse, trackball, game controller, voice-recognition device, or any other device that permits a system user to input information into and receive information from the information handling system 500.
- a display device 509 such as a monitor
- additional peripheral components 510 such as speakers, etc.
- a keyboard and/or controller 514 which can include a mouse, trackball, game controller, voice-recognition device, or any other device that permits a system user to input information into and receive information from the information handling system 500.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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EP10733911.1A EP2389633B1 (en) | 2009-01-23 | 2010-01-22 | Memory device power managers and methods |
EP17164770.4A EP3223281B1 (en) | 2009-01-23 | 2010-01-22 | Memory device power managers and methods |
CN201080005310.2A CN102292715B (en) | 2009-01-23 | 2010-01-22 | Memory device power managers and methods |
JP2011548138A JP5762312B2 (en) | 2009-01-23 | 2010-01-22 | Memory device power management device and method |
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US12/359,039 | 2009-01-23 | ||
US12/359,039 US9105323B2 (en) | 2009-01-23 | 2009-01-23 | Memory device power managers and methods |
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WO2010085657A2 true WO2010085657A2 (en) | 2010-07-29 |
WO2010085657A3 WO2010085657A3 (en) | 2010-10-21 |
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PCT/US2010/021820 WO2010085657A2 (en) | 2009-01-23 | 2010-01-22 | Memory device power managers and methods |
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EP (2) | EP2389633B1 (en) |
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CN (2) | CN102292715B (en) |
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WO (1) | WO2010085657A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9105323B2 (en) | 2009-01-23 | 2015-08-11 | Micron Technology, Inc. | Memory device power managers and methods |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7978721B2 (en) * | 2008-07-02 | 2011-07-12 | Micron Technology Inc. | Multi-serial interface stacked-die memory architecture |
US7929368B2 (en) * | 2008-12-30 | 2011-04-19 | Micron Technology, Inc. | Variable memory refresh devices and methods |
US8127185B2 (en) | 2009-01-23 | 2012-02-28 | Micron Technology, Inc. | Memory devices and methods for managing error regions |
US8018752B2 (en) | 2009-03-23 | 2011-09-13 | Micron Technology, Inc. | Configurable bandwidth memory devices and methods |
US8612809B2 (en) * | 2009-12-31 | 2013-12-17 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
US9123552B2 (en) | 2010-03-30 | 2015-09-01 | Micron Technology, Inc. | Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same |
US8547769B2 (en) * | 2011-03-31 | 2013-10-01 | Intel Corporation | Energy efficient power distribution for 3D integrated circuit stack |
WO2013003029A2 (en) | 2011-06-29 | 2013-01-03 | Rambus Inc. | Multi-element memory device with power control for individual elements |
KR101915073B1 (en) * | 2011-12-20 | 2018-11-06 | 인텔 코포레이션 | Dynamic partial power down of memory-side cache in a 2-level memory hierarchy |
CN104011620B (en) * | 2011-12-21 | 2017-07-07 | 英特尔公司 | Power management in separate memory part |
DE112011106009T5 (en) * | 2011-12-23 | 2014-12-18 | Intel Corp. | Isolated microchannel voltage domains in stacked memory architecture |
US9026808B2 (en) * | 2012-04-26 | 2015-05-05 | Freescale Semiconductor, Inc. | Memory with word level power gating |
US9317087B2 (en) | 2012-04-26 | 2016-04-19 | Ravindraraj Ramaraju | Memory column drowsy control |
US20140082385A1 (en) * | 2012-09-14 | 2014-03-20 | Curtis G. Reule | On demand power management for solid-state memory |
US10042750B2 (en) | 2013-03-15 | 2018-08-07 | Micron Technology, Inc. | Apparatuses and methods for adaptive control of memory using an adaptive memory controller with a memory management hypervisor |
WO2014200508A1 (en) * | 2013-06-14 | 2014-12-18 | Intel Corporation | Methods and apparatus to provide power to devices |
US9147438B2 (en) * | 2013-10-23 | 2015-09-29 | Qualcomm Incorporated | Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components, related systems and methods |
US9959936B1 (en) * | 2014-03-12 | 2018-05-01 | Marvell International Ltd. | Temperature-based memory access |
US10289604B2 (en) * | 2014-08-07 | 2019-05-14 | Wisconsin Alumni Research Foundation | Memory processing core architecture |
US10303235B2 (en) | 2015-03-04 | 2019-05-28 | Qualcomm Incorporated | Systems and methods for implementing power collapse in a memory |
US10117196B2 (en) * | 2015-08-26 | 2018-10-30 | Qualcomm Incorporated | Dynamically configurable apparatus for operating within the current capabilities of the power source |
US11487445B2 (en) * | 2016-11-22 | 2022-11-01 | Intel Corporation | Programmable integrated circuit with stacked memory die for storing configuration data |
US10353455B2 (en) | 2017-07-27 | 2019-07-16 | International Business Machines Corporation | Power management in multi-channel 3D stacked DRAM |
EP3580691B1 (en) * | 2017-08-31 | 2020-07-01 | FotoNation Limited | A peripheral processing device |
TWI659308B (en) * | 2017-12-08 | 2019-05-11 | 旺宏電子股份有限公司 | Memory device and operation method thereof |
KR20220030348A (en) | 2020-08-27 | 2022-03-11 | 삼성전자주식회사 | Memory device |
CN116324707A (en) * | 2020-09-18 | 2023-06-23 | 拉姆伯斯公司 | Method and circuit for aggregating processing units and dynamically allocating memory |
US11741043B2 (en) * | 2021-01-29 | 2023-08-29 | The Trustees Of Dartmouth College | Multi-core processing and memory arrangement |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050125701A1 (en) | 2003-12-03 | 2005-06-09 | International Business Machines Corporation | Method and system for energy management via energy-aware process scheduling |
US20070011421A1 (en) | 2005-07-07 | 2007-01-11 | Keller Thomas W Jr | Method and system for decreasing power consumption in memory arrays having usage-driven power management |
WO2008063251A2 (en) | 2006-07-31 | 2008-05-29 | Metaram, Inc. | Memory circuit system and method |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5197140A (en) * | 1989-11-17 | 1993-03-23 | Texas Instruments Incorporated | Sliced addressing multi-processor and method of operation |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Integrated circuit i/o using a high performance bus interface |
US5396635A (en) * | 1990-06-01 | 1995-03-07 | Vadem Corporation | Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system |
US5524248A (en) * | 1993-07-06 | 1996-06-04 | Dell Usa, L.P. | Random access memory power management system |
US6079024A (en) * | 1997-10-20 | 2000-06-20 | Sun Microsystems, Inc. | Bus interface unit having selectively enabled buffers |
JPH11161778A (en) * | 1997-11-26 | 1999-06-18 | Ricoh Co Ltd | Digital picture processing system |
DE69827589T2 (en) * | 1997-12-17 | 2005-11-03 | Elixent Ltd. | Configurable processing assembly and method of using this assembly to build a central processing unit |
US6125429A (en) * | 1998-03-12 | 2000-09-26 | Compaq Computer Corporation | Cache memory exchange optimized memory organization for a computer system |
US20020124195A1 (en) * | 1998-11-04 | 2002-09-05 | Puthiya K. Nizar | Method and apparatus for power management in a memory subsystem |
JP2000222285A (en) | 1999-01-29 | 2000-08-11 | Matsushita Electric Ind Co Ltd | Memory power managing device |
US6141283A (en) * | 1999-04-01 | 2000-10-31 | Intel Corporation | Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state |
JP2001035146A (en) | 1999-07-22 | 2001-02-09 | Hitachi Ltd | Semiconductor memory device |
KR100603926B1 (en) * | 1999-10-25 | 2006-07-24 | 삼성전자주식회사 | Power supply control circuit for computer system having a plurality of power management states and control method of the same |
US6691237B1 (en) * | 2000-08-08 | 2004-02-10 | Dell Products, L.P. | Active memory pool management policies |
US6618791B1 (en) * | 2000-09-29 | 2003-09-09 | Intel Corporation | System and method for controlling power states of a memory device via detection of a chip select signal |
US7089436B2 (en) * | 2001-02-05 | 2006-08-08 | Morpho Technologies | Power saving method and arrangement for a configurable processor array |
US7028200B2 (en) * | 2002-05-15 | 2006-04-11 | Broadcom Corporation | Method and apparatus for adaptive power management of memory subsystem |
JP3962924B2 (en) * | 2003-03-20 | 2007-08-22 | セイコーエプソン株式会社 | Semiconductor device, semiconductor circuit, electronic device, and clock supply control method |
US7428644B2 (en) * | 2003-06-20 | 2008-09-23 | Micron Technology, Inc. | System and method for selective memory module power management |
JP2005018740A (en) * | 2003-06-23 | 2005-01-20 | Samsung Electronics Co Ltd | Electronic device |
US7085152B2 (en) | 2003-12-29 | 2006-08-01 | Intel Corporation | Memory system segmented power supply and control |
US7064994B1 (en) * | 2004-01-30 | 2006-06-20 | Sun Microsystems, Inc. | Dynamic memory throttling for power and thermal limitations |
JP4205613B2 (en) | 2004-03-01 | 2009-01-07 | エルピーダメモリ株式会社 | Semiconductor device |
US7307338B1 (en) * | 2004-07-26 | 2007-12-11 | Spansion Llc | Three dimensional polymer memory cell systems |
DE102004047752B3 (en) | 2004-09-30 | 2006-01-26 | Infineon Technologies Ag | Semiconductor component with temperature sensor |
US9384818B2 (en) * | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
US20060258354A1 (en) * | 2005-05-13 | 2006-11-16 | Ul Haq Tanveer | Method for restricting mobility in wireless mobile systems |
US7444526B2 (en) * | 2005-06-16 | 2008-10-28 | International Business Machines Corporation | Performance conserving method for reducing power consumption in a server system |
JP2008544437A (en) | 2005-06-24 | 2008-12-04 | メタラム インコーポレイテッド | Integrated memory core and memory interface circuit |
US7464225B2 (en) | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
US7827190B2 (en) | 2006-12-08 | 2010-11-02 | Pandya Ashish A | Complex symbol evaluation for programmable intelligent search memory |
EP2102867B1 (en) * | 2006-12-14 | 2013-07-31 | Rambus Inc. | Multi-die memory device |
US7930576B2 (en) * | 2007-04-10 | 2011-04-19 | Standard Microsystems Corporation | Sharing non-sharable devices between an embedded controller and a processor in a computer system |
US20080270811A1 (en) * | 2007-04-26 | 2008-10-30 | Super Talent Electronics Inc. | Fast Suspend-Resume of Computer Motherboard Using Phase-Change Memory |
US8645740B2 (en) * | 2007-06-08 | 2014-02-04 | Apple Inc. | Methods and systems to dynamically manage performance states in a data processing system |
US9105323B2 (en) | 2009-01-23 | 2015-08-11 | Micron Technology, Inc. | Memory device power managers and methods |
-
2009
- 2009-01-23 US US12/359,039 patent/US9105323B2/en active Active
-
2010
- 2010-01-22 TW TW099101838A patent/TWI514409B/en active
- 2010-01-22 KR KR1020117019440A patent/KR101609311B1/en active IP Right Grant
- 2010-01-22 WO PCT/US2010/021820 patent/WO2010085657A2/en active Application Filing
- 2010-01-22 TW TW106114950A patent/TWI628665B/en active
- 2010-01-22 TW TW104136077A patent/TWI590255B/en active
- 2010-01-22 EP EP10733911.1A patent/EP2389633B1/en active Active
- 2010-01-22 EP EP17164770.4A patent/EP3223281B1/en active Active
- 2010-01-22 JP JP2011548138A patent/JP5762312B2/en active Active
- 2010-01-22 CN CN201080005310.2A patent/CN102292715B/en active Active
- 2010-01-22 CN CN201510124635.7A patent/CN104699226B/en active Active
-
2015
- 2015-05-08 JP JP2015095403A patent/JP6041928B2/en active Active
- 2015-08-07 US US14/821,005 patent/US9583157B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050125701A1 (en) | 2003-12-03 | 2005-06-09 | International Business Machines Corporation | Method and system for energy management via energy-aware process scheduling |
US20070011421A1 (en) | 2005-07-07 | 2007-01-11 | Keller Thomas W Jr | Method and system for decreasing power consumption in memory arrays having usage-driven power management |
WO2008063251A2 (en) | 2006-07-31 | 2008-05-29 | Metaram, Inc. | Memory circuit system and method |
Non-Patent Citations (1)
Title |
---|
See also references of EP2389633A4 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9105323B2 (en) | 2009-01-23 | 2015-08-11 | Micron Technology, Inc. | Memory device power managers and methods |
US9583157B2 (en) | 2009-01-23 | 2017-02-28 | Micron Technology, Inc. | Memory device power managers and methods |
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US9105323B2 (en) | 2015-08-11 |
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