WO2010082604A1

WO2010082604A1 - Data processing device, method of memory management, and memory management program

Info

Publication number: WO2010082604A1
Application number: PCT/JP2010/050349
Authority: WO
Inventors: 雅規上久保
Original assignee: 日本電気株式会社
Priority date: 2009-01-14
Filing date: 2010-01-14
Publication date: 2010-07-22
Also published as: JPWO2010082604A1

Abstract

Disclosed is a data processing device that improves efficiency in memory usage with a scarce processor resource, and reduces device costs. A data processing device (1), comprising a unit that temporarily stores and processes variable length data in a memory region, further comprises fixed length block management unit, which allocates and releases a fixed length block (31 – 3N) of the memory region, and a data storage region management unit (13), which maintains and releases a storage region (61 – 6M), which stores variable length data within the fixed length block, wherein the data storage region management unit further comprises a query counter preservation module (13a), which preserves a storage region quantity on a per fixed length block basis, an empty region pointer preservation module (13b), which preserves address information that denotes an end of a storage region, and a data storage region setting module (13c), which sequentially maintains and releases the fixed length data storage regions in order by the address information.

Description

Data processing apparatus, memory management method, and memory management program

The present invention relates to a technology for securing and releasing a data storage area in dynamic memory management on a data processing device, and in particular, securing and releasing an area for temporarily storing a communication frame on a memory of a communication device. Regarding technology.

A data processing apparatus that performs software processing using a processor and a memory needs a mechanism for managing a data storage area on the memory. This method of managing the data storage area on the memory can be classified according to the memory securing procedure, and can be considered in three ways: static memory management, automatic memory management, and dynamic memory management.

Static memory management is a method of allocating data areas at the stage of compiling a program before system startup. In the static memory management method, the allocation of the data storage area is not changed while the program is operating on the system. The merit of the static memory management method is that the memory management during operation is unnecessary, so the memory management load by the processor is very light. Since it cannot be deleted, it is suitable for holding system variables, but it is not suitable for storing user variables and data.

Automatic memory management is a method for securing and releasing memory areas on the call stack. The call stack is generated as an automatic variable area used in the function when the function call is executed, and is discarded when the function execution ends. Since it is not necessary to explicitly secure and release the area at the user level, the area is discarded when the function execution ends, and a memory leak due to the area release omission is less likely to occur.

Dynamic memory management is a memory management method in which a user explicitly secures or releases a memory area on an unused memory area called a heap area. In the dynamic memory management method, an explicit data area is secured at an arbitrary timing during program execution, and the secured data area is held on the heap area until an explicit release operation is executed from the program. Is done. In particular, dynamic memory management is often performed in a memory that temporarily stores communication frames in a communication device.

When storing communication frames temporarily in the memory, storage areas corresponding to individual communication frames are secured in the heap area by dynamic memory management. This is because the processing performed on a communication frame in a communication device is usually complicated processing, and in addition to being processed across multiple functions, it is necessary to hold communication at a certain time. This is also because the number of frames is indefinite.

There are two methods for determining the size of each data storage area when performing dynamic memory management: fixed-length allocation and variable-length allocation. In the fixed-length allocation, the heap area is divided into two or more fixed-length blocks of the same size, and the use and non-use are managed in accordance with a request for securing a memory area by a program in units of the fixed-length block. On the other hand, variable length allocation is a method of securing a data area by cutting it out from the heap area in accordance with the size required by the program.

Fixed length allocation is excellent in terms of low processing load for managing memory areas. This is because most of the fixed-length blocks that become free areas have the same size, so that most of the search and determination processing for determining which free area is used to secure the next data storage area can be simplified. Therefore, this is an allocation method that is often used in devices in which the computing power of the processor is limited by cost requirements. However, since the area can be secured only with a predetermined size, the remainder of subtracting the size of the required data area from the size of the fixed-length area becomes a useless area that is not used, so the data has a fixed length Except for the above, it is not necessarily a method with high memory use efficiency.

On the other hand, variable-length allocation is an allocation method that attempts to secure only the area required for data storage from the heap area, and therefore, an unused area is generated for the area allocated to each data. Hateful. However, when securing and releasing the data storage area are repeated to some extent, unequal length free areas called fragments are scattered, and the next time the data storage area is to be secured, the process for searching for an appropriate free area is performed. It tends to be complicated. Further, even if there is a sufficient difference between the total heap size and the total used area, if each free area is small, a state where a new data storage area cannot be secured may occur.

For this reason, variable-length allocation is often used in systems that are relatively versatile and have sufficient processing capacity of the processor. In a device such as a communication processing device, it is necessary to suppress the processing capacity of the processor as much as possible from the viewpoint of cost reduction, and there is a tendency to use a fixed length allocation that can relatively suppress the amount of processing for memory management by the processor.

Patent Document 1 describes a memory management method using a fixed-length heap area, although the target is an image forming apparatus. Specifically, in the memory area management method disclosed in Patent Document 1, when a plurality of fixed-length heap areas are used to secure a plurality of fixed-size areas in advance and the area is insufficient When a part of the variable-length heap area is used as a fixed-length area, and the size and number of data to be stored in the heap area at a certain time can be estimated in advance using these blocks, A fixed-length allocation that manages a plurality of data storage areas of the same size side by side simultaneously achieves high memory usage efficiency and low processing load.

Patent Document 2 describes a dynamic memory management method using variable length allocation. Specifically, in the memory area management method disclosed in Patent Document 2, a memory pool that is a heap area is divided in advance into a plurality of areas called sub-pools, and data storage is performed when a data storage area is secured. The search time is shortened by changing the order in which a plurality of subpools are searched for each required size. Patent Document 2 states that as the allocation is repeated, a data storage area of the same size is easily assigned to a predetermined address, and an optimum empty space can be easily obtained at an early stage when searching for the position. .

In other words, in Patent Document 2, the data size used as the threshold value in each sub-pool size and search pattern is a parameter for which an optimum value should be set in accordance with the size and number of data to be stored during operation. When the data size and number distribution are known in advance, it is possible to increase the memory usage efficiency.

Japanese Patent Application Laid-Open No. 2003-228561 discloses a technique for dividing a data area of a memory into a plurality of basic blocks, and further subdividing the basic blocks into a plurality of small blocks having an arbitrary size to efficiently use a storage area. Is described. Patent Document 4 describes a technique in which when writing swath data in a buffer, the write pointer is sequentially moved and the swath data is written in the next buffer following the last position of the previous swath data. Patent Document 5 describes a technique of managing writing using a FIFO block register and an EMPTY bit when writing data as a FIFO block in a buffer.

Japanese Patent Laid-Open No. 11-110281 Japanese Patent Laid-Open No. 2003-196152 JP 2001-265628 A JP 2002-137457 A JP 2004-030196 A

Since it is necessary to reduce the capacity of the memory device to be implemented and the amount of processing resources of the processor due to cost requirements, when securing the communication frame storage area in the communication device, the memory usage is minimized to the necessary heap area. While increasing efficiency, it is necessary to minimize the amount of processing required for dynamic memory management. For this reason, in dynamic memory management, it is desirable to achieve both the low processing load characteristic of fixed-length allocation and the high memory usage efficiency of dynamic memory allocation. For this purpose, it is desirable to arrange the data storage areas as close as possible in one direction in ascending order of time so as not to create a so-called fragment state.

The total amount of communication frames being processed by the communication device at a certain time is determined to be almost constant from the maximum communication bandwidth and the residence time of the communication frame according to the specifications. However, the size of each communication frame is variable, and the number of communication frames that must be temporarily stored is not constant. The reason is that each application on the upper layer of the communication protocol transmits / receives an optimal communication frame. When multiple different types of applications are communicating at the same time on a single physical communication path, communication frames of different sizes and average bandwidths are sent and received within the logical channel used by the connection established by each application. Because it is.

In the methods disclosed in

Patent Documents

1 and 2 in which the size and bandwidth of a communication frame need to be predicted with a relatively high accuracy in advance, such characteristics for each logical channel, that is, the size and number of communication frames are determined. It is difficult to make the above-mentioned cost requirements compatible by applying to communication equipment that handles a plurality of logical channels with different combinations.

Furthermore, it is desirable that the memory device capacity that must be physically prepared is constant even if the characteristics of the logical channel change. If the heap size to be prepared varies greatly depending on the communication conditions, a memory device must be prepared for the maximum variation, which is disadvantageous in terms of cost when considering the average usage state. is there.

In the method according to Patent Document 1, when there is a bias in the communication frame size handled during actual processing with respect to individual fixed-length heap areas prepared in advance, only the unused fixed-length area is stored in the memory area. Waste occurs. In order to compensate for this, a variable-length heap area is consumed, and an extra variable-length heap area must be prepared in advance, which is disadvantageous in terms of cost.

The configurations that solve the problems of

Patent Documents

1 and 2 described above are not described in any of Patent Documents 3 to 5.

An object of the present invention is a data processing apparatus that temporarily stores data such as communication frames in a memory and processes the data, and the data that makes it possible to increase the memory use efficiency and reduce the apparatus cost with a small number of processor resources. A processing device, a memory management method, and a memory management program are provided.

In order to achieve the above object, a data processing apparatus according to the present invention is a data processing apparatus including a unit that temporarily stores and processes variable-length data in a heap area on a memory. A fixed-length block management unit that allocates and releases fixed-length blocks and a data storage area management unit that secures and releases storage areas for storing variable-length data in fixed-length blocks. The data storage area management unit is fixed A reference counter holding module that holds the number of storage areas for each long block, a free area pointer holding module that holds address information indicating the end of the storage area, and a storage area for variable-length data in this address information order and release. And a data storage area setting module.

In order to achieve the above object, a memory management method according to the present invention is a data processing apparatus including a unit that temporarily stores and processes variable-length data in a heap area on a memory, and is variable on the memory. A memory management method for securing a storage area for storing long data, wherein the data storage area setting module reads address information indicating the end of the storage area from the free area pointer holding module, and the data storage area setting module in the order of the address information Sequentially reserve storage areas for variable length data, and the data storage area setting module stores variable length data in the reserved storage areas.

To achieve the above object, a memory management program according to the present invention is a data processing apparatus having a unit for temporarily storing and processing variable length data in a heap area on a memory, and holding a free area pointer. A function for the data storage area setting module to read address information indicating the end of the storage area from the module, a function for the data storage area setting module to sequentially secure a storage area for variable-length data in the order of this address information, and a reserved storage area The data storage area setting module causes the computer to execute a function of storing variable length data.

Since the present invention is configured to secure a new data storage area following the address indicated by the free area pointer in the memory area as described above, the data storage area can be secured with a small amount of calculation that does not place a heavy load on the processor. Can be arranged close to one direction in the order of time, and it is difficult to generate a fragment state. Therefore, it is possible to increase the memory usage efficiency and reduce the apparatus cost with a small number of processor resources.

It is explanatory drawing which shows the structure of the communication apparatus which concerns on the 1st Embodiment of this invention. FIG. 2 is an explanatory diagram illustrating a configuration of a storage area on a RAM (Random Access Memory) illustrated in FIG. 1. FIG. 2A shows a state where a heap area is secured on the RAM. FIG. 2B shows a state in which the fixed-length block management unit has secured N (N is an integer) fixed-length blocks on the heap area. FIG. 2C shows a state in which the data storage area setting module has secured the data storage area on the fixed-length block. 3 is a flowchart showing an operation when the data storage area management unit shown in FIG. 1 stores new data in a RAM. FIG. 4 is a flowchart showing an operation of securing a new fixed-length block by the fixed-length block management unit shown as step S202 in FIG. 3. FIG. 3 is a flowchart showing an operation in which the fixed-length block management unit and the data storage area management unit shown in FIG. 2 release a data storage area that is no longer needed. FIG. 3 is an explanatory diagram showing time transitions for securing and releasing a data storage area on the RAM shown in FIGS. It is explanatory drawing which shows the structure of the memory area on RAM in the 2nd Embodiment of this invention. FIG. 7A shows a state where a heap area is secured on the RAM. FIG. 7B shows a state in which the fixed-length block management unit has secured N (N is an integer) fixed-length blocks on the heap area. FIG. 7C shows a state where the data storage area setting module secures the data storage area on the fixed-length block.

(First embodiment)
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
First, the basic content of the present embodiment will be described, and then more specific content will be described.
The data processing apparatus according to the present embodiment is a data processing apparatus that includes a unit (CPU 10) that temporarily stores and processes variable-length data in a memory area (RAM 11). The fixed-length block management unit 12 that allocates and releases 31 to 3N (N is a natural number) and the storage areas 61 to 6M (M is a natural number) that stores variable-length data in the fixed-length blocks 31 to 3N are secured and released. And a data storage area management unit 13.
The data storage area management unit 13 includes a reference counter holding module 13a that holds the number of storage areas for each of the fixed-length blocks 31 to 3N, and a free area pointer holding module 13b that holds address information indicating the end of the storage area. And a data storage area setting module 13c for sequentially securing variable length data storage areas 61 to 6M in the order of the address information. The fixed length management unit 12 and the data storage area management unit 13 are constructed on software by the CPU executing a program, and these functions are implemented on the software. Further, the reference counter holding module 13a, the free area pointer holding module 13b, and the data storage area setting module 13c provided in the data storage area management unit 13 are constructed on software by the CPU executing a program. These functions are realized on software. A program for realizing the functions of the fixed length management unit 12 and the data storage area management unit 13, the functions of the reference counter holding module 13a, the free area pointer holding module 13b, and the data storage area setting module 13c on software is a recording medium. And is subject to commercial transactions.

Here, when the data storage area setting module 13c secures the variable length data storage areas 61 to 6M, the value held by the free area pointer holding module 13b is used as the head address and the end of the fixed length block to which the address belongs. A storage area setting function that uses a free area between them as a storage area, and a capacity determination function that determines whether the capacity of the free area is insufficient with respect to the capacity to be secured as the storage area. The fixed-length block management unit 12 has a new allocation function for newly allocating fixed-length blocks 31 to 3N when it is determined that the free space capacity is insufficient.

Further, the data storage area setting module 13c, when releasing the storage area, checks the reference counters 51 to 5N on the fixed-length block to which the released storage area belongs, and the reference of the storage area. When the counter value is 0 and the address pointed to by the free area pointer 42 does not indicate the fixed-length block, there is an unused block determination function that determines that the fixed-length block is not used. The fixed-length block management unit 12 has an unused block release function that releases the fixed-length block when the data storage area setting module 13c determines that the fixed-length block is not used.

Here, an unused area (unused heap area 41) that is not allocated as a fixed-length block in the memory area is managed as a management queue. The variable length data stored in the storage areas 61 to 6M is a communication frame or a communication packet. In the following description, the memory area is described as a heap area.

By providing this configuration, the present embodiment makes it difficult to generate a fragment state by arranging data storage areas close to each other in the order of time when a data storage area is secured with a small amount of calculation. Therefore, it is possible to increase the memory usage efficiency and reduce the apparatus cost with a small number of processor resources.
Hereinafter, this will be described in more detail.

FIG. 1 is an explanatory diagram showing the configuration of the communication device 1 according to the first embodiment of the present invention. The communication device 1 includes a processor 10 that controls the operation of the apparatus, a RAM (Random Access Memory) 11 that is one of the devices controlled by the processor 10, and a communication device 14 that transmits and receives communication packets. The communication device 14 includes many devices such as a modulator, an oscillator, a demodulator, an input / output device, etc., but it is not particularly necessary to refer to them in detail in explaining the present invention.

When the processor 10 receives the communication packet, the processor 10 temporarily writes the data of the packet in the RAM 11, performs processing on the packet by the communication device 14, and erases the packet when the processing is completed. When the processor 10 writes data to the RAM 11, the data to be stored and the address to store the data are transmitted to the RAM 11. When reading data from the RAM 11, a read command and a read source address are transmitted to the RAM 11.

When the processor 10 executes the program, a fixed-length block management unit 12 that secures and releases a fixed-length block (to be described later) on the RAM 11 and a data storage area management unit 13 that secures and releases a data storage area on the fixed-length block. And operate on software. The fixed-length block management unit 12 and the data storage area management unit 13 perform all operations related to securing and releasing the storage area described below based on the functions of the processor 10 and the OS (operation system, not shown). be able to.

The data storage area management unit 13 further holds a reference counter holding module 13a that holds the number of storage areas (reference counter value) for each fixed-length block, and address information (free area pointer 42) indicating the end of the storage area. The function module is divided into an empty area pointer holding module 13b and a data storage area setting module 13c that sequentially reserves variable length data storage areas in the order of address information indicated by the empty area pointer 42. These operations will be described later.

FIG. 2 is an explanatory diagram showing the configuration of the storage area on the RAM 11 shown in FIG. FIG. 2A shows a state in which the heap area 21 is secured on the RAM 11. FIG. 2B shows a state in which the fixed-length block management unit 12 has secured N fixed-length blocks 31 to 3N (N is an integer) on the heap area 21. An area other than the fixed-length blocks 31 to 3N becomes an unused heap area 41. FIG. 2C shows a state in which the data storage area setting module 13c secures the data storage areas 61 to 6M (M is an integer) on the fixed-length blocks 31 to 3N. Due to communication specifications, the data length of each of the data storage areas 61 to 6M is variable. The area indicated by “K” in FIG. 2C and hatched with diagonal lines represents the reserved data storage areas 61 to 6M.

The unused heap area 41 is managed by the fixed-length block management unit 12 using a queue (FIFO, first-in first-out) method. In that sense, the unused heap area 41 may be referred to as an unused queue.

In the heap area 21, the reference counter holding module 13a holds reference counters 51 to 5N corresponding to the fixed-length blocks 31 to 3N. Although the values of the reference counters 51 to 5N are stored at the heads of the fixed-length blocks 31 to 3N in FIG. 2, the values of all the reference counters 51 to 5N are collected in one place and managed centrally. It may be.

Each time the data storage areas 61 to 6M are secured, the reference counters 51 to 5N indicate the number of data storage areas newly secured by the reference counter holding module 13a as the value for which the data storage areas 61 to 6M are secured. Is incremented (added). Each time the data storage areas 61 to 6M are released, the values of the reference counters 51 to 5N of the fixed-length blocks 31 to 3N from which the data storage areas 61 to 6M are released are released by the reference counter holding module 13a. It is decremented (subtracted) by the number of data storage areas.

The fixed-length blocks 31 to 3N are areas secured on the heap area 21 by the fixed-length block management unit 12, respectively. The fixed-length blocks 31 to 3N do not necessarily have to be secured adjacent to each other and do not necessarily have to be arranged in the order of addresses. However, if the address at the end of the block can be easily obtained by calculation, the processing load on the processor 10 can be reduced.

The fixed-length block management unit 12 manages the unused heap area 41 by a queue (FIFO, first-in first-out) method, assigns a new fixed-length block from among them, and is no longer used in the fixed-length blocks 31 to 3N Can be released and returned to the unused heap area 41.

The values of the reference counters 51 to 5N are stored at the heads of the fixed-length blocks 31 to 3N by the reference counter holding module 13a. At the stage where a new fixed-length block is assigned, the reference counter corresponding to this fixed-length block is initialized to 0. Each time the data storage area setting module 13c secures a data storage area in the fixed-length block, the reference counter holding module 13a increments (adds) the value of the reference counter corresponding to this fixed-length block. Each time the data storage area setting module 13c releases the data storage area, the reference counter holding module 13a decrements (subtracts) the value of the reference counter corresponding to this fixed-length block.

The empty area pointer holding module 13b holds an empty area pointer 42 indicating the end address of the area where the data storage areas 61 to 6M are secured. When a new data storage area is secured, the data storage area setting module 13c starts with the address value pointed to by the free area pointer 42, and the fixed length block to which the free area pointer 42 and the address of the free area pointer belong. First, an attempt is made to secure an area in an empty area between the end of the. If a data storage area having a required capacity cannot be secured in the meantime, the data storage area setting module 13c notifies the fixed-length block management unit 12 and reserves a new fixed-length block from the unused heap area 41. In this case, a new data storage area is secured.

When the data storage area setting module 13c releases the data storage areas 61 to 6M in the fixed length blocks 31 to 3N and the value of the reference counters 51 to 5N becomes 0 by decrementing, the fixed length block management unit 12 becomes 0. The fixed-length blocks 31 to 3N corresponding to the reference counters 51 to 5N are released and returned to the unused heap area 41. At this time, the information indicating the released area is not retained, and the data storage area once released is re-used until the same area is secured as the fixed-length block after the fixed-length block is released once. It is never used.

FIG. 3 is a flowchart showing an operation when the data storage area management unit 13 shown in FIG. 2 stores new data on the RAM 11. When the operation is started, the data storage area setting module 13c first checks whether or not the data to be stored can be stored in the area indicated by the empty area pointer 42 as the head address (step S201). If there is not enough space to store the data in the area between the free area pointer 42 and the end of the area, the fixed-length block management unit 12 is allocated a new fixed-length block (step S202).

Then, the data storage area setting module 13c secures an empty area for the new data, and the empty area pointer holding module 13b moves the empty area pointer by the amount of the new data (step S203). The setting module 13c adds +1 to the reference counter for the fixed-length block (increment) (step S204).

FIG. 4 is a flowchart showing the operation of the fixed-length block management unit 12 for securing a new fixed-length block shown as step S202 in FIG. First, the fixed-length block management unit 12 secures one of the fixed-length blocks from the unused heap area 41 (step S301), and rewrites the free area pointer 42 with the start address of the secured fixed-length block (step S302). ). At the same time, the reference counter holding module 13a initializes the value of the reference counter corresponding to the fixed-length block as 0 (step S303).

FIG. 5 is a flowchart showing an operation in which the fixed-length block management unit 12 and the data storage area management unit 13 shown in FIG. 2 release an unnecessary data storage area. At the same time as the data storage area setting module 13c releases the data storage area, the reference counter holding module 13a decrements (decrements) the reference counter corresponding to the corresponding fixed-length block (step S401).

If the value of the reference counter is 0 (step S402), it is further determined whether or not the area in the fixed-length block indicated by the empty area pointer 42 by the empty area pointer holding module 13b is indicated (step S403). . When the value of the reference counter is 0 and the free area pointer 42 is not in the fixed-length block, the fixed-length block is not used, and there is no data storage area in the fixed-length block. Therefore, the fixed-length block management unit 12 returns the fixed-length block to the unused heap area 41 and releases the fixed-length block (step S404).

(Securing and releasing the data storage area)
FIG. 6 is an explanatory diagram showing the time transition of securing and releasing the data storage area on the RAM 11 shown in FIGS. In the initial state, no data storage area is secured on the RAM 11. When the processor 10 receives the leading communication frame pkt # 1 from this state, the fixed-length block management unit 12 first secures the fixed-length block 31 on the unused heap area 41 on the RAM 11 (FIG. 3: steps S201 to 202). . At the same time, the reference counter 51 corresponding to the fixed-length block 31 is also secured and set to the initial value 0 (FIG. 4: steps S301 to 302).

Following this, the data storage area setting module 13c of the data storage area management unit 13 secures the data storage area 61 of the communication frame pkt # 1 on the fixed-length block 31, and simultaneously stores the data of pkt # 1 therein. Then, the free area pointer 42 moves by that capacity (FIG. 3: step S203). In accordance with this, the value of the reference counter 51 corresponding to the fixed length block 31 is also incremented by 1 in the reference counter holding module 13a (FIG. 3: step S204). Thus, the state shown in step S501 of FIG. 6 is obtained.

Subsequently, when the processor 10 receives the communication frames pkt # 2 to pkt # 2 to 3, the data storage area setting module 13c similarly secures the data storage areas 62 to 63 corresponding to these and stores these data, and the free area The pointer holding module 13b moves the empty area pointer 42 (FIG. 3: step S203), and each time the reference counter holding module 13a increments the value of the reference counter 51 by 1 (FIG. 3: step S204). Thus, the state shown in steps S502 to S3 of FIG. 6 is obtained.

Subsequently, since the processor 10 completes the transmission of the communication frames pkt # 1 and pkt # 2 and the processing is completed, the data storage area setting module 13c releases these data storage areas, and the reference counter holding module 13a refers to them. The value of the counter 51 is subtracted by 1 (FIG. 5: step S401). Thus, the state shown in step S504 of FIG. 6 is obtained.

Subsequently, when the processor 10 receives the communication frame pkt # 4, the free area pointer holding module 13b moves the free area pointer 42 to the free area that follows pkt # 3, and the data storage area setting module 13c enters this area. A data storage area 64 is secured to store these data (FIG. 3: step S203), and the reference counter holding module 13a adds the value of the reference counter 51 correspondingly (FIG. 3: step S204). Thus, the state shown in step S505 in FIG. 6 is obtained.

At this point, since the areas of pkt # 1 and pkt # 2 are open, it is conceivable to secure the data storage area of pkt # 4 in this area, but this part is not used in this embodiment. As a result, in each fixed-length block, the data storage areas are arranged in one direction close to each other in the order in which the data storage areas are secured, and those having different data lifetimes are arranged in the same fixed-length block. This will prevent the occurrence of fragment causes.

Subsequently, when the processor 10 receives the communication frame pkt # 5, there is no remaining space for storing the pkt # 5 in the free area following the pkt # 4 of the fixed-length block 31 (the above-mentioned pkt # 1-2). Therefore, the fixed-length block management unit 12 secures a new fixed-length block 32 on the RAM 11 (FIG. 3: steps S201 to 202), and the reference corresponding to the fixed-length block 32 is stored. The counter 52 is secured and set to an initial value 0 (FIG. 4: steps S301 to S302).

The data storage area setting module 13c secures the data storage area 65 of the communication frame pkt # 5 on the fixed-length block 32 and stores these data, and the free area pointer holding module 13b moves the free area pointer 42. (FIG. 3: step S203), the reference counter holding module 13a adds 1 to the value of the reference counter 52 corresponding to the fixed length block 32 (FIG. 3: step S204). Thus, the state shown in step S506 of FIG. 6 is obtained.

Subsequently, since the processor 10 completes the transmission of the communication frames pkt # 3 to 4 and the processing is completed, the data storage area setting module 13c releases these data storage areas, and the reference counter holding module 13a refers to them. When the value of the counter 51 is subtracted (FIG. 5: Step S401), the value becomes 0 (FIG. 5: Step S402), and the empty area pointer 42 points to the fixed length block 32 (FIG. 5: Step S403). ), No data already exists in the fixed-length block 31. Therefore, the fixed-length block management unit 12 releases the fixed-length block 31 and returns it to the unused heap area 41 (FIG. 5: Step S404). Thus, the state shown in step S507 of FIG. 6 is obtained.

Thereafter, when the processor 10 receives the communication frame pkt # 6, the data storage area setting module 13c stores this pkt # 6 in the data storage area 66 subsequent to pkt # 5 on the fixed length block 32, and is referred to accordingly. The counter holding module 13a adds the value of the reference counter 52 (FIG. 3: steps S203 to 204). Thus, the state shown in step S508 of FIG. 6 is obtained. Thereafter, the same processing is repeated.

(Overall operation of the first embodiment)
Next, the overall operation of the above embodiment will be described. The operation according to this embodiment is a data processing apparatus including a unit that temporarily stores and processes variable length data in the heap area 21 on the memory 11, and stores the variable length data on the memory 11. A memory management method for securing storage areas 61 to 6M (M is a natural number), in which the data storage area setting module reads address information indicating the end of the storage areas 61 to 6M from the free area pointer holding module, and free area pointer 42 The data storage area setting module 13c sequentially secures the variable length data storage areas 61 to 6M in the order of the address information indicated by the data storage area 61 to 6M, and the data storage area setting module 13c stores the variable length data in the reserved storage areas 61 to 6M.

Here, when the data storage area setting module 13c secures the variable length data storage areas 61 to 6M, the fixed length block to which the address belongs, starting from the value indicated by the empty area pointer 42 held by the empty area pointer holding module 13b. The free area between 31 and 3N is defined as storage areas 61 to 6M (FIG. 3: step S203), and the capacity of the free area is insufficient for the capacity to be secured as the storage areas 61 to 6M. Then, a storage area is secured on the fixed-length block newly allocated by the fixed-length block management unit 12 (FIG. 3: steps S202 to 203).

When the data storage area setting module 13c releases the storage area, the data storage area setting module 13c checks the number of storage areas on the fixed-length blocks 31 to 3N to which the released storage areas 61 to 6M belong (see FIG. 4: Step S401-2), if the value of the reference counters 51-5N of the storage area is 0 and the address held by the free area pointer 42 does not indicate the fixed-length block, the fixed-length block management unit 12 The fixed-length block is released (FIG. 4: steps S402 to S4).

Here, each of the above-described operation steps may be programmed to be executable by a computer, and these may be executed by the CPU 10 which is a main body that directly executes each of the steps.
By this operation, this embodiment has the following effects.

This embodiment is premised on the characteristics of communication data that are “processed almost in the order of arrival” and the characteristics that “the lifetime of data is almost equal”. In this embodiment, using this premise, when securing a data area for storing a communication frame, the next data storage area is continuously secured immediately after the data area secured immediately before. Data stored in the data storage area in the fixed-length block is arranged in the order of arrival.

In most cases, these data storage areas continuously hold data whose lifetimes are close to each other. As communication processing progresses, in most cases, the data storage areas are released in the oldest order, so that the continuity of the data storage area is maintained, and it is difficult for a fragmentation state in which fragments of free areas are scattered. Therefore, the memory usage efficiency can be increased.

In addition, since the data storage area is continuously secured in the fixed-length block, the time during which either the fixed-length block can be used efficiently or unused can be increased. Even if this state exists, the data area is continuously released within a short time, so that the state changes to an unused state.

Since the product of the maximum bandwidth and the maximum dwell time is defined as the specification of communication processing, the maximum total amount of communication frames that must be held at a certain time is determined. In this embodiment, since the total amount of free area fragments in the heap area 21 can be reduced, the resource amount of the RAM 11 that must be physically prepared may be ensured in accordance with the maximum total communication frame amount. That is, according to the present embodiment, it is possible to accurately estimate the required amount of memory device resources.

In this embodiment, in any of the processes related to securing and releasing the areas shown in the flowcharts of FIGS. 3 to 5, it is determined whether the next data can be stored for each scattered free area generated by fragmentation. It does not require processing that changes the time depending on the usage status of the area, such as searching the heap area. Therefore, it is possible to perform processing in a substantially fixed time without depending on the number or amount of data being used. For this reason, even if the memory management area increases, memory management can always be performed in the same processing time, and the processing load on the processor related to memory management can be reduced.

(Second Embodiment)
The second embodiment of the present invention is the same as the first embodiment described with reference to FIGS. 1 to 6 in terms of the network and hardware configurations, and the general software configuration. The second embodiment differs from the first embodiment described above in that the fixed-length block management unit 12 allocates and releases fixed-length blocks for each of a plurality of logical channels set according to the lifetime of variable-length data. The free area pointer holding module 13b holds the free area pointers 71 to 7K one by one for each logical channel. As a result, even when data with different lifetimes coexist, the same effect as in the first embodiment can be obtained.
Hereinafter, this will be described in more detail.

In the second embodiment of the present invention, the hardware and software configurations of the communication device are the same as those in the first embodiment. FIG. 7 is an explanatory diagram showing the configuration of the storage area on the RAM 11 in the second embodiment of the present invention. FIG. 7A shows a state where the heap area 21 is secured on the RAM 11. FIG. 7B shows a state in which the fixed-length block management unit 12 has secured N fixed-length blocks 31 to 3N (N is an integer) on the heap area 21. An area other than the fixed-length blocks 31 to 3N becomes an unused heap area 41. FIG. 7C shows a state in which the data storage area setting module 13c has secured the data storage areas 61 to 6M (M is an integer) on the fixed-length blocks 31 to 3N. Areas hatched with diagonal lines denoted as “K1” and “K2” in FIG. 7C represent reserved data storage areas 61 to 6M. “K1” represents logical channel # 1, and “K2” represents logical channel # 2.

In the present embodiment, K logical channels (K is an integer) are prepared in N fixed-length blocks 31 to 3N (N is an integer) on the heap area 21, and each of these logical channels is free. Area pointers 71 to 7K are prepared. Except for this point, the configuration is the same as that of the first embodiment shown in FIG.

Here, the logical channel is a virtual channel assigned for each application when different communication is performed in the host device, and is a factor that determines the size and the number per time as a feature of the communication frame. The free area pointers 71 to 7K hold candidate addresses for securing new areas for each logical channel. As a result, different fixed-length blocks are used for each logical channel.

The free area pointers 71 to 7K perform the same operation as the free area pointer 42 in the first embodiment for each logical channel. For each logical channel, the data storage area can be secured and released by the same operation as in the first embodiment.

In the first embodiment, it is a premise that the above-described effects can be obtained that all data have substantially the same lifetime. However, in an environment where a plurality of applications operate simultaneously, a plurality of data types having different priorities and QoS parameters are set for each of the plurality of applications, and thus different lifetimes may be required for each data type. In such a case, the same effect as in the first embodiment cannot be obtained if data having different lifetimes are continuous in the data storage areas close to each other.

Thus, even when data having different lifetimes coexist in the RAM 11, if different logical channels are used for different lifetimes and different fixed-length blocks are used for different logical channels, this second According to the embodiment, the same effect as that of the first embodiment can be obtained.

The present invention has been described with reference to the specific embodiments shown in the drawings. However, the present invention is not limited to the embodiments shown in the drawings, and any known hitherto provided that the effects of the present invention are achieved. Even if it is a structure, it is employable.

This application claims priority based on Japanese Patent Application No. 2009-005942 filed on Jan. 14, 2009, the entire disclosure of which is incorporated herein.

The present invention can be applied to a device including a processor and a RAM controlled by the processor, but exhibits a remarkable effect particularly in a device that handles data types such as communication frames or communication packets as described above. . Therefore, it is suitable for a communication processing apparatus that processes frames and packets in various communication layers. Further, the present invention is also suitable for a device that performs streaming processing and a multimedia processing device that performs codec processing such as video and audio.

1 Communication equipment 10 Processor 11 RAM
12 Fixed-length block management unit 13 Data storage area management unit 21 Heap area 31-3N Fixed-length block 41 Unused heap area 42, 71-7K Free area pointer 51-5N Reference counter 61-6M Data storage area

Claims

A data processing apparatus comprising means for temporarily storing and processing variable length data in a memory area,
Fixed length block management means for allocating and releasing fixed length blocks in the memory area, and data storage area management means for securing and releasing storage areas for storing the variable length data in the fixed length blocks,
The data storage area management means includes a reference counter holding section that holds the number of storage areas for each fixed-length block, a free area pointer holding section that holds address information indicating the end of the storage area, and the address information A data processing apparatus comprising: a data storage area setting unit for sequentially securing and releasing the storage area for the variable length data in order.
When the data storage area setting unit secures the storage area for the variable length data, the empty area between the end of the fixed-length block to which the address belongs with the value held by the empty area pointer holding part as the start address Having a storage area setting function as a storage area, and having a capacity determination function for determining whether the capacity of the free area is insufficient with respect to the capacity to be secured as the storage area,
The fixed-length block management means has a new allocation function for newly allocating a fixed-length block when the data storage area setting unit determines that the capacity of the free area is insufficient. The data processing apparatus according to claim 1.
The data storage area setting unit has a reference counter check function for checking a numerical value of a reference counter corresponding to a fixed-length block to which the released storage area belongs when releasing the storage area, and the reference of the storage area A non-use block determination function for determining that the fixed-length block is not used when the counter value is 0 and the address held by the free area pointer does not indicate the fixed-length block;
The fixed-length block management means has an unused block release function for releasing the fixed-length block when the data storage area setting unit determines that the fixed-length block is not used. The data processing apparatus according to claim 2.
The data processing apparatus according to claim 1, further comprising a management queue for managing an unused area that is not allocated as the fixed-length block in the memory area.
The fixed-length block management means is configured to execute allocation and release of the fixed-length block for each of a plurality of logical channels set according to the lifetime of the variable-length data,
2. The data processing apparatus according to claim 1, wherein the free area pointer holding unit is configured to hold the free area pointer one by one for each logical channel.
In a data processing apparatus comprising means for temporarily storing and processing variable length data in a memory area, a memory management method for securing a storage area for storing the variable length data in the memory area,
The data storage area setting unit reads address information indicating the end of the storage area from the free area pointer holding unit,
The data storage area setting unit sequentially secures a storage area for the variable length data in the order of the address information,
A memory management method, wherein the data storage area setting unit stores the variable length data in the reserved storage area.
When the data storage area setting unit reserves a storage area for the variable length data, an empty area between the address and the end of the fixed length block to which the address belongs is used as the storage area, and the empty area 7. The storage area is secured on a fixed-length block newly allocated by fixed-length block management means if the capacity of the storage area is insufficient with respect to the capacity to be secured as the storage area. Memory management method described in 1.
When the data storage area setting unit releases the storage area, the data storage area setting unit checks the number of storage areas on the fixed-length block to which the released storage area belongs, and the number of storage areas is 8. The memory management method according to claim 7, wherein if the address is 0 and the address does not indicate the fixed length block, the fixed length block managing means releases the fixed length block.
A data processing apparatus having means for temporarily storing and processing variable length data in a memory area,
A function in which the data storage area setting unit reads address information indicating the end of the storage area from the free area pointer holding unit;
A function for the data storage area setting unit to sequentially secure storage areas for the variable-length data in the order of the address information;
A memory management program for causing a computer to execute a function of the data storage area setting unit storing the variable length data in the reserved storage area.
When the data storage area setting unit reserves a storage area for the variable length data, an empty area between the address and the end of the fixed length block to which the address belongs is used as the storage area, and the empty area If the capacity of the storage area is insufficient with respect to the capacity to be secured as the storage area, the fixed-length block management means causes the computer to execute a function of securing the storage area on the fixed-length block newly allocated. The memory management program according to claim 9.
When the data storage area setting unit releases the storage area, the data storage area setting unit checks the number of storage areas on the fixed-length block to which the released storage area belongs, and the number of storage areas is 11. The memory management program according to claim 10, wherein if the address is 0 and the address does not indicate the fixed-length block, the fixed-length block management means causes the computer to execute a function of releasing the fixed-length block. .