WO2010076956A3 - Compensation method for communication clock and communication data - Google Patents

Compensation method for communication clock and communication data Download PDF

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Publication number
WO2010076956A3
WO2010076956A3 PCT/KR2009/006017 KR2009006017W WO2010076956A3 WO 2010076956 A3 WO2010076956 A3 WO 2010076956A3 KR 2009006017 W KR2009006017 W KR 2009006017W WO 2010076956 A3 WO2010076956 A3 WO 2010076956A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock
communication
compensation method
data
during
Prior art date
Application number
PCT/KR2009/006017
Other languages
French (fr)
Korean (ko)
Other versions
WO2010076956A2 (en
Inventor
공경식
Original Assignee
주식회사 테라칩스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 테라칩스 filed Critical 주식회사 테라칩스
Publication of WO2010076956A2 publication Critical patent/WO2010076956A2/en
Publication of WO2010076956A3 publication Critical patent/WO2010076956A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The present invention relates to a compensation method for a communication clock which inverts a clock received from a previous system and outputs the inverted clock to a next system in a structure where plural systems are connected in parallel to sequentially transmit data and a communication clock. The invention also concerns a compensation method for communication data. Concerned with the structure, the compensation method for communication data outputs the data from the previous system to the next system during the falling edge of the received clock or the rising edge of the clock compensated by the compensation method for a communication clock in a system which receives data during the rising edge of the clock. In addition, the compensation method for communication data outputs the data from the previous system to the next system during the rising edge of the received clock or the falling edge of the clock compensated by the compensation method for a communication clock in a system which receives data during the falling edge of the clock.
PCT/KR2009/006017 2008-11-12 2009-10-19 Compensation method for communication clock and communication data WO2010076956A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20080112016 2008-11-12
KR10-2008-0112016 2008-11-12
KR1020090000112A KR20100053401A (en) 2008-11-12 2009-01-02 Method for recovery of communication clock or communication data
KR10-2009-0000112 2009-01-02

Publications (2)

Publication Number Publication Date
WO2010076956A2 WO2010076956A2 (en) 2010-07-08
WO2010076956A3 true WO2010076956A3 (en) 2010-08-19

Family

ID=42278530

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2009/006017 WO2010076956A2 (en) 2008-11-12 2009-10-19 Compensation method for communication clock and communication data

Country Status (2)

Country Link
KR (1) KR20100053401A (en)
WO (1) WO2010076956A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000025299A (en) * 1998-10-09 2000-05-06 김영환 Apparatus for synchronizing feedback path clock in cascade bus system
KR100321981B1 (en) * 1999-05-12 2002-02-04 윤종용 Apparatus for recompensing delay of clock
KR20030046686A (en) * 2001-12-06 2003-06-18 삼성전자주식회사 Apparatus for generating network synchronization clock in the mobile communication system
JP2004086905A (en) * 2002-08-28 2004-03-18 Samsung Electronics Co Ltd Data detection circuit and data detection method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000025299A (en) * 1998-10-09 2000-05-06 김영환 Apparatus for synchronizing feedback path clock in cascade bus system
KR100321981B1 (en) * 1999-05-12 2002-02-04 윤종용 Apparatus for recompensing delay of clock
KR20030046686A (en) * 2001-12-06 2003-06-18 삼성전자주식회사 Apparatus for generating network synchronization clock in the mobile communication system
JP2004086905A (en) * 2002-08-28 2004-03-18 Samsung Electronics Co Ltd Data detection circuit and data detection method

Also Published As

Publication number Publication date
KR20100053401A (en) 2010-05-20
WO2010076956A2 (en) 2010-07-08

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