WO2010067243A1 - Détection de mode de transfert de données automatique - Google Patents

Détection de mode de transfert de données automatique Download PDF

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Publication number
WO2010067243A1
WO2010067243A1 PCT/IB2009/055316 IB2009055316W WO2010067243A1 WO 2010067243 A1 WO2010067243 A1 WO 2010067243A1 IB 2009055316 W IB2009055316 W IB 2009055316W WO 2010067243 A1 WO2010067243 A1 WO 2010067243A1
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WO
WIPO (PCT)
Prior art keywords
data
data lines
mode
data transfer
interface
Prior art date
Application number
PCT/IB2009/055316
Other languages
English (en)
Inventor
Juhui Li Juhui
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2010067243A1 publication Critical patent/WO2010067243A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4273—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data

Definitions

  • This invention relates to integrated circuit devices.
  • the Universal Serial Bus 2.0 Transceiver Macrocell Interface is an interface which connects a USB transceiver to another device, such as an ASIC or a FPGA of a host or device.
  • the UTMI Low Pin Interface has been proposed as a way of implementing the UTMI with a reduced number of connecting lines. This allows devices at each end of the UTMI to have a reduced pin count. Examples of existing implementations of a USB Transceiver supporting the ULPI are given in datasheets for NXP Semiconductor devices ISP1504 and ISP1508. It is desirable to further reduce the pin count. Conventionally, reducing the pin count has been at the expense of a reduced set of features. It is desirable to reduce the pin count without sacrificing features of the integrated circuit.
  • a first aspect of the present invention provides a circuit comprising: an interface for communicating with another circu it, the interface comprising a parallel data bus having a set of data lines, wherein the interface is operable in a first data transfer mode in which the set of data lines are used to transfer data and in a second data transfer mode in which a sub-set of the data lines are used to transfer data; a mode detection module which is arranged to determine which of the data transfer modes is in use by detecting a state of at least one of the data lines which is only used by the first data transfer mode, the mode detection module generating a configuration output indicative of the determined data transfer mode for configuring operation of the circuit.
  • An advantage of the circuit detecting, by itself, which data transfer mode is in use is that there is no need for the circuit to receive a control signal which specifies which data transfer mode is in use. This avoids the need to provide a pin to receive the control signal on the package housing the circuit, and this saving in pin count can be made without a reduction in the feature-set of the circuit. This also avoids the need to provide a connecting line to the circuit carrying a configuration signal which instructs the circuit of the data transfer mode. Further advantages are a saving in cost and board area.
  • the configuration output is used to configure operation of other modules and devices within the circuit.
  • the detection of the data transfer mode can be performed without affecting the interface timing. The detection can be made by monitoring for any activity on the data lines.
  • a particularly quick and reliable detection of the data transfer mode can be made by the mode detection module detecting logic values received on the data lines at a time when a command having known logic values is expected to be received over the interface.
  • the data transfer mode is determined according to which data lines the known logic values are detected on.
  • the logic value can be signalled on a data line by a voltage value, or by a change in voltage value.
  • the mode detection module is arranged to perform the detection immediately following power-up.
  • a further aspect of the invention provides a method of operating a circuit, the circuit comprising an interface for communicating with another circuit, the interface comprising a parallel data bus having a set of data lines, the interface being operable in a first data transfer mode in which the set of data lines are used to transfer data and in a second data transfer mode in which a sub-set of the data lines are used to transfer data, the method comprising: determining which of the data transfer modes is in use by detecting a state of at least one of the data lines which is only used by the first data transfer mode; and, generating a configuration output indicative of the determined data transfer mode for configuring operation of the circuit.
  • Embodiments of the invention are described in which the interface is the UTMI Low Pin Interface (ULPI).
  • the circuit can be a USB or a Wireless USB (WUSB) integrated circuit. It will be appreciated that wh ile U LPI is an advantageous example of an interface, the invention can be more generally applied to other types of interface which support multiple modes of operation, with different numbers of data lines being used in the different modes.
  • the functionality described here can be implemented in software, hardware or a combination of these.
  • the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed processor. Accordingly, another aspect of the invention provides a machine-readable product carrying machine-executable instructions (software) for implementing the described functionality.
  • the software may be stored on an electronic memory device, hard disk, optical disk or other machine- readable storage medium.
  • the software may be downloaded directly to a processing device via a network connection.
  • Figure 1 shows a UTMI Low Pin Interface (ULPI) between a transceiver and a host device
  • Figure 2 shows SDR and DDR operation on a data line of the interface
  • Figure 3 shows a mode detector within the transceiver
  • Figure 4 shows data transfer of a command in SDR and DDR modes
  • Figure 5 shows logic to implement the mode detector
  • Figure 6 shows waveforms of the logic of Figure 5 when the SDR mode is in use
  • Figure 7 shows waveforms of the logic of Figure 5 when the DDR mode is in use.
  • FIG. 1 shows an example application of an embodiment of the invention.
  • a USB Transceiver 20 and another device, such as a host processor 10 are connected by a UTMI Low Pin Interface (ULPI) 30.
  • the ULPI 30 comprises a data bus formed by a set of data lines D7-D0, a direction controlling line (dir), clock (elk), and the lines stp and nxt.
  • Transceiver 20 and host processor 10 are each implemented as an integrated circuit.
  • the UTMI Low Pin Interface (ULPI) supports two data transfer modes: a first mode called Single Data Rate (SDR) and a second mode called Dual Data Rate (DDR).
  • SDR Single Data Rate
  • DDR Dual Data Rate
  • the single data rate mode toggles a data line only on a rising clock edge and uses a parallel data bus which is 8 bits wide, i.e. it uses the set 31 of data lines D7-D0.
  • This version of the ULPI has eight data lines and a total of twelve lines, and is shown in Figure 1 .
  • the dual data rate mode (DDR) toggles a data line on the rising and falling clock edges and uses a parallel data bus which is 4 bits wide, i.e. it uses the sub-set 32 of data lines D3-D0 and does not use the data lines D7-D4.
  • This version of the ULPI has four data lines and a total of eight lines.
  • Figure 2 shows a data signal on one of the data lines in both the SDR and DDR modes of operation. In the DDR mode each data line operates at twice the rate as a data line in SDR mode. The two modes achieve the same overall data rate as DDR uses half as many lines as SDR, with each line operating at twice the data rate of SDR.
  • the USB transceiver is capable of supporting both the SDR and DDR modes of operation. Only one mode can be used at any time. To support both modes of operation, the transceiver interface has eight data lines D7-D0. It is known to dedicate a further top level pin on the transceiver device to receive a control signal which instructs the transceiver to perform SDR or DDR operation, but this requires an external pin on the integrated circuit package.
  • a device of this kind is shown in the datasheet for NXP Semiconductor device ISP1508, with a configuration pin CFGO receiving a signal to select SDR/DDR mode.
  • the transceiver shown in Figures 1 and 3 improves on this by deriving a configuration signal CFG for itself, indicating which date rate (SDR/DDR) is being used, by monitoring the data lines 31.
  • FIG. 3 shows a USB transceiver 20 with a mode detector 50.
  • the mode detector connects to selected ones of the data lines D7-D0. Embodiments will be described in which the mode detector 50 connects to one, two or a larger number of the data lines.
  • the mode detector 50 also advantageously connects to the other lines of the interface such as clock (elk) and direction (dir).
  • Mode detection logic 52 detects activity on the selected data line(s) and decides, on the basis of the detected activity, which data rate the interface is using. This allows the transceiver 20 to determine the data rate for itself, without requiring an external configuration input.
  • Mode detector 50 outputs a configuration signal CFG which indicates the detected mode, i.e. SDR or DDR.
  • the configuration signal can be used to configure operation of the USB transceiver circuit 20, such as configuring which data bus lines D7-D0 the transceiver should transmit and receive on, timing for transmit/receive operations and any other parameter which is dependent on the data mode.
  • the mode detector 50 can operate in one of a number possible ways:
  • the mode detector 50 connects to at least one of the data lines (e.g. D7) which is only used during the SDR mode of operation.
  • Mode detection logic 52 monitors activity on the data line. If activity is detected on the line, the interface must be operating in the SDR mode, as this line is not used during DDR mode.
  • the detection is performed at a time when it is known that data is received.
  • the mode detector 50 connects to at least one of the data lines (e.g. D7) which is only used during the SDR mode of operation and also to at least one of the data lines which is used both during SDR and DDR modes (e.g. D3).
  • the mode detection logic 52 monitors activity on the data lines. If activity is detected on line D7 then the interface must be operating in the SDR mode. If activity is detected on line D3 but not on D7 then the interface must be operating in the DDR mode. In options (i) and (ii) above it is possible to monitor for any activity occurring on the monitored data lines. It is advantageous that the decision of which data rate is being used is made as quickly and correctly as possible.
  • This feature can be combined with any of (i) or (ii).
  • An embodiment of the mode detector 50 will now be described which follows (ii) above and monitors for the presence of a particular command following power-up.
  • the mode detector 50 connects to data line D7 (i.e. a data line which is only used in SDR mode) and data line D3 (i.e. a data line which is used during SDR and DDR mode) and looks at selected bits of the first byte of a predetermined command received on these lines.
  • data line D7 i.e. a data line which is only used in SDR mode
  • data line D3 i.e. a data line which is used during SDR and DDR mode
  • Figure 4 shows data transfer in SDR and DDR modes.
  • the set of data lines D7-D0 is shown.
  • this command will be sent in parallel across data lines D7-D0 as a byte.
  • this command will be sent across only data lines D3-D0 in two nibbles.
  • the time taken to transmit the two nibbles in DDR mode is the same as the time taken to transmit the byte in SDR mode.
  • the example command shown in Figure 4 is a transmit command (TXCMD) to perform a soft-reset, and is the first command expected to be received from device 10 in the ULPI specification. Consider that only data lines D7 and D3 are monitored.
  • Lines D[7:4] are set to 0. Accordingly, if a logic value of "1” is seen on data line D7 and a logic value of "0" is seen on data line D3, the mode is determined to be SDR. If a logic value of "0" is seen on data line D7 and a logic value of "1 " is seen on data line D3, the mode is determined to be DDR.
  • a USB transceiver waits to receive commands from device 10 on the ULPI interface 30.
  • Data lines D7 and D3, or D7, D6, D3 and D2 are monitored as described above.
  • the signal DIR is also defined in the ULPI specification. It is an output signal from the USB transceiver to indicate the data bus direction. Only when DIR is low, device 10 can drive TXCMD.
  • the line "dir" is also connected to the detection circuit so that the detection of the values on data lines D7, D6, D3, D2 is performed after signal DIR has changed to allow the device 10 to transmit.
  • USB transceiver 10 can remove the pull down on its data bus and both USB transceiver 20 and other device 10 are in normal functional status.
  • a more detailed embodiment of logic to perform the rate detection is shown in Figure 5 and waveforms showing operation of the circuit are shown in Figures 6 and 7. Pull down enable on the data bus is not shown in these figures.
  • the inputs to the logic circuit are: Dir_d (direction of data transmission); D7_d, D6_d, D3_d and D2_d (data lines of the data bus).
  • DDR The default mode of the USB transceiver is DDR. This is because there is some time margin in SDR case and DDR is very timing stringent.
  • Module 63 detects when the first TXCMD command is received on the interface, following power up and outputs a signal EN which is applied to other modules. Note, that module 63 only indicates when the first command is received. Module 61 checks whether the first command has the required logic values. Module 61 generates outputs "HIGH BITS" and "LOW BITS" which indicate when logic values on the data lines D7, D6, D3, D2 meets values of the first expected command. Module 62 latches logic values and decodes a set of inputs to generate the output CFG which indicates whether the data rate is SDR or DDR.
  • DFF3.Q then DFF3 and M5 enter Latch mode. EN will not change anymore even when there are changes on Dir_d, "HIGH BITS” and “LOW BITS".
  • "HIGH BITS” goes through M1 and M2 when Dir_d is '0' and EN is T.
  • "LOW BITS” goes through M3 and M4 when Dir_d is '0' and EN is T.
  • "HIGH BITS” and "LOW BITS” will be captured by DFF1 and DFF2 at the falling edge of Clk60MHz. If “HIGH BITS” or “LOW BITS" changes, EN will change from T to O'. M2 and M4 will pick up values from DFF1 and DFF2 other than “HIGH BITS" and "LOW BITS”.
  • M2, DFF1 and M4, DFF2 will enter latch mode. This means the value of M2.O and M4.O will not be changed anymore by "HIGH BITS” and “LOW BITS” unless PoR_n changes to 1 O'.
  • the signal Power on Reset (PoR) initialises all of the flip-flops in this circuit to be in a default value, for example, to initialize the detection to be in DDR mode and EN to be "T.
  • Decoder block The operation of the Decoder block is described by Table 1.
  • the various illustrative logical blocks, modules, circuits, and algorithm steps described above may be implemented as electronic hardware, as software modules executed by a processor, or as combinations of both.
  • the various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination designed to perform the described functions.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a method and apparatus for circuit 20 comprises an interface 30 for communicating with another circuit 10.
  • the interface 30 comprises a parallel data bus having a set of data lines 31 which are operable in a first data transfer mode in which the set of data lines 31 are used to transfer data and in a second data transfer mode in which a sub-set 32 of the data lines are used to transfer data.
  • a mode detection module 50 determines which of the data transfer modes is in use by detecting a state of at least one of the data lines which is only used by the first data transfer mode and detecting a state of at least one line from the sub-set of data lines.
  • the mode detection module can detect logic values received on the data lines at a time when a command having known logic values is expected to be received over the interface and determine the data transfer mode according to which of the data lines the known logic values are detected on.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Information Transfer Systems (AREA)

Abstract

L'invention porte sur un circuit (20) qui comprend une interface (30) pour communiquer avec un autre circuit (10). L'interface (30) comprend un bus de données parallèle ayant un ensemble de lignes de données (31) qui sont utilisables dans un premier mode de transfert de données dans lequel l'ensemble des lignes de données (31) est utilisé pour transférer des données et dans un second mode de transfert de données dans lequel un sous-ensemble (32) des lignes de données est utilisé pour transférer des données. Un module de détection de mode (50) détermine lequel des modes de transfert de données est en utilisation par détection d'un état d'au moins l'une des lignes de données qui est uniquement utilisée par le premier mode de transfert de données et par détection d'un état d'au moins une ligne du sous-ensemble de lignes de données. Le module de détection de mode (50) est capable de détecter des valeurs logiques reçues sur les lignes de données à un instant auquel la réception d’une instruction ayant des valeurs logiques connues est escomptée sur l'interface et ainsi que de déterminer le mode de transfert de données en fonction des lignes de données sur lesquelles les valeurs logiques connues sont détectées.
PCT/IB2009/055316 2008-12-10 2009-11-24 Détection de mode de transfert de données automatique WO2010067243A1 (fr)

Applications Claiming Priority (2)

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EP08105961.0 2008-12-10
EP08105961 2008-12-10

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WO2010067243A1 true WO2010067243A1 (fr) 2010-06-17

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1293931A2 (fr) * 2001-09-14 2003-03-19 Kabushiki Kaisha Toshiba Carte à mémoire
WO2004051491A1 (fr) * 2002-11-29 2004-06-17 Nokia Corporation Procede et systeme destines a detecter une largeur de bus, dispositif electronique et dispositif peripherique

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1293931A2 (fr) * 2001-09-14 2003-03-19 Kabushiki Kaisha Toshiba Carte à mémoire
WO2004051491A1 (fr) * 2002-11-29 2004-06-17 Nokia Corporation Procede et systeme destines a detecter une largeur de bus, dispositif electronique et dispositif peripherique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
STMICROELECTRONICS: "HS USB ULPI transceiver", August 2007 (2007-08-01), XP002566061, Retrieved from the Internet <URL:http://www.st.com/stonline/products/literature/bd/13859.pdf> [retrieved on 20100129] *

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