WO2010066778A1 - Method for turbo equalization of zarray coded words - Google Patents

Method for turbo equalization of zarray coded words Download PDF

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Publication number
WO2010066778A1
WO2010066778A1 PCT/EP2009/066708 EP2009066708W WO2010066778A1 WO 2010066778 A1 WO2010066778 A1 WO 2010066778A1 EP 2009066708 W EP2009066708 W EP 2009066708W WO 2010066778 A1 WO2010066778 A1 WO 2010066778A1
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decoding
codeword
code block
ldpc
zarray
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PCT/EP2009/066708
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French (fr)
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Oliver Theis
Xiao-ming CHEN
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Thomson Licensing
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2975—Judging correct decoding, e.g. iteration stopping criteria
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3746—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with iterative decoding
    • H03M13/3753—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with iterative decoding using iteration stopping criteria
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6331—Error control coding in combination with equalisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6343—Error control coding in combination with techniques for partial response channels, e.g. recording
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof

Definitions

  • ECC optical storage systems
  • It may also be applied to magnetic recording storage devices and transmission systems.
  • EP 08305688 A class of quasi-cyclic error correcting codes has been disclosed in Unpublished European Patent Application EP 08305688 and will be named zArray Codes in the following.
  • EP 08305688 also discloses a class of error correcting codes named pczArray Codes, which result from zArray codes through parallel concatenation. All these codes belong to the known class of Low Density Parity Check codes also denoted as LDPC codes.
  • Channel coding for optical data storage often is done in the form of Run Length Limited coding also denoted as RLL coding.
  • Channel coding is often also called channel modulation.
  • SISO is an abbreviation known in the field, which denotes the Soft Input, Soft Output versions of decoding or demodulation methods.
  • a SISO channel detector As well as a SISO RLL demodulator is necessary to propagate channel bit likelihoods, usually represented in the form of log- likelihood-ratios or LLRs, to the LDPC decoder.
  • Unpublished Eurpoean Patent Application EP 08101916 disclosed a combined channel detector/demodulator Finite State Machine or FSM, denoted as Super-Trellis, for the (1,9) RLL code presented in Unpublished European Patent Application EP 08101915, which can be used in conjunction with BCJR/SOVA like algorithms on PR-channels.
  • the Super-Trellis allows easy utilization of a priori information, which might come from the feedback of extrinsic information from previous LDPC decoding in order to reduce the number of random errors iteratively.
  • EP 1 217 776 purports to disclose an apparatus for stopping iterative decoding in a turbo decoder performing iterative decoding on a received frame comprised of information bits and then outputting the iteratively decoded results.
  • a turbo decoder sequentially outputs absolute LLR (Log Likelihood Ratio) values associated with the respective information bits of the received frame by the iterative decoding, and stops the iterative decoding in response to a stop command for the iterative decoding.
  • a minimum LLR detector selects a minimum value M(i) among the sequentially output absolute LLR values.
  • a controller issues a command to stop the iterative decoding, if the minimum value M(i) is larger than a first threshold determined based on a minimum value Fmin among absolute LLR values output through previous iterative decoding.
  • WO 2007/001305 purports to disclose a method, an apparatus and a computer program product for reducing power consumption in an iterative decoder, for example, for low-density parity check (LDPC) codes or turbo codes.
  • the apparatus includes a memory device and an iteration termination device.
  • the memory device is for storing a decoded codeword for a current iteration, for each iteration of the iterative decoder prior to a maximum number of iterations.
  • the iteration termination device is for comparing the decoded codeword for the current iteration to a previously stored decoded codeword for the previous iteration, incrementing a confidence value when the decoded codeword for the current iteration matches the previously stored decoded codeword for the previous iteration, and terminating further iterations of the iterative decoder when the confidence value exceeds a pre- specified threshold value.
  • 105 iteration are calculated. In one embodiment, if the sign of corresponding bits in the data block is different between the two iterations, an error was corrected. If the number of errors corrected is greater than a stopping value, a subsequent iteration of turbo equalization is performed. If the number of
  • the present invention is the outcome of dealing with three subtasks :
  • Subtask I How to decrease the bit error rate or BER in optical 120 disc systems using (1,9) RLL channel coding with a SuperTrellis detector and a zArray or pczArray LDPC soft-decision decoder on the receiver side.
  • Subtask II How to overcome the effect that, for optical data 125 storage, applying TE to single LDPC codewords does not reach full performance. The reason is that, due to noise colourization, neighboring intrinsic L-values of the LDPC codeword prior to decoding are mutually dependent, while, on the other hand, message-passing decoding performs best only if the intrinsic L- 130 values of the LDPC codeword are statistically independent.
  • Subtask III How to schedule or control TE for multiple LDPC codewords in such a way that improved BER results are achieved with a minimum number of TE iterations and LDPC decoder calls. 135
  • the invention proposes to use a bitwise interleaving scheme of 150 multiple zArray or pczArray codewords. This will break the statistical dependence of intrinsic L-values and allow to decrease the BER significantly through the outer iterations of TE
  • codeword interleaving and deinterleaving causes some implementation and memory cost, as well as a delay. This improves 155 BER performance through TE in the presence of colored noise.
  • the invention discloses a TE schedule where, in addition to the usual post syndrome check of the message passing decoder, it is checked whether decoding results are unchanged against those of the previous outer iteration.
  • the post syndrome check is known to be unreliable especially for zArray 165 codes. If the syndrome is zero and decoding results are unchanged, no further LDPC decoding will be performed on that codeword during the remaining outer iterations. Outer iterations stop altogether as soon as all LDPC codewords have been decoded successfully or a maximum number of outer iterations has been 170 performed. In this way, the high undetected error probability of zArray codes is overcome. This minimizes TE cost without performance loss, and overcomes the high undetected error probability of zArray codes.
  • the method according to the present invention provides for turbo equalization decoding of received binary words that were zArray coded, and comprises super trellis code block detecting, and LDPC code block decoding.
  • the method is characterized in that
  • the intrinsic L-values are deinterleaved within a code block
  • a success flag for every codeword is set in an iteration if the estimated codeword remains unchanged in the iteration;
  • the extrinsic L- values are interleaved within the code block.
  • Figure 1 shows a block diagram for Turbo Equalization of LDPC 195 codeblocks over synchronous PR-channels
  • Figure 2 illustrates a bitwise interleaving scheme for a codeblock C
  • Figure 3 illustrates a Block interleaving scheme for a codeblock 200 C
  • Figure 4 shows a flow diagram of an LDPC Block decoding schedule according to the invention.
  • Figure 1 shows a block diagram for Turbo Equalization of LDPC 210 codeblocks over synchronous PR-channels 103 with SuperTrellis detection 104.
  • a block diagram of transmission over a synchronous Partial Response or PR channel 103 with LDPC code protection against random errors is given in Figure 1. It is assumed that either zArray or pczArray codes are used.
  • TurboEqualization TE is 215 carried out by feeding back 115, 416 extrinsic information 116 from the LDPC message passing decoder 106, 403 back into the SuperTrellis detector 104, 401. This feedback initiates another detection/decoding cycle, which will also be called an "outer iteration". At reasonable SNRs, the amount of random errors after 220 LDPC decoding is expected to decrease after each iteration.
  • Intra-codeword interleaving of LDPC codes is usually not required 225 because of the inherent pseudo-random structure of the parity- check matrix. But the present invention has observed that receivers performing TE can take advantage of bitwise interleaving of multiple LDPC codewords. This results from the fact that PR-channels usually suffer from a high amount of 230 coloured noise which in turn causes locally correlated L-values after SuperTrellis detection. Any form of bitwise interleaving can break the correlation and allow optimum message passing performance.
  • the present invention therefore proposes to assemble an LDPC codeblock C from m codewords [C 1 ,1 ⁇ i ⁇ m ⁇ through
  • codebits can be subject to any permutation, while the codewords are selected in a round-robin way, i.e. a codebit from C 1 is followed by a codebit from C mO du,m)+i .
  • FIG. 240 illustrates a bitwise interleaving scheme for a codeblock C.
  • Each codebit Ci? is followed by a codebit C (mod(i,m) +1) ?. Accordingly, c2? 203 follows after cl? 202, and so on, until after cm? 205, cl? 206 follows again. This can be achieved through the use of a simple block interleaver where
  • Figure 3 illustrates a Block interleaving scheme for a codeblock C. Codewords (304) are written (301) into a memory column (303) by column and are read out (300) from the same memory row (302) by row.
  • Turbo Equalization TE on the receiver side will involve deinterleaving 105 the log-likelihood-values or L-values of the codeblock before LDPC decoding 106, and interleaving 107 the extrinsic L-values 115 before a new outer iteration starts with
  • codeword change checking in the following. Additionally, of course, the post LDPC decoding syndrome check must yield an all zero syndrome.
  • Figure 4 shows a flow diagram of an LDPC Block decoding schedule according to the invention
  • n denotes the outer iteration index assumed to be 0 ⁇ « ⁇ 72
  • 72 denotes the maximum number of outer 280 iterations
  • i denotes the codeword index l ⁇ i ⁇ m
  • m denotes the number of codewords per code block
  • C denotes the estimated code block
  • C 1 denotes the estimated i-th codeword
  • S 1 denotes the syndrome of codeword i
  • d denotes a binary decoding success indicator .
  • the elements of the estimated code block are preset by a special value denoting "not a number”
  • zArray and pczArray Codes are not limited to optical storage technology. TE techniques not involving (1,9) SuperTrellis detection will likely also be applied beneficially in other fields.
  • bitwise codeblock-interleavings makes sense whenever a high amount of noise colorization is present as in PR-channels.
  • the invention proposes a method comprising super trellis code block detecting 401 and LDPC code block decoding 403.
  • block interleaving is used, and within the step of LDPC code block decoding 403 a success flag d for every codeword is set 409 if the estimated codeword remains unchanged in an iteration, and LDPC code word decoding 408 is skipped 413, 412, 415 if the success flag d of the codeword is set 413.

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  • Physics & Mathematics (AREA)
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Abstract

For turbo equalization decoding of received binary words that were zArray coded, the invention proposes a method comprising super trellis code block detecting (401) and LDPC code block decoding (403). For decreasing the bit error rate in the presence of colored noise while minimizing the number of iterations, block interleaving is used, and within the step of LDPC code block decoding (403) a success flag (d) for every codeword is set (409) if the estimated codeword remains unchanged in an iteration, and LDPC code word decoding (408) is skipped (413, 412, 415) if the success flag (d) of the codeword is set (413).

Description

Method for Turbo Equalization of zArray coded words
TECHNICAL FIELD OF THE INVENTION:
The invention relates to the field of error correction codes
(ECC) for optical storage systems. It may also be applied to magnetic recording storage devices and transmission systems.
TECHNICAL BACKGROUND
A class of quasi-cyclic error correcting codes has been disclosed in Unpublished European Patent Application EP 08305688 and will be named zArray Codes in the following. EP 08305688 also discloses a class of error correcting codes named pczArray Codes, which result from zArray codes through parallel concatenation. All these codes belong to the known class of Low Density Parity Check codes also denoted as LDPC codes.
Channel coding for optical data storage often is done in the form of Run Length Limited coding also denoted as RLL coding. Channel coding is often also called channel modulation. "SISO" is an abbreviation known in the field, which denotes the Soft Input, Soft Output versions of decoding or demodulation methods.
For optical storage in order to apply soft decision message passing algorithms for LDPC decoding, a SISO channel detector as well as a SISO RLL demodulator is necessary to propagate channel bit likelihoods, usually represented in the form of log- likelihood-ratios or LLRs, to the LDPC decoder. Unpublished Eurpoean Patent Application EP 08101916 disclosed a combined channel detector/demodulator Finite State Machine or FSM, denoted as Super-Trellis, for the (1,9) RLL code presented in Unpublished European Patent Application EP 08101915, which can be used in conjunction with BCJR/SOVA like algorithms on PR-channels. The Super-Trellis allows easy utilization of a priori information, which might come from the feedback of extrinsic information from previous LDPC decoding in order to reduce the number of random errors iteratively.
This iterative exchange of soft information between a Super- Trellis detector and a LDPC decoder known as "Turbo Equalization" or TE, with application to optical storage, has been presented in 2002 by Eiji Yamada, Tetsuo Iwaki and Takeshi Yamaguchi in "Turbo Decoding with Run Length Limited Code for Optical Storage" [1] .
A similar scheme was proposed in 2003 by Zhao Fang, George Mathew and B . Farhang-Borouj eny in "Joint Turbo Channel Detection und RLL Decoding for (1,7) Coded Partial Response Recording Channels" [2] The authors investigated the bit error rate or BER performance of a Super-Trellis (1,7) detector in conjunction with turbo decoders
TE in conjunction with LDPC over Partial response or PR channels, but without RLL decoding, has already been presented in 2001 by Thomas Mittelholzer, Ajay Dholakia and Evangelos Eleftheriou in "Reduced-Complexity Decoding of Low Density Parity Check Codes for Generalized Partial Response Channels" [3] .
None of [1], [2] or [3] incorporate multiple codeword interleaving .
TE techniques can generally be traced back to 1995 where C.
Douillard, M. Jezequel, and C. Berrou, presented "Iterative correction of intersymbol interference: Turbo-Equalization" in
European Transactions on Telecommunication. TE might also incorporate the use of a MMSE Equalizer instead of a BCJR/SOVA like detector. This is well explained by RaIf Kόtter, Andrew C. Singer and Michael Tuchler in "Turbo Equalization"
EP 1 217 776 purports to disclose an apparatus for stopping iterative decoding in a turbo decoder performing iterative decoding on a received frame comprised of information bits and then outputting the iteratively decoded results. A turbo decoder sequentially outputs absolute LLR (Log Likelihood Ratio) values associated with the respective information bits of the received frame by the iterative decoding, and stops the iterative decoding in response to a stop command for the iterative decoding. A minimum LLR detector selects a minimum value M(i) among the sequentially output absolute LLR values. A controller issues a command to stop the iterative decoding, if the minimum value M(i) is larger than a first threshold determined based on a minimum value Fmin among absolute LLR values output through previous iterative decoding.
WO 2007/001305 purports to disclose a method, an apparatus and a computer program product for reducing power consumption in an iterative decoder, for example, for low-density parity check (LDPC) codes or turbo codes. The apparatus includes a memory device and an iteration termination device. The memory device is for storing a decoded codeword for a current iteration, for each iteration of the iterative decoder prior to a maximum number of iterations. The iteration termination device is for comparing the decoded codeword for the current iteration to a previously stored decoded codeword for the previous iteration, incrementing a confidence value when the decoded codeword for the current iteration matches the previously stored decoded codeword for the previous iteration, and terminating further iterations of the iterative decoder when the confidence value exceeds a pre- specified threshold value.
100
US 2008/0115038 purports to disclose a method and apparatus for selectively terminating turbo equalization. At least two iterations of turbo equalization are performed. The number of errors corrected between the first iteration and the second
105 iteration are calculated. In one embodiment, if the sign of corresponding bits in the data block is different between the two iterations, an error was corrected. If the number of errors corrected is greater than a stopping value, a subsequent iteration of turbo equalization is performed. If the number of
110 errors corrected is less than or equal to the stopping value, then associated values for the data are output and the turbo equalization is terminated.
Invention 115
The present invention is the outcome of dealing with three subtasks :
Subtask I) How to decrease the bit error rate or BER in optical 120 disc systems using (1,9) RLL channel coding with a SuperTrellis detector and a zArray or pczArray LDPC soft-decision decoder on the receiver side.
Subtask II) How to overcome the effect that, for optical data 125 storage, applying TE to single LDPC codewords does not reach full performance. The reason is that, due to noise colourization, neighboring intrinsic L-values of the LDPC codeword prior to decoding are mutually dependent, while, on the other hand, message-passing decoding performs best only if the intrinsic L- 130 values of the LDPC codeword are statistically independent. Subtask III) How to schedule or control TE for multiple LDPC codewords in such a way that improved BER results are achieved with a minimum number of TE iterations and LDPC decoder calls. 135
Solution to subtask I)
The general idea is to apply TE techniques especially to single zArray or pczArray codewords, or to codeblocks consisting of
140 multiple zArray or pczArray codewords, in conjunction with the Super-Trellis detection, especially incorporating (1,9) RLL demodulation as presented in EP 08101915. However, applying TE will increase the computation cost, since the detector and the decoder will usually be run several times. This improves bit
145 error rate or BER performance through Turbo Equalization.
Solution to subtask II)
The invention proposes to use a bitwise interleaving scheme of 150 multiple zArray or pczArray codewords. This will break the statistical dependence of intrinsic L-values and allow to decrease the BER significantly through the outer iterations of TE However, codeword interleaving and deinterleaving causes some implementation and memory cost, as well as a delay. This improves 155 BER performance through TE in the presence of colored noise.
Solution to subtask III)
In order to keep the number of TE iterations and LDPC decoder 160 calls at a minimum, the invention discloses a TE schedule where, in addition to the usual post syndrome check of the message passing decoder, it is checked whether decoding results are unchanged against those of the previous outer iteration. The post syndrome check is known to be unreliable especially for zArray 165 codes. If the syndrome is zero and decoding results are unchanged, no further LDPC decoding will be performed on that codeword during the remaining outer iterations. Outer iterations stop altogether as soon as all LDPC codewords have been decoded successfully or a maximum number of outer iterations has been 170 performed. In this way, the high undetected error probability of zArray codes is overcome. This minimizes TE cost without performance loss, and overcomes the high undetected error probability of zArray codes.
175 In total, the method according to the present invention provides for turbo equalization decoding of received binary words that were zArray coded, and comprises super trellis code block detecting, and LDPC code block decoding. The method is characterized in that
180 - after the step of super trellis code block detecting, the intrinsic L-values are deinterleaved within a code block,
- within the step of LDPC code block decoding, a success flag for every codeword is set in an iteration if the estimated codeword remains unchanged in the iteration; and LDPC code word decoding
185 is skipped if the success flag of the codeword is set; and
- after the step of LDPC code block decoding, the extrinsic L- values are interleaved within the code block.
190 Drawings
An embodiment of the present invention is illustrated in the following description and Figures, in which:
Figure 1 shows a block diagram for Turbo Equalization of LDPC 195 codeblocks over synchronous PR-channels with
SuperTrellis detection; Figure 2 illustrates a bitwise interleaving scheme for a codeblock C;
Figure 3 illustrates a Block interleaving scheme for a codeblock 200 C; and
Figure 4 shows a flow diagram of an LDPC Block decoding schedule according to the invention.
205 Details of the invention
Embodiment of the solution of Subtask I)
Figure 1 shows a block diagram for Turbo Equalization of LDPC 210 codeblocks over synchronous PR-channels 103 with SuperTrellis detection 104. A block diagram of transmission over a synchronous Partial Response or PR channel 103 with LDPC code protection against random errors is given in Figure 1. It is assumed that either zArray or pczArray codes are used. TurboEqualization TE is 215 carried out by feeding back 115, 416 extrinsic information 116 from the LDPC message passing decoder 106, 403 back into the SuperTrellis detector 104, 401. This feedback initiates another detection/decoding cycle, which will also be called an "outer iteration". At reasonable SNRs, the amount of random errors after 220 LDPC decoding is expected to decrease after each iteration.
Embodiment of the solution of Subtask II)
Intra-codeword interleaving of LDPC codes is usually not required 225 because of the inherent pseudo-random structure of the parity- check matrix. But the present invention has observed that receivers performing TE can take advantage of bitwise interleaving of multiple LDPC codewords. This results from the fact that PR-channels usually suffer from a high amount of 230 coloured noise which in turn causes locally correlated L-values after SuperTrellis detection. Any form of bitwise interleaving can break the correlation and allow optimum message passing performance. The present invention therefore proposes to assemble an LDPC codeblock C from m codewords [C1 ,1 < i ≤ m} through
235 bitwise interleaving as shown in Figure 2. In this, codebits can be subject to any permutation, while the codewords are selected in a round-robin way, i.e. a codebit from C1 is followed by a codebit from CmOdu,m)+i .
240 Figure 2 illustrates a bitwise interleaving scheme for a codeblock C. Each codebit Ci? is followed by a codebit C (mod(i,m) +1) ?. Accordingly, c2? 203 follows after cl? 202, and so on, until after cm? 205, cl? 206 follows again. This can be achieved through the use of a simple block interleaver where
245 codewords are written into a memory column by column and read row by row as shown in Figure 3. Figure 3 illustrates a Block interleaving scheme for a codeblock C. Codewords (304) are written (301) into a memory column (303) by column and are read out (300) from the same memory row (302) by row.
250
Turbo Equalization TE on the receiver side will involve deinterleaving 105 the log-likelihood-values or L-values of the codeblock before LDPC decoding 106, and interleaving 107 the extrinsic L-values 115 before a new outer iteration starts with
255 SuperTrellis detection 104.
Embodiment of the solution of Subtask III)
During each outer iteration, some LDPC codewords of the codeblock
260 will successfully be decoded while others will fail. The present invention is based on recognizing that in subsequent outer iterations it is unnecessary to decode over and over again codewords which have already been successfully decoded. In this, a codeword C1 is said to be successfully decoded if no single bit 265 changes during two successive outer iterations. Testing this will be called "codeword change checking" in the following. Additionally, of course, the post LDPC decoding syndrome check must yield an all zero syndrome.
270 The present invention has recognized that relying exclusively on the syndrome check is disadvantageous when zArray codes are used, because these codes show a high amount of undetected errors, thereby falsely indicating successful decoding. TE with codeword change checking is therefore a way to overcome the undetected
275 error problem of zArray codes.
Figure 4 shows a flow diagram of an LDPC Block decoding schedule according to the invention, n denotes the outer iteration index assumed to be 0 < « < 72 , 72 denotes the maximum number of outer 280 iterations, i denotes the codeword index l≤i≤m , m denotes the number of codewords per code block, C denotes the estimated code block, C1 denotes the estimated i-th codeword, S1 denotes the syndrome of codeword i, and d denotes a binary decoding success indicator .
285
At the beginning of the TE schedule 400, the outer iteration index is initialized to n=0, the codeword index is initialized to z=l , the elements of the estimated code block are preset by a special value denoting "not a number", and the binary decoding
290 success indicator is initialized to J=O, meaning "false".
The sequence diagram of the invented TE schedule is shown in Figure 4. A decoding state indicator Ci1 keeps track of the decoding success for each codeword C1. Codewords found to be successfully decoded 407 during any of the previous outer iterations will not be decoded again 413. Outer decoding stops 417 as soon as d equals the all one vector (d=l) or when the maximum number of outer iterations have been reached 404; otherwise, a new outer iteration is started 416, 405.
The use of zArray and pczArray Codes is not limited to optical storage technology. TE techniques not involving (1,9) SuperTrellis detection will likely also be applied beneficially in other fields. The use of bitwise codeblock-interleavings makes sense whenever a high amount of noise colorization is present as in PR-channels.
With other words, for turbo equalization decoding of received binary words that were zArray coded, the invention proposes a method comprising super trellis code block detecting 401 and LDPC code block decoding 403. For decreasing the bit error rate in the presence of colored noise while minimizing the number of iterations, block interleaving is used, and within the step of LDPC code block decoding 403 a success flag d for every codeword is set 409 if the estimated codeword remains unchanged in an iteration, and LDPC code word decoding 408 is skipped 413, 412, 415 if the success flag d of the codeword is set 413.

Claims

Claims
1. Method for turbo equalization decoding of received binary words that were zArray coded, the method comprising super trellis code block detecting (401), and LDPC code block decoding (403), and characterized in that
- after the step of super trellis code block detecting (401), the intrinsic L-values are deinterleaved (402) within a code block,
- within the step of LDPC code block decoding (403) , a success flag (d) for every codeword is set (409) in an iteration if the estimated codeword remains unchanged in the iteration; and LDPC code word decoding (408) is skipped (413, 412, 415) if the success flag (d) of the codeword is set (413) ; and
- after the step of LDPC code block decoding (403) , the extrinsic L-values are interleaved (406) within the code block.
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