WO2010064000A2

WO2010064000A2 - Analogue to digital converter

Info

Publication number: WO2010064000A2
Application number: PCT/GB2009/002798
Authority: WO
Inventors: Trond Ytterdal
Original assignee: Ntnu Technology Transfer As; Jackson, Robert
Priority date: 2008-12-01
Filing date: 2009-12-01
Publication date: 2010-06-10
Also published as: GB0821940D0; WO2010064000A3

Abstract

An analogue to digital converter ("ADC") has a plurality of electrically interconnected semiconductor layers (3, 7, 9, 11) arranged in a stack. Each layer has an input for an analogue signal on one layer and an output for a digital signal on another layer. The conversion of the input signal to the output signal is performed in a plurality of steps which are divided between the respective layers. Each layer comprises a silicon wafer with CMOS circuitry formed thereon and conductive via (16, 17, 18) are provided through the semiconductor layers. The ADC is of pipeline configuration; at least one bit is extracted from the analogue input signal in each of the plurality of layers.

Description

Analogue to Digital Converter

The present invention relates to an analogue to digital converter (ADC) and in particular to such a device having a small footprint such that a high density of them may be provided in a two dimensional array.

There are numerous applications where it is desirable to provide a large number of analogue-to-digital converters in an array. One example is in the field of ultrasound imaging devices. Recently, ultrasound systems for real time 3- dimensional (3D) medical imaging have become available, the most advanced of which are based upon a 2-dimensional matrix of transducers to facilitate ultrasound beam steering within a cone shaped volume. To obtain adequate spatial resolution in combination with a large imaging volume, the transducer matrix is composed of several thousand individual transducer elements which each have to be connected electrically to transmit and receive circuitry.

The escalation from 2- to 3-dimensional imaging increases the number of elements by at least a factor of 20-30. In addition to the higher complexity caused by this, the necessary downscaling of element size increases the electrical impedance to a level where electrical matching to each element becomes difficult and critical in order to maintain high operational acoustic and electric performance of the transducer assembly. As a result all matrix transducers for 3D imaging available in the market have electronic circuitry integrated inside the transducer probe assembly.

There remains a need to increase the operating frequency of the transducers in order to improve resolution. A radically different transducer technology that is attracting interest is the so called CMUT (Capacitive Micro machined Ultrasound Transducer) technology (see, for example, J. Knight, J. McLean, and F. L. Degertekin, "Low temperature Fabrication of Immersion Capacitive Micromachined Ultrasonic transducers on Silicon and Dielectric Substrates", IEEE Trans, on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 51, no. 10, pp. 1324-1333, Oct. 2004.)

Traditionally, readout of the transducer and signal processing inside the probe has been performed in the analog domain before the signals are brought outside to the main processing unit where they are sampled and quantized by analog- to-digital converters (ADCs). However, this causes problems with regard to signal noise being introduced before conversion can take place and it also places constraints on flexibility and the ability to re-configure the device. It would therefore be desirable to be able to place the ADCs inside the probe, with one provided per CMUT transducer. Since the CMUT transducers are placed in a 2D matrix, the space available for electronic circuitry on the substrate directly below each CMUT element is limited by the size of the element, which is much smaller than the area needed by a conventional complete ADC. Thus, the provision of a suitable ADC with a much reduced "footprint" is needed in order to allow CMUT transducers to achieve their full potential. However, ADCs involve the use of analogue signals and there are fundamental physical limits which make it unlikely that they will decrease in size in future in any way remotely comparable to that occurring with digital CMOS technology. The main limit is the need for a sufficiently high signal-to-noise ratio; the former depends on the square of the voltage and the latter is governed by temperature and capacitance.

Furthermore, there are numerous other applications where small-footprint ADCs would be highly beneficial. Imaging devices such as CCDs are inevitably employed in two-dimensional matrices and so a similar issue applies if it is desired to reduce the pitch of the matrix. Another field is that of radio and radar systems at 60GHz-90GHz. For example, ultra-miniature transmitters may be used for short range transmission of TV signals from a DVD player or the like. Such transmitters may employ tiny farms of miniature antennae, each one having an individual ADC associated with it.

According to a first aspect of the invention there is provided an analogue to digital converter ("ADC") comprising a plurality of electrically interconnected semiconductor layers arranged in a stack and having an input for an analogue signal on one layer and an output for a digital signal on another layer, wherein the conversion of the input signal to the output signal is performed in a plurality of steps which are divided between the respective layers.

Thus, by means of the present invention the footprint (the area of the device normal to the stacking direction) can be significantly reduced compared to conventional ADCs. As previously discussed, this is highly advantageous because there are numerous applications where ADCs have to be arranged in a matrix having the smallest possible area, whereas any increase in the height of the device is of less consequence.

Although the invention is applicable to many kinds of semiconductor technologies, the layers will typically be silicon wafers and it is preferred that CMOS circuitry is formed thereon. A further advantage of this arrangement is that different technologies can be used for each layer as appropriate although in many cases CMOS circuitry will be used for each layer.

There are a number of known techniques for the vertical interconnection of semiconductor wafers and in principle any of these can be applied to the present invention. However, those systems which use external wire bonding would be useful only for limited applications because of their impact on the overall footprint of the device. On the other hand, technologies which allow the provision of feed through passages through the layers/wafers (known as "vias") are preferred. Such techniques involve the provision of a small aperture through the silicon wafer which is insulated and then filled with a conductive material. The preferred technique is the "Bosch process" described in more detail below.

Thus, typically the analogue to digital converter of the invention will comprise a plurality of semiconductor layers with some or preferably all being formed with a plurality of conductive vias therethrough. The conductor layers are stacked so that the vias in one wafer align with appropriate circuitry formed on an adjacent wafer. The plurality of wafers are secured together by any suitable means such as the use of adhesive, molten metal techniques (soldering), etc.

A number of ADC architectures may be employed with the present invention. One possibility is the known delta-sigma ADC which may be configured such that its functionality is split between the plurality of layers. However, it is preferred that architecture be used which does not involve a global feedback loop from the output to the input because this avoids the need for an extra set of vias in order to carry the feedback signal and it also facilitates the parallel processing of signals.

It is therefore particularly preferred that the known pipeline ADC architecture be employed in the present invention. In a pipeline ADC the most significant bit(s) is/are extracted in a first stage, the next most significant bit(s) in a second stage and so on until the least significant bit(s) are extracted at the last stage. When employed in the present invention, the separate layers can each carry the circuitry associated with a separate bit(s) extraction stage. Most preferably, the most significant bit is extracted in the first stage which is located physically closest (proximal) to the input and therefore the most important part of the signal is least likely to be affected by noise.

The invention may also comprise a hybrid of ADC architectures so that, for example, the first stages may be a pipeline arrangement with the last stage being a flash ADC (i.e. an ADC that uses a set of comparators to determine what binary output corresponds to a given analogue input).

If the smallest possible footprint is the most important criteria then each layer may contain only a single stage of the pipeline ADC and may therefore extract only a single bit (though a single stage may extract more than one bit). This may be necessary since each stage of the pipeline uses an analogue signal and is therefore subject to the physical constraints mentioned above. However, it is presently preferred that two or three bits are extracted on each layer. This is believed to provide the optimum balance between footprint size and manufacturing convenience since increasing the number of layers increases the degree of manufacturing complexity to some extent.

Thus, a typical device may provide 7 bit ADC with two bits (preferably the most significant) being extracted in the first stage, the next two in the second stage and three in the last (which might be a flash stage). A simpler, but also useful device may be produced having only two stages with the first stage extracting two bits and the second stage extracting two or three bits to provide a four or five bit ADC respectively. Alternatively, further stages may be added to provide a two, two, two, three bit arrangement, etc. In principle, more layers can be added to be able to reach 12-14 bits, which is currently the maximum resolution offered by pipeline ADCs.

Each stage in the ADC is preferably provided using CMOS circuitry on a silicon wafer and the outputs from each stage may be connected using vias passing through the wafer to the wafer below, where the next two bits are extracted , or, in the case of the last stage, an output is provided. The output may also use vias to connect to further circuitry in another layer.

The use of a pipeline ADC allows for what is effectively parallel processing because its global-feedback-free design allows the different stages to process parts of different analogue inputs. Thus, whilst the least significant bit of a first analogue sample input is being processed in the last stage, the second-least significant bit of the second (subsequent) analogue input may be processed in the previous stage, and so on.

So far, the invention has been described in the context of a single ADC. In practice, however, the main advantages of the invention are achieved when a plurality of ADCs according to the invention are provided in an array.

In particular, there is preferably provided a two-dimensional array of ADCs, whereby the respective layers are common to all of the ADCs. Thus, a given layer of semiconductor material preferably forms one layer of a plurality of ADCs and therefore has formed thereon an array of (preferably identical) ADC stages. In such an arrangement, a first layer comprises a plurality of first stages, a second layer a plurality of second stages, etc. to provide the desired number of stages as previously described , whereby respective stages are aligned to provide the two-dimensional array. In other words, if each layer is regarded as a horizontal plane, then each ADC comprises a vertical column of stages.

Thus, viewed from another aspect, the invention provides an array of ADCs comprising a plurality of electrically interconnected semiconductor layers arranged in a stack and having an inputs for analogue signals on one layer and corresponding outputs for digital signals on another layer, whereby an ADC is formed between each respective input and output, wherein the conversion of the input signal to the output signal is performed in a plurality of steps which are divided between the respective layers

As previously discussed, one particularly interesting application of such technology is in the field of ultrasound transducers and therefore viewed from a further aspect, the present invention provides an integrated ultrasound transducer unit comprising a layered structure in which a first layer comprises a matrix of ultrasound transducer elements and a plurality of further layers connected thereto is used to provide a matrix of analogue to digital converters, whereby each ultrasound element has an associated analogue to digital converter and each said analogue to digital converter is formed over a plurality of said further layers, each of which performs a part of the analogue to digital conversion process.

Although conventional (e.g. piezo-electric) ultrasound elements may be used in this aspect of the invention, it is preferred that CMUT technology be used so that the first element comprises a CMUT substrate forming a (two dimensional) matrix of ultrasound transducer elements.

The analogue to digital converter layers may be increased or decreased in number as required, but in a typical application 7 bit ADC will be provided as described above. In simpler applications where there lower resolution is required then 4 bit ADC may be provided using two layers.

Although it is possible to output the raw digital signals from each ADC for external processing, this will involve a large number of parallel connections and so it is preferred that the device comprise a further layer in which signal processing and/or communication functions be performed. Thus, preferably this layer comprises data compression units and/or units for pre-purchasing the signal in order to communicate with an external device.

By means of this aspect of the invention it is possible to increase the frequency of the ultrasound to say 30 MHz which provides high resolution and involves transducers of approximately 25 microns square. However, it is possible to apply the technology to frequencies of 100 MHz and higher, though this involves a corresponding decrease in the size of the transducers. At the other end of the scale, useful miniature lower resolution imaging devices are possible which need only 3 to 5 MHz and in which case each ultrasound transducer may be as large as 200 to 250 microns square. This level of resolution is useful for implantable heart monitoring devices.

The system described above provides the receive chain for an ultrasound system. In a simple case, separate transducers may be used to generate the ultrasound output pulses. These may also be formed in the same, or a similar, substrate. In order to supply an operating voltage to output transducers, vias may be provided through the layers of the device. Thus, this aspect of the present invention allows the provision of an integrated sub-miniature ultrasound transducer of reduced dimensions which is capable of three-dimensional imaging and of performing most of the necessary signal processing on board.

As set out below, the invention also extends to a method of manufacturing an analogue to digital converter and an ultrasound transducer as of the kind described above comprising forming a layered structure as described and to a method of converting analogue to digital signals using such a device. It also extends to a method of creating an ultrasound image using an ultrasound transducer of the type previously described.

Thus, according to another aspect the invention provides a method of manufacturing an analogue to digital converter ("ADC") assembly comprising: arranging a plurality of electrically interconnected semiconductor layers in a stack to form an ADC; providing an input for an analogue signal on one of said layers and an output for a digital signal on another of said layers, wherein the ADC is arranged such that the conversion of an analogue input signal to a digital output signal is performed in a plurality of steps which are divided between the respective layers.

From a further aspect, there is provided method of manufacturing an ADC array comprising: arranging a plurality of electrically interconnected semiconductor layers in a stack to form a plurality of ADCs; providing inputs for analogue signals on one layer and corresponding outputs for digital signals on another layer, whereby an ADC is formed between each respective input and output; and wherein the ADCs are arranged such that conversion of the input signal to the output signal is performed in a plurality of steps which are divided between the respective layers.

Viewed from a still further aspect, the invention provides a method of manufacturing an integrated ultrasound transducer unit comprising a layered structure, the method comprising: providing as a first layer a matrix of ultrasound transducer elements; providing a plurality of further layers, the further layers forming a matrix of analogue to digital converters; connecting the further layers to the first layer; the layers being arranged such that each ultrasound element has an associated analogue to digital converter ("ADC") and each layer of the analogue to digital converter performs a part of the analogue to digital conversion process. The invention also provides a method of converting an analogue signal to a digital signal comprising: arranging a plurality of electrically interconnected semiconductor layers in a stack to form an ADC; inputting an analogue signal to one of said layers; converting said analogue signal to a digital signal in a plurality of steps, said steps being divided between the respective layers; and outputting the digital signal from another of said layers.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings:

Figure 1 is a schematic perspective view of an integrated ultrasound transducer array according to an aspect of the present invention;

Figure 2 is an enlarged and more detailed view of the portion of Figure 1 identified by 'A'; and

Figure 3 is a schematic diagram showing the pipeline ADC circuit used in the above embodiment.

As may be seen from Figure 1 , the ultrasound transducer array 1 is formed of a number of layers which are sandwiched in order to form an integrated structure. At the upper part of the figure is shown a layer 2 comprising an array of ultrasound elements 3. These are formed in a capacitive micro-machined ultrasound transducer (CMUT) substrate. The overall dimensions of the array are about 1 mm square. In use, reflected ultrasound beams are received at the upper surface of the matrix 4. Each element 3 provides its own output signal.

Bonded beneath the lower surface 5 of CMUT substrate 2 are three layers of CMOS circuitry 6, 8 and 10 that together form an analogue to digital converter ("ADC"). Layer 6 comprises a plurality of identical elements 7 and likewise layers 8 and 10 are formed from elements 9 and 11 respectively.

The final illustrated layer 12 is a further layer of CMOS circuitry which forms the signal processing and communication layer of the device. In use this is connected to external apparatus.

As will be seen, the device forms a three-dimensional array in which the top layer comprises a two-dimensional array of individual CMUT elements 3, each of which is associated with an individual analogue to digital converter formed in three vertically stacked stages 7, 9 and 11. The signals from the CMUT substrate 3 are transmitted through it to the ADC layers which in turn feed the signal processing and communication layer 12.

The analogue to digital converter (ADC) is designed to produce a readout accuracy (SNDR) of 4OdB, which corresponds to 6.6 bits accuracy for the ADC. Thus, the converter needs to extract seven bits from its input. For CMUTs having a centre frequency of 3 MHz, a sampling frequency of 50 MHz is employed and since the outward impedance from the CMUT is capacitive, a charge sampling ADC front end is employed. At this level of accuracy, the ADC will not be limited by thermal noise and so it can be scaled down using nano scale CMOS process technology to reduce the transistor capacitances and thereby reduce power consumption.

The element 7 forms the first stage of the pipeline ADC at which the two most significant bits are extracted. The next two most significant bits are extracted from elements 9 and then the final three in element 11 which is a three-bit flash ADC.

As is well known in the art, with a pipeline architecture ADC the analogue input signal is converted to a digital output in a number of sequential stages.

As noted above, the signal processing layer 12 takes as its inputs the outputs from all of the third stages 11 of the ADCs and converts them into a suitable form for transmitting as an output signal from the ultrasound array. It includes conventional compression technology in order to reduce the number of output channels and may optionally be reprogrammable so as to enable or disable certain elements of the array for power saving or other purposes.

The most significant bit is determined first and by means of the described arrangement this is achieved as close as possible to the CMUT element so that the most significant bit is extracted nearest to the signal source. The remainder signal is amplified/normalised before the next most significant bit is extracted and the process is repeated (in subsequent stages) until all seven bits have been determined. Although for a given input signal this is a serial, stepwise, process, the different stages in fact operate in parallel because as the second bit is being extracted from a given CMUT output signal, the first bit is being extracted from a subsequent signal. No feedback signal is required and so the signal goes in only one direction through the ADC. The construction of the embodiment will now be described in further detail with reference to Figure 2 which shows a single column through the array of Figure 1 as identified by reference A in that figure.

Each layer of the array is formed from a silicon wafer. In order to transmit signals from one silicon layer to the next, feedthrough paths are provided, which are referred to herein as vias, as identified by references 14 to 18. These are formed by an etching process known as deep via etching or the "Bosch" process. This process uses SF₆ in order to etch a blind hole into the silicon and then C₄Fg in order to passivate the side walls. This process is to use extremely vertical side walls. The vias are then lined with an insulator formed by depositing a layer of silicon dioxide SiO₂ insulator. A TiN or TaN adhesion/barrier area is then deposited followed by a seed layer of copper to form the conductor.

It will be appreciated that at this stage the copper is not accessible from the underside of the wafer; this is achieved by thinning the wafer, i.e. grinding away the lower surface, until the conductor and insulator forming the via are exposed.

The individual substrate layers are then bonded together using adhesive or conventional bonding techniques using molten metal.

The individual vias are formed in each substrate layer separately prior to them being precisely lined and bonded. For reasons of clarity, Figure 2 shows only a single via per layer, but it will be appreciated that between each layer of the ADC a number of vias will be required.

Thus, as may be seen from Figure 2, via 14 provides a connection from the CMUT element 2 to the first layer of CMOS circuitry formed on a silicon substrate 19 that forms the first element 7 of the ADC. As previously noted, this layer extracts the first two most significant bits before the output signals are transmitted along a plurality of vias 16 to CMOS circuitry layer 20 forming the second ADC stage. Likewise, its outputs pass through further vias 17 to the third ADC layer formed on CMOS circuitry 21 before the output from the ADC as a whole is transmitted along vias 18 to the respective part 13 of the signal processing and communication layer 12 formed on CMOS circuitry layer 22.

Thus, the apparatus described above provides an essentially complete ultrasound receiver. Ultrasound signals reflected from a target are detected by the

10 CMUT elements 3 forming the array 2. The analogue signals from the CMUT elements provide a set of parallel inputs into the ADCs formed over layers 6, 8 and 10 where they are converted into a set of parallel digital signals which are in turn output to the processing and communication layer 12. This then outputs suitable signals to a display or other apparatus.

Figure 3 shows a schematic flow diagram of the pipeline ADC circuit 20 provided by the CMOS circuitry discussed above.

The inputs are the analogue input voltage 21 as provided by the output from a single CMUT element 3, a reference voltage 22 and a supply voltage to clock driver 24. The latter provides clock pulses 25 as an output which are used to synchronise the remaining stages of the ADC.

As discussed above, the ADC comprises three stages 26, 27 and 28 which are arranged in sequence. Each stage has an output that is connected to respective inputs of register 29, the output 40 from which forms the output of the ADC.

As discussed above, the first stage 26 and second stage 27 are 2-bit ADC stages and are formed on elements 7 and 8 (i.e. on layers 6 and 8) of the device (see Figures 1 and 2). Third stage 28 is formed on element 11 (layer 10). The clock driver 24 and register 29 are formed as part of the signal processing layer. As was also explained, the interconnections between the respective stages are formed using vias (e.g. 16, 17, 18 - see Figure 2) as are other "vertical" connections such as those between the components on the signal processing layer and the ADC stages. The "horizontal" interconnections within each layer, as well as the respective components are formed using the standard CMOS techniques.

Since the first stage 26 and second stage 27 are identical, the diagram shows only the latter in more detail. Input 30 is the analogue input, which is either the voltage output from the transducer (i.e. input voltage 21) or the analogue output ("residue") from the first stage (see below). The stage comprises a two-bit ADC 31, a digital-to-analogue converter (DAC) 32, a subtractor 33 and an amplifier 34, the , output from which provides the stage's output 35.

The analogue input 30 is supplied to ADC which extracts the two most significant bits from the signal. These are transmitted via output 36 to register 29. In addition, the same two bits are input via a sample and hold unit 37 into DAC 32.

11 The analogue output from DAC 32 is then supplied, along with the stage's analogue input 30 to subtracter 33. The output from the subtractor is the difference between the two inputs which represents the unconverted part of the analogue signal is then passed to amplifier 34. This applies a gain of a factor of 4 in order to provide a suitable input voltage level for the next stage.

The third stage 28 comprises a three-bit ADC which provides a three-bit output 36 from the analogue signal supplied to it.

It will be appreciated that the first stage 26, which takes output voltage from the transducer, provides the two most significant bits to the register 29. The second stage 27 then takes the residue (corresponding to the remaining bits) and extracts the next most significant bits (i.e. the third and fourth bits). The residue from this stage is supplied to the third stage 28, which provides the last three bits. Thus, in total seven bits are supplied to the register 29 which carries out any necessary error correction, etc.

It will be appreciated that in embodiments where more bits are required, further stages similar to the first and second stages may be added between them and the 3-bit ADC 28 by providing further layers of the device.

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Claims

1. An analogue to digital converter ("ADC") comprising a plurality of electrically interconnected semiconductor layers arranged in a stack and having an input for an analogue signal on one layer and an output for a digital signal on another layer, wherein the conversion of the input signal to the output signal is performed in a plurality of steps which are divided between the respective layers.

2. An ADC as claimed in claim 1 wherein each layer comprises a silicon wafer with CMOS circuitry formed thereon.

3. An ADC as claimed in claim 1 or 2, wherein conductive vias are provided through the semiconductor layers in order to interconnect circuitry formed thereon.

4. An ADC as claimed in claim 3, wherein the vias are of the "Bosch" type as defined herein.

5. An ADC as claimed in any preceding claim, wherein the ADC is of pipeline configuration, whereby in use at least one bit extracted from the analogue input signal in each of the plurality of layers.

6. An ADC as claimed in any preceding claim, wherein the most significant bit is extracted from the analogue input signal in the layer that is proximal to the input.

7. An ADC as claimed in any preceding claim, wherein one layer comprises a flash ADC.

8. An ADC as claimed in any preceding claim, wherein the ADC is a pipeline ADC arranged to provide 7 bits output and wherein the two most significant bits are extracted in a first stage formed in the a first layer arranged proximal to the input, the next two bits are extracted in a second stage formed in a second layer adjacent to

13 the first layer, and the remaining three bits are extracted in a third stage adjacent to the second layer.

9. A two-dimensional array of ADCs comprising a plurality of ADCs as claimed in any preceding claim, whereby the respective layers are common to all of the ADCs forming the array.

10. An array of ADCs comprising a plurality of electrically interconnected semiconductor layers arranged in a stack and having an inputs for analogue signals on one layer and corresponding outputs for digital signals on another layer, whereby an ADC is formed between each respective input and output, wherein the conversion of the input signal to the output signal is performed in a plurality of steps which are divided between the respective layers.

11. An array of ADCs as claimed in claim 10, wherein the individual ADCs comprise an ADC according to any of claims 1 to 8.

12. An ADC array as claimed in claim 10 or 11 in combination with an ultrasound transducer matrix electrically connected thereto, whereby an integrated three-dimensional ultrasound probe is provided having a digital output therefrom.

13. An integrated ultrasound transducer unit comprising a layered structure, the structure having as a first layer a matrix of ultrasound transducer elements, and a plurality of further layers connected thereto, the further layers forming a matrix of analogue to digital converters, whereby each ultrasound element has an associated analogue to digital converter and each layer of the analogue to digital converter performs a part of the analogue to digital conversion process.

14. Apparatus as claimed in claim 12 or 13, wherein there is provided a further layer comprising signal processing and/or communication functionality.

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15. Apparatus as claimed in claim 14, wherein the further layer provides data compression on the data output from the outputs of the ADCs.

16. A method of manufacturing an analogue to digital converter ("ADC") assembly comprising: arranging a plurality of electrically interconnected semiconductor layers in a stack to form an ADC; providing an input for an analogue signal on one of said layers and an output for a digital signal on another of said layers, wherein the ADC is arranged such that the conversion of an analogue input signal to a digital output signal is performed in a plurality of steps which are divided between the respective layers.

17. A method of manufacturing an ADC assembly, wherein the ADC is according to any of claims 1 to 9

18. A method of manufacturing an ADC array comprising: arranging a plurality of electrically interconnected semiconductor layers in a stack to form a plurality of ADCs; providing inputs for analogue signals on one layer and corresponding outputs for digital signals on another layer, whereby an ADC is formed between each respective input and output; and wherein the ADCs are arranged such that conversion of the input signal to the output signal is performed in a plurality of steps which are divided between the respective layers.

19. A method as claimed in claim 18, wherein the ADC array is according to any of claims 10 to 12.

20. A method of manufacturing an integrated ultrasound transducer unit comprising a layered structure, the method comprising: providing as a first layer a matrix of ultrasound transducer elements;

15 providing a plurality of further layers, the further layers forming a matrix of analogue to digital converters; connecting the further layers to the first layer; the layers being arranged such that each ultrasound element has an associated analogue to digital converter ("ADC") and each layer of the analogue to digital converter performs a part of the analogue to digital conversion process.

21. A method as claimed in claim 20, further comprising the step of adding a further layer comprising signal processing and/or communication functionality.

22. A method as claimed in claim 21, wherein the further layer provides data compression on the data output from the outputs of the ADCs.

23. A method of converting an analogue signal to a digital signal comprising: arranging a plurality of electrically interconnected semiconductor layers in a stack to form an ADC; inputting an analogue signal to one of said layers; converting said analogue signal to a digital signal in a plurality of steps, said steps being divided between the respective layers; and outputting the digital signal from another of said layers.

24. A method as claimed in claim 23, wherein the layer to which the analogue signal is input is at the opposite end of the stack from the layer from which the digital signal is output.

25. A method as claimed in claim 23, wherein the ADC is as claimed in any of claims 1 to 9, or forms part of an array as claimed in any of claims 10 to 12.

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