WO2010059146A1 - Wear leveling memory cells - Google Patents

Wear leveling memory cells Download PDF

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Publication number
WO2010059146A1
WO2010059146A1 PCT/US2008/013064 US2008013064W WO2010059146A1 WO 2010059146 A1 WO2010059146 A1 WO 2010059146A1 US 2008013064 W US2008013064 W US 2008013064W WO 2010059146 A1 WO2010059146 A1 WO 2010059146A1
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WO
WIPO (PCT)
Prior art keywords
storage
area
size
storage device
available unused
Prior art date
Application number
PCT/US2008/013064
Other languages
French (fr)
Inventor
Kent E. Biggs
Michael A. Provencher
Lee B. Hinkle
Original Assignee
Hewlett-Packard Development Company L.P.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett-Packard Development Company L.P. filed Critical Hewlett-Packard Development Company L.P.
Priority to PCT/US2008/013064 priority Critical patent/WO2010059146A1/en
Priority to TW098139296A priority patent/TW201025331A/en
Publication of WO2010059146A1 publication Critical patent/WO2010059146A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping

Definitions

  • Flash memory is a particular type of EEPROM 1 Electrically Erasable Programmable Read-Only Memory. Erasing and programming, or writing, in flash memory is performed in blocks of memory cells.
  • NAND flash memory is a specific type of flash memory that uses NAND gates to form the memory cells. NAND flash memory is frequently used in removable USB storage devices and thin client hardware. NAND flash memory is often used as a primary storage device for an embedded operating system.
  • Memory cells in NAND flash memory wear out over time. Typical memory cells in a NAND flash module last only between 10,000 to 300,000 writes. Reads have no impact on the life of the memory cells.
  • Figure 1 is a block diagram illustrating an embodiment of a system for wear leveling memory cells in a storage device.
  • Figure 2 is a block diagram illustrating an embodiment of the memory cells of Figure 1.
  • Figure 3 is a flow chart illustrating an embodiment of a method for wear leveling memory cells in a storage device.
  • Figure 4 is a flow chart illustrating another embodiment of a method for wear leveling memory cells in a storage device.
  • FIG. 1 illustrates one embodiment of a wear leveling system 2 for wear leveling memory cells 4.
  • Wear leveling system 2 includes a storage device 6 and a boot system 8.
  • Storage device 6 is any type of data or program storage device, for example, magnetic, electronic, or optical memory.
  • storage device 6 is a flash memory storage device.
  • storage device 6 is a NAND flash memory storage device.
  • Storage device 6 includes a plurality of memory cells 4. The number of memory cells 4 is directly related to the capacity of the storage device 6 and is typically far greater than may be conveniently illustrated in Figure 1.
  • Figure 2 illustrates one embodiment of memory cells 4.
  • Memory cells 4 are cells for storing data or information. Memory cells 4 may be logically divided into two different use types. The first is a static area 10 that, in one embodiment, contains the operating system, drivers, and applications and rarely or never changes. The second is a dynamic area 12 containing settings and other data that changes on a regular basis.
  • Area of static storage 10 includes all of the cells 4 holding data that infrequently or never changes. Although illustrated in Figure 2 as contiguous cells 4, area of static storage 10 may be either contiguous or noncontiguous.
  • Area of available unused storage 12 includes all of the cells 4 that are designated as not holding data. Although illustrated in Figure 2 as contiguous cells 4, area of available unused storage 12 may be either contiguous or noncontiguous.
  • Memory cells 4 may also include area of dynamic storage 14. Area of dynamic storage 14 includes all of the cells 4 holding data that frequently changes. Although illustrated in Figure 2 as contiguous cells 4, area of dynamic storage 14 may be either contiguous or noncontiguous.
  • Boot system 8 is any combination of hardware and executable code configured to boot storage device 6, discover a size of the available unused storage on storage device 6, and move a portion of area of static storage 10 to available unused storage 12. In one embodiment, moving the area of the static storage to the available unused storage includes copying the portion of area of static storage 10 and freeing the copied area of the static storage to available unused storage. [0015] In one embodiment boot system 6 is further configured to discover a size of area of static storage 10 on storage device 6. In one embodiment, the size of the portion of area of static storage 10 moved to available unused storage 12 is equal in size to the size of the available unused storage.
  • boot system 8 includes BIOS (built in operating system) 16.
  • BIOS 16 is any combination of hardware and executable code configured to initialize storage device 6.
  • BIOS 16 is configured to execute the functions of boot system 8.
  • boot system 8 is further configured to evaluate whether booting storage device 6 triggers discovering the size of the available unused storage on storage device 6.
  • booting a predetermined number of times triggers the discovering.
  • booting a predetermined number of times after a predetermined time period has lapsed since the most recent wear leveling for storage device 6, triggers the discovering.
  • a boot with a command to initiate wear leveling triggers the discovering.
  • Figure 3 is a flow chart representing steps of one embodiment method for wear leveling memory cells 4 in storage device 6. Although the steps represented in
  • System 2 waits 18 until storage device 6 is booted. Storage device 6 is booted 20. In one embodiment, whether booting 20 storage device 6 triggers discovering the size of the available unused storage on storage device 6 is evaluated 22.
  • booting 20 does not trigger the discovering, system 2 again waits 18 until storage device 6 is booted. If booting 20 does trigger the discovering, responsive to the boot of storage device 6, a size of the available unused storage 12 on storage device 6 is discovered 24.
  • moving 26 the portion of the area of static storage 10 to available unused storage 12 includes copying the portion of area of static storage 10 to the available unused storage 12 and freeing the copied portion of area of static storage
  • Figure 4 is a flow chart representing steps of another embodiment method for wear leveling memory cells 4 in storage device 6. Although the steps represented in Figure 4 are presented in a specific order, the technology presented herein can be performed in any variation of this order. Furthermore, additional steps may be executed between the steps illustrated in Figure 4.
  • Figure 4 differs from Figure 3 only in the determination of the size of portion of area of static storage 10 to be moved to area of available unused storage 12.
  • System 2 waits 18 until storage device 6 is booted. Storage device 6 is booted 20. In one embodiment, whether booting 20 storage device 6 triggers discovering the size of the available unused storage on storage device 6 is evaluated 22.
  • booting 20 does not trigger the discovering, system 2 again waits 18 until storage device 6 is booted. If booting 20 does trigger the discovering, responsive to the boot of storage device 6, a size of the available unused storage 12 on storage device 6 is discovered 24. A size of area of static storage 10 on storage device 6 is also discovered 28.
  • a portion of area of static storage 10 is moved 26 to area of available unused storage 12.
  • the size of the portion moved is equal to the lesser of the size of the available unused storage and the size of area of static storage 10.
  • moving 26 the portion of the area of static storage 10 to available unused storage 12 includes copying the portion of area of static storage
  • the present invention addresses the condition where a dynamic storage area can wear out, while the static flash area, typically holding an operating system, has thousands of write cycles remaining.
  • Implementing the present invention on a storage device acts to level the wear on memory cells of the storage device, potentially extending the useful life of the storage device.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Memory cells in a storage device are wear leveled. The storage device has an area of static storage and an area of available unused storage. The memory cells are wear leveled by first booting the storage device. Responsive to booting the storage device, a size of the available unused storage on the storage device is discovered. A portion of the area of the static storage is moved to the available unused storage.

Description

WEAR LEVELING MEMORY CELLS
BACKGROUND
[001] Flash memory is a particular type of EEPROM1 Electrically Erasable Programmable Read-Only Memory. Erasing and programming, or writing, in flash memory is performed in blocks of memory cells. NAND flash memory is a specific type of flash memory that uses NAND gates to form the memory cells. NAND flash memory is frequently used in removable USB storage devices and thin client hardware. NAND flash memory is often used as a primary storage device for an embedded operating system.
[002] Memory cells in NAND flash memory wear out over time. Typical memory cells in a NAND flash module last only between 10,000 to 300,000 writes. Reads have no impact on the life of the memory cells.
DESCRIPTION OF THE DRAWINGS
[003] Figure 1 is a block diagram illustrating an embodiment of a system for wear leveling memory cells in a storage device.
[004] Figure 2 is a block diagram illustrating an embodiment of the memory cells of Figure 1.
[005] Figure 3 is a flow chart illustrating an embodiment of a method for wear leveling memory cells in a storage device.
[006] Figure 4 is a flow chart illustrating another embodiment of a method for wear leveling memory cells in a storage device.
DETAILED DESCRIPTION
[007] Figure 1 illustrates one embodiment of a wear leveling system 2 for wear leveling memory cells 4. Wear leveling system 2 includes a storage device 6 and a boot system 8.
[008] Storage device 6 is any type of data or program storage device, for example, magnetic, electronic, or optical memory. In one embodiment, storage device 6 is a flash memory storage device. In another embodiment, storage device 6 is a NAND flash memory storage device. [009] Storage device 6 includes a plurality of memory cells 4. The number of memory cells 4 is directly related to the capacity of the storage device 6 and is typically far greater than may be conveniently illustrated in Figure 1. [0010] Figure 2 illustrates one embodiment of memory cells 4. Memory cells 4 are cells for storing data or information. Memory cells 4 may be logically divided into two different use types. The first is a static area 10 that, in one embodiment, contains the operating system, drivers, and applications and rarely or never changes. The second is a dynamic area 12 containing settings and other data that changes on a regular basis.
[0011] Area of static storage 10 includes all of the cells 4 holding data that infrequently or never changes. Although illustrated in Figure 2 as contiguous cells 4, area of static storage 10 may be either contiguous or noncontiguous. [0012] Area of available unused storage 12 includes all of the cells 4 that are designated as not holding data. Although illustrated in Figure 2 as contiguous cells 4, area of available unused storage 12 may be either contiguous or noncontiguous. [0013] Memory cells 4 may also include area of dynamic storage 14. Area of dynamic storage 14 includes all of the cells 4 holding data that frequently changes. Although illustrated in Figure 2 as contiguous cells 4, area of dynamic storage 14 may be either contiguous or noncontiguous.
[0014] Boot system 8 is any combination of hardware and executable code configured to boot storage device 6, discover a size of the available unused storage on storage device 6, and move a portion of area of static storage 10 to available unused storage 12. In one embodiment, moving the area of the static storage to the available unused storage includes copying the portion of area of static storage 10 and freeing the copied area of the static storage to available unused storage. [0015] In one embodiment boot system 6 is further configured to discover a size of area of static storage 10 on storage device 6. In one embodiment, the size of the portion of area of static storage 10 moved to available unused storage 12 is equal in size to the size of the available unused storage. In an alternative embodiment, the size of the portion moved is equal to the lesser of the size of the available unused storage and the size of area of static storage 10. [0016] In an embodiment of boot system 8, boot system 8 includes BIOS (built in operating system) 16. BIOS 16 is any combination of hardware and executable code configured to initialize storage device 6. In one embodiment, BIOS 16 is configured to execute the functions of boot system 8.
[0017] In one embodiment, boot system 8 is further configured to evaluate whether booting storage device 6 triggers discovering the size of the available unused storage on storage device 6. Alternative embodiments exist for evaluating whether booting storage device 6 triggers discovering the size of the available unused storage on storage device 6. In one embodiment, booting a predetermined number of times triggers the discovering. In another embodiment, booting a predetermined number of times after a predetermined time period has lapsed since the most recent wear leveling for storage device 6, triggers the discovering. In still another embodiment, a boot with a command to initiate wear leveling triggers the discovering.
[0018] Figure 3 is a flow chart representing steps of one embodiment method for wear leveling memory cells 4 in storage device 6. Although the steps represented in
Figure 3 are presented in a specific order, the technology presented herein can be performed in any variation of this order. Furthermore, additional steps may be executed between the steps illustrated in Figure 3.
[0019] System 2 waits 18 until storage device 6 is booted. Storage device 6 is booted 20. In one embodiment, whether booting 20 storage device 6 triggers discovering the size of the available unused storage on storage device 6 is evaluated 22.
[0020] If booting 20 does not trigger the discovering, system 2 again waits 18 until storage device 6 is booted. If booting 20 does trigger the discovering, responsive to the boot of storage device 6, a size of the available unused storage 12 on storage device 6 is discovered 24.
[0021] A portion of area of static storage 10, equal in size to the size of area of available unused storage 12, is moved 26 to area of available unused storage 12. In one embodiment, moving 26 the portion of the area of static storage 10 to available unused storage 12 includes copying the portion of area of static storage 10 to the available unused storage 12 and freeing the copied portion of area of static storage
10 to area of available unused storage 12.
[0022] Figure 4 is a flow chart representing steps of another embodiment method for wear leveling memory cells 4 in storage device 6. Although the steps represented in Figure 4 are presented in a specific order, the technology presented herein can be performed in any variation of this order. Furthermore, additional steps may be executed between the steps illustrated in Figure 4.
[0023] Figure 4 differs from Figure 3 only in the determination of the size of portion of area of static storage 10 to be moved to area of available unused storage 12.
Those steps in Figure 4 which are identical to the corresponding step in Figure 3 are given identical reference numbers to the corresponding steps in Figure 3.
[0024] System 2 waits 18 until storage device 6 is booted. Storage device 6 is booted 20. In one embodiment, whether booting 20 storage device 6 triggers discovering the size of the available unused storage on storage device 6 is evaluated 22.
[0025] If booting 20 does not trigger the discovering, system 2 again waits 18 until storage device 6 is booted. If booting 20 does trigger the discovering, responsive to the boot of storage device 6, a size of the available unused storage 12 on storage device 6 is discovered 24. A size of area of static storage 10 on storage device 6 is also discovered 28.
[0026] A portion of area of static storage 10 is moved 26 to area of available unused storage 12. The size of the portion moved is equal to the lesser of the size of the available unused storage and the size of area of static storage 10.
[0027] In one embodiment, moving 26 the portion of the area of static storage 10 to available unused storage 12 includes copying the portion of area of static storage
10 to the available unused storage 12 and freeing the copied portion of area of static storage 10 to area of available unused storage 12.
[0028] The present invention addresses the condition where a dynamic storage area can wear out, while the static flash area, typically holding an operating system, has thousands of write cycles remaining. Implementing the present invention on a storage device acts to level the wear on memory cells of the storage device, potentially extending the useful life of the storage device. [0029] The foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the invention. Accordingly, the present invention embraces all such alternatives, modifications, and variances that fall within the scope of the appended claims.

Claims

CLAIMSWhat is claimed is:
1. A method for wear leveling memory cells in a storage device having an area of static storage and an area of available unused storage, the method comprising: booting the storage device; responsive to the boot of the storage device, discovering a size of the available unused storage on the storage device; and moving a portion of the area of static storage, equal in size to the size of the available unused storage, to the available unused storage.
2. The method of claim 1 wherein the storage device includes a NAND flash storage.
3. The method of claim 1 further including evaluating whether booting the storage device triggers discovering the size of the available unused storage on the storage device.
4. The method of claim 1 wherein moving the portion of the area of the static storage to the available unused storage includes: copying the portion of the area of static storage, equal in size to the size of the available unused storage, to the available unused storage and freeing the copied portion of the area of the static storage to available unused storage.
5. A method for wear leveling memory cells in a storage device having an area of static storage and an area of available unused storage, the method comprising: booting the storage device; responsive to the boot of the storage device, discovering a size of the available unused storage on the storage device; discovering a size of the area of static storage on the storage device; and moving a portion of the area of the static storage to the available unused storage, the size of the portion moved being equal to the lesser of the size of the available unused storage and the size of the area of static storage.
6. The method of claim 5 wherein the storage device includes a NAND flash storage.
7. The method of claim 5 further including evaluating whether booting the storage device triggers discovering the size of the available unused storage on the storage device.
8. The method of claim 5 wherein moving the portion of the area of the static storage to the available unused storage includes: copying the portion of the area of the static storage to the available unused storage, the size of the portion moved being equal to the lesser of the size of the available unused storage and the size of the area of static storage and freeing the copied portion of the area of the static storage to available unused storage.
9. A system for wear leveling memory cells, the system comprising: a storage device having an area of static storage and an area of available unused storage and a boot system configured to: boot the storage device; discover a size of the available unused storage on the storage device; and move a portion of the area of the static storage, equal in size to the size of the available unused storage, to the available unused storage.
10. The system of claim 9 wherein the storage device includes a NAND flash storage.
11. The system of claim 9 wherein the boot system is further configured to evaluate whether booting the storage device triggers discovering the size of the available unused storage on the storage device.
12. The system of claim 9 wherein moving the portion of the area of the static storage to the available unused storage includes: copying the portion of the area of static storage, equal in size to the size of the available unused storage, to the available unused storage and freeing the copied portion of the area of the static storage to available unused storage.
PCT/US2008/013064 2008-11-24 2008-11-24 Wear leveling memory cells WO2010059146A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/US2008/013064 WO2010059146A1 (en) 2008-11-24 2008-11-24 Wear leveling memory cells
TW098139296A TW201025331A (en) 2008-11-24 2009-11-19 Wear leveling memory cells

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PCT/US2008/013064 WO2010059146A1 (en) 2008-11-24 2008-11-24 Wear leveling memory cells

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016275A (en) * 1998-03-13 2000-01-18 Lg Semicon Co., Ltd. Flash memory wear leveling system and method
US6732221B2 (en) * 2001-06-01 2004-05-04 M-Systems Flash Disk Pioneers Ltd Wear leveling of static areas in flash memory
US20050055495A1 (en) * 2003-09-05 2005-03-10 Nokia Corporation Memory wear leveling
US20070088940A1 (en) * 2005-10-13 2007-04-19 Sandisk Corporation Initialization of flash storage via an embedded controller
US7353325B2 (en) * 1991-09-13 2008-04-01 Sandisk Corporation Wear leveling techniques for flash EEPROM systems

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7353325B2 (en) * 1991-09-13 2008-04-01 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
US6016275A (en) * 1998-03-13 2000-01-18 Lg Semicon Co., Ltd. Flash memory wear leveling system and method
US6732221B2 (en) * 2001-06-01 2004-05-04 M-Systems Flash Disk Pioneers Ltd Wear leveling of static areas in flash memory
US20050055495A1 (en) * 2003-09-05 2005-03-10 Nokia Corporation Memory wear leveling
US20070088940A1 (en) * 2005-10-13 2007-04-19 Sandisk Corporation Initialization of flash storage via an embedded controller

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