WO2010054875A1 - Arrangement of at least two wafers with a bonding connection and method for producing such an arrangement - Google Patents

Arrangement of at least two wafers with a bonding connection and method for producing such an arrangement Download PDF

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Publication number
WO2010054875A1
WO2010054875A1 PCT/EP2009/061832 EP2009061832W WO2010054875A1 WO 2010054875 A1 WO2010054875 A1 WO 2010054875A1 EP 2009061832 W EP2009061832 W EP 2009061832W WO 2010054875 A1 WO2010054875 A1 WO 2010054875A1
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WO
WIPO (PCT)
Prior art keywords
bonding
wafer
bonding material
microns
bond
Prior art date
Application number
PCT/EP2009/061832
Other languages
German (de)
French (fr)
Inventor
Axel Franke
Achim Trautmann
Ando Feyh
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2010054875A1 publication Critical patent/WO2010054875A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261Processes for packaging MEMS devices
    • B81C1/00269Bonding of solid lids or wafers to the substrate
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Definitions

  • the invention relates to an arrangement of at least two wafers with a
  • Bonding of a first and a second bonding material and a method for producing such an arrangement.
  • bonding compounds can be used. Different methods have been developed for the realization of bond connections. Examples of known bonding methods include eutectic bonding, thermocompression bonding and direct bonding.
  • bonding materials there are several bonding materials available, wherein the bonding materials may be different on the two wafers to be joined.
  • the combinations Au-Si, Al-Ge or Au-Sn are known as bonding materials.
  • a disadvantage of eutectic bonding is that, due to the formation of a liquid phase, bleeding and melting of the bonding material occur. As a result, the layer thickness of the bonding material between the wafers changes, and the setting of a defined distance between the wafers is not possible.
  • the reduction of the layer thickness of the bonding material is associated with an increase in the layer area of the bonding material.
  • additional, targeted countermeasures are required. So For example, as a countermeasure, special structures such as trenches are provided to prevent bleeding of the deliquescent bonding material.
  • thermocompression bonding and direct bonding on the other hand, strict requirements are placed on the surfaces to be joined in their hitherto known embodiment. Thus, only bonding surfaces with very low roughness can be considered in these bonding methods.
  • Wafer known wherein various bonding materials are described as suitable. It is suggested to use gold bondpads. As other materials which are also suitable to be joined together, mention is made of silicon, indium, aluminum, copper, silver, alloys of these and compounds thereof.
  • the inventive arrangement and the inventive method have the advantage that the formation of a reliable and stable bond of two wafers is achieved in a simple manner.
  • This beneficial effect is achieved by a special, specific
  • the invention also makes it possible to realize a bond without noticeable melting, crimping or bleeding of the bonding materials occurring.
  • no liquid phase is formed by the proposed combination of materials (eutectic). Consequently, this makes it possible to obtain a defined, i. to set a controlled distance between the two wafers to be joined.
  • the mechanical and electrical properties of the bond connection can be set to a greater extent than with conventional eutectic connections using the bond parameters bonding pressure, bond temperature and bonding time. Comparable mechanical or electrical properties of the bond to be formed can be realized in various ways. For example, instead of a higher bond temperature, a longer bond time can be selected.
  • the process presented no critical temperature, as otherwise known from eutectic bonding, is present in the process presented.
  • the process can be carried out so that only low temperature loads of up to 400 0 C occur. This ensures a simple process control.
  • the invention also offers the advantage that no special requirements are placed on the roughness of the bonding surfaces. By contrast, in previous methods, for example in direct bonding, a very low roughness of the bonding surfaces is required.
  • the method according to the invention also allows the wafers to be joined to have an anti-adhesion layer, for example an anti-adhesion layer on micromechanical structures.
  • the method is thus compatible with possible non-stick layers.
  • Figure 1 shows an embodiment of the invention before the bonding process of two wafers to be joined together
  • FIG. 2 shows the two wafers from FIG. 1 after the bonding process.
  • the method according to the invention for producing a bond connection between at least two wafers basically comprises the following steps: a) applying a first bonding material on a first wafer, wherein as the first bonding material aluminum or an aluminum alloy is selected, b) applying a second bonding material on a second wafer, wherein gold is selected as the second bonding material, and c) performing a bonding process, the first and the second
  • Bond material are joined together to achieve a wafer-to-wafer bond.
  • Fig. 1 the two wafers 1, 4 are shown, which are to be joined together.
  • the first bonding material 3 has been applied according to step a).
  • aluminum (Al) or an aluminum alloy was selected.
  • aluminum alloy AISi, AICu or AISiCu can be provided.
  • a closed circumferential bonding frame 3a is formed in step a) by the application of the first bonding material 3.
  • the later bond has a self-contained, circumferential shape.
  • an electrical contact pad 3b is formed in step a) by the application of the first bonding material 3.
  • a suitable thickness of the first bonding material 3 is 200 nm to 3 ⁇ m.
  • a wafer 1 with a MEMS (microelectromechanical system) element 2 was selected in step a).
  • a second bonding material 6 is applied to a second wafer 4, wherein the second bonding material 6 is gold (Au). It is provided in this embodiment that the second bonding material 6 is not applied directly to the second wafer 4, but on a bonding surface 7.
  • the bonding surface 7 forms a closed circumferential bonding frame 7a or an electrical contact pad 7b of the second wafer 4. While an interior with a set internal pressure is formed by the closed circumferential bonding frame 7a after a later-to-be-performed bonding operation is generated, the electrical contact pad 7b later serves an electrical chip-to-chip contact.
  • Width values also apply to the bonding frame in the layer region of the second bonding material 6a made of gold and to the bonding frame 3a made of the first bonding material 3 of the first wafer 1.
  • width of the electrical contact pad 7b of the second wafer 4 a size of at most 50 ⁇ m, in particular smaller than 30 ⁇ m, is likewise proposed. These width values also apply to the contact pad in the layer region of the second bonding material 6b made of gold and also to the contact pad 3b made of the first bonding material 3 of the first wafer 1.
  • the material of the bonding surface 7 that is, as the material of the bonding frame 7a or the electric bonding pad 7b on the second wafer 4, it is preferable to select Al (aluminum), AISi, AICu or AISiCu.
  • the second bonding material 6 can also consist of a composition of the materials mentioned as needed. In this case, the bonding frame 7a or the electrical
  • Contact pad 7b has a thickness of 200 nm to 3 ⁇ m.
  • step b) gold can be applied as the second bonding material 6 with a sputtering or electroplating process. Both processes are fundamentally suitable, since both processes are within the framework of the presented
  • the sputter process offers a good opportunity to apply gold, in particular thicker than 2 ⁇ m. However, if gold is to be applied 1-30 ⁇ m thick, this can preferably also be achieved with a galvanic process.
  • the presented method can advantageously be used for versatile application examples with regard to the selection of the two wafers 1, 4 to be connected.
  • the first wafer 1 in step a) may be an ME MS wafer, ie the first wafer 1 comprises at least one MEMS element 2.
  • the second wafer 4 a selection is also possible for the second wafer 4 a selection.
  • the second wafer 4 is a cap wafer.
  • the second wafer 4 can have an ASIC (application-specific integrated circuit) element 5, ie the second wafer 4 is an ASIC wafer.
  • ASIC application-specific integrated circuit
  • FIG. 1 shows the particularly advantageous embodiment, in which the first wafer 1 has a MEMS (microelectromechanical system) element 2 and the second wafer 4 has an ASIC (application-specific integrated circuit) element 5.
  • the second wafer 4 serves as a cap wafer at the same time.
  • a bonding process is carried out, wherein the first 3 and the second bonding material 6 are joined together to achieve a wafer-to-wafer bonding connection.
  • This bond connection does not serve for external contacting of circuits or sensors, but rather an internal wafer-to-wafer connection. Thus, this wafer-to-
  • wafer bonding from a bond of an external wire to a wafer technically.
  • the two wafers 1, 4 can be adjusted and bonded by means of marks.
  • FIG. 1 The state of the wafers 1, 4 connected in this way is shown in FIG.
  • a first wafer 1 and a second wafer 4 are connected to one another by a bonding connection, and the bond connection comprises a first bonding material 3 and a second bonding material 6. It is important that the first bonding material
  • the bond is realized by aluminum Al or by an aluminum alloy, while the second bonding material 6 is gold.
  • the transition from the first 3 to the second bonding material 6 is the actual bond 8 between the two wafers 1, 4.
  • the actual bond 8 is the actual bond 8 between the two wafers 1, 4.
  • Bond connection 8 here comprises the bond connection of the bonding frame 8a and the bond connection of the electrical bond pad 8b. It is proposed to perform the bonding process with a bonding pressure of 0.5 to 15 MPa. This pressure range is on the one hand sufficiently large enough to bring about a reliable material connection of the two bonding materials 3, 6, on the other hand not unnecessarily too large, so that possible mechanical damage can be avoided by excessive pressure.
  • a temperature at and below 400 0 C in particular a temperature of 200 0 C to 400 0 C is considered.
  • the bonding time is from a few minutes to an hour.
  • the proposed method is also suitable for connecting a plurality of wafers with a number of wafers to be connected in a row greater than two.
  • a stacking of several wafers can be achieved.
  • the individual wafers arranged one above the other in the stack by means of a bonding connection can comprise both ASIC and MEMS elements.
  • Wafern 1, 4 well defined in wide ranges of at least 2 microns, in particular in a range of 2 microns to 30 microns, can be adjusted. This is made possible by the combination of bonding materials described above, which hardly form fluxes during the bonding process and thus maintain their respective layer thicknesses. These respective layer thicknesses are shown in FIG.
  • the invention ensures a controllable and simple production method of a wafer-to-wafer bond connection and provides a reliable arrangement of two wafers 1, 4 with a stable bond connection.
  • There are disadvantages arising from the state of the Technique are known, eliminated or at least greatly reduced.
  • deliquescence of the bonding materials 3, 6, 7 hardly occurs during the bonding process, as is otherwise known from previous methods.
  • the invention allows, for example, that the environment of the bond connections is free of structures against the flow of the bonding materials 3, 6, 7, in particular structures in the form of trenches. So-called stop trenches, which were necessary in previous arrangements of the wafer-to-wafer bond connections, are now advantageously dispensed with.

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Abstract

An arrangement of at least two wafers (1; 4) is described, a first wafer (1) and a second wafer (4) being connected to each other by a bonding connection.  Furthermore, a method for producing such an arrangement is proposed, the method comprising the following steps: a) applying a first bonding material (3) to a first wafer (1), wherein aluminium (Al) or an aluminium alloy is selected as the first bonding material (3), b) applying a second bonding material (6) to a second wafer (4), wherein gold (Au) is selected as the second bonding material, and c) carrying out a bonding process, wherein the first bonding material (3) and the second bonding material (6) are connected to each other to achieve a wafer-to-wafer bonding connection.

Description

ROBERT BOSCH GMBH, 70442 Stuttgart ROBERT BOSCH GMBH, 70442 Stuttgart
Anordnung von mindestens zwei Wafern mit einer Bondverbindung und Verfahren zur Herstellung einer solchen AnordnungArrangement of at least two wafers with a bond connection and method for producing such an arrangement
Stand der TechnikState of the art
Die Erfindung betrifft eine Anordnung von mindestens zwei Wafern mit einerThe invention relates to an arrangement of at least two wafers with a
Bondverbindung aus einem ersten und einem zweiten Bondmaterial und ein Verfahren zur Herstellung einer solchen Anordnung.Bonding of a first and a second bonding material and a method for producing such an arrangement.
Um zwei Wafer miteinander zu verbinden, können Bondverbindungen eingesetzt werden. Zur Realisierung von Bondverbindungen sind unterschiedliche Verfahren entwickelt worden. Zu den bekannten Bondverfahren zählen beispielsweise das eutektische Bonden, das Thermokompressionsbonden sowie das Direktbonden.To connect two wafers with each other, bonding compounds can be used. Different methods have been developed for the realization of bond connections. Examples of known bonding methods include eutectic bonding, thermocompression bonding and direct bonding.
Grundsätzlich stehen dabei mehrere Bondmaterialien zur Verfügung, wobei die Bondmaterialien auf den beiden zu verbindenden Wafern unterschiedlich sein können. So sind beim eutektischen Bonden als Bondmaterialien die Kombinationen Au-Si, Al-Ge oder auch Au-Sn bekannt. Nachteilig wirkt sich bei einem eutektischen Bonden jedoch aus, dass dabei aufgrund einer Ausbildung einer flüssigen Phase ein Verlaufen und Aufschmelzen des Bondmaterials auftritt. Dadurch ändert sich die Schichtdicke des Bondmaterials zwischen den Wafern, und die Einstellung eines definierten Abstands zwischen den Wafern ist nicht möglich. Darüber hinaus ist die Reduzierung der Schichtdicke des Bondmaterials verbunden mit einer Vergrößerung der Schichtfläche des Bondmaterials. Um solch eine ungewollte Verbreiterung der Schichtfläche des Bondmaterials zu verhindern, sind daher zusätzliche, gezielte Gegenmaßnahmen erforderlich. So werden als eine Gegenmaßnahme beispielsweise spezielle Strukturen wie Gräben vorgesehen, die ein Verlaufen des zerfließenden Bondmaterials hindern sollen.Basically, there are several bonding materials available, wherein the bonding materials may be different on the two wafers to be joined. For eutectic bonding, the combinations Au-Si, Al-Ge or Au-Sn are known as bonding materials. A disadvantage of eutectic bonding, however, is that, due to the formation of a liquid phase, bleeding and melting of the bonding material occur. As a result, the layer thickness of the bonding material between the wafers changes, and the setting of a defined distance between the wafers is not possible. In addition, the reduction of the layer thickness of the bonding material is associated with an increase in the layer area of the bonding material. In order to prevent such unwanted broadening of the layer surface of the bonding material, therefore, additional, targeted countermeasures are required. So For example, as a countermeasure, special structures such as trenches are provided to prevent bleeding of the deliquescent bonding material.
Beim Thermokompressionsbonden sowie beim Direktbonden werden in ihrer bisher bekannten Ausführungsform andererseits strenge Anforderungen an die zu verbindenden Flächen gestellt. So können bei diesen Bondverfahren nur Bondflächen mit sehr geringer Rauhigkeit in Betracht gezogen werden.On thermocompression bonding and direct bonding, on the other hand, strict requirements are placed on the surfaces to be joined in their hitherto known embodiment. Thus, only bonding surfaces with very low roughness can be considered in these bonding methods.
Weiter ist beispielsweise aus EP 1071126 Bl das Zusammenbonden zweierFurther, for example, from EP 1071126 Bl, the bonding together two
Wafer bekannt, wobei verschiedene Bondmaterialien als geeignet beschrieben werden. Es wird vorgeschlagen, Bondpads aus Gold zu verwenden. Als andere Materialien, die ebenso geeignet sind, miteinander verbunden zu werden, werden Silizium, Indium, Aluminium, Kupfer, Silber, Legierungen aus diesen und Verbindungen aus diesen genannt.Wafer known, wherein various bonding materials are described as suitable. It is suggested to use gold bondpads. As other materials which are also suitable to be joined together, mention is made of silicon, indium, aluminum, copper, silver, alloys of these and compounds thereof.
Obwohl die bekannten Bondverbindungen grundsätzlich eine Verbindung zweier Wafer ermöglichen, gibt es wie oben ausgeführt dennoch Bedarf an einer Verbesserung.Although the known bonding connections in principle allow a connection of two wafers, there is still a need for improvement as stated above.
Die bisher bekannten, oben beschriebenen Bondverfahren erfordern zudem oftmals eine gründliche Reinigung der Bondflächen zeitnah vor dem eigentlichen Bondprozess. Eine Oberflächenbehandlung der Bondflächen ist notwendig, um beispielsweise Oxide, die sich auf alle bisher bekannten Bondmaterialien außer Gold bilden, zu entfernen. Solche Oberflächenbehandlung ist also notwendig, um letztendlich eine zuverlässige Bondverbindung zu ermöglichen. Jedoch ist sie prozesstechnisch sehr aufwändig, insbesondere wenn M E M S -Strukturen (microelectromechanical Systems) vorliegen. Das Vorhandensein von freibeweglichen Strukturen, die zum Teil möglicherweise noch mit einer Antihaftschicht versehen sind, erschwert die Oberflächenbehandlung zusätzlich.In addition, the previously known bonding methods described above often require a thorough cleaning of the bonding surfaces shortly before the actual bonding process. A surface treatment of the bonding surfaces is necessary, for example, to remove oxides which form on all previously known bonding materials other than gold. Such surface treatment is therefore necessary to ultimately enable a reliable bond. However, it is technically very complex, especially when M E M S structures (microelectromechanical systems) are present. The presence of freely movable structures, some of which may still be provided with an anti-adhesion layer, further complicates the surface treatment.
In solchen Fällen scheiden gängige Reinigungsverfahren wie nasschemisches Abätzen der Oxide aus. Vorteile der ErfindungIn such cases, common cleaning methods such as wet-chemical etching of the oxides are eliminated. Advantages of the invention
Die erfindungsgemäße Anordnung und das erfindungsgemäße Verfahren haben den Vorteil, dass die Ausbildung einer zuverlässigen und stabilen Bondverbindung zweier Wafer auf eine einfache Weise erzielt wird. Insbesondere ist es nicht notwendig, dass eine oder gar beide Bondflächen der zu verbindenden Wafer vor dem Bonden gereinigt werden muss. Dies vereinfacht die Prozessführung erheblich und stellt zudem eine kostengünstige Lösung dar, die insbesondere für einen industriellen Einsatz eine zentrale Bedeutung hat. Erreicht wird diese vorteilhafte Wirkung durch eine spezielle, bestimmteThe inventive arrangement and the inventive method have the advantage that the formation of a reliable and stable bond of two wafers is achieved in a simple manner. In particular, it is not necessary that one or even both bonding surfaces of the wafers to be bonded must be cleaned before bonding. This considerably simplifies the process management and, moreover, represents a cost-effective solution which is of central importance, in particular, for industrial use. This beneficial effect is achieved by a special, specific
Kombination der Bondmaterialien.Combination of bonding materials.
Auch erlaubt die Erfindung, eine Bondverbindung zu realisieren, ohne dass dabei ein merkliches Aufschmelzen, Verquetschen oder Verlaufen der Bondmaterialien auftritt. Insbesondere wird durch die vorgeschlagene Materialkombination keine flüssige Phase ausgebildet (Eutektikum). Folglich wird dadurch ermöglicht, einen definierten, d.h. bestimmten Abstand zwischen den beiden zu verbindenden Wafer kontrolliert einzustellen.The invention also makes it possible to realize a bond without noticeable melting, crimping or bleeding of the bonding materials occurring. In particular, no liquid phase is formed by the proposed combination of materials (eutectic). Consequently, this makes it possible to obtain a defined, i. to set a controlled distance between the two wafers to be joined.
Ein weiterer Vorteil der Erfindung resultiert aus dem relativ großenAnother advantage of the invention results from the relatively large
Prozessfenster bezüglich der einzelnen Prozessparameter beim Bonden. Bei der erfindungsgemäß vorgesehenen Materialkombination können mit den Bondparametern Bonddruck, Bondtemperatur und Bondzeit die mechanischen und elektrischen Eigenschaften der Bondverbindung in weiterem Umfang eingestellt werden als bei üblichen eutektischen Verbindungen. Vergleichbare mechanische oder elektrische Eigenschaften der zu bildenden Bondverbindung können dabei auf verschiedenen Wegen realisiert werden. So kann beispielsweise statt einer höheren Bondtemperatur eine längere Bondzeit gewählt werden.Process window regarding the individual process parameters during bonding. In the case of the material combination provided according to the invention, the mechanical and electrical properties of the bond connection can be set to a greater extent than with conventional eutectic connections using the bond parameters bonding pressure, bond temperature and bonding time. Comparable mechanical or electrical properties of the bond to be formed can be realized in various ways. For example, instead of a higher bond temperature, a longer bond time can be selected.
Insbesondere ist beim vorgestellten Verfahren keine kritische Temperatur, wie sonst aus dem eutektischen Bonden bekannt, vorhanden. Das Verfahren kann so durchgeführt werden, dass dabei nur geringe Temperaturbelastungen von bis zu 400 0C auftreten. So wird eine einfache Prozesskontrolle gewährleistet. Zusätzlich bietet die Erfindung auch den Vorteil, dass keine besonderen Anforderungen an Rauhigkeit der Bondflächen gestellt werden. Hingegen ist bei bisherigen Verfahren, beispielsweise beim Direktbonden, eine sehr geringe Rauhigkeit der Bondflächen erforderlich.In particular, no critical temperature, as otherwise known from eutectic bonding, is present in the process presented. The process can be carried out so that only low temperature loads of up to 400 0 C occur. This ensures a simple process control. In addition, the invention also offers the advantage that no special requirements are placed on the roughness of the bonding surfaces. By contrast, in previous methods, for example in direct bonding, a very low roughness of the bonding surfaces is required.
Auch erlaubt das erfindungsgemäße Verfahren, dass die zu verbindenden Wafer eine Antihaftschicht aufweisen, beispielsweise eine Antihaftschicht auf mikromechanischen Strukturen. Das Verfahren ist also kompatibel zu möglichen Antihaftschichten.The method according to the invention also allows the wafers to be joined to have an anti-adhesion layer, for example an anti-adhesion layer on micromechanical structures. The method is thus compatible with possible non-stick layers.
Ein weiterer Vorteil ergibt sich dadurch, dass das Aufbringen von Aluminium oder Gold auf einem Wafer an sich bekannt ist und hierfür zuverlässige Methoden entwickelt worden sind. Auf diese Methoden kann nun bequem zurückgegriffen werden.Another advantage results from the fact that the application of aluminum or gold on a wafer is known per se and reliable methods have been developed for this purpose. These methods can now be used conveniently.
Vorteilhafte Weiterbildungen der Erfindung sind in den Unteransprüchen angegeben und in der Beschreibung beschrieben.Advantageous developments of the invention are specified in the subclaims and described in the description.
Zeichnungdrawing
Ausführungsbeispiele der Erfindung werden anhand der Zeichnungen und der nachfolgenden Beschreibung näher erläutert. Es zeigen:Embodiments of the invention will be explained in more detail with reference to the drawings and the description below. Show it:
Figur 1 ein Ausführungsbeispiel der Erfindung vor dem Bondprozess zweier miteinander zu verbindenden Wafer, undFigure 1 shows an embodiment of the invention before the bonding process of two wafers to be joined together, and
Figur 2 die beiden Wafer aus Fig. 1 nach dem Bondprozess.FIG. 2 shows the two wafers from FIG. 1 after the bonding process.
Beschreibung der AusführungsbeispieleDescription of the embodiments
Das erfindungsgemäße Verfahren zur Herstellung einer Bondverbindung zwischen mindestens zwei Wafern umfasst grundsätzlich folgende Schritte: a) Aufbringen eines ersten Bondmaterials auf einem ersten Wafer, wobei als das erste Bondmaterial Aluminium oder eine Aluminiumlegierung ausgewählt wird, b) Aufbringen eines zweiten Bondmaterials auf einem zweiten Wafer, wobei als das zweite Bondmaterial Gold ausgewählt wird, und c) Durchführen eines Bondprozesses, wobei das erste und das zweiteThe method according to the invention for producing a bond connection between at least two wafers basically comprises the following steps: a) applying a first bonding material on a first wafer, wherein as the first bonding material aluminum or an aluminum alloy is selected, b) applying a second bonding material on a second wafer, wherein gold is selected as the second bonding material, and c) performing a bonding process, the first and the second
Bondmaterial miteinander verbunden werden zur Erreichung einer Wafer-to- Wafer Bondverbindung.Bond material are joined together to achieve a wafer-to-wafer bond.
In Fig. 1 sind die beiden Wafer 1, 4 dargestellt, die miteinander zu verbinden sind. Auf dem ersten Wafer 1 ist gemäß Schritt a) das erste Bondmaterial 3 aufgebracht worden. Als das erste Bondmaterial 3 wurde Aluminium (AI) oder eine Aluminiumlegierung ausgewählt. Als Aluminumlegierung kann AISi, AICu oder AISiCu vorgesehen werden.In Fig. 1, the two wafers 1, 4 are shown, which are to be joined together. On the first wafer 1, the first bonding material 3 has been applied according to step a). As the first bonding material 3, aluminum (Al) or an aluminum alloy was selected. As aluminum alloy AISi, AICu or AISiCu can be provided.
Vorteilhaft wird im Schritt a) durch das Aufbringen des ersten Bondmaterials 3 ein geschlossen umlaufender Bondrahmen 3a gebildet. Daraus resultiert, dass die spätere Bondverbindung eine ebenfalls in sich geschlossene, umlaufende Form aufweist. Alternativ oder zusätzlich hierzu ist es auch möglich, dass im Schritt a) durch das Aufbringen des ersten Bondmaterials 3 ein elektrischer Kontaktpad 3b gebildet wird. In diesem Fall entsteht durch die spätere Bondverbindung eine elektrische Kontaktierung zwischen dem ersten Wafer 1 und dem zweiten Wafer 4. Eine geeignete Dicke des ersten Bondmaterials 3 beträgt 200 nm bis 3 μm.Advantageously, a closed circumferential bonding frame 3a is formed in step a) by the application of the first bonding material 3. As a result, the later bond has a self-contained, circumferential shape. Alternatively or additionally, it is also possible that in step a) by the application of the first bonding material 3, an electrical contact pad 3b is formed. In this case, an electrical contact between the first wafer 1 and the second wafer 4 is created by the later bonding connection. A suitable thickness of the first bonding material 3 is 200 nm to 3 μm.
Im Ausführungsbeispiel gemäß Fig. 1 wurde im Schritt a) ein Wafer 1 mit einem MEMS (microelectromechanical System)- Element 2 ausgewählt.In the exemplary embodiment according to FIG. 1, a wafer 1 with a MEMS (microelectromechanical system) element 2 was selected in step a).
Weiter wird gemäß Schritt b) ein zweites Bondmaterial 6 auf einem zweiten Wafer 4 aufgebracht, wobei das zweite Bondmaterial 6 Gold (Au) ist. Es ist in diesem Ausführungsbeispiel vorgesehen, dass das zweite Bondmaterial 6 nicht direkt auf dem zweiten Wafer 4, sondern auf einer Bondfläche 7 aufgebracht wird. Die Bondfläche 7 bildet einen geschlossen umlaufenden Bondrahmen 7a oder einen elektrischen Kontaktpad 7b des zweiten Wafers 4. Während durch den geschlossen umlaufenden Bondrahmen 7a nach einem später zu erfolgenden Bondvorgang ein Innenraum mit einem eingestellten Innendruck erzeugt wird, dient der elektrische Kontaktpad 7b später einem elektrischen Chip- to-Chip Kontakt.Further, according to step b), a second bonding material 6 is applied to a second wafer 4, wherein the second bonding material 6 is gold (Au). It is provided in this embodiment that the second bonding material 6 is not applied directly to the second wafer 4, but on a bonding surface 7. The bonding surface 7 forms a closed circumferential bonding frame 7a or an electrical contact pad 7b of the second wafer 4. While an interior with a set internal pressure is formed by the closed circumferential bonding frame 7a after a later-to-be-performed bonding operation is generated, the electrical contact pad 7b later serves an electrical chip-to-chip contact.
Bezüglich der Breite des Bondrahmens 7a des zweiten Wafers 4 wird eine Größe von maximal 50 μm, insbesondere maximal 30 μm, vorgeschlagen. DieseWith regard to the width of the bonding frame 7a of the second wafer 4, a maximum size of 50 μm, in particular a maximum of 30 μm, is proposed. These
Breitenwerte gelten ebenso für den Bondrahmen im Schichtbereich des zweiten Bondmaterials 6a aus Gold als auch für den Bondrahmen 3a aus dem ersten Bondmaterial 3 des ersten Wafers 1.Width values also apply to the bonding frame in the layer region of the second bonding material 6a made of gold and to the bonding frame 3a made of the first bonding material 3 of the first wafer 1.
Bezüglich der Breite des elektrischen Kontaktpads 7b des zweiten Wafers 4 wird ebenfalls eine Größe von maximal 50 μm, insbesondere kleiner als 30 μm, vorgeschlagen. Diese Breitenwerte gelten ebenso für den Kontaktpad im Schichtbereich des zweiten Bondmaterials 6b aus Gold als auch für den Kontaktpad 3b aus dem ersten Bondmaterial 3 des ersten Wafers 1.With regard to the width of the electrical contact pad 7b of the second wafer 4, a size of at most 50 μm, in particular smaller than 30 μm, is likewise proposed. These width values also apply to the contact pad in the layer region of the second bonding material 6b made of gold and also to the contact pad 3b made of the first bonding material 3 of the first wafer 1.
Als Material der Bondfläche 7, also als Material des Bondrahmens 7a oder des elektrischen Bondpads 7b auf dem zweiten Wafer 4, wird bevorzugt AI (Aluminium), AISi, AICu oder AISiCu ausgewählt. Das zweite Bondmaterial 6 kann je nach Bedarf auch aus einer Zusammensetzung der genannten Materialien bestehen. Dabei weist der Bondrahmen 7a oder der elektrischeAs the material of the bonding surface 7, that is, as the material of the bonding frame 7a or the electric bonding pad 7b on the second wafer 4, it is preferable to select Al (aluminum), AISi, AICu or AISiCu. The second bonding material 6 can also consist of a composition of the materials mentioned as needed. In this case, the bonding frame 7a or the electrical
Kontaktpad 7b eine Dicke von 200 nm bis 3 μm auf.Contact pad 7b has a thickness of 200 nm to 3 μm.
Im übrigen kann im Schritt b) Gold als das zweite Bondmaterial 6 mit einem Sputter- oder Galvanik- Prozess aufgebracht werden. Beide Prozesse sind grundsätzlich geeignet, da beide Prozesse im Rahmen des vorgestelltenMoreover, in step b) gold can be applied as the second bonding material 6 with a sputtering or electroplating process. Both processes are fundamentally suitable, since both processes are within the framework of the presented
Verfahrens zuverlässig und kontrolliert durchgeführbar sind. Der Sputter- Prozess bietet eine gute Möglichkeit, Gold insbesondere dicker als 2 μm aufzubringen. Soll jedoch Gold 1-30 μm dick aufgebracht werden, kann dies bevorzugt auch mit einem Galvanik- Prozess realisiert werden.Method reliable and controlled carried out. The sputter process offers a good opportunity to apply gold, in particular thicker than 2 μm. However, if gold is to be applied 1-30 μm thick, this can preferably also be achieved with a galvanic process.
Das vorgestellte Verfahren ist bezüglich der Auswahl der beiden zu verbindenden Wafers 1, 4 vorteilhafterweise für vielseitige Anwendungsbeispiele einsetzbar. Wie bereits oben erwähnt, kann der erste Wafer 1 im Schritt a) ein M E MS- Wafer sein, d.h. der erste Wafer 1 umfasst mindestens ein MEMS-Element 2. Im Schritt b) ist ebenso für den zweiten Wafer 4 eine Auswahl möglich. So ist der zweite Wafer 4 beispielsweise ein Kappenwafer. Alternativ oder zusätzlich hierzu kann der zweite Wafer 4 ein ASIC (application-specific integrated circuit)- Element 5 aufweisen, d.h. der zweite Wafer 4 ist ein ASIC-Wafer.The presented method can advantageously be used for versatile application examples with regard to the selection of the two wafers 1, 4 to be connected. As already mentioned above, the first wafer 1 in step a) may be an ME MS wafer, ie the first wafer 1 comprises at least one MEMS element 2. In step b) is also possible for the second wafer 4 a selection. For example, the second wafer 4 is a cap wafer. Alternatively or additionally, the second wafer 4 can have an ASIC (application-specific integrated circuit) element 5, ie the second wafer 4 is an ASIC wafer.
In Fig. 1 ist die besonders vorteilhafte Ausführungsform gezeigt, bei der der erste Wafer 1 ein MEMS (microelectromechanical System)- Element 2 aufweist und der zweite Wafer 4 ein ASIC (application-specific integrated circuit)- Element 5 aufweist. Hier dient der zweite Wafer 4 gleichzeitig als ein Kappenwafer.FIG. 1 shows the particularly advantageous embodiment, in which the first wafer 1 has a MEMS (microelectromechanical system) element 2 and the second wafer 4 has an ASIC (application-specific integrated circuit) element 5. Here, the second wafer 4 serves as a cap wafer at the same time.
In einem Schritt c) wird schließlich ein Bondprozess durchgeführt, wobei das erste 3 und das zweite Bondmaterial 6 miteinander verbunden werden zur Erreichung einer Wafer-to- Wafer Bondverbindung. Diese Bondverbindung dient also nicht einer externen Kontaktierung von Schaltungen oder Sensoren, sondern vielmehr einer internen Wafer-to-Wafer- Verbindung. Damit ist diese Wafer-to-Finally, in a step c), a bonding process is carried out, wherein the first 3 and the second bonding material 6 are joined together to achieve a wafer-to-wafer bonding connection. This bond connection does not serve for external contacting of circuits or sensors, but rather an internal wafer-to-wafer connection. Thus, this wafer-to-
Wafer Bondverbindung technisch klar zu unterscheiden von einer Bondverbindung eines externen Drahtes zu einem Wafer. Beim Wafer-to-Wafer Bonden können die beiden Wafer 1, 4 mittels Marken aufeinander justiert und gebondet werden.Clearly differentiate wafer bonding from a bond of an external wire to a wafer technically. In the wafer-to-wafer bonding, the two wafers 1, 4 can be adjusted and bonded by means of marks.
Der Zustand der so miteinander verbundenen Wafer 1, 4 ist in Fig. 2 dargestellt. Es wird im Ergebnis eine Anordnung von zwei Wafern 1, 4 erzielt, wobei ein erster Wafer 1 und ein zweiter Wafer 4 durch eine Bondverbindung miteinander verbunden sind, und die Bondverbindung ein erstes Bondmaterial 3 und ein zweites Bondmaterial 6 aufweist. Wichtig ist dabei, dass das erste BondmaterialThe state of the wafers 1, 4 connected in this way is shown in FIG. As a result, an arrangement of two wafers 1, 4 is achieved, wherein a first wafer 1 and a second wafer 4 are connected to one another by a bonding connection, and the bond connection comprises a first bonding material 3 and a second bonding material 6. It is important that the first bonding material
3 der Bondverbindung durch Aluminium AI oder durch eine Aluminiumlegierung realisiert ist, während das zweite Bondmaterial 6 Gold ist.3 of the bond is realized by aluminum Al or by an aluminum alloy, while the second bonding material 6 is gold.
Der Übergang vom ersten 3 zum zweiten Bondmaterial 6 ist die eigentliche Bondverbindung 8 zwischen den beiden Wafern 1, 4. Die eigentlicheThe transition from the first 3 to the second bonding material 6 is the actual bond 8 between the two wafers 1, 4. The actual
Bondverbindung 8 umfasst hier die Bondverbindung des Bondrahmens 8a sowie die Bondverbindung des elektrischen Bondpads 8b. Es wird vorgeschlagen, den Bondprozess mit einem Bonddruck von 0,5 bis 15 MPa durchzuführen. Dieser Druckbereich ist einerseits ausreichend gross genug, um eine zuverlässige materielle Verbindung der beiden Bondmaterialien 3, 6 herbeizuführen, andererseits nicht unnötig zu gross, sodass mögliche mechanische Schäden durch zu starke Druckeinwirkung vermieden werden können.Bond connection 8 here comprises the bond connection of the bonding frame 8a and the bond connection of the electrical bond pad 8b. It is proposed to perform the bonding process with a bonding pressure of 0.5 to 15 MPa. This pressure range is on the one hand sufficiently large enough to bring about a reliable material connection of the two bonding materials 3, 6, on the other hand not unnecessarily too large, so that possible mechanical damage can be avoided by excessive pressure.
Als eine geeignete Prozesstemperatur beim Bonden wird eine Temperatur um und unterhalb von 400 0C, insbesondere eine Temperatur von 200 0C bis 400 0C betrachtet. Die Bondzeit beträgt von wenigen Minuten bis zu einer Stunde.As a suitable process temperature during bonding, a temperature at and below 400 0 C, in particular a temperature of 200 0 C to 400 0 C is considered. The bonding time is from a few minutes to an hour.
Es wird darauf hingewiesen, dass das vorgestellte Verfahren auch zum Verbinden mehrerer Wafer mit einer Anzahl der miteinader zu verbindenden Wafer größer als zwei geeignet ist. So können mit dem erfindungsgemäßen Verfahren eine Stapelung mehrerer Wafer erzielt werden. Die in der Stapelung miteinander mittels Bondverbindung verbundenen, übereinander angeordneten einzelnen Wafer können sowohl ASIC- als auch MEMS-Elemente umfassen.It should be noted that the proposed method is also suitable for connecting a plurality of wafers with a number of wafers to be connected in a row greater than two. Thus, with the method according to the invention, a stacking of several wafers can be achieved. The individual wafers arranged one above the other in the stack by means of a bonding connection can comprise both ASIC and MEMS elements.
Besonders vorteilhaft ist, dass der Abstand 9 zwischen den einzelnen Wafern 1, 4, entweder in der Stapelung oder auch bei einer Anordnung mit genau zweiIt is particularly advantageous that the distance 9 between the individual wafers 1, 4, either in the stacking or even in an arrangement with exactly two
Wafern 1, 4, wohldefiniert in weiten Bereichen von mindestens 2 μm, insbesondere in einem Bereich von 2 μm bis 30 μm, eingestellt werden kann. Dies wird ermöglicht durch die zuvor beschriebene Kombination der Bondmaterialien, die beim Bondprozess kaum flüsse Phase bilden und so ihre jeweiligen Schichtdicken beibehalten. Diese jeweiligen Schichtdicken sind in Fig.Wafern 1, 4, well defined in wide ranges of at least 2 microns, in particular in a range of 2 microns to 30 microns, can be adjusted. This is made possible by the combination of bonding materials described above, which hardly form fluxes during the bonding process and thus maintain their respective layer thicknesses. These respective layer thicknesses are shown in FIG.
2 im einzelnen die Schichtdicke der Bondflächen 7, die Schichtdicke des zweiten Bondmaterials 6 und die Schichtdicke des ersten Bondmaterials 3. Im Ergebnis wird ein einstellbarer, wohldefinierter Abstand 9 zwischen MEMS- und ASIC- Wafern, MEMS- und Kappenwafern oder zwischen Chipstapeln gewährleistet.2 shows in detail the layer thickness of the bonding surfaces 7, the layer thickness of the second bonding material 6 and the layer thickness of the first bonding material 3. As a result, an adjustable, well-defined distance 9 between MEMS and ASIC wafers, MEMS and cap wafers or between chip stacks is ensured.
Zusammenfassend wird mit der Erfindung ein kontrollierbares und einfaches Herstellungsverfahren einer Wafer-to-Wafer-Bondverbindung gewährleistet und eine zuverlässige Anordnung zweier Wafer 1, 4 mit einer stabilen Bondverbindung bereitgestellt. Dabei werden Nachteile, die aus dem Stand der Technik bekannt sind, beseitigt oder zumindest stark reduziert. Insbesondere tritt ein Zerfließen der Bondmaterialien 3, 6, 7 während des Bondvorgangs, wie sonst aus bisherigen Verfahren bekannt, kaum auf. So erlaubt die Erfindung beispielsweise, dass die Umgebung der Bondverbindungen frei von Strukturen gegen das Verfließen der Bondmaterialien 3, 6, 7, insbesondere Strukturen in Form von Gräben, ist. Auf sogenannte Stopp-Gräben, die in bisherigen Anordnungen der Wafer-to-Wafer Bondverbindungen notwendig waren, wird nun vorteilhafterweise verzichtet. In summary, the invention ensures a controllable and simple production method of a wafer-to-wafer bond connection and provides a reliable arrangement of two wafers 1, 4 with a stable bond connection. There are disadvantages arising from the state of the Technique are known, eliminated or at least greatly reduced. In particular, deliquescence of the bonding materials 3, 6, 7 hardly occurs during the bonding process, as is otherwise known from previous methods. Thus, the invention allows, for example, that the environment of the bond connections is free of structures against the flow of the bonding materials 3, 6, 7, in particular structures in the form of trenches. So-called stop trenches, which were necessary in previous arrangements of the wafer-to-wafer bond connections, are now advantageously dispensed with.

Claims

ROBERT BOSCH GMBH, 70442 StuttgartAnsprüche ROBERT BOSCH GMBH, 70442 Stuttgart claims
1. Verfahren zur Herstellung einer Bondverbindung zwischen mindestens zwei Wafern (1; 4), umfassend: a) Aufbringen eines ersten Bondmaterials (3) auf einem ersten Wafer (1), wobei als das erste Bondmaterial (3) Aluminium (AI) oder eine Aluminiumlegierung ausgewählt wird, b) Aufbringen eines zweiten Bondmaterials (6) auf einem zweiten Wafer (4), wobei als das zweite Bondmaterial Gold (Au) ausgewählt wird, und c) Durchführen eines Bondprozesses, wobei das erste (3) und das zweite Bondmaterial (6) miteinander verbunden werden zur Erreichung einer Wafer- to-Wafer Bondverbindung.A method of making a bond between at least two wafers (1; 4), comprising: a) depositing a first bonding material (3) on a first wafer (1), wherein as the first bonding material (3) aluminum (AI) or a Aluminum alloy is selected, b) applying a second bonding material (6) on a second wafer (4), wherein as the second bonding material gold (Au) is selected, and c) performing a bonding process, wherein the first (3) and the second bonding material (6) are interconnected to achieve a wafer-to-wafer bond.
2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass im Schritt a) als Aluminumlegierung AISi, AICu oder AISiCu ausgewählt wird.2. The method according to claim 1, characterized in that in step a) is selected as aluminum alloy AISi, AICu or AISiCu.
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass im Schritt a) durch das Aufbringen des ersten Bondmaterials (3) ein geschlossen umlaufender Bondrahmen (3a) gebildet wird.3. The method according to claim 1 or 2, characterized in that in step a) by the application of the first bonding material (3) a closed circumferential bonding frame (3a) is formed.
4. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass im Schritt a) durch das Aufbringen des ersten Bondmaterials (3) ein elektrischer Kontaktpad (3b) gebildet wird. 4. The method according to claim 1 or 2, characterized in that in step a) by the application of the first bonding material (3), an electrical contact pad (3b) is formed.
5. Verfahren nach einem der Ansprüche 1 bis 4, dad urch gekennzeichnet, dass im Schritt a) ein Wafer (1) mit einem MEMS (microelectromechanical system)-Element (2) ausgewählt wird.5. The method according to any one of claims 1 to 4, dad urch in that in step a) a wafer (1) with a MEMS (microelectromechanical system) element (2) is selected.
6. Verfahren nach einem der Ansprüche 1 bis 5, dad urch gekennzeichnet, dass im Schritt a) das erste Bondmaterial (3) mit einer Dicke von 200 nm bis 3 μm aufgebracht wird.6. The method according to any one of claims 1 to 5, dad urch in that in step a) the first bonding material (3) is applied with a thickness of 200 nm to 3 microns.
7. Verfahren nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass im Schritt b) Gold (Au) als das zweite Bondmaterial (6) auf einem geschlossen umlaufenden Bondrahmen (7a) oder einem elektrischen Kontaktpad7. The method according to any one of claims 1 to 6, characterized in that in step b) gold (Au) as the second bonding material (6) on a closed circumferential bonding frame (7a) or an electrical contact pad
(7b) des zweiten Wafers (4) aufgebracht wird.(7b) of the second wafer (4) is applied.
8. Verfahren nach Anspruch 7, dadurch gekennzeichnet, dass als Material des Bondrahmens (7a) oder des elektrischen Bondpads (7b) des zweiten Wafers (4) AI (Aluminium), AISi, AICu oder AISiCu ausgewählt wird.8. The method according to claim 7, characterized in that as the material of the bonding frame (7a) or the electrical bonding pads (7b) of the second wafer (4) Al (aluminum), AISi, AICu or AISiCu is selected.
9. Verfahren nach einem Anspruch 7 oder 8, dadurch gekennzeichnet, dass im Schritt b) der Bondrahmen (7a) oder der elektrische Kontaktpad (7b) eine Dicke von 200 nm bis 3 μm aufweist.9. The method according to claim 7 or 8, characterized in that in step b) of the bonding frame (7a) or the electrical contact pad (7b) has a thickness of 200 nm to 3 microns.
10. Verfahren nach einem der Ansprüche 1 bis 9, dad urch gekennzeichnet, dass im Schritt b) Gold als das zweite Bondmaterial (6) mit einem Sputter- oder10. The method according to any one of claims 1 to 9, dad urch in that in step b) gold as the second bonding material (6) with a sputtering or
Galvanik- Prozess aufgebracht wird. Electroplating process is applied.
11. Verfahren nach Anspruch 10, dad urch gekennzeichnet, dass im Schritt b) Gold mit einem Sputter-Prozess dicker als 2 μm aufgebracht wird.11. The method of claim 10, dad urch in that in step b) gold is applied with a sputtering process thicker than 2 microns.
12. Verfahren nach Anspruch 10, dad urch gekennzeichnet, dass im Schritt b) Gold mit einem Galvanik- Prozess 1-30 μm dick aufgebracht wird.12. The method according to claim 10, dad urch in that in step b) gold with a galvanic process is applied 1-30 microns thick.
13. Verfahren nach einem der Ansprüche 1 bis 12, dad urch gekennzeichnet, dass im Schritt b) als den zweiten Wafer (4) ein Kappenwafer ausgewählt wird.13. The method according to any one of claims 1 to 12, dad urch in that in step b) as the second wafer (4) a cap wafer is selected.
14. Verfahren nach einem der Ansprüche 1 bis 13, dad urch gekennzeichnet, dass im Schritt b) ein Wafer (4) mit einem ASIC (application-specific integrated circuit)- Element (5) ausgewählt wird.14. The method according to any one of claims 1 to 13, dad urch in that in step b) a wafer (4) with an ASIC (application-specific integrated circuit) - element (5) is selected.
15. Verfahren nach einem der Ansprüche 1 bis 14, dad urch gekennzeichnet, dass im Schritt c) der Bondprozess mit einem Bonddruck von 0,5 bis 15 MPa durchgeführt wird.15. The method according to any one of claims 1 to 14, dad urch in that in step c) of the bonding process with a bond pressure of 0.5 to 15 MPa is performed.
16. Anordnung von mindestens zwei Wafern (1; 4), wobei ein erster Wafer16. Arrangement of at least two wafers (1, 4), wherein a first wafer
(1) und ein zweiter Wafer (4) durch eine Bondverbindung miteinander verbunden sind, und die Bondverbindung ein erstes Bondmaterial (3) und ein zweites Bondmaterial (6) aufweist, dad urch gekennzeichnet, dass das erste Bondmaterial (3) der Bondverbindung durch Aluminium (AI) oder durch eine Aluminiumlegierung realisiert ist, während das zweite Bondmaterial (6) Gold ist. (1) and a second wafer (4) are connected to each other by a bonding connection, and the bonding compound comprises a first bonding material (3) and a second bonding material (6), characterized in that the first bonding material (3) of the bonding compound is aluminum (AI) or by an aluminum alloy, while the second bonding material (6) is gold.
17. Anordnung nach Anspruch 16, dad urch gekennzeichnet, dass die Aluminumlegierung AISi, AICu oder AISiCu ist.17. Arrangement according to claim 16, characterized in that the aluminum alloy is AISi, AICu or AISiCu.
18. Anordnung nach Anspruch 16 oder 17, dad urch gekennzeichnet, dass die Bondverbindung mindestens einen Bondrahmen (3a, 6a, 7a) in einer in sich geschlossenen, umlaufenden Form aufweist.18. Arrangement according to claim 16 or 17, dad urch in that the bond has at least one bonding frame (3a, 6a, 7a) in a self-contained, circumferential shape.
19. Anordnung nach Anspruch 18, dad urch gekennzeichnet, dass der Bondrahmen (3a, 6a, 7a) eine Breite von maximal 50 μm, insbesondere maximal 30 μm, aufweist.19. Arrangement according to claim 18, dad urch in that the bonding frame (3a, 6a, 7a) has a maximum width of 50 microns, in particular a maximum of 30 microns.
20. Anordnung nach Anspruch 16 oder 17, dad urch gekennzeichnet, dass die Bondverbindung mindestens einen elektrischen Kontaktpad (3b, 6b, 7b) zur elektrischen Kontaktierung zwischen dem ersten Wafer (1) und dem zweiten Wafer (4) aufweist.20. Arrangement according to claim 16 or 17, characterized in that the bond connection has at least one electrical contact pad (3b, 6b, 7b) for electrical contacting between the first wafer (1) and the second wafer (4).
21. Anordnung nach Anspruch 20, dad urch gekennzeichnet, dass der elektrische Kontaktpad (3b, 6b, 7b) eine Breite von maximal 50 μm, insbesondere kleiner als 30 μm, aufweist.21. Arrangement according to claim 20, dad urch in that the electrical contact pad (3b, 6b, 7b) has a maximum width of 50 microns, in particular less than 30 microns.
22. Anordnung nach einem der Ansprüche 16 bis 21, dad urch gekennzeichnet, dass der erste Wafer (1) ein MEMS (microelectromechanical System) -Element (2) aufweist und der zweite Wafer (4) ein ASIC (application-specific integrated circuit)- Element (5) aufweist und/oder durch ein Kappenwafer realisiert ist. 22. Arrangement according to one of claims 16 to 21, characterized in that the first wafer (1) has a MEMS (microelectromechanical system) element (2) and the second wafer (4) has an ASIC (application-specific integrated circuit). - Has element (5) and / or realized by a cap wafer.
23. Anordnung nach einem der Ansprüche 16 bis 22, dadurch gekennzeichnet, dass zwischen dem zweiten Bondmaterial (6) Gold und dem zweiten Wafer (4) eine Bondfläche (7) aus AI (Aluminium), AISi, AICu oder AISiCu angeordnet ist.23. Arrangement according to one of claims 16 to 22, characterized in that between the second bonding material (6) gold and the second wafer (4) a bonding surface (7) made of Al (aluminum), AISi, AICu or AISiCu is arranged.
24. Anordnung nach einem der Ansprüche 16 bis 23, dadurch gekennzeichnet, dass ein Abstand (9) zwischen dem ersten (1) und zweiten Wafer (4) durch die Bondmaterialien (3, 6, 7) von mindestens 2 μm, insbesondere von 2 μm bis 30 μm, gebildet wird.24. Arrangement according to one of claims 16 to 23, characterized in that a distance (9) between the first (1) and second wafer (4) by the bonding materials (3, 6, 7) of at least 2 microns, in particular of 2 μm to 30 μm.
25. Anordnung nach einem der Ansprüche 16 bis 24, dadurch gekennzeichnet, dass die Umgebung der Bondverbindungen frei von Strukturen gegen das Verfließen der Bondmaterialien (3, 6, 7), insbesondere Strukturen in Form von25. Arrangement according to one of claims 16 to 24, characterized in that the environment of the bond connections free of structures against the flow of the bonding materials (3, 6, 7), in particular structures in the form of
Gräben, ist. Ditches, is.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015534642A (en) * 2012-09-18 2015-12-03 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングRobert Bosch Gmbh Apparatus having at least two wafers for detecting electromagnetic waves, and method for manufacturing the apparatus
CN113582131A (en) * 2021-07-27 2021-11-02 绍兴中芯集成电路制造股份有限公司 Wafer level packaging method and wafer level packaging structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014221546A1 (en) 2014-10-23 2016-04-28 Robert Bosch Gmbh Microelectronic component arrangement with a plurality of substrates and corresponding production method
FR3099953B1 (en) * 2019-08-14 2021-07-30 Elichens Collective manufacturing process of a pyroelectric detector

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1333494A2 (en) * 2002-01-25 2003-08-06 Texas Instruments Incorporated Semiconductor device and method of fabricating a semiconductor assembly
US20040157407A1 (en) * 2003-02-07 2004-08-12 Ziptronix Room temperature metal direct bonding
US20060125084A1 (en) * 2004-12-15 2006-06-15 Fazzio Ronald S Integration of micro-electro mechanical systems and active circuitry
WO2006084028A2 (en) * 2005-02-03 2006-08-10 Analog Devices, Inc. Interdiffusion bonded stacked die device
EP1071126B1 (en) * 1999-07-23 2006-12-06 Agilent Technologies, Inc. (a Delaware corporation) Microcap wafer-level package with vias
US20070090536A1 (en) * 2005-10-21 2007-04-26 Denso Corporation Sensor having semiconductor chip and circuit chip
US7276789B1 (en) * 1999-10-12 2007-10-02 Microassembly Technologies, Inc. Microelectromechanical systems using thermocompression bonding
US20080245843A1 (en) * 2004-01-22 2008-10-09 Bondtech Inc. Joining Method and Device Produced by this Method and Joining Unit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1071126B1 (en) * 1999-07-23 2006-12-06 Agilent Technologies, Inc. (a Delaware corporation) Microcap wafer-level package with vias
US7276789B1 (en) * 1999-10-12 2007-10-02 Microassembly Technologies, Inc. Microelectromechanical systems using thermocompression bonding
EP1333494A2 (en) * 2002-01-25 2003-08-06 Texas Instruments Incorporated Semiconductor device and method of fabricating a semiconductor assembly
US20040157407A1 (en) * 2003-02-07 2004-08-12 Ziptronix Room temperature metal direct bonding
US20080245843A1 (en) * 2004-01-22 2008-10-09 Bondtech Inc. Joining Method and Device Produced by this Method and Joining Unit
US20060125084A1 (en) * 2004-12-15 2006-06-15 Fazzio Ronald S Integration of micro-electro mechanical systems and active circuitry
WO2006084028A2 (en) * 2005-02-03 2006-08-10 Analog Devices, Inc. Interdiffusion bonded stacked die device
US20070090536A1 (en) * 2005-10-21 2007-04-26 Denso Corporation Sensor having semiconductor chip and circuit chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015534642A (en) * 2012-09-18 2015-12-03 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングRobert Bosch Gmbh Apparatus having at least two wafers for detecting electromagnetic waves, and method for manufacturing the apparatus
US10270001B2 (en) 2012-09-18 2019-04-23 Robert Bosch Gmbh Device having at least two wafers for detecting electromagnetic radiation and method for producing said device
CN113582131A (en) * 2021-07-27 2021-11-02 绍兴中芯集成电路制造股份有限公司 Wafer level packaging method and wafer level packaging structure

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