WO2010054674A1

WO2010054674A1 - Apparatus for determining a position in a bit sequence

Info

Publication number: WO2010054674A1
Application number: PCT/EP2008/009598
Authority: WO
Inventors: Jochen Rivoir
Original assignee: Verigy (Singapore) Pte.Ltd.
Priority date: 2008-11-13
Filing date: 2008-11-13
Publication date: 2010-05-20
Also published as: TW201031134A

Abstract

An apparatus for determining a position in a bit sequence in a digital stream of data of a reference time, wherein a plurality of transitions in the bit sequence comprise a time information each, comprising a bit number determiner and a position determiner. The bit number determiner is configured to assign a bit number to a reference bit in the bit sequence on the basis of a time information of a transition associated with the reference bit and the position determiner is configured to determine the position in the bit sequence at the reference time on the basis of a plurality of reference bits with bit numbers and a direction of the respectively associated transition.

Description

Apparatus for Determining a Position in a Bit Sequence

Description

Embodiments according to the invention relate to an apparatus for determining a position in a bit sequence in a digital stream of data at a reference time and a method for determining a position in a bit sequence in a digital stream of data at a reference time. Some embodiments according to the invention relate to an apparatus for determining a data dependent jitter and a method for determining a data dependent jitter.

Data dependent jitter (DDJ) is, for example, an important performance characteristic of high speed digital interfaces that quantifies to what degree a transition time depends on the history of bits before that transition. So, data dependent jitter (DDJ) measures the dependency of transition times on the history of preceding bits and, therefore, inherently requires the knowledge of the immediate bit history before a measured transition. Because time measurements are usually not faster than 100 Msa/s (mega sample per second) and relevant high speed interfaces run at 2.5 Gb/s (gigabit per second) and above, it is generally impossible to timestamp all transitions (to assign a time information to all transitions) . As a consequence, time stamping alone does not provide the necessary information about the bit history.

For example, data dependent jitter may be measured using a PRBS (pseudo random bit sequence) , because a PRBS of order M contains all possible bit sequences of length M-I. While the generating polynomial and, therefore, the bit sequence is usually known in practical cases, the bit alignment (the position in the bit sequence) is usually not known, because, for example, it is difficult to apply a synchronous reset to the generating linear feedback shift register (LFSR) circuitry. Consequently, the pseudo random bit sequence (PRBS) starts at an unknown time with respect to the test equipment. A key challenge, for example, is to determine this unknown bit alignment.

An alternative is adding dedicated hardware (HW) to the time measurement unit that stores the proceeding bit history along with each time stamped transition. This is not possible when the signal has already passed a pre- scaler, and is particularly difficult in the presence of time drift, because a generic at-speed bit stream recovery must be implemented to track the varying bit phase. It also adds significantly to the band width requirement for storing each timestamp. Another alternative is adding a second time measurement unit in order to timestamp the preceding transition, however this provides only partial information about the preceding bit history, adds difficulties to synchronize both measurements that may have passed an asynchronous pre-scaler, doubles the implementation cost, and doubles the bandwidth requirements to store measurement results.

Summary of the Invention

It is the object of the present invention to provide an improved apparatus for determining a position in a bit sequence in a digital stream of data at a reference time based on a plurality of transitions with time information. This object is solved by an apparatus according to claim 1 and a method according to claim 12.

An embodiment of the invention provides an apparatus for determining a position in a bit sequence in a digital stream of data of a reference time, wherein a plurality of transitions in the bit sequence comprise a time information each, comprising a bit number determiner and a position determiner.

The bit number determiner is configured to assign a bit number to a reference bit in the bit sequence on the basis of a time information of a transition associated with the reference bit and the position determiner is configured to determine the position in the bit sequence at the reference time on the basis of a plurality of reference bits with bit numbers and a direction of the respectively associated transition.

Further embodiments according to the invention provide a method for determining a position in a bit sequence in a digital stream of data at a reference time, wherein a plurality of transitions in the bit sequence comprise a time information each.

The method comprises an assignment of a bit number to a reference bit in the bit sequence on the basis of a time information of a transition associated with the reference bit and a determination of a position in the bit sequence at a reference time on the basis of a plurality of reference bits with bit numbers and a direction of the respectively associated transition. Embodiments according to the present invention are based on the central idea that time information of a plurality of transitions provides an information about the distance of reference bits in the bit sequence, which means that it is possible to determine bit numbers for the reference bits. The bit numbers, for example, indicate how many bits are between two reference bits.

Based on the bit numbers of the reference bits and the direction of a transition related to each reference bit the position in the bit sequence at the reference time may be determined.

Therefore only few information is necessary to determine the position in the bit sequence and the effort and costs may be kept very low.

Some embodiments according to the invention relate to an apparatus for determining a data dependent jitter using an apparatus for determining a position in a bit sequence.

In some embodiments according to the invention, the bit sequence is based on a known generating function.

Brief Description of the Drawings

Embodiments according to the invention will be detailed subsequently referring to the appended drawings, in which:

Fig. 1 is a schematic illustration of an apparatus for determining a position in a bit sequence in a digital stream of data at a reference time; Fig. 2 is a schematic illustration of a linear feedback shift register;

Fig. 3 is an illustration of a pseudo random bit sequence;

Fig. 4 is an illustration of a pseudo random bit sequence with transitions with time information;

Fig. 5 is an illustration of a pseudo random bit sequence with transitions with time information;

Fig. 6 is an illustration of a pseudo random bit sequence with transistors with time information; and

Fig. 7 is a flow chart of a method for determining a position in a bit sequence in a digital stream of data at a reference time.

Detailed Description of Embodiments

Fig. 1 shows a schematic illustration of an apparatus 100 for determining a position 122 in a bit sequence 102 at a reference time 104 according to an embodiment of the invention, wherein a plurality of transitions 106 in the bit sequence 102 comprise a time information each.

The apparatus 100 comprises a bit number determiner 110 and a position determiner 120. The bit number determiner 110 is configured to assign a bit number (BN) 112 to a reference bit (RB) 107 in the bit sequence 102 on the basis of a time information of a transition (T2) 106 associated with the reference bit 107 and the position determiner 120 is configured to determine the position (P) 122 in the bit sequence 102 at the reference time (RT) 104 on the basis of a plurality of reference bits 107 with bit numbers and a direction 108 of the respectively associated transition (Tl, T2) 106.

The bit number determiner 110 receives as input a transition 106 with time information and determine a bit number 112 for a corresponding reference bit 107. For example, the bit number determiner 110 calculates the time difference between the reference time 104 and the transition 106 and divides it by a unit interval T, which is also called bit period, to calculate the number of bits between the reference time 104 and the transition 106. Then the bit number determiner 110 assigns a bit number 112 to the reference bit 107 according to the position of the reference bit 107 in the bit sequence 102 with respect to a first bit.

The bits of the bit sequence may be consecutively numbered, wherein, for example, the bit at the reference time or the bit before or after a first transition with time information may be indicated as first bit. If the reference time, for example, indicates a time related to a border between two neighboring bits (which may be a transition for different bit values) , one of these two bits may be indicated as first bit. One alternative may be to set the reference time to the moment of the first transition.

The position determiner 120 determines the position 122 in the bit sequence 102 based on the plurality of transition directions 108 and the associated reference bits 107 with bit numbers 112, for example, by comparing the direction 108 and positions of the transitions 106 with the whole bit sequence 102, wherein a position of a transition 106 is determined by the bit number 112 of the associated reference bit 107.

Based on the bit numbers 112 of the reference bits 107 and the directions 108 of the corresponding transitions 106 a position 122 in the bit sequence 102 may be determined.

The bit sequence, for example, may be stored and provided by a memory unit.

The position in the bit sequence, for example, refers to a bit or a border between two neighboring bits (which may be a transition for different bit values of the neighboring bits) depending on the reference time.

If the bit sequence, for example, repeats after a number of bits, the position in the bit sequence may be unambiguous only within the length of the not repeated bit sequence, because an offset of one or more bit sequence lengths would lead to the same result.

For example, due to the time information (also denoted as timestamp) of the transitions 106 the bit numbers 112 of the reference bits 107 may be determined by the bit number determiner 110, whereby the number of bits between two reference bits 107 may be determined. Knowing the distance (number of bits between reference bits) of the reference bits 107, for example, allows an alignment of the transitions 106 with time information and the directions 108 of the transitions 106 with transitions and directions of the transitions of the whole bit sequence by the position determiner 120.

Therefore, for example, for a determination of a data dependent jitter it may be unnecessary to implement hardware to capture the bit history before a transition.

Matching the measured timestamps (the transitions with time information) to all possible bit alignments may be practical for short bit sequences. Matching the measured time stamps to all possible sequence alignments of, for example, a long pseudo random bit sequence is often not practical since a pseudo random bit sequence of, for example, order 32 repeats only after 2³² -1 bits and would, therefore, typically require more than 2,000,000,000 pattern matches, which is not practical.

Some embodiments according to the invention relate to an apparatus for determining a position 122 in a bit sequence 102, wherein the bit sequence 102 is a pseudo random bit sequence. For example, when arbitrary timestamps are taken from a pseudo random bit sequence, the bit history is not readily known, because the position 122 in the bit sequence 102, which is also called bit alignment, is usually not repeatable. With known bit alignment, the bit history before each transition 106 can be determined and, for example, conventional data dependent jitter algorithms can be applied to determine the data dependent jitter. Therefore, the need for hardware to capture the bit history before each transition may be eliminated.

For example, a pseudo random bit sequence of length 2^M -1 may be generated by a linear feedback shift register (LFSR) , consisting of M flip-flops in a shift register configuration and a suitable XOR feedback to the first flip-flop, unless all flip-flops start in the reset state.

Fig. 2 shows a schematic illustration of a linear feedback shift register 200 with 5 flip-flops, which is implemented using the so-called Fibonacci topology.

The linear feedback shift register 200 comprises an arrangement of 5 flip-flops 210 (xl, x2, x3, x4, x5) and a logical combiner 230. An output of flip-flop xl is connected to an input of flip-flop x2, an output of flip- flop x2 is connected to an input of flip-flop x3 and to the logical combiner 230, an output of the flip-flop x3 is connected to an input of flip-flop x4, an output of flip- flop x4 is connected to an input of flip-flop x5, an output of flip-flop x5 is connected to an output y 220 of the linear feedback shift register 200 and to the logical combiner 230 and an output of the logical combiner 230 is connected to an input of flip-flop xl. The linear feedback shift register 200 outputs a pseudo random bit sequence at output y 220.

The generating polynomial in Fig. 2 is denoted as:

g(x) = \®x²θx⁵ ,

(D

The logical combiner 230, denoted as summation circle (^ΛΘ') in Fig. 2, combining output x2 and output x5 denotes a binary XOR. The XOR tap positions (x2, x5) determine the exponents with non-zero coefficients. A thorough engineering explanation for this notation can be found in "A. Neubauer, J. Freudenberger, V. Kϋhn: Coding Theory - Algorithms, Architectures and Applications, Wiley 2007", and more mathematical treatment in "D. S. Dummit, R. M. Foote: Abstract Algebra, Wiley 2004". When g(x) is a so- called primitive polynomial, the sequence length is:

L = 2^M -1 (2)

I.e. the output sequence {y(l),y(2),...} repeats after the maximum possible number of steps.

y(k+L) = y(k), for £eZ

(3)

The zero state, where all flip-flops are reset, is excluded, because the linear feedback shift register 200 would stay stuck in this state and subsequently produce only zeros at its output. Practical linear feedback shift register makes sure not to power up in the zero state. The sequence length of non-primitive polynomials are dividers of L, so that equation (3) holds for arbitrary polynomials.

For example, when the initial state is X_{1 5} =10100, the linear feedback shift register 200 in Fig. 2 and described by polynomial (1) outputs the following pseudo random bit sequence at output y 220:

0101011101100011111001101001000-01010111011000111... The position in the bit sequence of a state machine (e.g. a LFSR) may be related to a state of the state machine. Since succeeding states of a state machine may not comprise consecutively numbered states, the position also may not be a consecutive number for succeeding bits of the bit sequence. Nevertheless the position is unambiguous within the not repeated bit sequence.

For example, for the above shown bit sequence the position in the bit sequence may be related to the initial state Xi._..5=10100 and therefore the first bit in the shown bit sequence may be indicated as position 20 in the bit sequence. If the bit sequence would start one bit later, the initial state would be xi...₅=01010 and therefore the first bit in the bit sequence may be indicated as position 10 in the bit sequence.

In the example mentioned before, wherein a memory unit provides a bit sequence, the position of each bit in the bit sequence may be consecutively numbered. For example, the position may be related to an address where a bit of the bit sequence is stored in the memory unit.

Fittingly, Fig. 3 shows a pseudo random bit sequence 300 generated by polynomial g (x) 310 and an initial state xθ 320, which is also known as seed. The Figure shows the first 75 bits of the pseudo random bit sequence, for a bit period of T = 1 and a small period-to-period jitter, uniformly distributed in, for example, [-0.01, 0.01], wherein the bit period is the length of time of one bit in the stream of data and the period-to-period jitter is a potential deviation of the bit period. The time is indicated in multiples of the unit interval. The pseudo random bit sequence repeats after every 31 cycles, indicated by the dotted vertical lines 330.

A general linear feedback shift register with M flip-flops is described by its generating polynomial of order M:

g(x) = \®(_gιΘx)®(g₂Ox²)®...®(g_MOx^M), xeB

(4)

^ΛΘ' denotes the binary XOR operation, and ^ΛΘ' the binary

AND operation in B ={θ,l}. ^y + '_f ^λ-' will be used in most cases for the usual summation and multiplication of integers and real numbers.

A pseudo random bit sequence is uniquely specified by its generating polynomial g(x) 310 and a non-zero vector xo 320 with the initial states of M linear feedback shift register flip-flops in cycle number 0, also known as seed.

(5)

Some embodiments according to the invention relate to computing the seed Xo of a linear feedback shift register from N sparse, arbitrarily distributed transition timestamps t_ne.R, n=l...N and transition directions c/_ne{θ,l}, where d=l indicates a rising transition, d=0 a falling transition. This definition of the transition directions is not mandatory and may also be inverted to provide the same results.

By computing the seed Xo the position in the pseudo random bit sequence of the linear feedback shift register at a reference time may be determined by the position determiner. The transitions with timestamps may also be equally distributed and/or may be available in a large number.

For example, the time stamps indicate transition times of a pseudo random bit sequence with known generating polynomial g(x), approximately or exact known bit period T (for example, for approximately known bit period T , T_min ≤T ≤ T_max ) , and unknown seed Xo with M elements. Necessary and sufficient conditions for t_n,n = l...N , for example, will be given. The bit period T is also known as the unit interval (UI) .

Fig. 4 shows the pseudo random bit sequence 300 of Fig. 3 with sparse timestamps, where, starting with the second transition, every 9^th transition 106 is time stamped. In this example, time stamping returns times

{*„} = {3.01, 22.13, 36.21, 56.31, 71.39} and directions 108 {<} ={0,1,0,1,0}.

Alternatively, another sampling scheme could timestamp the next transition after the conversion time of a time-to- digital converter (TDC) , or take intentionally randomized samples.

In some embodiments according to the invention an ordered set of timestamps will be assumed, i.e. t_n<t_m for n<m . If necessary, the time stamps can be sorted in ascending order.

Some further embodiments according to the invention comprise a unit interval determiner configured to compute an estimated unit interval T, based on, for example, sparse timestamps t_n,n = \...N .

Usually the unit interval T is accurately known, for example in ATE applications, but sometimes the unit interval is only known to be somewhere in the interval

T_miB≤T≤T_msx. In this case the unit interval T may be estimated based on the timestamps.

Consider the time intervals At_n between subsequent timestamps, άt_n=t_n—t_n__λ , n=2...N. This time difference is caused by an unknown number β_n of bits of duration T and a random jitter variable J_n, with upper absolute limit J for all intervals, |/_n|≤J.

At_n=β_nT+j_n, for _Λ=2..JV

(6)

Upper and lower bounds for the number of bits can be computed from formula (6), which is shown in formula (7):

[7)

(^".^"] and |_.J denotes rounding up, or down to the closest integer, respectively. Going back to formula (6) allows updating upper and lower bounds for the unit interval:

(8)

For example, equations (7) and (8) may be repeated for all N-I intervals and iterated across all intervals until all bit numbers are uniquely known, /?_nmin =β_nmax when the sum of bit uncertainties

JV π=2

(9)

is not reduced in a given iteration of all N-I intervals, the uncertainty intervals, T_min ≤T ≤T_max , may be too large for the given time intervals At_n . It may not be possible to estimate the unit interval accurately enough to determine the exact number of bits between timestamps which, for example, is important for any unit interval tracking algorithm. If all bit numbers are uniquely known, for example, β_n,_mi_n = βn,maxf the unit interval can be estimated as (with t₀ as reference time) :

¹f-hNiZh

n=2

(10)

So, a unit interval T may refer to an accurately known (for example, with a tolerance of +/- 5%) or to an estimated unit interval.

Some further embodiments according to the invention relate to a determination of unit interval (UI) numbers β_n for transitions t_n, for known nominal bit period T.

£l_

«1 ¹ =L JT.J

(H)

[.] denotes rounding to the closest integer and ti, for example, is the time between the reference time and the occurrence of the first transition. For the example shown in Fig. 4, the tracked unit intervals are {u_n} = {3,22,36, 56,71} , as expected.

Inherently, this assumes less than half a unit interval of drift between consecutive timestamps. When the timestamp sample rate is f_s (for example, in units of timestamps per bit) , the drift rate should be less than: T - f Drift < — ^-

( 12a )

For example, when using a time-to-digital converter (TDC) the time stamp rate of the TDC is f_TDC with a bit rate and the drift rate should be less than:

Drif_t <LJm^ ₌ IrSc.

2 2f

^JB" (12b)

For example, for a 5 Gbps PCIe (Gbps: Gigabits per second,

PCIe: Peripheral Component Interconnect Express) and a TDC with 100 Msa/s, the tolerable drift is 1/100, i.e. 0.01 UI/UI.

Some embodiments according to the invention relate to a generation of a state space representation of a linear feedback shift register. For example, the linear feedback shift register in Fig. 2 is described by five equations for the state flip-flops and one output equation.

x_λ(k + \) = X₂(Zc) Q X₅ (Zc) X₂(Zc ₊ I) = X₁ (Ic) X₃(Jc ₊ I) = X₂(Ic) X₄ (Ic ₊ I) = X₃ (Jc) X₅(Zc ₊ I) = X₄(Jc) y(k) = X₅(Jc)

: i 3 )

Or, combined into a matrix equation:

(14:

^λX<8>" denotes the inner product between binary vectors:

ι'® b=(a,,...a_My®(b_λ,...b_M) = (a_iQb_i)®...θ(a_MΘb_M)

(15)

For a general generating polynominal g(x), g_M ≠ 0, the state equations are:

( 16 ) Or, in matrix notation:

τ(k+l) = A®x(k) y(k)=c®x(k)

(17)

with:

(18)

and the state matrix A and state-output vector c, which are a sole function of the generating polynominal g(x).

0 0 0 1 )

:i9)

This general state equation (17) covers, for example, also the so-called Galois linear feedback shift register topology, which can be used alternatively to generate the same pseudo random bit sequence. The actual implementation topology of the generating linear feedback shift register is irrelevant as long as, for example, the generated pseudo random bit sequence is unambiguously defined. The output value y(k) after k steps can be computed by iteratively applying the state equation (17), starting with the initial condition x_o=x(O) .

5 y(k) = c®A^k®x₀

(20)

For example, the cyclic nature of the pseudo random bit 10 sequence, y (k+L) =y (k) , as stated in formula (3), leads directly to:

A*⁺ⁱ=A*

(21) 15

When the exponent k is written as an integer multiple of L and the remainder, k=nL+q, with q=k mod L, then:

p /-) A k A nL+(k mod Z.) ( i i \" jo. Λ λ modt A t modL

(22)

Equation (20) reveals that the output values y(k) are linear combinations of the M elements in the seed vector

25 X₀, weighted with a row vector c<8>A* that is known for known time step k and known polynomial g(x), and therefore known matrix A. So, for example, it is possible to compute the M elements of the seed vector Xo from M known output values z_m,m=l...M (reference bit) at known corresponding bit

30 times (or bit number) b_m, if the resulting equations are linearly independent. Unless, for example, too much drift leads to a wrong numbering of bits, a solution Xo exists, since the time stamped pseudo random bit sequence is generated by a known polynomial with some seed Xo ≠ 0.

35 However, it is not obvious whether M given bit sample times b_m provide enough independent information to uniquely identify a seed. The M known bit values z_m at bit numbers b_m in equation (20) define M equations.

z_m=y{b_m),m = \...M

:23)

Substitution of equation (20) into equation (23) leads to:

z_m =c®A*"®x_o,m = l...M

(24

The above M equations can now be combined into one matrix equation:

z =Q®x₀,

(25)

The vector z=(zχ, ..., z_m) ' contains the known bit levels, vector b=(bχ, ..., b_M) ' contains the corresponding bit numbers and Q is the Mx M matrix:

(26 )

If all rows of Q are linearly independent, Q can be inverted to solve equation (25) for seed X₀:

:27; Obviously, not all bit values z_m, m=l...M can be zero, otherwise equation (27) leads to Xo=O, which would be a mathematically correct but undesired solution, because linear feedback shift registers are known to start in a non-zero state, XQ ≠ 0.

z≠O (28)

The reason for this expectation is that there are 2^ combinations of M arbitrary bit sample values, while a pseudo random bit sequence goes through only 2"-I states, all of which could be the desired seed Xς>. The illegal zero seed is the missing state.

For example, a necessary condition for linearly independent rows is that the terms A^bm in rows m=l...M are unique. Equation (22) requires unique (b_m mod L), i.e. unique bit numbers within the sequence length.

(b_m mod L) ≠ (b_j mod X) , for m≠j both in {l,...,M} • (29)

This is not a every time a sufficient condition. For example, regularity of Q must be checked for a given set of bit times b.

The equation for calculating the seed Xo may be provided by an external source or the apparatus for determining the position in the bit sequence may comprise a processor for determining this equations.

Some further embodiments according to the invention relate to an apparatus for determining a position in a bit sequence comprising a reference bit selecting means configured to select reference bits, which are also called bit samples, from measured transitions with time information.

For example, each measured transition at unit interval U_n with direction d_n specifies two bit samples of opposite level, one before and one after the transition. To satisfy condition (28), for example, at least one bit sample value must be 1. This is easily achieved by selecting at least one bit sample behind a rising transition or at least one bit sample before a falling transition. Linear independency of the rows c®A^ό" in Q must still be checked explicitly.

For example, the reference bit selecting means may find the solution by adding a bit sample b_n with associated row vector c(8>A" that is linearly independent of the already selected cΘA*¹" .

An alternative is to select all reference bits or more reference bits than necessary to compute the seed Xo. However, the received system of equations has to be invertible and therefore the matrix has to be of maximum rank. The inversion may be done by a pseudo inversion.

Some embodiments according to the invention comprise a method for selecting bit samples from measured transitions.

Start with both bits around a first transition, b=(u₁-l,u_l)' ,

. This ensures condition (28) and meets condition (29) , because the bit numbers are consecutive, and guarantees to start with two linearly independent rows in Q(b) . Set the number of selected bits to m = 2. Set the transition search pointer (indicates the current transition) to the first transition, «=1.

While there are less than M selected bit samples, m<M , repeat the remaining steps. First, increment the transition search pointer, n=n+l . If n>N , wherein N is the number of transitions in a bit sequence without repetition, report error "Not enough transitions".

Then, temporarily add the bit before the current transition to all selected bits, b = (b_v...,b_m,b_n -l)', z =(z_l,...,z_m,_^d_n)' . If matrix Q(b) according to equation (26) has rank rø+1, then keep this addition and increment the selection count, m-m+l . Otherwise, delete the added bit or do nothing if the temporarily added entry will be overwritten in the next step.

If m = M , exit with the completed set of M bit samples (reference bits) , b and z .

Otherwise, temporarily add the bit after the current transition to all selected bits, b = (b_l,...,b_m,b_n)' , z = (z,,...,z_m,d_n)' . If matrix Q(b) according to equation (26) has rank m+l, then keep this addition and increment the selection count, m = m +l.

For the example shown in Fig. 4, this algorithm (method) returns 5 bit samples with bit numbers b = (2,3,21,22,36) and bit values z = (1,0,0,1,0) . The algorithm selects both bits around the first two transitions, skips the bit before the third transition and finally selects the bit after the third transition.

These bit samples (reference bits) are highlighted in Fig. 5, which shows the pseudo random bit sequence 300 of Fig. 4 with selected bit samples 107 and bit numbers 112 to compute seed.

Some embodiments according to the invention comprise a computation of the seed X₀ following the derivation described before. First, the matrix Q is constructed based on the selected bit numbers b = (b_v...,b_M)' , copied from equation (26) :

(30)

The bit numbers b may be selected in a way described before, such that Q has linearly independent rows and is therefore invertible. With known bit levels z = (z,,...,z_w)' , the seed X₀ can be computed according to equation (27) :

:31)

For the example shown in Fig. 5, this procedure returns x'_o =(1,0,1,0,0) , which is, correctly, the seed that was used to generate the time stamped pseudo random bit sequence.

Equation (31) prescribes, for example, a binary matrix inversion.

Some further embodiments according to the invention comprise a computation of a pseudo random bit sequence.

With known X₀ , the output y(k) at any time step k in the sequence can be computed using equation (20) :

(32)

Some embodiments according to the invention comprise a consistency check. For example, the measured signal may have violated the assumption of less than half a unit interval of drift and/or jitter between subsequent timestamps, which, for example, could have corrupted the determination of the unit interval (the unit interval tracking algorithm), described before. Such a possible violation can be tested by comparing the computed sequence bits y(k) before and after expected transitions at unit interval numbers U_n, with the bit values that are implied by transition directions d_n . For example, before a rising transition, d =\ , bit level "0" is expected.

Xw_n-¹) = -^, ^and y(u_n) = d_n for Ti = 1..JV

(33)

Both above conditions may be verified for all JV transitions, where equation (32) computes the sequence bits y(k).

Some further embodiments according to the invention relate to an apparatus for determining a data depending jitter comprising an apparatus for determining a position in a bit sequence and a jitter determiner configured to determine the data dependent jitter based on the position in the bit sequence.

The ability to compute any bit in the sequence allows applying conventional data dependent jitter algorithms that assume knowledge of the complete bit sequence.

Data dependent jitter analyzes the time errors τ_n of transitions t_n to obtain an unbiased time error, which can be computed as:

(34) Computation of data dependent jitter requires knowledge of the bit history before transitions t_n , for example, the bit levels before unit interval numbers U_n . Various degrees of detail can be of interest.

For example, the most general method looks at the history H_n of H consecutive bits before each transition t_n of direction d_n .

H_n ={y(u_n -2) ... y{u_n-H))

(35)

The bit level y{u_n-X) right before the transition is not included in H_n , because it is implied by the transition direction,

. For each of 2^H~X possible different bit histories of H-I consecutive bits, h = \...2^H~λ , and for both transition directions, de{θ,\), the average time error may be computed:

N n=l,H =h,d=d

(36)

The worst case data dependent jitter variation S^(h'^d) across all bit histories, h =\...2^H~λ , and transition directions, </e{0,l} is then:

->«-' i 2"-',1 δ^{ ' ' = Am=l,arfx=0ε_h ^M _ή-Am=Lidn=Oε_h ^M. (37;

Other metrics of interest can, for example, be the data dependent jitter variation δ_d ^h) across all bit histories, but for a given transition direction d :

δ_d ^h) = m A=aIxε_{h d} -ψ

( 38 ) Or just average time difference between rising and falling transitions:

N N

5 rise Jai_l = ^=_I ^" ^=O = ™g T₁ - OVg T,

Another, simpler method just looks at the numbers R_n of equal repeated bits before transitions t_n at unit intervals u

R_n = argmax _V^(y(u_n -1) =y(u_n -i)) J ' ^'"' (40)

An algorithm to obtain R_n may be, initialize R_n=I- While

where y(k) is computed using equation (32).

Fig. 6 shows the number of repeated bits, R_n for the example described in Fig. 5, labeling the bit levels that precede transition t_n . The computed number of repeated bits is shown above the levels before the timestamp transition. In this example, [R_n] ={1,2,1,1,3} .

For each of M-I possible numbers 610 of repeated bits, r =\...M-\, and for both transition directions, de[θ,\)_f the average time error can be computed:

N ε_rd = avg τ_n n=\R=r,d=d

(41)

The worst case data dependent jitter variation δ^(r'^d) across all numbers of repeated bits, r =\...M-\, and across both transition directions, rfe{0,l}, is: W-I₁I M-l.l

S^(r-^d) = max ε_{r H} - min ε _H

( 42 )

For a given transition direction d , the worst case data dependent jitter variation δ_d ^{r) across all numbers of repeated bits is:

M M --II M M--II # y_d ^r)' == ]maxε_{r d} -mmε_{r d}

( 43 )

Fig. 7 shows a flow chart of a method 700 for determining a position in a bit sequence in a digital stream of data at a reference time according to an embodiment of the invention, wherein a plurality of transitions in the bit sequence comprise a time information each.

The method 700 comprises an assignment 710 of a bit number to a reference bit in the bit sequence on the basis of a time information of a transition associated with the reference bit and a determination 720 of a position in the bit sequence at a reference time on the basis of a plurality of reference bits with bit numbers and a direction of the respectively associated transition.

Some embodiments according to the invention relate to a method of determining or computing a bit alignment of a jittered pseudo random bit sequence from sparse timestamps.

Some further embodiments according to the invention relate to computing data dependent jitter of a pseudo random bit sequence from sparse timestamps. Some embodiments according to the invention relate to an algorithmic and computationally efficient method to compute the bit alignment of a pseudo random bit sequence with known polynomial using a small subset of timestamps. With known bit alignment, for example, usual data dependent jitter algorithms can be applied.

Some further embodiments according to the invention relate to an algorithm (method) for determining the bit alignment (the position) in a bit sequence.

First, if not known prior, estimate the unit interval T.

Then extract the unit interval numbers for the timestamps, for example, by applying a phase tracking algorithm.

The next step is creating a state space representation of the linear feedback shift register based on its generating polynomial .

Then select a suitable bit sample in the pseudo random bit sequence that defines a linearly independent equation for the unknown seed.

Afterwards compute the seed with M unknown initial bits using the M bit samples and the state space representation of the linear feedback shift register.

Finally, compute the pseudo random bit sequence using the seed and the linear feedback shift register state space representation. Some embodiments according to the invention relate to a software method to compute the data dependent jitter from sparse timestamps. The method may require, for example, knowledge of the pseudo random bit sequence polynomial, approximate knowledge of the unit interval, and less than half a unit interval of drift between subsequent timestamps. For example, the latter conditions may be ensured by a very fast TDC sampling rate, such as in Tequila-based automatic test equipment (ATE) .

Some further embodiments according to the invention relate to a use of an apparatus for determining a position in a bit sequence or a method for determining a position in a bit sequence by an automatic test equipment.

Some embodiments according to the invention relate to a use of an apparatus for determining a data dependent jitter or a method for determining a data dependent jitter by an automatic test equipment (ATE) .

Some further embodiments according to the invention relate to a method to find a bit alignment of a bit sequence based on a subset of timestamed transitions. The method comprises associating bit numbers to timestamps and matching a bit alignment consistent with transition directions at bit numbers .

This includes, for example, brute force methods of scanning through all possible bit alignments and includes also using non pseudo random bit sequences.

Some embodiments according to the invention relate to a method to find a bit alignment of an algorithmic bit sequence by solving the state of a certain time step, based on a set of equations defined by bit samples (reference bits), derived from timestamps.

This includes, for example, also non pseudo random bit sequences, even non-linear state machines.

Some further embodiments according to the invention relate to a method to compute an initial state of pseudo random bit sequences with known polynomial based on bit samples, derived from bit samples that are obtained from timestamps.

In general a bit sequence means a digital sequence of a plurality of logical 0 and logical 1. This bit sequence may be generated at random or by a generating function like a polynomial as described before. A transition in a bit sequence is a change from a logical 0 to a logical 1 or from a logical 1 to a logic 0 in the bit sequence. A direction of a transition indicates whether the transition is from a logical 0 to a logical 1 or from a logical 1 to a logical 0. A unit interval variation or jitter is , for example, a variation of the length of time of the unit interval .

In the present application, the same reference numerals are partly used for objects and functional units having the same or similar functional properties.

In particular, it is pointed out that, depending on the conditions, the inventive scheme may also be implemented in software. The implementation may be on a digital storage medium, particularly a floppy disk or a CD with electronically readable control signals capable of cooperating with a programmable computer system so that the corresponding method is executed. In general, the invention thus also consists in a computer program product with a program code stored on a machine-readable carrier for performing the inventive method, when the computer program product is executed on a computer. Stated in other words, the invention may thus also be realized as a computer program with a program code for performing the method, when the computer program product is executed on a computer.

Claims

1. Apparatus (100) for determining a position (122) in a bit sequence (102) in a digital stream of data at a reference time (104), wherein a plurality of transitions (106) in the bit sequence (102) comprise a time information each, comprising:

a bit number determiner (110) configured to assign a bit number (112) to a reference bit (107) in the bit sequence (102) on the basis of a time information of a transition (106) associated with the reference bit (107);

a position determiner (120) configured to determine the position (122) in the bit sequence (102) at the reference time (104) on the basis of a plurality of reference bits (107) with bit numbers (112) and a direction (108) of the respectively associated transition (106) .

2. Apparatus for determining a position in a bit sequence according to claim 1, wherein the bit sequence (102) is generated on the basis of a known function.

3. Apparatus for determining a position in a bit sequence according to claim 1 or 2, wherein the position determiner (110) is configured to determine the position (122) on the basis of the plurality of reference bits (107) with bit numbers (112), the direction (108) of the respectively associated transition (108) , and the generating function, wherein it is determined, on the basis of the direction (108) of a transition (106) , whether the accompanying reference bit (107) is a logical 0 or a logical 1.

4. Apparatus for determining a position in a bit sequence according to claim 2 or 3, wherein the position determiner (110) is configured to determine an initial state of the generating function at the reference time (104), wherein an initial state of the generating function at the reference time (104) determines the position (122) in the bit sequence.

5. Apparatus for determining a position in a bit sequence according to claim 4, wherein the position determiner (110) determines the initial state of the generating function on the basis of a matrix, wherein the matrix is based on the plurality of reference bits (107) and must be invertible.

6. Apparatus for determining a position in a bit sequence according to one of claims 2 to 5, wherein the bit sequence (102) repeats after a number of bits, wherein the number of bits is determined by the generating function.

7. Apparatus for determining a position in a bit sequence according to claim 6, wherein no reference bit (107) of the plurality of reference bits (107) is allowed to correspond to a further reference bit (107) of the plurality of reference bits (107) in a repetition of the bit sequence (102) .

8. Apparatus for determining a position in a bit sequence according to one of claims 1 to 7, comprising a reference bit counter configured to select the plurality of reference bits (107) for determining the position (102), wherein a selected reference bit (107) is included in the bit sequence (102) either directly before or directly after a transition (106) with time information.

9. Apparatus for determining a position in a bit sequence according to one of claims 1 to 8, wherein the bit number determiner (110) is configured to determine the bit number (112) of the reference bit (107) on the basis of a unit interval, wherein the unit interval indicates the temporal length of a bit in the stream of data, and wherein the bit number (112) of the reference bit (107) indicates which bit in the bit sequence (102) is the reference bit (107") with respect to a first bit.

10. Apparatus for determining a position in a bit sequence according to one of claims 1 to 9, comprising a unit interval determiner configured to determine a unit interval on the basis of two items of time information of two transitions (106), a maximum unit interval, a minimum unit interval, and a maximum unit interval variation, wherein the unit interval indicates the temporal length of a bit in the stream of data.

11. Apparatus for determining data dependent jitter with an apparatus for determining a position in a bit sequence according to one of claims 1 to 10, comprising:

a jitter determiner configured to determine the data- dependent jitter on the basis of the position (122) in the bit sequence (107) .

12. Method (700) of determining a position in a bit sequence in a digital stream of data at a reference time, wherein a plurality of transitions in the bit sequence comprise a time information each, comprising:

assigning (710) a bit number to a reference bit in the bit sequence on the basis of a time information of a transition associated with the reference bit; and

determining (720) a position in the bit sequence at a reference time on the basis of a plurality of reference bits with bit numbers and a direction of the respectively associated transition.

13. Method of determining a position in a bit sequence according to claim 12, wherein the bit sequence is generated on the basis of a known function, and wherein determining a position in a bit sequence comprises :

determining a matrix for calculating an initial state of the generating function at the reference time on the basis of the generating function, the plurality of reference bits with bit numbers and the directions of the respectively associated transitions, wherein the initial state of the generating function at the reference time determines the position in the bit sequence; and

calculating the initial state on the basis of the matrix.

14. Method of determining a position in a bit sequence according to claim 13, wherein determining a matrix comprises:

selecting a reference bit;

adding a row to the matrix, wherein the new row is based on the selected reference bit;

checking as to whether the new row of the matrix is linearly independent of an already existing row of the matrix; and

removing the new row if the new row is not linearly independent of the already existing row of the matrix.

15. Method of determining data dependent jitter with a method of determining a position in a bit sequence according to one of claims 12 to 14, comprising:

determining the data dependent jitter on the basis of the position in the bit sequence.

16. Computer program with a program code for performing the method according to one of claims 12 to 15, when the computer program runs on a computer or a microcontroller.