WO2010052065A1

WO2010052065A1 - High frequency differential amplifier and transceiver circuit

Info

Publication number: WO2010052065A1
Application number: PCT/EP2009/062423
Authority: WO
Inventors: Marco Neuscheler; Ricardo Erckert; Axel Wenzler
Original assignee: Robert Bosch Gmbh
Priority date: 2008-11-10
Filing date: 2009-09-25
Publication date: 2010-05-14
Also published as: DE102008057629B4; CN102210097A; CN102210097B; DE102008057629A1

Abstract

The invention relates to a high frequency differential amplifier (61) for a transceiver circuit (21) for a bus system (11), having two transistor stages (63, 65) with metal-insulator-semiconductor field effect transistors (M1, M2), and with a common branch (67) connected to both transistor stages (63, 65) for coupling the transistor stages (63, 65) with each other. A current source (75) of the high frequency differential amplifier (61), for producing an operating current (Ibias) flowing through the common branch (67), is assigned to the common branch (67). In order to provide a high frequency amplifier (61), the amplification of which is substantially independent of temperature (T) and of the spatial distribution of components of the amplifier (61), it is suggested that the transistor stages (63, 65) are configured to operate the metal-insulator-semiconductor field effect transistors (M1, M2) given weak inversion, and that the current source (75) is designed to compensate the temperature dependency of the amplification of at least one metal-insulator-semiconductor field effect transistor (M1, M2) in such a manner that the operating current (lbias) depends on a temperature (T) of the high frequency differential amplifier (61).

Description

description

title

High frequency differential amplifier and transceiver circuit

State of the art

The invention relates to a high-frequency differential amplifier having the features of the preamble of claim 1 and a transceiver circuit having the features of the preamble of claim 5.

Commercial vehicles are often interconnected by means of a communication system, such as the bus system known as "FlexRay". The communication traffic on the bus system, access and reception mechanisms, as well as error handling are regulated by a protocol. FlexRay is a fast, deterministic and fault-tolerant bus system, especially for use in motor vehicles. The FlexRay protocol operates on the principle of Time Division Multiple Access (TDMA), whereby the subscribers or the messages to be transmitted are assigned fixed time slots in which they have exclusive access to the communication connection. The time slots are repeated in a fixed cycle, so that the time at which a message is transmitted over the bus, can be accurately predicted and the bus access is deterministic.

To make the most of the bandwidth used to transmit messages on the bus system, FlexRay divides the cycle into a static and a dynamic part. The fixed time slots are located in the static part at the beginning of a bus cycle. In the dynamic part, the time slots are specified dynamically. In this case, exclusive bus access is now only possible for a short time, for the duration of at least one so-called minislot. Only if a bus access occurs within a minislot, the Timeslot extended by the required time. Thus, bandwidth is only consumed when it is actually needed. FlexRay communicates via one or two physically separate lines with a maximum data rate of 10 Mbit / sec. FlexRay can also operate at lower data rates. Through the lines realized channels correspond to the

Physical layer, in particular the so-called OSI (Open System Architecture) layer model. The use of two channels is mainly for the redundant and thus fault-tolerant transmission of messages, but it can also transmit different messages, which would then double the data rate. Usually, the

Messages transmitted by means of a differential signal, that is, the signal transmitted via the connecting lines results from the difference of transmitted over the two lines of individual signals. The layer lying in the layer model over the physical layer is designed such that an electrical or an optical transmission of the signal or signals over the

Line (s) or a transfer by other means is possible.

Known transceiver circuits for FlexRay typically include a receiver circuit for receiving a digital signal transmitted over the lines. In such a receiver circuit is usually a

High frequency amplifier for amplifying the digital signal available. A gain, in particular a straight-line gain, of such a known high-frequency amplifier is dependent on the temperature of the components and on the production spread of the components. In the known high-frequency amplifiers, a constant gain can only be achieved by an external negative feedback (closed-loop operation). The external negative feedback has a disturbing effect on the operation of the known amplifiers in a transceiver circuit, because the negative feedback can lead to stability problems of the amplifiers (oscillations, ringing, etc.) and through a network commonly used for negative feedback

Resistors disturbing reactions to inputs of the amplifier caused.

Apart from the closed-loop amplifiers, bipolar circuits are also known since there is also an exponential control characteristic there. As pure CMOS Amplifiers are also used circuits with MOS diodes as a load. These circuits operate sufficiently linearly only for small signal levels.

Disclosure of the invention

The object of the invention is to provide a high-frequency amplifier whose gain is largely independent of the temperature and of the dispersion of components of the amplifier, so that the amplifier is also applicable without external negative feedback for amplifying an input signal of a receiver circuit, in particular for a FlexRay communication system.

The object is achieved by an amplifier having the features of claim 1 and by a transceiver circuit having the features of claim 5. Advantageous developments of the amplifier according to the invention are specified in the subclaims. Overall, the invention provides an amplifier with temperature-independent amplification, in particular with temperature-independent straight-line amplification.

Preferably, according to claim 3, one or more transistors, preferably a plurality of transistors connected in parallel, the power source operated at low inversion, so that by means of these transistors, the required for the temperature-compensated operation of the amplifying transistor stages temperature dependence of the current source can be achieved. These transistors operate as a temperature sensor of the power source.

The amplifier may be realized by any semiconductor technology, but preferably by CMOS semiconductor technology.

Due to the constant gain can be omitted in known amplifiers negative feedback path. As a result, repercussions are avoided on the Einganssignal. In addition, the amplifier according to the invention operates particularly stable and is characterized by a low tendency to oscillate. Furthermore, the amplifier according to the invention requires a relatively small area on a semiconductor chip. Because the modern CMOS technologies that can be used to manufacture the amplifier allow smaller transistors than would be possible with bipolar technologies.

Further features and advantages of the invention will become apparent from the following description in which exemplary embodiments of the invention are explained in more detail with reference to the drawings. Showing:

1 shows a bus system with nodes, each having a transceiver circuit with a receiver circuit;

Figure 2 shows an amplifier for amplifying a at the receiver circuit

Figure 1 adjacent input signal;

Figure 2 is a schematic representation of a Isolierschichtfeldeffekttransistors (MOSFET); and

Figure 4 shows a known amplifier with a negative feedback path.

FIG. 1 shows a bus system 11 to which a plurality of nodes 13 are connected. The bus system 1 1 may be a FlexRay communication system, and thus the bus system 1 1 may be constructed according to the specifications of the FlexRay consortium.

The individual nodes 13 are connected via bus lines 15 either directly or indirectly via a star coupler 17. Each bus line 15 is formed as a cable with at least one wire pair consisting of two wires 19, each forming an electrical conductor. The bus system 11 thus has a channel for transferring data passing through the wires 19 of the

Cores pair is formed. In an embodiment which is not shown, the bus system 11 may comprise a plurality of channels, preferably two channels, which are implemented by two separate pairs of wires (not shown). By using two channels, the payload rate of data transfers between nodes 13 can be increased by transmitting different data over the two channels. Since that Bus system can continue to work in case of a defect on one of the two wire pairs, results in a higher reliability of the bus system 1 1.

Each node 13 has a transceiver circuit 21, which is preferably designed as an integrated circuit. A first bus connection BP and a second bus connection BM of the transceiver circuit 21 are each connected to one of the wires 19 of one of the bus lines 15.

The transceiver circuit 21 has a receiver circuit 23 for receiving data via the bus line 15 and a transmitter circuit 25 for transmitting data via the bus line 15 to which the node 13 is connected. Both the receiver circuit 23 and the transmitter circuit 25 are connected within the transceiver circuit 21 to the two bus terminals BP and BM. Both the receiver circuit 23 and the transmitter circuit 25 are set up to transmit a differential digital signal via the pair of wires of the bus line 15 connected to the corresponding transceiver circuit 21.

The transceiver circuit 21 also has a logic unit 27 which is coupled to the receiver circuit 23 and to the transmitter circuit 25. The

Logic unit 27 has terminals for connecting the transceiver circuit 21 to a control circuit formed, for example, by a microcontroller 31 or a microcomputer. These connections or lines connected thereto form an interface 29 between the transceiver circuit 21 and the control circuit or the microcontroller 31.

The microcontroller 31 has a communication controller 33 for controlling communications between the nodes 13 via the bus line 15. The communication controller 33 is configured to control the communication operations in accordance with the protocols of the bus system 11, in particular for carrying out media access methods of the bus system 11. The communication controller 33 may also be configured to calculate checksums of data frames to be transmitted over the bus 15, for example according to the CRC method and / or to check the checksums of the received data frames. Specifically, interface lines include a line RxD for transmitting data received from the transceiver circuit 21 via the bus line 15 from the transceiver circuit 21 to the communication controller 33, and a line TxD for transmitting data to be sent to the transceiver circuit 21 via the bus line 15 , from the communication controller 33 to the

Transceiver circuit 21 is provided. In addition to the two lines RxD and TXD, the interface 29 also includes further lines 34, which serve, for example, for the exchange of control information between the communication controller 33 and the transceiver circuit 21.

The microcontroller 31 has a calculation core 35, memory 37 (main memory and / or read-only memory) and input and output devices 39. The microcontroller 31 may be configured to execute further protocol software and / or application programs.

In the embodiment shown, the communication controller 33 is integrated in the microcontroller 31. Notwithstanding this, in an embodiment, not shown, the communication controller 33 is designed as a separate circuit from the microcontroller 31, preferably as an integrated circuit.

FIG. 2 shows a high-frequency amplifier 61 of the receiver circuit 23. The high-frequency amplifier 61 may be used for amplifying a digital signal applied to the two bus terminals BP and BM. However, it is also conceivable to use the amplifier 61 in other circuits, in particular in the transceiver circuit 21.

The amplifier 61 is constructed overall as a differential amplifier. It has a first transistor stage 63, which is connected in parallel with a second transistor stage 65. This parallel connection of the two transistor stages 63 and 65 is connected in series with a common branch 67 formed by a drain-source path of a transistor M3. In this case, a drain terminal of the transistor M3 of the common branch 67 is connected to a source terminal of a transistor M1 of the first transistor stage 63 and to a source terminal of a transistor M2 of the second transistor stage 65. The source

Terminal of the transistor M3 is connected to a ground line 69 of the amplifier 61 connected. A drain terminal of the transistor M1 forms an inverting output OUT_MINUS of the amplifier 61. The drain terminal of the transistor M1 is also connected via a resistor M1 to a supply voltage line 71 of the amplifier 61. Similarly, a drain terminal of the transistor M2 is a non-inverting output

OUT_PLUS of the amplifier 61 and via a resistor R2 to the supply voltage line 71. The transistors M1, M2 and M3 are formed as n-channel insulating layer field effect transistors (n-channel MOSFETs).

The transistor M3 forms, together with an n-channel MOSFET M4, a current mirror 73. A gate terminal of the transistor M3 is connected to a gate terminal and a drain terminal of the transistor M4. A source terminal of the transistor M4 is connected to the ground line 69 of the amplifier 61. A drain-source path of a p-channel MOSFET

M5 is disposed between the power supply line 71 and the drain of the transistor M4.

The amplifier 61 has a ring current source 75, which is formed by p-channel MOSFETs M6 and M7 and by n-channel MOSFETs M8, M9, M10 and M1. A drain terminal of the transistor M6 is connected to drains of the parallel-connected transistors M9, M10 and M1 1. Source terminals of the three transistors M9, M10 and M1 1 are connected via a resistor R3 to the ground line 69. Gate terminals of these three transistors M9, M10 and M1 1 are connected to a gate terminal of the transistor

M8 connected. A source terminal of the transistor M8 is connected to the ground line 69, and a drain terminal of the transistor M8 is connected to a drain terminal of the transistor M7. A source terminal of the transistor M7 is connected to the power supply line 71. A gate terminal of the transistor M7 is connected to a gate terminal and to the drain terminal of the transistor M6.

During operation of the amplifier 61, the ring current source 75 generates a temperature-dependent current. In this case, the parallel-connected transistors M9, M10 and M1 1 act as a temperature sensor. The one of the

Ring current source 75 is generated by means of the transistor M5 and the Current mirror 73 transmitted to the common branch 67 of the amplifier 61. A current conversion ratio of the ring current source 75 may be arbitrary; the current transmission ratio is preferably 1.

The amplifier 61 is preferably constructed so that the individual ones

Transistors M1 - M1 1 are thermally coupled together. For example, the amplifier 61 may be arranged on the same chip of an integrated circuit, resulting in a good thermal coupling between the individual components of the amplifier 61.

The amplifier 61 is designed so that at least the transistors M1 and M2, preferably the transistors M1, M2, M8, M9, M10 and M1 1, operate in an operating range of weak inversion. The weak inversion operation can be achieved by a suitable choice of the operating points of these transistors M1, M2, M8, M9, M10, M1 1.

In this case, the operating point can be selected, for example, such that a difference between a gate-source voltage V _gs and a threshold voltage V _{th of} the transistors M1, M2, M8, M9, M10, M1 1 is less than or equal to 100 mV. That is, V _gs - V _th <= 100 mV.

When the transistors M1 and M2 operate at low inversion, the gain of these MOS transistors is largely independent of at least such parameters of the technology by which they have been manufactured, which are associated with relatively large manufacturing tolerances of a manufacturing process for manufacturing the amplifier 61. For the gain gm the following applies:

gm = Id ^* e / (n ^* k ^* T),

in which

e for the elementary charge 1 .602 ^* 10 ^"19 As, k for the Boltzmann constant 1 .38 ^* 10 ^{" 23} Vas / K and

T for the temperature of the amplifier 61 measured in Kelvin

stands. The parameters e, k, T are independent of the technology. The parameter n describes the capacitive division of an input signal of a MOS transistor through a first capacitance Cgch between gate and channel and a second capacitance Cchsub between channel and BuIk (see FIG. 3). The parameter n is calculated to

n = (Cgch + Cchsub) / Cgch

The first capacitance Cgch is determined by the oxide thickness of a gate oxide of the MOS transistor. This is the core parameter of any CMOS process and is subject to the most accurate control possible, and thus at most low

Manufacturing tolerances.

The second capacity Cchsub is dependent on a width of a space charge zone between the channel and BuIk. This width follows the root of a bulk stress and the reciprocal of the root of a bulk doping. This means that the error propagation of doping or bulk voltage changes are disproportionate (see, e.g., R. Mueller, Semiconductor Electronics Components, Springer 1987 and Willy M.C. Sansen, Analog Design Essentials, Springer 2006). In practice, the parameter n usually moves in a range between 1.2 and 1 .6.

An amplification gain of the amplifier 61, that is of the stage M1, M2, R1, R2 is calculated as:

gain = R1 ^* _lbias ^* e / (n ^* k ^* T)

This equation holds as long as M1 and M2 operate at low inversion. The value I _b i _as stands for a current through the drain-source path of the transistor M3. The gain gain becomes independent of the temperature by generating a temperature proportional current. This stream is through the

Ringstromqelle 75, that is generated by the transistors M6 - M1 1 and by the resistor R3. The transistors M8 to M1 1 also operate at low inversion. For the current through the drain-source path of the transistor M3 results

_lbias = ln (m) ^* n ^* k ^* T / (R3 ^* e), where the parameter m = W / L stands for a ratio between channel width and channel length of the transistors M9 - M1 1 and M8. In the embodiment shown, m = 3. By inserting the last equation into the penultimate equation results

gain = R1 ^* ln (m) / R3.

The ratio R1 / R3 is determined by the geometry of the resistors and is process independent. The parameter m is also a pure one

Aspect ratio. Thus, the gain is independent of process parameters and temperature.

It is preferred that the components used can be realized well paired.

In known amplifiers, it is common to operate MOSFETs in a strong-inversion operating range. Here, however, other equations apply to the gain gm of the individual transistors:

gm _{strand ιnversιon} = 2 ^* K ' ^* (V _gs -V _th ) ^* W / L

K 'contains both technology, semiconductor material and temperature dependent parameters.

The term V _gs -V _th is the root of the current.

V _gs -V _th = (L ^* 1 _bιas / (W ^* K ')) ^1/2

Because of these relationships, it is not possible to build an amplifier independent of the temperature and the process parameters in the case of strong inversion, which operates in open-loop mode.

FIG. 4 shows a known amplifier 77. In order to achieve stable amplifications, the known amplifier 77 is used in closed-loop mode.

The closed-loop circuit 77 shown here has one through resistors R "l, R'2, R'3 and R'4 formed external negative feedback and therefore has repercussions on the inputs IN_PLUS and IN_MINUS and often suffers from stability problems. That is, depending on the load and the gain set by resistors R "1, R'2, R'3 and R'4, the conventional closed-loop amplifier 77 tends to ring or oscillate.

Claims

claims

1 . High-frequency differential amplifier (61) for a transceiver circuit (21) for a bus system (1 1) comprising two transistor stages (63, 65) with insulated-gate field-effect transistors (M1, M2) and a common branch (67) connected to the two transistor stages (63, 65). to the

Coupling the transistor stages (63, 65) to each other, wherein the common branch (67) is associated with a current source (75) of the high frequency differential amplifier (61) for generating an operating current (I _b i _as ) flowing through the common branch (67), characterized in that the transistor stages (63, 65) are arranged to operate the insulated-gate field-effect transistors (M 1, M2) at low inversion, and in that the current source (75) is designed to compensate for a temperature dependence of a gain of at least one insulated-gate field-effect transistor (M1, M2) is that the operating _current (l _bιas ) of a temperature (T) of the

High frequency difference amplifier (61) depends.

Second amplifier (61) according to claim 1, characterized in that the of the current source (75) generated operating current (I _b i _as ) is at least substantially proportional to the temperature (T) of the high frequency amplifier (61).

3. Amplifier (61) according to claim 1 or 2, characterized in that the current source (75) further Isolierschichtfeldeffekttransistoren (M6, M7, M8, M9, M10, M1 1) and that the current source (75) for operating at least one of these Insulating layer field effect transistors (M9, M10, M1 1) are set up in weak inversion.

4. Amplifier (61) according to one of the preceding claims, characterized in that the current source is a ring current source (75) for generating the operating current (l _b , _as ) and that the amplifier (61) has a current mirror (73) for impressing the operating current (l _b , as) in the common branch (67).

5. Transceiver circuit (21) for a bus system, comprising a high-frequency difference amplifier (61), the two transistor stages (63, 65) with

Insulated-layer field-effect transistors (M1, M2) and a common branch (67) connected to the two transistor stages (63, 65) for coupling the transistor stages (63, 65) to each other, the common branch (67) being a current source (75) of the high-frequency differential amplifier (67). 61) for generating an operating current (l _b , as) flowing through the common branch (67), characterized in that the high-frequency difference amplifier (61) is designed according to one of the preceding claims.